👋 I'm Yhely Orgad
🎓 Electrical Engineering graduate from BIU, Israel
🔬 Specialized in Nanoelectronics, VLSI Circuits, and Communication
💻 3+ years of experience in Digital Design
📝 Focused on RTL design, SystemVerilog coding, and simulation of large-scale digital architectures
🧰 Tools: Vivado, Synplify, ModelSim, VCS, Verdi, Xcelium
✅ Formal Verification expertise
🖥️ Environment: Git, Linux
📊 Scripting & Automation: MATLAB, various programming languages