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interpreter.cpp
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interpreter.cpp
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/*
Copyright 2019-2020 Hydr8gon
This file is part of NooDS.
NooDS is free software: you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
NooDS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
General Public License for more details.
You should have received a copy of the GNU General Public License
along with NooDS. If not, see <https://www.gnu.org/licenses/>.
*/
#include "interpreter.h"
#include "interpreter_alu.h"
#include "interpreter_branch.h"
#include "interpreter_transfer.h"
Interpreter::Interpreter(Core *core, bool cpu): core(core), cpu(cpu)
{
for (int i = 0; i < 16; i++)
registers[i] = ®istersUsr[i];
// Prepare to boot the BIOS
registersUsr[15] = ((cpu == 0) ? 0xFFFF0000 : 0x00000000) + 4;
cpsr = 0x000000C0;
setMode(0x13); // Supervisor
}
void Interpreter::directBoot()
{
uint32_t entryAddr;
// Prepare to directly boot an NDS ROM
if (cpu == 0) // ARM9
{
entryAddr = core->memory.read<uint32_t>(0, 0x27FFE24);
registersUsr[13] = 0x03002F7C;
registersIrq[0] = 0x03003F80;
registersSvc[0] = 0x03003FC0;
}
else // ARM7
{
entryAddr = core->memory.read<uint32_t>(0, 0x27FFE34);
registersUsr[13] = 0x0380FD80;
registersIrq[0] = 0x0380FF80;
registersSvc[0] = 0x0380FFC0;
}
registersUsr[12] = entryAddr;
registersUsr[14] = entryAddr;
registersUsr[15] = entryAddr + 4;
cpsr = 0x000000C0;
setMode(0x1F); // System
}
void Interpreter::enterGbaMode()
{
// Prepare to boot the GBA BIOS (and rely on it to initialize everything else)
registersUsr[15] = 0x00000000 + 4;
cpsr = 0x000000C0;
setMode(0x13); // Supervisor
postFlg = 0;
}
void Interpreter::runCycle()
{
// Trigger an interrupt if one was requested and enabled
if (ime && (ie & irf) && !(cpsr & BIT(7)))
{
// Switch the CPU to interrupt mode
uint32_t cpsrOld = cpsr;
setMode(0x12);
*spsr = cpsrOld;
// Switch to ARM mode and block other interrupts
cpsr &= ~BIT(5);
cpsr |= BIT(7);
// Save the return address and jump to the interrupt handler
*registers[14] = *registers[15] + ((cpsrOld & BIT(5)) ? 2 : 0);
*registers[15] = ((cpu == 0) ? core->cp15.getExceptionAddr() : 0x00000000) + 0x18 + 4;
}
// Execute an instruction
if (cpsr & BIT(5)) // THUMB mode
{
// Increment the program counter
*registers[15] += 2;
// Execute 2 opcodes behind the program counter because of pipelining
// In THUMB mode, this is 4 bytes behind
uint16_t opcode = core->memory.read<uint16_t>(cpu, *registers[15] - 4);
// THUMB lookup table, based on the map found at http://imrannazar.com/ARM-Opcode-Map
// Uses bits 15-8 of an opcode to find the appropriate instruction
switch ((opcode & 0xFF00) >> 8)
{
case 0x00: case 0x01: case 0x02: case 0x03:
case 0x04: case 0x05: case 0x06: case 0x07:
return lslImmT(opcode); // LSL Rd,Rs,#i
case 0x08: case 0x09: case 0x0A: case 0x0B:
case 0x0C: case 0x0D: case 0x0E: case 0x0F:
return lsrImmT(opcode); // LSR Rd,Rs,#i
case 0x10: case 0x11: case 0x12: case 0x13:
case 0x14: case 0x15: case 0x16: case 0x17:
return asrImmT(opcode); // ASR Rd,Rs,#i
case 0x18: case 0x19:
return addRegT(opcode); // ADD Rd,Rs,Rn
case 0x1A: case 0x1B:
return subRegT(opcode); // SUB Rd,Rs,Rn
case 0x1C: case 0x1D:
return addImm3T(opcode); // ADD Rd,Rs,#i
case 0x1E: case 0x1F:
return subImm3T(opcode); // SUB Rd,Rs,#i
case 0x20: case 0x21: case 0x22: case 0x23:
case 0x24: case 0x25: case 0x26: case 0x27:
return movImm8T(opcode); // MOV Rd,#i
case 0x28: case 0x29: case 0x2A: case 0x2B:
case 0x2C: case 0x2D: case 0x2E: case 0x2F:
return cmpImm8T(opcode); // CMP Rd,#i
case 0x30: case 0x31: case 0x32: case 0x33:
case 0x34: case 0x35: case 0x36: case 0x37:
return addImm8T(opcode); // ADD Rd,#i
case 0x38: case 0x39: case 0x3A: case 0x3B:
case 0x3C: case 0x3D: case 0x3E: case 0x3F:
return subImm8T(opcode); // SUB Rd,#i
case 0x40:
switch ((opcode & 0x00C0) >> 6)
{
case 0: return andDpT(opcode); // AND Rd,Rs
case 1: return eorDpT(opcode); // EOR Rd,Rs
case 2: return lslDpT(opcode); // LSL Rd,Rs
default: return lsrDpT(opcode); // LSR Rd,Rs
}
case 0x41:
switch ((opcode & 0x00C0) >> 6)
{
case 0: return asrDpT(opcode); // ASR Rd,Rs
case 1: return adcDpT(opcode); // ADC Rd,Rs
case 2: return sbcDpT(opcode); // SBC Rd,Rs
default: return rorDpT(opcode); // ROR Rd,Rs
}
case 0x42:
switch ((opcode & 0x00C0) >> 6)
{
case 0: return tstDpT(opcode); // TST Rd,Rs
case 1: return negDpT(opcode); // NEG Rd,Rs
case 2: return cmpDpT(opcode); // CMP Rd,Rs
default: return cmnDpT(opcode); // CMN Rd,Rs
}
case 0x43:
switch ((opcode & 0x00C0) >> 6)
{
case 0: return orrDpT(opcode); // ORR Rd,Rs
case 1: return mulDpT(opcode); // MUL Rd,Rs
case 2: return bicDpT(opcode); // BIC Rd,Rs
default: return mvnDpT(opcode); // MVN Rd,Rs
}
case 0x44:
return addHT(opcode); // ADD Rd,Rs
case 0x45:
return cmpHT(opcode); // CMP Rd,Rs
case 0x46:
return movHT(opcode); // MOV Rd,Rs
case 0x47:
if (opcode & BIT(7))
return blxRegT(opcode); // BLX Rs
else
return bxRegT(opcode); // BX Rs
case 0x48: case 0x49: case 0x4A: case 0x4B:
case 0x4C: case 0x4D: case 0x4E: case 0x4F:
return ldrPcT(opcode); // LDR Rd,[PC,#i]
case 0x50: case 0x51:
return strRegT(opcode); // STR Rd,[Rb,Ro]
case 0x52: case 0x53:
return strhRegT(opcode); // STRH Rd,[Rb,Ro]
case 0x54: case 0x55:
return strbRegT(opcode); // STRB Rd,[Rb,Ro]
case 0x56: case 0x57:
return ldrsbRegT(opcode); // LDRSB Rd,[Rb,Ro]
case 0x58: case 0x59:
return ldrRegT(opcode); // LDR Rd,[Rb,Ro]
case 0x5A: case 0x5B:
return ldrhRegT(opcode); // LDRH Rd,[Rb,Ro]
case 0x5C: case 0x5D:
return ldrbRegT(opcode); // LDRB Rd,[Rb,Ro]
case 0x5E: case 0x5F:
return ldrshRegT(opcode); // LDRSH Rd,[Rb,Ro]
case 0x60: case 0x61: case 0x62: case 0x63:
case 0x64: case 0x65: case 0x66: case 0x67:
return strImm5T(opcode); // STR Rd,[Rb,#i]
case 0x68: case 0x69: case 0x6A: case 0x6B:
case 0x6C: case 0x6D: case 0x6E: case 0x6F:
return ldrImm5T(opcode); // LDR Rd,[Rb,#i]
case 0x70: case 0x71: case 0x72: case 0x73:
case 0x74: case 0x75: case 0x76: case 0x77:
return strbImm5T(opcode); // STRB Rd,[Rb,#i]
case 0x78: case 0x79: case 0x7A: case 0x7B:
case 0x7C: case 0x7D: case 0x7E: case 0x7F:
return ldrbImm5T(opcode); // LDRB Rd,[Rb,#i]
case 0x80: case 0x81: case 0x82: case 0x83:
case 0x84: case 0x85: case 0x86: case 0x87:
return strhImm5T(opcode); // STRH Rd,[Rb,#i]
case 0x88: case 0x89: case 0x8A: case 0x8B:
case 0x8C: case 0x8D: case 0x8E: case 0x8F:
return ldrhImm5T(opcode); // LDRH Rd,[Rb,#i]
case 0x90: case 0x91: case 0x92: case 0x93:
case 0x94: case 0x95: case 0x96: case 0x97:
return strSpT(opcode); // STR Rd,[SP,#i]
case 0x98: case 0x99: case 0x9A: case 0x9B:
case 0x9C: case 0x9D: case 0x9E: case 0x9F:
return ldrSpT(opcode); // LDR Rd,[SP,#i]
case 0xA0: case 0xA1: case 0xA2: case 0xA3:
case 0xA4: case 0xA5: case 0xA6: case 0xA7:
return addPcT(opcode); // ADD Rd,PC,#i
case 0xA8: case 0xA9: case 0xAA: case 0xAB:
case 0xAC: case 0xAD: case 0xAE: case 0xAF:
return addSpT(opcode); // ADD Rd,SP,#i
case 0xB0:
return addSpImmT(opcode); // ADD SP,#i
case 0xB4:
return pushT(opcode); // PUSH <Rlist>
case 0xB5:
return pushLrT(opcode); // PUSH <Rlist>,LR
case 0xBC:
return popT(opcode); // POP <Rlist>
case 0xBD:
return popPcT(opcode); // POP <Rlist>,PC
case 0xC0: case 0xC1: case 0xC2: case 0xC3:
case 0xC4: case 0xC5: case 0xC6: case 0xC7:
return stmiaT(opcode); // STMIA Rb!,<Rlist>
case 0xC8: case 0xC9: case 0xCA: case 0xCB:
case 0xCC: case 0xCD: case 0xCE: case 0xCF:
return ldmiaT(opcode); // LDMIA Rb!,<Rlist>
case 0xD0:
return beqT(opcode); // BEQ label
case 0xD1:
return bneT(opcode); // BNE label
case 0xD2:
return bcsT(opcode); // BCS label
case 0xD3:
return bccT(opcode); // BCC label
case 0xD4:
return bmiT(opcode); // BMI label
case 0xD5:
return bplT(opcode); // BPL label
case 0xD6:
return bvsT(opcode); // BVS label
case 0xD7:
return bvcT(opcode); // BVC label
case 0xD8:
return bhiT(opcode); // BHI label
case 0xD9:
return blsT(opcode); // BLS label
case 0xDA:
return bgeT(opcode); // BGE label
case 0xDB:
return bltT(opcode); // BLT label
case 0xDC:
return bgtT(opcode); // BGT label
case 0xDD:
return bleT(opcode); // BLE label
case 0xDF:
return swiT(); // SWI #i
case 0xE0: case 0xE1: case 0xE2: case 0xE3:
case 0xE4: case 0xE5: case 0xE6: case 0xE7:
return bT(opcode); // B label
case 0xE8: case 0xE9: case 0xEA: case 0xEB:
case 0xEC: case 0xED: case 0xEE: case 0xEF:
return blxOffT(opcode); // BLX label
case 0xF0: case 0xF1: case 0xF2: case 0xF3:
case 0xF4: case 0xF5: case 0xF6: case 0xF7:
return blSetupT(opcode); // BL/BLX label
case 0xF8: case 0xF9: case 0xFA: case 0xFB:
case 0xFC: case 0xFD: case 0xFE: case 0xFF:
return blOffT(opcode); // BL label
default:
printf("Unknown ARM%d THUMB opcode: 0x%X\n", ((cpu == 0) ? 9 : 7), opcode);
return;
}
}
else // ARM mode
{
// Increment the program counter
*registers[15] += 4;
// Execute 2 opcodes behind the program counter because of pipelining
// In ARM mode, this is 8 bytes behind
uint32_t opcode = core->memory.read<uint32_t>(cpu, *registers[15] - 8);
if (condition(opcode))
{
// ARM lookup table, based on the map found at http://imrannazar.com/ARM-Opcode-Map
// Uses bits 27-20 and 7-4 of an opcode to find the appropriate instruction
switch (((opcode & 0x0FF00000) >> 16) | ((opcode & 0x000000F0) >> 4))
{
case 0x000: case 0x008:
return _and(opcode, lli(opcode)); // AND Rd,Rn,Rm,LSL #i
case 0x001:
return _and(opcode, llr(opcode)); // AND Rd,Rn,Rm,LSL Rs
case 0x002: case 0x00A:
return _and(opcode, lri(opcode)); // AND Rd,Rn,Rm,LSR #i
case 0x003:
return _and(opcode, lrr(opcode)); // AND Rd,Rn,Rm,LSR Rs
case 0x004: case 0x00C:
return _and(opcode, ari(opcode)); // AND Rd,Rn,Rm,ASR #i
case 0x005:
return _and(opcode, arr(opcode)); // AND Rd,Rn,Rm,ASR Rs
case 0x006: case 0x00E:
return _and(opcode, rri(opcode)); // AND Rd,Rn,Rm,ROR #i
case 0x007:
return _and(opcode, rrr(opcode)); // AND Rd,Rn,Rm,ROR Rs
case 0x009:
return mul(opcode); // MUL Rd,Rm,Rs
case 0x00B: case 0x02B:
return strhPt(opcode, -rp(opcode)); // STRH Rd,[Rn],-Rm
case 0x00D: case 0x02D:
return ldrdPt(opcode, -rp(opcode)); // LDRD Rd,[Rn],-Rm
case 0x00F: case 0x02F:
return strdPt(opcode, -rp(opcode)); // STRD Rd,[Rn],-Rm
case 0x010: case 0x018:
return ands(opcode, lliS(opcode)); // ANDS Rd,Rn,Rm,LSL #i
case 0x011:
return ands(opcode, llrS(opcode)); // ANDS Rd,Rn,Rm,LSL Rs
case 0x012: case 0x01A:
return ands(opcode, lriS(opcode)); // ANDS Rd,Rn,Rm,LSR #i
case 0x013:
return ands(opcode, lrrS(opcode)); // ANDS Rd,Rn,Rm,LSR Rs
case 0x014: case 0x01C:
return ands(opcode, ariS(opcode)); // ANDS Rd,Rn,Rm,ASR #i
case 0x015:
return ands(opcode, arrS(opcode)); // ANDS Rd,Rn,Rm,ASR Rs
case 0x016: case 0x01E:
return ands(opcode, rriS(opcode)); // ANDS Rd,Rn,Rm,ROR #i
case 0x017:
return ands(opcode, rrrS(opcode)); // ANDS Rd,Rn,Rm,ROR Rs
case 0x019:
return muls(opcode); // MULS Rd,Rm,Rs
case 0x01B: case 0x03B:
return ldrhPt(opcode, -rp(opcode)); // LDRH Rd,[Rn],-Rm
case 0x01D: case 0x03D:
return ldrsbPt(opcode, -rp(opcode)); // LDRSB Rd,[Rn],-Rm
case 0x01F: case 0x03F:
return ldrshPt(opcode, -rp(opcode)); // LDRSH Rd,[Rn],-Rm
case 0x020: case 0x028:
return eor(opcode, lli(opcode)); // EOR Rd,Rn,Rm,LSL #i
case 0x021:
return eor(opcode, llr(opcode)); // EOR Rd,Rn,Rm,LSL Rs
case 0x022: case 0x02A:
return eor(opcode, lri(opcode)); // EOR Rd,Rn,Rm,LSR #i
case 0x023:
return eor(opcode, lrr(opcode)); // EOR Rd,Rn,Rm,LSR Rs
case 0x024: case 0x02C:
return eor(opcode, ari(opcode)); // EOR Rd,Rn,Rm,ASR #i
case 0x025:
return eor(opcode, arr(opcode)); // EOR Rd,Rn,Rm,ASR Rs
case 0x026: case 0x02E:
return eor(opcode, rri(opcode)); // EOR Rd,Rn,Rm,ROR #i
case 0x027:
return eor(opcode, rrr(opcode)); // EOR Rd,Rn,Rm,ROR Rs
case 0x029:
return mla(opcode); // MLA Rd,Rm,Rs,Rn
case 0x030: case 0x038:
return eors(opcode, lliS(opcode)); // EORS Rd,Rn,Rm,LSL #i
case 0x031:
return eors(opcode, llrS(opcode)); // EORS Rd,Rn,Rm,LSL Rs
case 0x032: case 0x03A:
return eors(opcode, lriS(opcode)); // EORS Rd,Rn,Rm,LSR #i
case 0x033:
return eors(opcode, lrrS(opcode)); // EORS Rd,Rn,Rm,LSR Rs
case 0x034: case 0x03C:
return eors(opcode, ariS(opcode)); // EORS Rd,Rn,Rm,ASR #i
case 0x035:
return eors(opcode, arrS(opcode)); // EORS Rd,Rn,Rm,ASR Rs
case 0x036: case 0x03E:
return eors(opcode, rriS(opcode)); // EORS Rd,Rn,Rm,ROR #i
case 0x037:
return eors(opcode, rrrS(opcode)); // EORS Rd,Rn,Rm,ROR Rs
case 0x039:
return mlas(opcode); // MLAS Rd,Rm,Rs,Rn
case 0x040: case 0x048:
return sub(opcode, lli(opcode)); // SUB Rd,Rn,Rm,LSL #i
case 0x041:
return sub(opcode, llr(opcode)); // SUB Rd,Rn,Rm,LSL Rs
case 0x042: case 0x04A:
return sub(opcode, lri(opcode)); // SUB Rd,Rn,Rm,LSR #i
case 0x043:
return sub(opcode, lrr(opcode)); // SUB Rd,Rn,Rm,LSR Rs
case 0x044: case 0x04C:
return sub(opcode, ari(opcode)); // SUB Rd,Rn,Rm,ASR #i
case 0x045:
return sub(opcode, arr(opcode)); // SUB Rd,Rn,Rm,ASR Rs
case 0x046: case 0x04E:
return sub(opcode, rri(opcode)); // SUB Rd,Rn,Rm,ROR #i
case 0x047:
return sub(opcode, rrr(opcode)); // SUB Rd,Rn,Rm,ROR Rs
case 0x04B: case 0x06B:
return strhPt(opcode, -ipH(opcode)); // STRH Rd,[Rn],-#i
case 0x04D: case 0x06D:
return ldrdPt(opcode, -ipH(opcode)); // LDRD Rd,[Rn],-#i
case 0x04F: case 0x06F:
return strdPt(opcode, -ipH(opcode)); // STRD Rd,[Rn],-#i
case 0x050: case 0x058:
return subs(opcode, lli(opcode)); // SUBS Rd,Rn,Rm,LSL #i
case 0x051:
return subs(opcode, llr(opcode)); // SUBS Rd,Rn,Rm,LSL Rs
case 0x052: case 0x05A:
return subs(opcode, lri(opcode)); // SUBS Rd,Rn,Rm,LSR #i
case 0x053:
return subs(opcode, lrr(opcode)); // SUBS Rd,Rn,Rm,LSR Rs
case 0x054: case 0x05C:
return subs(opcode, ari(opcode)); // SUBS Rd,Rn,Rm,ASR #i
case 0x055:
return subs(opcode, arr(opcode)); // SUBS Rd,Rn,Rm,ASR Rs
case 0x056: case 0x05E:
return subs(opcode, rri(opcode)); // SUBS Rd,Rn,Rm,ROR #i
case 0x057:
return subs(opcode, rrr(opcode)); // SUBS Rd,Rn,Rm,ROR Rs
case 0x05B: case 0x07B:
return ldrhPt(opcode, -ipH(opcode)); // LDRH Rd,[Rn],-#i
case 0x05D: case 0x07D:
return ldrsbPt(opcode, -ipH(opcode)); // LDRSB Rd,[Rn],-#i
case 0x05F: case 0x07F:
return ldrshPt(opcode, -ipH(opcode)); // LDRSH Rd,[Rn],-#i
case 0x060: case 0x068:
return rsb(opcode, lli(opcode)); // RSB Rd,Rn,Rm,LSL #i
case 0x061:
return rsb(opcode, llr(opcode)); // RSB Rd,Rn,Rm,LSL Rs
case 0x062: case 0x06A:
return rsb(opcode, lri(opcode)); // RSB Rd,Rn,Rm,LSR #i
case 0x063:
return rsb(opcode, lrr(opcode)); // RSB Rd,Rn,Rm,LSR Rs
case 0x064: case 0x06C:
return rsb(opcode, ari(opcode)); // RSB Rd,Rn,Rm,ASR #i
case 0x065:
return rsb(opcode, arr(opcode)); // RSB Rd,Rn,Rm,ASR Rs
case 0x066: case 0x06E:
return rsb(opcode, rri(opcode)); // RSB Rd,Rn,Rm,ROR #i
case 0x067:
return rsb(opcode, rrr(opcode)); // RSB Rd,Rn,Rm,ROR Rs
case 0x070: case 0x078:
return rsbs(opcode, lli(opcode)); // RSBS Rd,Rn,Rm,LSL #i
case 0x071:
return rsbs(opcode, llr(opcode)); // RSBS Rd,Rn,Rm,LSL Rs
case 0x072: case 0x07A:
return rsbs(opcode, lri(opcode)); // RSBS Rd,Rn,Rm,LSR #i
case 0x073:
return rsbs(opcode, lrr(opcode)); // RSBS Rd,Rn,Rm,LSR Rs
case 0x074: case 0x07C:
return rsbs(opcode, ari(opcode)); // RSBS Rd,Rn,Rm,ASR #i
case 0x075:
return rsbs(opcode, arr(opcode)); // RSBS Rd,Rn,Rm,ASR Rs
case 0x076: case 0x07E:
return rsbs(opcode, rri(opcode)); // RSBS Rd,Rn,Rm,ROR #i
case 0x077:
return rsbs(opcode, rrr(opcode)); // RSBS Rd,Rn,Rm,ROR Rs
case 0x080: case 0x088:
return add(opcode, lli(opcode)); // ADD Rd,Rn,Rm,LSL #i
case 0x081:
return add(opcode, llr(opcode)); // ADD Rd,Rn,Rm,LSL Rs
case 0x082: case 0x08A:
return add(opcode, lri(opcode)); // ADD Rd,Rn,Rm,LSR #i
case 0x083:
return add(opcode, lrr(opcode)); // ADD Rd,Rn,Rm,LSR Rs
case 0x084: case 0x08C:
return add(opcode, ari(opcode)); // ADD Rd,Rn,Rm,ASR #i
case 0x085:
return add(opcode, arr(opcode)); // ADD Rd,Rn,Rm,ASR Rs
case 0x086: case 0x08E:
return add(opcode, rri(opcode)); // ADD Rd,Rn,Rm,ROR #i
case 0x087:
return add(opcode, rrr(opcode)); // ADD Rd,Rn,Rm,ROR Rs
case 0x089:
return umull(opcode); // UMULL RdLo,RdHi,Rm,Rs
case 0x08B: case 0x0AB:
return strhPt(opcode, rp(opcode)); // STRH Rd,[Rn],Rm
case 0x08D: case 0x0AD:
return ldrdPt(opcode, rp(opcode)); // LDRD Rd,[Rn],Rm
case 0x08F: case 0x0AF:
return strdPt(opcode, rp(opcode)); // STRD Rd,[Rn],Rm
case 0x090: case 0x098:
return adds(opcode, lli(opcode)); // ADDS Rd,Rn,Rm,LSL #i
case 0x091:
return adds(opcode, llr(opcode)); // ADDS Rd,Rn,Rm,LSL Rs
case 0x092: case 0x09A:
return adds(opcode, lri(opcode)); // ADDS Rd,Rn,Rm,LSR #i
case 0x093:
return adds(opcode, lrr(opcode)); // ADDS Rd,Rn,Rm,LSR Rs
case 0x094: case 0x09C:
return adds(opcode, ari(opcode)); // ADDS Rd,Rn,Rm,ASR #i
case 0x095:
return adds(opcode, arr(opcode)); // ADDS Rd,Rn,Rm,ASR Rs
case 0x096: case 0x09E:
return adds(opcode, rri(opcode)); // ADDS Rd,Rn,Rm,ROR #i
case 0x097:
return adds(opcode, rrr(opcode)); // ADDS Rd,Rn,Rm,ROR Rs
case 0x099:
return umulls(opcode); // UMULLS RdLo,RdHi,Rm,Rs
case 0x09B: case 0x0BB:
return ldrhPt(opcode, rp(opcode)); // LDRH Rd,[Rn],Rm
case 0x09D: case 0x0BD:
return ldrsbPt(opcode, rp(opcode)); // LDRSB Rd,[Rn],Rm
case 0x09F: case 0x0BF:
return ldrshPt(opcode, rp(opcode)); // LDRSH Rd,[Rn],Rm
case 0x0A0: case 0x0A8:
return adc(opcode, lli(opcode)); // ADC Rd,Rn,Rm,LSL #i
case 0x0A1:
return adc(opcode, llr(opcode)); // ADC Rd,Rn,Rm,LSL Rs
case 0x0A2: case 0x0AA:
return adc(opcode, lri(opcode)); // ADC Rd,Rn,Rm,LSR #i
case 0x0A3:
return adc(opcode, lrr(opcode)); // ADC Rd,Rn,Rm,LSR Rs
case 0x0A4: case 0x0AC:
return adc(opcode, ari(opcode)); // ADC Rd,Rn,Rm,ASR #i
case 0x0A5:
return adc(opcode, arr(opcode)); // ADC Rd,Rn,Rm,ASR Rs
case 0x0A6: case 0x0AE:
return adc(opcode, rri(opcode)); // ADC Rd,Rn,Rm,ROR #i
case 0x0A7:
return adc(opcode, rrr(opcode)); // ADC Rd,Rn,Rm,ROR Rs
case 0x0A9:
return umlal(opcode); // UMLAL RdLo,RdHi,Rm,Rs
case 0x0B0: case 0x0B8:
return adcs(opcode, lli(opcode)); // ADCS Rd,Rn,Rm,LSL #i
case 0x0B1:
return adcs(opcode, llr(opcode)); // ADCS Rd,Rn,Rm,LSL Rs
case 0x0B2: case 0x0BA:
return adcs(opcode, lri(opcode)); // ADCS Rd,Rn,Rm,LSR #i
case 0x0B3:
return adcs(opcode, lrr(opcode)); // ADCS Rd,Rn,Rm,LSR Rs
case 0x0B4: case 0x0BC:
return adcs(opcode, ari(opcode)); // ADCS Rd,Rn,Rm,ASR #i
case 0x0B5:
return adcs(opcode, arr(opcode)); // ADCS Rd,Rn,Rm,ASR Rs
case 0x0B6: case 0x0BE:
return adcs(opcode, rri(opcode)); // ADCS Rd,Rn,Rm,ROR #i
case 0x0B7:
return adcs(opcode, rrr(opcode)); // ADCS Rd,Rn,Rm,ROR Rs
case 0x0B9:
return umlals(opcode); // UMLALS RdLo,RdHi,Rm,Rs
case 0x0C0: case 0x0C8:
return sbc(opcode, lli(opcode)); // SBC Rd,Rn,Rm,LSL #i
case 0x0C1:
return sbc(opcode, llr(opcode)); // SBC Rd,Rn,Rm,LSL Rs
case 0x0C2: case 0x0CA:
return sbc(opcode, lri(opcode)); // SBC Rd,Rn,Rm,LSR #i
case 0x0C3:
return sbc(opcode, lrr(opcode)); // SBC Rd,Rn,Rm,LSR Rs
case 0x0C4: case 0x0CC:
return sbc(opcode, ari(opcode)); // SBC Rd,Rn,Rm,ASR #i
case 0x0C5:
return sbc(opcode, arr(opcode)); // SBC Rd,Rn,Rm,ASR Rs
case 0x0C6: case 0x0CE:
return sbc(opcode, rri(opcode)); // SBC Rd,Rn,Rm,ROR #i
case 0x0C7:
return sbc(opcode, rrr(opcode)); // SBC Rd,Rn,Rm,ROR Rs
case 0x0C9:
return smull(opcode); // SMULL RdLo,RdHi,Rm,Rs
case 0x0CB: case 0x0EB:
return strhPt(opcode, ipH(opcode)); // STRH Rd,[Rn],#i
case 0x0CD: case 0x0ED:
return ldrdPt(opcode, ipH(opcode)); // LDRD Rd,[Rn],#i
case 0x0CF: case 0x0EF:
return strdPt(opcode, ipH(opcode)); // STRD Rd,[Rn],#i
case 0x0D0: case 0x0D8:
return sbcs(opcode, lli(opcode)); // SBCS Rd,Rn,Rm,LSL #i
case 0x0D1:
return sbcs(opcode, llr(opcode)); // SBCS Rd,Rn,Rm,LSL Rs
case 0x0D2: case 0x0DA:
return sbcs(opcode, lri(opcode)); // SBCS Rd,Rn,Rm,LSR #i
case 0x0D3:
return sbcs(opcode, lrr(opcode)); // SBCS Rd,Rn,Rm,LSR Rs
case 0x0D4: case 0x0DC:
return sbcs(opcode, ari(opcode)); // SBCS Rd,Rn,Rm,ASR #i
case 0x0D5:
return sbcs(opcode, arr(opcode)); // SBCS Rd,Rn,Rm,ASR Rs
case 0x0D6: case 0x0DE:
return sbcs(opcode, rri(opcode)); // SBCS Rd,Rn,Rm,ROR #i
case 0x0D7:
return sbcs(opcode, rrr(opcode)); // SBCS Rd,Rn,Rm,ROR Rs
case 0x0D9:
return smulls(opcode); // SMULLS RdLo,RdHi,Rm,Rs
case 0x0DB: case 0x0FB:
return ldrhPt(opcode, ipH(opcode)); // LDRH Rd,[Rn],#i
case 0x0DD: case 0x0FD:
return ldrsbPt(opcode, ipH(opcode)); // LDRSB Rd,[Rn],#i
case 0x0DF: case 0x0FF:
return ldrshPt(opcode, ipH(opcode)); // LDRSH Rd,[Rn],#i
case 0x0E0: case 0x0E8:
return rsc(opcode, lli(opcode)); // RSC Rd,Rn,Rm,LSL #i
case 0x0E1:
return rsc(opcode, llr(opcode)); // RSC Rd,Rn,Rm,LSL Rs
case 0x0E2: case 0x0EA:
return rsc(opcode, lri(opcode)); // RSC Rd,Rn,Rm,LSR #i
case 0x0E3:
return rsc(opcode, lrr(opcode)); // RSC Rd,Rn,Rm,LSR Rs
case 0x0E4: case 0x0EC:
return rsc(opcode, ari(opcode)); // RSC Rd,Rn,Rm,ASR #i
case 0x0E5:
return rsc(opcode, arr(opcode)); // RSC Rd,Rn,Rm,ASR Rs
case 0x0E6: case 0x0EE:
return rsc(opcode, rri(opcode)); // RSC Rd,Rn,Rm,ROR #i
case 0x0E7:
return rsc(opcode, rrr(opcode)); // RSC Rd,Rn,Rm,ROR Rs
case 0x0E9:
return smlal(opcode); // SMLAL RdLo,RdHi,Rm,Rs
case 0x0F0: case 0x0F8:
return rscs(opcode, lli(opcode)); // RSCS Rd,Rn,Rm,LSL #i
case 0x0F1:
return rscs(opcode, llr(opcode)); // RSCS Rd,Rn,Rm,LSL Rs
case 0x0F2: case 0x0FA:
return rscs(opcode, lri(opcode)); // RSCS Rd,Rn,Rm,LSR #i
case 0x0F3:
return rscs(opcode, lrr(opcode)); // RSCS Rd,Rn,Rm,LSR Rs
case 0x0F4: case 0x0FC:
return rscs(opcode, ari(opcode)); // RSCS Rd,Rn,Rm,ASR #i
case 0x0F5:
return rscs(opcode, arr(opcode)); // RSCS Rd,Rn,Rm,ASR Rs
case 0x0F6: case 0x0FE:
return rscs(opcode, rri(opcode)); // RSCS Rd,Rn,Rm,ROR #i
case 0x0F7:
return rscs(opcode, rrr(opcode)); // RSCS Rd,Rn,Rm,ROR Rs
case 0x0F9:
return smlals(opcode); // SMLALS RdLo,RdHi,Rm,Rs
case 0x100:
return mrsRc(opcode); // MRS Rd,CPSR
case 0x105:
return qadd(opcode); // QADD Rd,Rm,Rn
case 0x108:
return smlabb(opcode); // SMLABB Rd,Rm,Rs,Rn
case 0x109:
return swp(opcode); // SWP Rd,Rm,[Rn]
case 0x10A:
return smlatb(opcode); // SMLATB Rd,Rm,Rs,Rn
case 0x10B:
return strhOf(opcode, -rp(opcode)); // STRH Rd,[Rn,-Rm]
case 0x10C:
return smlabt(opcode); // SMLABT Rd,Rm,Rs,Rn
case 0x10D:
return ldrdOf(opcode, -rp(opcode)); // LDRD Rd,[Rn,-Rm]
case 0x10E:
return smlatt(opcode); // SMLATT Rd,Rm,Rs,Rn
case 0x10F:
return strdOf(opcode, -rp(opcode)); // STRD Rd,[Rn,-Rm]
case 0x110: case 0x118:
return tst(opcode, lliS(opcode)); // TST Rn,Rm,LSL #i
case 0x111:
return tst(opcode, llrS(opcode)); // TST Rn,Rm,LSL Rs
case 0x112: case 0x11A:
return tst(opcode, lriS(opcode)); // TST Rn,Rm,LSR #i
case 0x113:
return tst(opcode, lrrS(opcode)); // TST Rn,Rm,LSR Rs
case 0x114: case 0x11C:
return tst(opcode, ariS(opcode)); // TST Rn,Rm,ASR #i
case 0x115:
return tst(opcode, arrS(opcode)); // TST Rn,Rm,ASR Rs
case 0x116: case 0x11E:
return tst(opcode, rriS(opcode)); // TST Rn,Rm,ROR #i
case 0x117:
return tst(opcode, rrrS(opcode)); // TST Rn,Rm,ROR Rs
case 0x11B:
return ldrhOf(opcode, -rp(opcode)); // LDRH Rd,[Rn,-Rm]
case 0x11D:
return ldrsbOf(opcode, -rp(opcode)); // LDRSB Rd,[Rn,-Rm]
case 0x11F:
return ldrshOf(opcode, -rp(opcode)); // LDRSH Rd,[Rn,-Rm]
case 0x120:
return msrRc(opcode); // MSR CPSR,Rm
case 0x121:
return bx(opcode); // BX Rn
case 0x123:
return blxReg(opcode); // BLX Rn
case 0x125:
return qsub(opcode); // QSUB Rd,Rm,Rn
case 0x128:
return smlawb(opcode); // SMLAWB Rd,Rm,Rs,Rn
case 0x12A:
return smulwb(opcode); // SMULWB Rd,Rm,Rs
case 0x12B:
return strhPr(opcode, -rp(opcode)); // STRH Rd,[Rn,-Rm]!
case 0x12C:
return smlawt(opcode); // SMLAWT Rd,Rm,Rs,Rn
case 0x12D:
return ldrdPr(opcode, -rp(opcode)); // LDRD Rd,[Rn,-Rm]!
case 0x12E:
return smulwt(opcode); // SMULWT Rd,Rm,Rs
case 0x12F:
return strdPr(opcode, -rp(opcode)); // STRD Rd,[Rn,-Rm]!
case 0x130: case 0x138:
return teq(opcode, lliS(opcode)); // TEQ Rn,Rm,LSL #i
case 0x131:
return teq(opcode, llrS(opcode)); // TEQ Rn,Rm,LSL Rs
case 0x132: case 0x13A:
return teq(opcode, lriS(opcode)); // TEQ Rn,Rm,LSR #i
case 0x133:
return teq(opcode, lrrS(opcode)); // TEQ Rn,Rm,LSR Rs
case 0x134: case 0x13C:
return teq(opcode, ariS(opcode)); // TEQ Rn,Rm,ASR #i
case 0x135:
return teq(opcode, arrS(opcode)); // TEQ Rn,Rm,ASR Rs
case 0x136: case 0x13E:
return teq(opcode, rriS(opcode)); // TEQ Rn,Rm,ROR #i
case 0x137:
return teq(opcode, rrrS(opcode)); // TEQ Rn,Rm,ROR Rs
case 0x13B:
return ldrhPr(opcode, -rp(opcode)); // LDRH Rd,[Rn,-Rm]!
case 0x13D:
return ldrsbPr(opcode, -rp(opcode)); // LDRSB Rd,[Rn,-Rm]!
case 0x13F:
return ldrshPr(opcode, -rp(opcode)); // LDRSH Rd,[Rn,-Rm]!
case 0x140:
return mrsRs(opcode); // MRS Rd,SPSR
case 0x145:
return qdadd(opcode); // QDADD Rd,Rm,Rn
case 0x148:
return smlalbb(opcode); // SMLALBB RdLo,RdHi,Rm,Rs
case 0x149:
return swpb(opcode); // SWPB Rd,Rm,[Rn]