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Merge tag 'pull-tcg-20221220' of https://gitlab.com/rth7680/qemu into staging
Use interval trees for user-only vma mappings. Assorted cleanups to page locking. # gpg: Signature made Wed 21 Dec 2022 05:00:30 GMT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * tag 'pull-tcg-20221220' of https://gitlab.com/rth7680/qemu: accel/tcg: Restrict page_collection structure to system TB maintainance accel/tcg: Factor tb_invalidate_phys_range_fast() out accel/tcg: Rename tb_invalidate_phys_page_fast{,__locked}() accel/tcg: Remove trace events from trace-root.h accel/tcg: Restrict cpu_io_recompile() to system emulation accel/tcg: Move remainder of page locking to tb-maint.c accel/tcg: Move PageDesc tree into tb-maint.c for system accel/tcg: Use interval tree for user-only page tracking accel/tcg: Move page_{get,set}_flags to user-exec.c accel/tcg: Drop PAGE_RESERVED for CONFIG_BSD accel/tcg: Use interval tree for TARGET_PAGE_DATA_SIZE accel/tcg: Use interval tree for TBs in user-only mode accel/tcg: Rename page_flush_tb util: Add interval-tree.c Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 parents 6394578 + 8112426 commit 700ce3b

15 files changed

+2667
-1167
lines changed

‎accel/tcg/cputlb.c

+2-5
Original file line numberDiff line numberDiff line change
@@ -33,7 +33,7 @@
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#include "qemu/atomic.h"
3434
#include "qemu/atomic128.h"
3535
#include "exec/translate-all.h"
36-
#include "trace/trace-root.h"
36+
#include "trace.h"
3737
#include "tb-hash.h"
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#include "internal.h"
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#ifdef CONFIG_PLUGIN
@@ -1508,10 +1508,7 @@ static void notdirty_write(CPUState *cpu, vaddr mem_vaddr, unsigned size,
15081508
trace_memory_notdirty_write_access(mem_vaddr, ram_addr, size);
15091509

15101510
if (!cpu_physical_memory_get_dirty_flag(ram_addr, DIRTY_MEMORY_CODE)) {
1511-
struct page_collection *pages
1512-
= page_collection_lock(ram_addr, ram_addr + size);
1513-
tb_invalidate_phys_page_fast(pages, ram_addr, size, retaddr);
1514-
page_collection_unlock(pages);
1511+
tb_invalidate_phys_range_fast(ram_addr, size, retaddr);
15151512
}
15161513

15171514
/*

‎accel/tcg/internal.h

+13-68
Original file line numberDiff line numberDiff line change
@@ -23,83 +23,28 @@
2323
#define assert_memory_lock() tcg_debug_assert(have_mmap_lock())
2424
#endif
2525

26-
typedef struct PageDesc {
27-
/* list of TBs intersecting this ram page */
28-
uintptr_t first_tb;
29-
#ifdef CONFIG_USER_ONLY
30-
unsigned long flags;
31-
void *target_data;
32-
#endif
33-
#ifdef CONFIG_SOFTMMU
34-
QemuSpin lock;
26+
#if defined(CONFIG_SOFTMMU) && defined(CONFIG_DEBUG_TCG)
27+
void assert_no_pages_locked(void);
28+
#else
29+
static inline void assert_no_pages_locked(void) { }
3530
#endif
36-
} PageDesc;
37-
38-
/* Size of the L2 (and L3, etc) page tables. */
39-
#define V_L2_BITS 10
40-
#define V_L2_SIZE (1 << V_L2_BITS)
41-
42-
/*
43-
* L1 Mapping properties
44-
*/
45-
extern int v_l1_size;
46-
extern int v_l1_shift;
47-
extern int v_l2_levels;
48-
49-
/*
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* The bottom level has pointers to PageDesc, and is indexed by
51-
* anything from 4 to (V_L2_BITS + 3) bits, depending on target page size.
52-
*/
53-
#define V_L1_MIN_BITS 4
54-
#define V_L1_MAX_BITS (V_L2_BITS + 3)
55-
#define V_L1_MAX_SIZE (1 << V_L1_MAX_BITS)
56-
57-
extern void *l1_map[V_L1_MAX_SIZE];
5831

59-
PageDesc *page_find_alloc(tb_page_addr_t index, bool alloc);
60-
61-
static inline PageDesc *page_find(tb_page_addr_t index)
62-
{
63-
return page_find_alloc(index, false);
64-
}
65-
66-
/* list iterators for lists of tagged pointers in TranslationBlock */
67-
#define TB_FOR_EACH_TAGGED(head, tb, n, field) \
68-
for (n = (head) & 1, tb = (TranslationBlock *)((head) & ~1); \
69-
tb; tb = (TranslationBlock *)tb->field[n], n = (uintptr_t)tb & 1, \
70-
tb = (TranslationBlock *)((uintptr_t)tb & ~1))
71-
72-
#define PAGE_FOR_EACH_TB(pagedesc, tb, n) \
73-
TB_FOR_EACH_TAGGED((pagedesc)->first_tb, tb, n, page_next)
74-
75-
#define TB_FOR_EACH_JMP(head_tb, tb, n) \
76-
TB_FOR_EACH_TAGGED((head_tb)->jmp_list_head, tb, n, jmp_list_next)
77-
78-
/* In user-mode page locks aren't used; mmap_lock is enough */
7932
#ifdef CONFIG_USER_ONLY
80-
#define assert_page_locked(pd) tcg_debug_assert(have_mmap_lock())
81-
static inline void page_lock(PageDesc *pd) { }
82-
static inline void page_unlock(PageDesc *pd) { }
83-
#else
84-
#ifdef CONFIG_DEBUG_TCG
85-
void do_assert_page_locked(const PageDesc *pd, const char *file, int line);
86-
#define assert_page_locked(pd) do_assert_page_locked(pd, __FILE__, __LINE__)
33+
static inline void page_table_config_init(void) { }
8734
#else
88-
#define assert_page_locked(pd)
89-
#endif
90-
void page_lock(PageDesc *pd);
91-
void page_unlock(PageDesc *pd);
92-
#endif
93-
#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_DEBUG_TCG)
94-
void assert_no_pages_locked(void);
95-
#else
96-
static inline void assert_no_pages_locked(void) { }
35+
void page_table_config_init(void);
9736
#endif
9837

38+
#ifdef CONFIG_SOFTMMU
39+
void tb_invalidate_phys_range_fast(ram_addr_t ram_addr,
40+
unsigned size,
41+
uintptr_t retaddr);
42+
G_NORETURN void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr);
43+
#endif /* CONFIG_SOFTMMU */
44+
9945
TranslationBlock *tb_gen_code(CPUState *cpu, target_ulong pc,
10046
target_ulong cs_base, uint32_t flags,
10147
int cflags);
102-
G_NORETURN void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr);
10348
void page_init(void);
10449
void tb_htable_init(void);
10550
void tb_reset_jump(TranslationBlock *tb, int n);

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