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Add and update final SIMD opcodes #1621

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Add and update final SIMD opcodes #1621

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8f42f68
Add and update final SIMD opcodes
ngzhian Mar 3, 2021
cfec195
Rebase test/dump/simd-binary.txt
ngzhian Mar 3, 2021
847fc8a
Fix return type of sqrt
ngzhian Mar 3, 2021
7e84368
Rebase test/dump/simd-unary.txt
ngzhian Mar 3, 2021
c8ee8f1
Fix test/interp/simd-unary.txt for v128.any_true
ngzhian Mar 3, 2021
6d6588b
Fix test/roundtrip/fold-simd.txt
ngzhian Mar 3, 2021
a940fcc
Add new opcodes to interp/istream.cc
ngzhian Mar 3, 2021
8948b21
Update third_party/testsuite
ngzhian Mar 3, 2021
2b904e8
Rebase test/spec/simd/simd_i16x8_arith2.txt
ngzhian Mar 3, 2021
a653bf4
Update lexer keywords
ngzhian Mar 3, 2021
795b0c2
Add popcnt and int extends to binary-reader, rebase test
ngzhian Mar 3, 2021
71561c3
Add double precision conversions and rebase test
ngzhian Mar 3, 2021
29112e1
Rebase float rounding tests
ngzhian Mar 3, 2021
5a2b38c
Add i64x2.bitmask and i64x2.all_true, rebase simd_boolean
ngzhian Mar 3, 2021
9c7e31e
Update test/spec/memory64 from testsuite
ngzhian Mar 4, 2021
6203fa4
Rebase some tests in test/spec based on latest update to testsuite
ngzhian Mar 4, 2021
a15ddaf
Define global_i64 for wasm2c global tests
ngzhian Mar 4, 2021
bc56de0
Handle all unimplemented SIMD opcodes
ngzhian Mar 4, 2021
b41725d
Attempt to fix build on windows (ambiguous call to Popcount)
ngzhian Mar 4, 2021
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33 changes: 22 additions & 11 deletions src/binary-reader.cc
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Expand Up @@ -1203,15 +1203,15 @@ Result BinaryReader::ReadFunctionBody(Offset end_offset) {
case Opcode::I32X4Neg:
case Opcode::I64X2Neg:
case Opcode::V128Not:
case Opcode::I8X16AnyTrue:
case Opcode::I16X8AnyTrue:
case Opcode::I32X4AnyTrue:
case Opcode::V128AnyTrue:
case Opcode::I8X16Bitmask:
case Opcode::I16X8Bitmask:
case Opcode::I32X4Bitmask:
case Opcode::I64X2Bitmask:
case Opcode::I8X16AllTrue:
case Opcode::I16X8AllTrue:
case Opcode::I32X4AllTrue:
case Opcode::I64X2AllTrue:
case Opcode::F32X4Ceil:
case Opcode::F64X2Ceil:
case Opcode::F32X4Floor:
Expand All @@ -1226,14 +1226,19 @@ Result BinaryReader::ReadFunctionBody(Offset end_offset) {
case Opcode::F64X2Abs:
case Opcode::F32X4Sqrt:
case Opcode::F64X2Sqrt:
case Opcode::I16X8WidenLowI8X16S:
case Opcode::I16X8WidenHighI8X16S:
case Opcode::I16X8WidenLowI8X16U:
case Opcode::I16X8WidenHighI8X16U:
case Opcode::I32X4WidenLowI16X8S:
case Opcode::I32X4WidenHighI16X8S:
case Opcode::I32X4WidenLowI16X8U:
case Opcode::I32X4WidenHighI16X8U:
case Opcode::I16X8ExtendLowI8X16S:
case Opcode::I16X8ExtendHighI8X16S:
case Opcode::I16X8ExtendLowI8X16U:
case Opcode::I16X8ExtendHighI8X16U:
case Opcode::I32X4ExtendLowI16X8S:
case Opcode::I32X4ExtendHighI16X8S:
case Opcode::I32X4ExtendLowI16X8U:
case Opcode::I32X4ExtendHighI16X8U:
case Opcode::I64X2ExtendLowI32X4S:
case Opcode::I64X2ExtendHighI32X4S:
case Opcode::I64X2ExtendLowI32X4U:
case Opcode::I64X2ExtendHighI32X4U:
case Opcode::I8X16Popcnt:
case Opcode::I8X16Abs:
case Opcode::I16X8Abs:
case Opcode::I32X4Abs:
Expand Down Expand Up @@ -1319,6 +1324,12 @@ Result BinaryReader::ReadFunctionBody(Offset end_offset) {
case Opcode::F32X4ConvertI32X4U:
case Opcode::I32X4TruncSatF32X4S:
case Opcode::I32X4TruncSatF32X4U:
case Opcode::F32X4DemoteF64X2Zero:
case Opcode::F64X2PromoteLowF32X4:
case Opcode::I32X4TruncSatF64X2SZero:
case Opcode::I32X4TruncSatF64X2UZero:
case Opcode::F64X2ConvertLowI32X4S:
case Opcode::F64X2ConvertLowI32X4U:
CALLBACK(OnConvertExpr, opcode);
CALLBACK0(OnOpcodeBare);
break;
Expand Down
5 changes: 5 additions & 0 deletions src/config.h.in
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Expand Up @@ -130,6 +130,7 @@ inline int Ctz(unsigned x) { return x ? __builtin_ctz(x) : sizeof(x) * 8; }
inline int Ctz(unsigned long x) { return x ? __builtin_ctzl(x) : sizeof(x) * 8; }
inline int Ctz(unsigned long long x) { return x ? __builtin_ctzll(x) : sizeof(x) * 8; }

inline int Popcount(uint8_t x) { return __builtin_popcount(x); }
inline int Popcount(unsigned x) { return __builtin_popcount(x); }
inline int Popcount(unsigned long x) { return __builtin_popcountl(x); }
inline int Popcount(unsigned long long x) { return __builtin_popcountll(x); }
Expand Down Expand Up @@ -212,6 +213,10 @@ inline int Ctz(unsigned __int64 mask) {
#endif
}

inline int Popcount(uint8_t value) {
return __popcnt(value);
}

inline int Popcount(unsigned long value) {
return __popcnt(value);
}
Expand Down
86 changes: 75 additions & 11 deletions src/interp/interp.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -1516,9 +1516,9 @@ RunResult Thread::StepInternal(Trap::Ptr* out_trap) {
case O::V128Or: return DoSimdBinop(IntOr<u64>);
case O::V128Xor: return DoSimdBinop(IntXor<u64>);
case O::V128BitSelect: return DoSimdBitSelect();
case O::V128AnyTrue: return DoSimdIsTrue<u8x16, 1>();

case O::I8X16Neg: return DoSimdUnop(IntNeg<u8>);
case O::I8X16AnyTrue: return DoSimdIsTrue<u8x16, 1>();
case O::I8X16Bitmask: return DoSimdBitmask<s8x16>();
case O::I8X16AllTrue: return DoSimdIsTrue<u8x16, 16>();
case O::I8X16Shl: return DoSimdShift(IntShl<u8>);
Expand All @@ -1536,7 +1536,6 @@ RunResult Thread::StepInternal(Trap::Ptr* out_trap) {
case O::I8X16MaxU: return DoSimdBinop(IntMax<u8>);

case O::I16X8Neg: return DoSimdUnop(IntNeg<u16>);
case O::I16X8AnyTrue: return DoSimdIsTrue<u16x8, 1>();
case O::I16X8Bitmask: return DoSimdBitmask<s16x8>();
case O::I16X8AllTrue: return DoSimdIsTrue<u16x8, 8>();
case O::I16X8Shl: return DoSimdShift(IntShl<u16>);
Expand All @@ -1555,7 +1554,6 @@ RunResult Thread::StepInternal(Trap::Ptr* out_trap) {
case O::I16X8MaxU: return DoSimdBinop(IntMax<u16>);

case O::I32X4Neg: return DoSimdUnop(IntNeg<u32>);
case O::I32X4AnyTrue: return DoSimdIsTrue<u32x4, 1>();
case O::I32X4Bitmask: return DoSimdBitmask<s32x4>();
case O::I32X4AllTrue: return DoSimdIsTrue<u32x4, 4>();
case O::I32X4Shl: return DoSimdShift(IntShl<u32>);
Expand All @@ -1570,6 +1568,8 @@ RunResult Thread::StepInternal(Trap::Ptr* out_trap) {
case O::I32X4MaxU: return DoSimdBinop(IntMax<u32>);

case O::I64X2Neg: return DoSimdUnop(IntNeg<u64>);
case O::I64X2Bitmask: return DoSimdBitmask<s64x2>();
case O::I64X2AllTrue: return DoSimdIsTrue<u64x2, 2>();
case O::I64X2Shl: return DoSimdShift(IntShl<u64>);
case O::I64X2ShrS: return DoSimdShift(IntShr<s64>);
case O::I64X2ShrU: return DoSimdShift(IntShr<u64>);
Expand Down Expand Up @@ -1615,6 +1615,12 @@ RunResult Thread::StepInternal(Trap::Ptr* out_trap) {
case O::I32X4TruncSatF32X4U: return DoSimdUnop(IntTruncSat<u32, f32>);
case O::F32X4ConvertI32X4S: return DoSimdUnop(Convert<f32, s32>);
case O::F32X4ConvertI32X4U: return DoSimdUnop(Convert<f32, u32>);
case O::F32X4DemoteF64X2Zero: return DoSimdUnopZero(Convert<f32, f64>);
case O::F64X2PromoteLowF32X4: return DoSimdUnop(Convert<f64, f32>);
case O::I32X4TruncSatF64X2SZero: return DoSimdUnopZero(IntTruncSat<s32, f64>);
case O::I32X4TruncSatF64X2UZero: return DoSimdUnopZero(IntTruncSat<u32, f64>);
case O::F64X2ConvertLowI32X4S: return DoSimdUnop(Convert<f64, s32>);
case O::F64X2ConvertLowI32X4U: return DoSimdUnop(Convert<f64, u32>);

case O::I8X16Swizzle: return DoSimdSwizzle();
case O::I8X16Shuffle: return DoSimdShuffle(instr);
Expand All @@ -1628,14 +1634,18 @@ RunResult Thread::StepInternal(Trap::Ptr* out_trap) {
case O::I8X16NarrowI16X8U: return DoSimdNarrow<u8x16, s16x8>();
case O::I16X8NarrowI32X4S: return DoSimdNarrow<s16x8, s32x4>();
case O::I16X8NarrowI32X4U: return DoSimdNarrow<u16x8, s32x4>();
case O::I16X8WidenLowI8X16S: return DoSimdWiden<s16x8, s8x16, true>();
case O::I16X8WidenHighI8X16S: return DoSimdWiden<s16x8, s8x16, false>();
case O::I16X8WidenLowI8X16U: return DoSimdWiden<u16x8, u8x16, true>();
case O::I16X8WidenHighI8X16U: return DoSimdWiden<u16x8, u8x16, false>();
case O::I32X4WidenLowI16X8S: return DoSimdWiden<s32x4, s16x8, true>();
case O::I32X4WidenHighI16X8S: return DoSimdWiden<s32x4, s16x8, false>();
case O::I32X4WidenLowI16X8U: return DoSimdWiden<u32x4, u16x8, true>();
case O::I32X4WidenHighI16X8U: return DoSimdWiden<u32x4, u16x8, false>();
case O::I16X8ExtendLowI8X16S: return DoSimdWiden<s16x8, s8x16, true>();
case O::I16X8ExtendHighI8X16S: return DoSimdWiden<s16x8, s8x16, false>();
case O::I16X8ExtendLowI8X16U: return DoSimdWiden<u16x8, u8x16, true>();
case O::I16X8ExtendHighI8X16U: return DoSimdWiden<u16x8, u8x16, false>();
case O::I32X4ExtendLowI16X8S: return DoSimdWiden<s32x4, s16x8, true>();
case O::I32X4ExtendHighI16X8S: return DoSimdWiden<s32x4, s16x8, false>();
case O::I32X4ExtendLowI16X8U: return DoSimdWiden<u32x4, u16x8, true>();
case O::I32X4ExtendHighI16X8U: return DoSimdWiden<u32x4, u16x8, false>();
case O::I64X2ExtendLowI32X4S: return DoSimdWiden<s64x2, s32x4, true>();
case O::I64X2ExtendHighI32X4S: return DoSimdWiden<s64x2, s32x4, false>();
case O::I64X2ExtendLowI32X4U: return DoSimdWiden<u64x2, u32x4, true>();
case O::I64X2ExtendHighI32X4U: return DoSimdWiden<u64x2, u32x4, false>();

case O::V128Load8X8S: return DoSimdLoadExtend<s16x8, s8x8>(instr, out_trap);
case O::V128Load8X8U: return DoSimdLoadExtend<u16x8, u8x8>(instr, out_trap);
Expand All @@ -1652,6 +1662,8 @@ RunResult Thread::StepInternal(Trap::Ptr* out_trap) {
case O::I16X8Abs: return DoSimdUnop(IntAbs<u16>);
case O::I32X4Abs: return DoSimdUnop(IntAbs<u32>);

case O::I8X16Popcnt: return DoSimdUnop(IntPopcnt<u8>);

case O::AtomicFence:
case O::MemoryAtomicNotify:
case O::MemoryAtomicWait32:
Expand Down Expand Up @@ -1743,6 +1755,41 @@ RunResult Thread::StepInternal(Trap::Ptr* out_trap) {
case O::Rethrow:
case O::InterpData:
case O::Invalid:
case O::V128Load8Lane:
case O::V128Load16Lane:
case O::V128Load32Lane:
case O::V128Load64Lane:
case O::V128Store8Lane:
case O::V128Store16Lane:
case O::V128Store32Lane:
case O::V128Store64Lane:
case O::V128Load32Zero:
case O::V128Load64Zero:
case O::I16X8ExtaddPairwiseI8X16S:
case O::I16X8ExtaddPairwiseI8X16U:
case O::I32X4ExtaddPairwiseI16X8S:
case O::I32X4ExtaddPairwiseI16X8U:
case O::I16X8Q15mulrSatS:
case O::I16X8ExtmulLowI8X16S:
case O::I16X8ExtmulHighI8X16S:
case O::I16X8ExtmulLowI8X16U:
case O::I16X8ExtmulHighI8X16U:
case O::I32X4DotI16X8S:
case O::I32X4ExtmulLowI16X8S:
case O::I32X4ExtmulHighI16X8S:
case O::I32X4ExtmulLowI16X8U:
case O::I32X4ExtmulHighI16X8U:
case O::I64X2Abs:
case O::I64X2Eq:
case O::I64X2Ne:
case O::I64X2LtS:
case O::I64X2GtS:
case O::I64X2LeS:
case O::I64X2GeS:
case O::I64X2ExtmulLowI32X4S:
case O::I64X2ExtmulHighI32X4S:
case O::I64X2ExtmulLowI32X4U:
case O::I64X2ExtmulHighI32X4U:
WABT_UNREACHABLE;
break;
}
Expand Down Expand Up @@ -2026,6 +2073,23 @@ RunResult Thread::DoSimdUnop(UnopFunc<R, T> f) {
return RunResult::Ok;
}

template <typename R, typename T>
RunResult Thread::DoSimdUnopZero(UnopFunc<R, T> f) {
using ST = typename Simd128<T>::Type;
using SR = typename Simd128<R>::Type;
auto val = Pop<ST>();
SR result;
std::transform(std::begin(val.v), std::end(val.v), std::begin(result.v), f);
for (u8 i = 0; i < ST::lanes; ++i) {
result[i] = f(val[i]);
}
for (u8 i = ST::lanes; i < SR::lanes; ++i) {
result[i] = 0;
}
Push(result);
return RunResult::Ok;
}

template <typename R, typename T>
RunResult Thread::DoSimdBinop(BinopFunc<R, T> f) {
using ST = typename Simd128<T>::Type;
Expand Down
3 changes: 3 additions & 0 deletions src/interp/interp.h
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Expand Up @@ -1138,6 +1138,9 @@ class Thread : public Object {

template <typename R, typename T>
RunResult DoSimdUnop(UnopFunc<R, T>);
// Like DoSimdUnop but zeroes top half.
template <typename R, typename T>
RunResult DoSimdUnopZero(UnopFunc<R, T>);
template <typename R, typename T>
RunResult DoSimdBinop(BinopFunc<R, T>);
RunResult DoSimdBitSelect();
Expand Down
68 changes: 57 additions & 11 deletions src/interp/istream.cc
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Expand Up @@ -116,6 +116,7 @@ Instr Istream::Read(Offset* offset) const {
instr.kind = InstrKind::Imm_0_Op_0;
break;

case Opcode::V128AnyTrue:
case Opcode::F32Abs:
case Opcode::F32Ceil:
case Opcode::F32ConvertI32S:
Expand Down Expand Up @@ -161,14 +162,13 @@ Instr Istream::Read(Offset* offset) const {
case Opcode::F64X2Sqrt:
case Opcode::F64X2Trunc:
case Opcode::I16X8AllTrue:
case Opcode::I16X8AnyTrue:
case Opcode::I16X8Bitmask:
case Opcode::I16X8Neg:
case Opcode::I16X8Splat:
case Opcode::I16X8WidenHighI8X16S:
case Opcode::I16X8WidenHighI8X16U:
case Opcode::I16X8WidenLowI8X16S:
case Opcode::I16X8WidenLowI8X16U:
case Opcode::I16X8ExtendHighI8X16S:
case Opcode::I16X8ExtendHighI8X16U:
case Opcode::I16X8ExtendLowI8X16S:
case Opcode::I16X8ExtendLowI8X16U:
case Opcode::I32Clz:
case Opcode::I32Ctz:
case Opcode::I32Eqz:
Expand All @@ -186,16 +186,15 @@ Instr Istream::Read(Offset* offset) const {
case Opcode::I32TruncSatF64U:
case Opcode::I32WrapI64:
case Opcode::I32X4AllTrue:
case Opcode::I32X4AnyTrue:
case Opcode::I32X4Bitmask:
case Opcode::I32X4Neg:
case Opcode::I32X4Splat:
case Opcode::I32X4TruncSatF32X4S:
case Opcode::I32X4TruncSatF32X4U:
case Opcode::I32X4WidenHighI16X8S:
case Opcode::I32X4WidenHighI16X8U:
case Opcode::I32X4WidenLowI16X8S:
case Opcode::I32X4WidenLowI16X8U:
case Opcode::I32X4ExtendHighI16X8S:
case Opcode::I32X4ExtendHighI16X8U:
case Opcode::I32X4ExtendLowI16X8S:
case Opcode::I32X4ExtendLowI16X8U:
case Opcode::I64Clz:
case Opcode::I64Ctz:
case Opcode::I64Eqz:
Expand All @@ -217,7 +216,6 @@ Instr Istream::Read(Offset* offset) const {
case Opcode::I64X2Neg:
case Opcode::I64X2Splat:
case Opcode::I8X16AllTrue:
case Opcode::I8X16AnyTrue:
case Opcode::I8X16Bitmask:
case Opcode::I8X16Neg:
case Opcode::I8X16Splat:
Expand All @@ -226,6 +224,24 @@ Instr Istream::Read(Offset* offset) const {
case Opcode::I8X16Abs:
case Opcode::I16X8Abs:
case Opcode::I32X4Abs:
case Opcode::I8X16Popcnt:
case Opcode::F32X4DemoteF64X2Zero:
case Opcode::F64X2PromoteLowF32X4:
case Opcode::I16X8ExtaddPairwiseI8X16S:
case Opcode::I16X8ExtaddPairwiseI8X16U:
case Opcode::I32X4ExtaddPairwiseI16X8S:
case Opcode::I32X4ExtaddPairwiseI16X8U:
case Opcode::I64X2Abs:
case Opcode::I64X2AllTrue:
case Opcode::I64X2Bitmask:
case Opcode::I64X2ExtendLowI32X4S:
case Opcode::I64X2ExtendHighI32X4S:
case Opcode::I64X2ExtendLowI32X4U:
case Opcode::I64X2ExtendHighI32X4U:
case Opcode::I32X4TruncSatF64X2SZero:
case Opcode::I32X4TruncSatF64X2UZero:
case Opcode::F64X2ConvertLowI32X4S:
case Opcode::F64X2ConvertLowI32X4U:
// 0 immediates, 1 operand.
instr.kind = InstrKind::Imm_0_Op_1;
break;
Expand Down Expand Up @@ -419,6 +435,26 @@ Instr Istream::Read(Offset* offset) const {
case Opcode::V128Or:
case Opcode::V128Xor:
case Opcode::I8X16Swizzle:
case Opcode::I16X8Q15mulrSatS:
case Opcode::I16X8ExtmulLowI8X16S:
case Opcode::I16X8ExtmulHighI8X16S:
case Opcode::I16X8ExtmulLowI8X16U:
case Opcode::I16X8ExtmulHighI8X16U:
case Opcode::I32X4DotI16X8S:
case Opcode::I32X4ExtmulLowI16X8S:
case Opcode::I32X4ExtmulHighI16X8S:
case Opcode::I32X4ExtmulLowI16X8U:
case Opcode::I32X4ExtmulHighI16X8U:
case Opcode::I64X2Eq:
case Opcode::I64X2Ne:
case Opcode::I64X2LtS:
case Opcode::I64X2GtS:
case Opcode::I64X2LeS:
case Opcode::I64X2GeS:
case Opcode::I64X2ExtmulLowI32X4S:
case Opcode::I64X2ExtmulHighI32X4S:
case Opcode::I64X2ExtmulLowI32X4U:
case Opcode::I64X2ExtmulHighI32X4U:
// 0 immediates, 2 operands
instr.kind = InstrKind::Imm_0_Op_2;
break;
Expand Down Expand Up @@ -534,6 +570,8 @@ Instr Istream::Read(Offset* offset) const {
case Opcode::V128Load32X2U:
case Opcode::V128Load64Splat:
case Opcode::V128Load8Splat:
case Opcode::V128Load32Zero:
case Opcode::V128Load64Zero:
case Opcode::V128Load:
// Index + memory offset immediates, 1 operand.
instr.kind = InstrKind::Imm_Index_Offset_Op_1;
Expand Down Expand Up @@ -601,6 +639,14 @@ Instr Istream::Read(Offset* offset) const {
case Opcode::I64Store32:
case Opcode::I64Store8:
case Opcode::V128Store:
case Opcode::V128Load8Lane:
case Opcode::V128Load16Lane:
case Opcode::V128Load32Lane:
case Opcode::V128Load64Lane:
case Opcode::V128Store8Lane:
case Opcode::V128Store16Lane:
case Opcode::V128Store32Lane:
case Opcode::V128Store64Lane:
// Index and memory offset immediates, 2 operands.
instr.kind = InstrKind::Imm_Index_Offset_Op_2;
instr.imm_u32x2.fst = ReadAt<u32>(offset);
Expand Down
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