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WajahatRiaz/README.md

Hi! My name is Wajahat Riaz

Senior CPU Verfification Engineer | Semiconductor Industry Fellowship Alumnus

  • 👋 I’m an ingenious and devoted electronics and embedded systems engineer. I’m currently pursuing a master’s degree from the University of Engineering and Technology Lahore, specializing in SoC design and verification.
  • 👀 I'm actively seeking potential full-time, part-time, and remote roles as an IC Design and Verification Engineer to push forward my skillset.
  • 🌱 I’m also looking to collaborate on various projects related to electronics and embedded systems.
  • 💞️ I have a strong work ethic, which makes me capable of working both in a team and individually.
  • 🌍  I'm based in Lahore, Pakistan but I'm willing to relocate.
  • 📫 You can reach me out via email wajahatriazmirza@gmail.com
  • 👀 I’m interested in electronics, mircoprocessor systems (ARM Cortex-M), IoT and PCB Design.

Education

Degree Institute Location Year
Masters in Electrical Engineering University of Engineering & Technology Lahore, Pakistan August 2024
Bachelors in Electrical Engineering University of Engineering & Technology Lahore, Pakistan August 2020
Intermediate Pre-Engineering & Pre-Medical Forman Christian College Lahore, Pakistan September 2016
Matriculation Science Group Laurelbank Public School Lahore, Pakistan July 2012

Experience

Feb 2023 – Present
10xEngineers Technologies
Red Oak: CPU Verification Engineer
(Editing this section, you can peek though)
• Helped Red Oak to build an accelerating verification environment using Cloud FPGAs and paradigm-shifting tools and packages.
• Designed scalable verification environments for multicore SoC both in simulation and emulation.
• Firmware development including PCIe, OpenOCD, etc.
• Worked with the design team to verify and debug complex IPs.
• Served as the project lead for Red Oak. Oversaw entire development including design, verification, methodology and emulation.
• Closely managed the AI tools team at Red Oak to plan and build a cloud deployed generative LLM for synthesizable RTL design.
• Closely managed Clooud team at Red Oak to build new solutions for different cloud platforms.
• Helped the leadership team at Red Oak to become a part of Amazon Partner Network which was a major milestone for Red Oak.

July 2023 – Jan 2024
10xEngineers Technologies
Treaty Oak: Design Verification Engineer
Helping to build the most powerful, scalable AI accelerator on Earth by:
• Designing scalable verification environments for a complex SoC;
• Developing UVM-SV Scoreboards for self-checking regressions;
• Creating Functional Coverage metrics for effective verification;
• Formulating SystemVerilog Assertions for Formal and Simulation Environments;
• Defining and managing vPlans with Cadence vManager;
• Establishing automated regression environments;
• Collaborating with Design Engineers to debug complex test scenarios.

March 2023 – July 2023
10xEngineers Technologies
Cohort: Associate Engineer

February 2023 – March 2023
10xEngineers Technologies
Semiconductor Industry Fellowship: Graduate Intern

May 2022 – September 2022
Siemens Digital Industries Software Private Limited
Nucleus Connectivity/Kernel Team: Intern

I’m currently working as an intern at Siemens Digital Industries Software Private Limited (formerly known as Mentor Graphics) in their Nucleus Connectivity/Kernel Team. Nucleus is a Real-Time Operating System (RTOS) that enables system developers to address the complex requirements demanded by today’s advanced embedded designs. Nucleus brings kernel-rich functionality and tooling features ideal for applications where a scalable footprint, connectivity, security, power management, and deterministic performance are essential.

January 2022 – May 2022
Wateen Telecom Private Limited
Transmission Network Operations Center (NOC): Intern

Intern at Wateen Telecom Private Limited in Network Services and Strategic Department. I’m receiving training for the position of Transmission NOC Executive. My primary objectives are to understand Dense Wavelength Division Multiplexing (DWDM) and Synchronous Digital Hierarchy (SDH) technologies and their implementations on Huawei’s network management system iMaster NCE.

June 2019 – August 2019
Lahore Electric Supply Company (LESCO)
Department of Operations: Intern

Gained practical knowledge about how power stations operate. Trained to simulate electric power transmission networks in steady-state conditions as well as over time scales of a few seconds to tens of seconds by using Power System Simulator for Engineering (PSS/E) which is a high-performance transmission planning and analysis software. Gained a brief overview of GIS-based power stations which emphasized the development of smart and dependable power systems.

Relevant Skills

• Proficient in C/C++ and Assembly language.
• Experiences in hardware description and verification languages like Verilog HDL and SystemVerilog.
• Novice in Python as a scripting language.
• Familiar with ARM Cortex-M and ARM Cortex-A series of microcontrollers and development boards.
• Experience in development environments like Sourcery Codebench, Keil uVision5, STM32CubeIDE, etc.
• Strong knowledge of real-time operating systems like Nucleus and Zephyr.
• Familiar with bootloaders like U-Boot.
• Experience in developing real-time applications for connectivity protocols like UART, SPI, I2C, etc.
• Experience in basic network protocols and stacks like TCP/IP, TFTP, DHCP, STP, etc.
• Accustomed to the software development life cycle and version control via Git.
• Familiar with developing daily automated tests in Jenkins.

Soft Skills

• Adaptability
• Proactive
• Synergy
• Willingness to learn
• Strong belief in sharing
• Effective communication
• Good documentation
• Public speaking

Verify Me


I'm a PEC Registered Engineer: ELECT/85875.
Scan to verify me.

Support Me

Pinned Loading

  1. HandwrittenUrduCharacterRecognition HandwrittenUrduCharacterRecognition Public

    Handwritten Urdu Character Recognition in Machine Learning using Scikit-learn

    Python 2 2

  2. SingleLabelTextClassification SingleLabelTextClassification Public

    Text Classification techniques are necessary to find relevant information in many different tasks that deal with large quantities of information in text form.

    Python

  3. Simple-Memory-Verification Simple-Memory-Verification Public

    This repository is a simple framework for verifying a memory using SystemVerilog on QuestaSim.

    SystemVerilog 3

  4. QuadSPI QuadSPI Public

    RTL development of Quad Serial Peripheral Interface (Quad-SPI) on QuestaSim using SystemVerilog.

    SystemVerilog 18 9