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Added clock jitter
1 parent 0903721 commit fe28e26

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main_tb.sv

Lines changed: 9 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -21,11 +21,17 @@ initial begin
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end
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// external device "asynchronous" clock
24-
logic clk33;
24+
logic clk33a;
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initial begin
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#0 clk33 = 1'b0;
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#0 clk33a = 1'b0;
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forever
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#15.151 clk33 = ~clk33;
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#7 clk33a = ~clk33a;
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end
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logic clk33;
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//assign clk33 = clk33a;
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always @(*) begin
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clk33 = #($urandom_range(0, 2000)*10ps) clk33a;
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end
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logic rst;

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