controlunit.vhd

-- File: controlunit.vhd
-- Generated by MyHDL 1.0dev
-- Date: Tue Jun 28 23:51:44 2016


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;

use work.pck_myhdl_10.all;

entity controlunit is
    port (
        reset: in std_logic;
        clock: in std_logic;
        operand: in unsigned(9 downto 0);
        result: out unsigned(9 downto 0)
    );
end entity controlunit;


architecture MyHDL of controlunit is


signal sel: unsigned(1 downto 0);
signal opb: unsigned(3 downto 0);
signal opa: unsigned(3 downto 0);

procedure MYHDL3_mul(
    c: out unsigned;
    a: in unsigned;
    b: in unsigned) is
begin
    c <= (a * b);
end procedure MYHDL3_mul;

procedure MYHDL4_add(
    c: out unsigned;
    a: in unsigned;
    b: in unsigned) is
begin
    c <= (a + b);
end procedure MYHDL4_add;

procedure MYHDL5_sub(
    c: out unsigned;
    a: in unsigned;
    b: in unsigned) is
begin
    c <= (a - b);
end procedure MYHDL5_sub;

procedure MYHDL6_shift_l(
    c: out unsigned;
    a: in unsigned;
    b: in unsigned) is
begin
    c <= shift_left(a, b);
end procedure MYHDL6_shift_l;

begin





sel <= operand(10-1 downto 8);
opa <= operand(8-1 downto 4);
opb <= operand(4-1 downto 0);

CONTROLUNIT_ASSIGN2: process (clock, reset) is
begin
    if (reset = '1') then
    elsif rising_edge(clock) then
        case sel is
            when "00" =>
                MYHDL3_mul(result, opa, opb);
            when "01" =>
                MYHDL4_add(result, opa, opb);
            when "10" =>
                MYHDL5_sub(result, opa, opb);
            when "11" =>
                MYHDL6_shift_l(result, opa, opb);
            when others =>
                null;
        end case;
    end if;
end process CONTROLUNIT_ASSIGN2;

end architecture MyHDL;