100-Days-RTL-using-Verilog/037 8x1 MUX_by_2x1,4x1 at verilog · VenuPabbuleti/100-Days-RTL-using-Verilog · GitHub

Name		Name	Last commit message	Last commit date
parent directory ..
8X1MUX_BY_4X1_2X1.v		8X1MUX_BY_4X1_2X1.v
8X1MUX_TESTBENCH.v		8X1MUX_TESTBENCH.v
MUX_2X1.v		MUX_2X1.v
MUX_4X1.v		MUX_4X1.v
RTL1.JPG		RTL1.JPG
RTL2.JPG		RTL2.JPG
Simulation_Output.JPG		Simulation_Output.JPG
Simulation_Waveforms.JPG		Simulation_Waveforms.JPG