100-Days-RTL-using-Verilog/033 BCD TO BINARY at verilog · VenuPabbuleti/100-Days-RTL-using-Verilog · GitHub

Name		Name	Last commit message	Last commit date
parent directory ..
BCD_TO_BINARY.v		BCD_TO_BINARY.v
BCD_TO_BINARY_TESTBENCH.v		BCD_TO_BINARY_TESTBENCH.v
RTL.JPG		RTL.JPG
Simulation_Output.JPG		Simulation_Output.JPG
Simulation_Waveform.JPG		Simulation_Waveform.JPG
Synthesized.JPG		Synthesized.JPG