100-Days-RTL-using-Verilog/028 MULTIPLIER 2 BIT at verilog · VenuPabbuleti/100-Days-RTL-using-Verilog · GitHub

Name		Name	Last commit message	Last commit date
parent directory ..
Half_Adder.v		Half_Adder.v
Multipler_2bit.v		Multipler_2bit.v
RTL1.JPG		RTL1.JPG
RTL2.JPG		RTL2.JPG
Simulation_Output.JPG		Simulation_Output.JPG
Simulation_Waveforms.JPG		Simulation_Waveforms.JPG
Synthesis.JPG		Synthesis.JPG
multiplierr_tb.v		multiplierr_tb.v