-
Notifications
You must be signed in to change notification settings - Fork 236
/
Copy pathil.cpp
4248 lines (3811 loc) · 120 KB
/
il.cpp
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
#include <inttypes.h>
#include "il.h"
#include "lowlevelilinstruction.h"
#include "arch_x86_common_architecture.h"
using namespace BinaryNinja;
using namespace std;
static xed_reg_enum_t GetStackPointer(const size_t addrSize)
{
switch (addrSize)
{
case 2:
return XED_REG_SP;
case 4:
return XED_REG_ESP;
default:
return XED_REG_RSP;
}
}
static xed_reg_enum_t GetFramePointer(const size_t addrSize)
{
switch (addrSize)
{
case 2:
return XED_REG_BP;
case 4:
return XED_REG_EBP;
default:
return XED_REG_RBP;
}
}
static xed_reg_enum_t GetCountRegister(const size_t addrSize)
{
switch (addrSize)
{
case 2:
return XED_REG_CX;
case 4:
return XED_REG_ECX;
default:
return XED_REG_RCX;
}
}
//TODO handle imms for MPX args
// For most instructions, instruction_index == operand_index, but some instructions (floating point, some others) have an implicit first operand (st0), so we have to remap things a bit
// Instruction index represents the 'nth' argument/opcode in the instruction, whereas the operand index is index that XED holds that operand in the instruction
static size_t GetILOperandMemoryAddress(LowLevelILFunction& il, const xed_decoded_inst_t* xedd, const uint64_t addr, const size_t instruction_index, const size_t operand_index)
{
const xed_inst_t* xi = xed_decoded_inst_inst(xedd);
const xed_operand_t* op = xed_inst_operand(xi, (unsigned)operand_index);
const xed_operand_values_t* ov = xed_decoded_inst_operands_const(xedd);
const xed_operand_enum_t op_name = xed_operand_name(op);
size_t offset = BN_INVALID_EXPR;
const size_t addrSize = xed_decoded_inst_get_machine_mode_bits(xedd) / 8;
switch(op_name)
{
case XED_OPERAND_AGEN:
case XED_OPERAND_MEM0:
{
const int64_t disp = xed_decoded_inst_get_memory_displacement(xedd, 0);
// [reg] if reg != instruction_pointer
const xed_reg_enum_t base = xed_decoded_inst_get_base_reg(xedd, 0);
if ((base != XED_REG_INVALID) && !((base == XED_REG_RIP) || (base == XED_REG_EIP) || (base == XED_REG_IP)))
{
offset = il.Register(addrSize, base);
}
else if ((base == XED_REG_RIP) || (base == XED_REG_EIP) || (base == XED_REG_IP)) // Resolve RIP to a constant
{
if (xed_operand_values_has_memory_displacement(ov) && (disp != 0))
return il.Operand(instruction_index, il.ConstPointer(addrSize, disp + addr + xed_decoded_inst_get_length(xedd)));
else
return il.Operand(instruction_index, il.ConstPointer(addrSize, addr + xed_decoded_inst_get_length(xedd)));
}
// [...+reg] or [...+reg*const] or [reg*const]
const xed_reg_enum_t index = xed_decoded_inst_get_index_reg(xedd, 0);
bool constIsPointer = false;
if (index != XED_REG_INVALID)
if (!xed_decoded_inst_get_attribute(xedd, XED_ATTRIBUTE_INDEX_REG_IS_POINTER)) // MPX...TODO (extra registers)
{
const unsigned int scale = xed_decoded_inst_get_scale(xedd, 0);
if (scale != 1)
{
unsigned short shift = 0;
if (scale == 2)
shift = 1;
else if (scale == 4)
shift = 2;
else if (scale == 8)
shift = 3;
if (offset != BN_INVALID_EXPR)
offset = il.Add(addrSize,
offset,
il.ShiftLeft(addrSize,
il.Register(addrSize, index),
il.Const(1, shift)));
else
{
// case for [...+reg*const] so we know that the const must be a pointer
constIsPointer = true;
offset = il.ShiftLeft(addrSize,
il.Register(addrSize, index),
il.Const(1, shift));
}
}
else
if (offset != BN_INVALID_EXPR)
offset = il.Add(addrSize,
offset,
il.Register(addrSize, index));
else
offset = il.Register(addrSize, index);
}
// The [...+const] bit or just [const]
bool isJmpClass = (XED_ICLASS_JMP == xed_decoded_inst_get_iclass(xedd)) || constIsPointer;
if (xed_operand_values_has_memory_displacement(xed_decoded_inst_operands_const(xedd)) && (disp != 0))
{
if (offset != BN_INVALID_EXPR)
offset = il.Add(addrSize, offset, isJmpClass ? il.ConstPointer(addrSize, disp) : il.Const(addrSize, disp));
else
offset = isJmpClass ? il.ConstPointer(addrSize, disp) : il.Const(addrSize, disp);
}
else if (xed_operand_values_has_memory_displacement(xed_decoded_inst_operands_const(xedd)) && (disp == 0) && (offset == BN_INVALID_EXPR))
{
offset = isJmpClass ? il.ConstPointer(addrSize, disp) : il.Const(addrSize, disp);
}
// If there's a non-default segment in use
xed_reg_enum_t seg = xed_decoded_inst_get_seg_reg(xedd, 0);
if (seg != XED_REG_INVALID && !xed_operand_values_using_default_segment(ov, 0))
{
// Remap FS/GS to FSbase/GSbase respectively
if (seg == XED_REG_FS)
seg = XED_REG_FSBASE;
else if (seg == XED_REG_GS)
seg = XED_REG_GSBASE;
if (offset == BN_INVALID_EXPR) // The only logical path that brings us here with an invalid offset is a disp of 0
offset = il.Register(addrSize, seg);
else
offset = il.Add(addrSize, il.Register(addrSize, seg), offset);
}
break;
}
case XED_OPERAND_MEM1:
{
const xed_reg_enum_t base = xed_decoded_inst_get_base_reg(xedd, 1);
if (base != XED_REG_INVALID)
{
if ((base == XED_REG_RIP) || (base == XED_REG_EIP) || (base == XED_REG_IP))
offset = il.ConstPointer(addrSize, addr);
else
offset = il.Register(addrSize, base);
}
xed_reg_enum_t seg = xed_decoded_inst_get_seg_reg(xedd, 1);
if (seg != XED_REG_INVALID && !xed_operand_values_using_default_segment(ov, 1))
{
if (seg == XED_REG_FS)
seg = XED_REG_FSBASE;
else if (seg == XED_REG_GS)
seg = XED_REG_GSBASE;
offset = il.Add(addrSize,
il.Register(addrSize, seg),
offset);
}
break;
}
default:
LogError("%s not implemented in GetILOperandMemoryAddress at address 0x%" PRIx64 ".", xed_operand_enum_t2str(op_name), addr);
}
return il.Operand(instruction_index, offset);
}
// For most instructions, instruction_index == operand_index, but some instructions (floating point, some others) have an implicit first operand (st0), so we have to remap things a bit
// Instruction index represents the 'nth' argument/opcode in the instruction, whereas the operand index is index that XED holds that operand in the instruction
static size_t ReadILOperand(LowLevelILFunction& il, const xed_decoded_inst_t* const xedd,
const size_t addr, const size_t instruction_index,
const size_t operand_index, size_t sizeToRead = 0)
{
if (sizeToRead == 0)
sizeToRead = xed_decoded_inst_operand_length_bits(xedd, (unsigned)operand_index) / 8;
const unsigned int immediateSize = xed_decoded_inst_get_operand_width(xedd) / 8;
const int64_t relbr = xed_decoded_inst_get_branch_displacement(xedd) + addr + xed_decoded_inst_get_length(xedd);
const xed_operand_enum_t op_name = xed_operand_name(xed_inst_operand(xed_decoded_inst_inst(xedd), (unsigned)operand_index));
const auto reg1 = xed_decoded_inst_get_reg(xedd, op_name);
const size_t addrSize = xed_decoded_inst_get_machine_mode_bits(xedd) / 8;
switch (op_name)
{
// Register cases
case XED_OPERAND_REG0:
case XED_OPERAND_REG1:
case XED_OPERAND_REG2:
case XED_OPERAND_REG3:
case XED_OPERAND_REG4:
case XED_OPERAND_REG5:
case XED_OPERAND_REG6:
case XED_OPERAND_REG7:
case XED_OPERAND_REG8:
case XED_OPERAND_BASE0:
case XED_OPERAND_BASE1:
if ((reg1 == XED_REG_RIP) || (reg1 == XED_REG_EIP) || (reg1 == XED_REG_IP))
return il.Operand(instruction_index, il.ConstPointer(sizeToRead, addr));
return il.Operand(instruction_index, il.Register(sizeToRead, (uint32_t)reg1));
// Immediates:
case XED_OPERAND_IMM0:
if (xed_decoded_inst_get_immediate_is_signed(xedd))
return il.Operand(instruction_index, il.Const(immediateSize, xed_decoded_inst_get_signed_immediate(xedd)));
else
return il.Operand(instruction_index, il.Const(immediateSize, xed_decoded_inst_get_unsigned_immediate(xedd)));
// Second Immdiate Value
case XED_OPERAND_IMM1:
return il.Operand(instruction_index, il.Const(1, xed_decoded_inst_get_second_immediate(xedd)));
// Immediate Address Value
case XED_OPERAND_PTR:
case XED_OPERAND_RELBR:
return il.Operand(instruction_index, il.ConstPointer(addrSize, relbr));
// Memory Acesses
case XED_OPERAND_AGEN:
case XED_OPERAND_MEM0:
case XED_OPERAND_MEM1:
return il.Operand(instruction_index, il.Load(sizeToRead, GetILOperandMemoryAddress(il, xedd, addr, instruction_index, operand_index)));
// Not implimented or error
default:
return il.Undefined();
}
}
// For most instructions, instruction_index == operand_index, but some instructions (floating point, some others) have an implicit first operand (st0), so we have to remap things a bit
// Instruction index represents the 'nth' argument/opcode in the instruction, whereas the operand index is index that XED holds that operand in the instruction
static size_t ReadFloatILOperand(LowLevelILFunction& il, const xed_decoded_inst_t* xedd, const size_t addr, const size_t instruction_index, const size_t operand_index, size_t opLen = 10)
{
const unsigned int operandSize = xed_decoded_inst_operand_length_bits(xedd, (unsigned)operand_index) / 8;
const xed_operand_enum_t op_name = xed_operand_name(xed_inst_operand(xed_decoded_inst_inst(xedd), (unsigned)operand_index));
switch (op_name)
{
// Register cases
case XED_OPERAND_REG0:
case XED_OPERAND_REG1:
case XED_OPERAND_REG2:
case XED_OPERAND_REG3:
case XED_OPERAND_REG4:
case XED_OPERAND_REG5:
case XED_OPERAND_REG6:
case XED_OPERAND_REG7:
case XED_OPERAND_REG8:
case XED_OPERAND_BASE0:
case XED_OPERAND_BASE1:
return il.Operand(instruction_index, il.Register(operandSize, (uint32_t)xed_decoded_inst_get_reg(xedd, op_name)));
// Immediates
case XED_OPERAND_IMM0:
case XED_OPERAND_PTR:
case XED_OPERAND_RELBR:
if (xed_decoded_inst_get_immediate_is_signed(xedd))
return il.Operand(instruction_index, il.FloatConvert(opLen, il.FloatConstRaw(operandSize, xed_decoded_inst_get_signed_immediate(xedd))));
else
return il.Operand(instruction_index, il.FloatConvert(opLen, il.FloatConstRaw(operandSize, xed_decoded_inst_get_unsigned_immediate(xedd))));
case XED_OPERAND_IMM1:
return il.Operand(instruction_index, il.FloatConvert(opLen, il.FloatConstRaw(operandSize, xed_decoded_inst_get_second_immediate(xedd))));
// Memory Acesses
case XED_OPERAND_AGEN:
case XED_OPERAND_MEM0:
case XED_OPERAND_MEM1: // In what case would the memory address size be 10?? (floating point ops?)
if (operandSize != opLen)
return il.Operand(instruction_index, il.FloatConvert(opLen, il.Load(operandSize, GetILOperandMemoryAddress(il, xedd, addr, instruction_index, operand_index))));
return il.Operand(instruction_index, il.Load(opLen, GetILOperandMemoryAddress(il, xedd, addr, instruction_index, operand_index)));
default:
return il.Undefined();
}
}
// For most instructions, instruction_index == operand_index, but some instructions (floating point, some others) have an implicit first operand (st0), so we have to remap things a bit
// Instruction index represents the 'nth' argument/opcode in the instruction, whereas the operand index is index that XED holds that operand in the instruction
static size_t WriteILOperand(LowLevelILFunction& il, const xed_decoded_inst_t* const xedd, const size_t addr,
const size_t instruction_index, const size_t operand_index,
const size_t value, size_t sizeToWrite = 0)
{
// sizeToWrite allows one to specify a part of the operand to write
// other than the whole
// this solves some of the problems we have; but not all
// we still need the ability to read and write a slice of the operand
if (sizeToWrite == 0)
sizeToWrite = xed_decoded_inst_operand_length(xedd, operand_index);
const xed_operand_enum_t op_name = xed_operand_name(xed_inst_operand(xed_decoded_inst_inst(xedd), operand_index));
switch (op_name)
{
// Register cases
case XED_OPERAND_REG0:
case XED_OPERAND_REG1:
case XED_OPERAND_REG2:
case XED_OPERAND_REG3:
case XED_OPERAND_REG4:
case XED_OPERAND_REG5:
case XED_OPERAND_REG6:
case XED_OPERAND_REG7:
case XED_OPERAND_REG8:
case XED_OPERAND_BASE0:
case XED_OPERAND_BASE1:
return il.Operand(instruction_index, il.SetRegister(sizeToWrite, xed_decoded_inst_get_reg(xedd, op_name), value));
// Memory Accesses
case XED_OPERAND_AGEN:
case XED_OPERAND_MEM0:
case XED_OPERAND_MEM1:
return il.Operand(instruction_index, il.Store(sizeToWrite, GetILOperandMemoryAddress(il, xedd, addr, instruction_index, operand_index), value));
default:
return il.Undefined();
}
}
static void ConditionalJump(Architecture* arch, LowLevelILFunction& il, size_t cond, size_t addrSize, uint64_t t, uint64_t f)
{
BNLowLevelILLabel* trueLabel = il.GetLabelForAddress(arch, t);
BNLowLevelILLabel* falseLabel = il.GetLabelForAddress(arch, f);
if (trueLabel && falseLabel)
{
il.AddInstruction(il.If(cond, *trueLabel, *falseLabel));
return;
}
LowLevelILLabel trueCode, falseCode;
if (trueLabel)
{
il.AddInstruction(il.If(cond, *trueLabel, falseCode));
il.MarkLabel(falseCode);
il.AddInstruction(il.Jump(il.ConstPointer(addrSize, f)));
return;
}
if (falseLabel)
{
il.AddInstruction(il.If(cond, trueCode, *falseLabel));
il.MarkLabel(trueCode);
il.AddInstruction(il.Jump(il.ConstPointer(addrSize, t)));
return;
}
il.AddInstruction(il.If(cond, trueCode, falseCode));
il.MarkLabel(trueCode);
il.AddInstruction(il.Jump(il.ConstPointer(addrSize, t)));
il.MarkLabel(falseCode);
il.AddInstruction(il.Jump(il.ConstPointer(addrSize, f)));
}
static void DirFlagIf(LowLevelILFunction& il,
std::function<void()> addPreTestIl,
std::function<void()> addDirFlagSetIl,
std::function<void()> addDirFlagClearIl)
{
LowLevelILLabel dirFlagSet, dirFlagClear, dirFlagDone;
addPreTestIl();
il.AddInstruction(il.If(il.Flag(IL_FLAG_D), dirFlagSet, dirFlagClear));
il.MarkLabel(dirFlagSet);
addDirFlagSetIl();
il.AddInstruction(il.Goto(dirFlagDone));
il.MarkLabel(dirFlagClear);
addDirFlagClearIl();
il.AddInstruction(il.Goto(dirFlagDone));
il.MarkLabel(dirFlagDone);
}
static void Repeat(
const xed_decoded_inst_t* const xedd,
LowLevelILFunction& il,
std::function<void ()> addil)
{
const size_t addrSize = xed_decoded_inst_get_machine_mode_bits(xedd) / 8;
LowLevelILLabel trueLabel, falseLabel, doneLabel;
const xed_operand_values_t* const ov = xed_decoded_inst_operands_const(xedd);
if (xed_operand_values_has_real_rep(ov))
{
il.AddInstruction(il.Goto(trueLabel));
il.MarkLabel(trueLabel);
il.AddInstruction(il.If(
il.CompareNotEqual(addrSize,
il.Register(addrSize, GetCountRegister(addrSize)),
il.Const(addrSize, 0)), falseLabel, doneLabel));
il.MarkLabel(falseLabel);
}
addil();
if (xed_operand_values_has_real_rep(ov))
{
il.AddInstruction(
il.SetRegister(addrSize,
GetCountRegister(addrSize),
il.Sub(addrSize,
il.Register(addrSize, GetCountRegister(addrSize)),
il.Const(addrSize, 1))));
const xed_iclass_enum_t xeddiClass = xed_decoded_inst_get_iclass(xedd);
if (xed_operand_values_has_repne_prefix(ov))
il.AddInstruction(il.If(il.FlagCondition(LLFC_NE), trueLabel, doneLabel));
else if (xed_repe_map(xed_norep_map(xeddiClass)) == xeddiClass)
il.AddInstruction(il.If(il.FlagCondition(LLFC_E), trueLabel, doneLabel));
else
il.AddInstruction(il.Goto(trueLabel));
il.MarkLabel(doneLabel);
}
}
static void CMovFlagCond(const int64_t addr, const xed_decoded_inst_t* xedd, LowLevelILFunction& il, BNLowLevelILFlagCondition flag)
{
// keep the true branch but let the false branch goto doneLabel directly
LowLevelILLabel trueLabel, doneLabel;
il.AddInstruction(
il.If(
il.FlagCondition(flag),
trueLabel, doneLabel));
il.MarkLabel(trueLabel);
il.AddInstruction(
WriteILOperand(il, xedd, addr, 0, 0,
ReadILOperand(il, xedd, addr, 1, 1)));
il.AddInstruction(il.Goto(doneLabel));
il.MarkLabel(doneLabel);
}
static void CMovFlagGroup(const int64_t addr, const xed_decoded_inst_t* xedd, LowLevelILFunction& il, uint32_t flag)
{
// keep the true branch but let the false branch goto doneLabel directly
LowLevelILLabel trueLabel, doneLabel;
il.AddInstruction(
il.If(
il.FlagGroup(flag),
trueLabel, doneLabel
)
);
il.MarkLabel(trueLabel);
il.AddInstruction(
WriteILOperand(il, xedd, addr, 0, 0,
ReadILOperand(il, xedd, addr, 1, 1)));
il.AddInstruction(il.Goto(doneLabel));
il.MarkLabel(doneLabel);
}
bool GetLowLevelILForInstruction(Architecture* arch, const uint64_t addr, LowLevelILFunction& il, const xed_decoded_inst_t* const xedd)
{
LowLevelILLabel trueLabel, falseLabel, doneLabel, dirFlagSet, dirFlagClear, dirFlagDone, startLabel;
LowLevelILLabel trueLabel2, falseLabel2;
const xed_iclass_enum_t xedd_iClass = xed_decoded_inst_get_iclass(xedd);
const xed_iform_enum_t xedd_iForm = xed_decoded_inst_get_iform_enum(xedd);
const xed_inst_t* const xi = xed_decoded_inst_inst(xedd);
// const xed_operand_values_t* const ov = xed_decoded_inst_operands_const(xedd);
const unsigned short instLen = xed_decoded_inst_get_length(xedd);
// mode_bits can be used to determine whether the current instruciton is in 16/32/64 bit mode
const size_t mode_bits = xed_decoded_inst_get_machine_mode_bits(xedd);
const size_t addrSize = mode_bits / 8;
const unsigned short opOneLen = xed_decoded_inst_operand_length_bits(xedd, 0) / 8;
const unsigned short opTwoLen = xed_decoded_inst_operand_length_bits(xedd, 1) / 8;
[[maybe_unused]] const unsigned short
opTreLen = xed_decoded_inst_operand_length_bits(xedd, 2) / 8;
const xed_operand_t* const opOne = xed_inst_operand(xi, 0);
const xed_operand_t* const opTwo = xed_inst_operand(xi, 1);
// this is problematic as operand three may or may not exist at all
// latest version of xed will complain about this
const xed_operand_t* const opTre = xed_inst_operand(xi, 2);
const xed_operand_enum_t opOne_name = xed_operand_name(opOne);
const xed_operand_enum_t opTwo_name = xed_operand_name(opTwo);
const xed_operand_enum_t opTre_name = xed_operand_name(opTre);
const xed_reg_enum_t regOne = xed_decoded_inst_get_reg(xedd, opOne_name);
const xed_reg_enum_t regTwo = xed_decoded_inst_get_reg(xedd, opTwo_name);
// const xed_reg_enum_t regTre = xed_decoded_inst_get_reg(xedd, opTre_name);
// const xed_reg_enum_t baseReg1 = xed_decoded_inst_get_base_reg(xedd, 0);
// const xed_reg_enum_t baseReg2 = xed_decoded_inst_get_base_reg(xedd, 1);
const xed_reg_enum_t segReg1 = xed_decoded_inst_get_seg_reg (xedd, 0);
// const xed_reg_enum_t segReg2 = xed_decoded_inst_get_seg_reg (xedd, 1);
const uint64_t immediateOne = xed_decoded_inst_get_unsigned_immediate(xedd);
const int64_t branchDestination = xed_decoded_inst_get_branch_displacement(xedd) + addr + instLen;
auto LiftAsIntrinsic = [& il, xi, xedd, addr, xedd_iForm] () mutable {
typedef struct
{
uint32_t index;
size_t width;
} MemoryOperandWriteInfo;
vector<RegisterOrFlag> outputs = {};
vector<ExprId> parameters = {};
size_t noperands = xed_inst_noperands(xi);
vector<MemoryOperandWriteInfo> memoryOperandWrites = {};
size_t numTempRegUsed = 0;
for (uint32_t i = 0; i < noperands; i++)
{
const xed_operand_t* op = xed_inst_operand(xi, i);
xed_operand_enum_t op_name = xed_operand_name(op);
if (xed_operand_written(op))
{
switch(op_name)
{
case XED_OPERAND_REG0:
case XED_OPERAND_REG1:
case XED_OPERAND_REG2:
case XED_OPERAND_REG3:
case XED_OPERAND_REG4:
case XED_OPERAND_REG5:
case XED_OPERAND_REG6:
case XED_OPERAND_REG7:
case XED_OPERAND_REG8:
case XED_OPERAND_BASE0:
case XED_OPERAND_BASE1:
{
xed_reg_enum_t r = xed_decoded_inst_get_reg(xedd, op_name);
outputs.push_back(RegisterOrFlag::Register(r));
break;
}
default:
// The intrinsic system can only accept registers or flags as outputs,
// since it might be strange to write to an arbitrary ExprId.
// In order to handle intrinsics that write to memory, we create a temp IL register and
// later generate another il intrustion to write the register value to the memory
// An example of this is:
// vmovss dword [eax], k1, xmm0 (bytes: 6762f17e091100)
// which lifts to:
// temp0 = _mm_mask_store_ss(k1, xmm0)
// [eax.q].d = temp0.d
// Note, however, it is quite rare for an intrinsic to write to memory
size_t operandWidth = (xed_decoded_inst_operand_length_bits(xedd, i) + 7) >> 3;
memoryOperandWrites.push_back({i, operandWidth});
outputs.push_back(RegisterOrFlag::Register(LLIL_TEMP(numTempRegUsed)));
numTempRegUsed++;
break;
}
}
if (xed_operand_read(op))
{
switch(op_name)
{
case XED_OPERAND_REG0:
case XED_OPERAND_REG1:
case XED_OPERAND_REG2:
case XED_OPERAND_REG3:
case XED_OPERAND_REG4:
case XED_OPERAND_REG5:
case XED_OPERAND_REG6:
case XED_OPERAND_REG7:
case XED_OPERAND_REG8:
case XED_OPERAND_BASE0:
case XED_OPERAND_BASE1:
{
// XED includes some things that are not actual registers in
// xed_reg_enum_t. We'll just omit those special cases here.
xed_reg_enum_t r = xed_decoded_inst_get_reg(xedd, op_name);
switch(r)
{
case XED_REG_INVALID:
case XED_REG_MSRS:
case XED_REG_STACKPUSH:
case XED_REG_STACKPOP:
case XED_REG_ERROR:
case XED_REG_LAST:
continue;
default:
break;
}
}
default:
break;
}
parameters.push_back(ReadILOperand(il, xedd, addr, i, i));
}
}
X86_INTRINSIC intrinsic = (X86_INTRINSIC)(xedd_iForm + 1000);
il.AddInstruction(il.Intrinsic(outputs, intrinsic, parameters));
// Generate IL instruction for memory writes
for (size_t i = 0; i < memoryOperandWrites.size(); i++)
{
uint32_t operand = memoryOperandWrites[i].index;
size_t openradWidth = memoryOperandWrites[i].width;
il.AddInstruction(WriteILOperand(il, xedd, addr, operand, operand,
il.Register(openradWidth, LLIL_TEMP(i))));
}
};
switch (xedd_iClass)
{
case XED_ICLASS_ADC_LOCK: // TODO: Add Lock construct
case XED_ICLASS_ADC:
il.AddInstruction(
WriteILOperand(il, xedd, addr, 0, 0,
il.AddCarry(opOneLen,
ReadILOperand(il, xedd, addr, 0, 0),
ReadILOperand(il, xedd, addr, 1, 1),
il.Flag(IL_FLAG_C), IL_FLAGWRITE_ALL)));
break;
case XED_ICLASS_ADCX:
il.AddInstruction(
WriteILOperand(il, xedd, addr, 0, 0,
il.AddCarry(opOneLen,
ReadILOperand(il, xedd, addr, 0, 0),
ReadILOperand(il, xedd, addr, 1, 1),
il.Flag(IL_FLAG_C), IL_FLAG_C)));
break;
case XED_ICLASS_ADOX:
il.AddInstruction(
WriteILOperand(il, xedd, addr, 0, 0,
il.AddCarry(opOneLen,
ReadILOperand(il, xedd, addr, 0, 0),
ReadILOperand(il, xedd, addr, 1, 1),
il.Flag(IL_FLAG_O), IL_FLAG_O)));
break;
case XED_ICLASS_ADD_LOCK: // TODO: Add Lock construct
case XED_ICLASS_ADD:
il.AddInstruction(
WriteILOperand(il, xedd, addr, 0, 0,
il.Add(opOneLen,
ReadILOperand(il, xedd, addr, 0, 0),
ReadILOperand(il, xedd, addr, 1, 1),
IL_FLAGWRITE_ALL)));
break;
case XED_ICLASS_AND_LOCK: // TODO: Add Lock construct
case XED_ICLASS_AND:
il.AddInstruction(
WriteILOperand(il, xedd, addr, 0, 0,
il.And(opOneLen,
ReadILOperand(il, xedd, addr, 0, 0),
ReadILOperand(il, xedd, addr, 1, 1),
IL_FLAGWRITE_ALL)));
break;
case XED_ICLASS_PAND:
il.AddInstruction(
WriteILOperand(il, xedd, addr, 0, 0,
il.And(opOneLen,
ReadILOperand(il, xedd, addr, 0, 0),
ReadILOperand(il, xedd, addr, 1, 1),
0))); // PAND doesn't modify any flag.
break;
case XED_ICLASS_VPAND:
il.AddInstruction(
WriteILOperand(il, xedd, addr, 0, 0,
il.And(opOneLen,
ReadILOperand(il, xedd, addr, 1, 1),
ReadILOperand(il, xedd, addr, 2, 2),
0))); // VPAND doesn't modify any flag
break;
case XED_ICLASS_ANDN:
il.AddInstruction(
WriteILOperand(il, xedd, addr, 0, 0,
il.And(opOneLen,
ReadILOperand(il, xedd, addr, 0, 0),
il.Not(
opTwoLen,
ReadILOperand(il, xedd, addr, 1, 1)
),
IL_FLAGWRITE_ALL)));
break;
case XED_ICLASS_PANDN:
il.AddInstruction(
WriteILOperand(il, xedd, addr, 0, 0,
il.And(opOneLen,
ReadILOperand(il, xedd, addr, 0, 0),
il.Not(
opTwoLen,
ReadILOperand(il, xedd, addr, 1, 1)
),
0))); // Does not affect flags
break;
case XED_ICLASS_VPANDN:
il.AddInstruction(
WriteILOperand(il, xedd, addr, 0, 0,
il.And(opOneLen,
ReadILOperand(il, xedd, addr, 1, 1),
il.Not(
opTwoLen,
ReadILOperand(il, xedd, addr, 2, 2)
),
IL_FLAGWRITE_ALL)));
break;
case XED_ICLASS_BT:
il.AddInstruction(il.SetFlag(IL_FLAG_C,
il.TestBit(opOneLen,
ReadILOperand(il, xedd, addr, 0, 0),
ReadILOperand(il, xedd, addr, 1, 1))));
break;
case XED_ICLASS_BTC_LOCK:
case XED_ICLASS_BTC:
// TODO: Handle lock prefix
il.AddInstruction(il.SetFlag(IL_FLAG_C,
il.TestBit(opOneLen,
ReadILOperand(il, xedd, addr, 0, 0),
ReadILOperand(il, xedd, addr, 1, 1))));
// Complement the bit specified by operand[1] in operand[0]
// operand[0] = operand[0] ^ (1 << operand[1])
// or in the case operand[1] is a register
// operand[0] = operand[0] ^ (1 << (operand[1] % operand[0].size))
if (opTwo_name == XED_OPERAND_IMM0)
{
il.AddInstruction(WriteILOperand(il, xedd, addr, 0, 0,
il.Xor(opOneLen,
ReadILOperand(il, xedd, addr, 0, 0),
il.ShiftLeft(opOneLen,
il.Const(opOneLen, 1),
ReadILOperand(il, xedd, addr, 1, 1)))));
}
else
{
il.AddInstruction(WriteILOperand(il, xedd, addr, 0, 0,
il.Xor(opOneLen,
ReadILOperand(il, xedd, addr, 0, 0),
il.ShiftLeft(opOneLen,
il.Const(opOneLen, 1),
il.ModUnsigned(opTwoLen,
ReadILOperand(il, xedd, addr, 1, 1),
il.Const(1, opOneLen * 8))))));
}
break;
case XED_ICLASS_BTR_LOCK:
case XED_ICLASS_BTR:
// TODO: Handle lock prefix
il.AddInstruction(il.SetFlag(IL_FLAG_C,
il.TestBit(opOneLen,
ReadILOperand(il, xedd, addr, 0, 0),
ReadILOperand(il, xedd, addr, 1, 1))));
// Reset the bit specified by operand[1] in operand[0]
// operand[0] = operand[0] & ~(1 << operand[1])
// or in the case operand[1] is a register
// operand[0] = operand[0] & ~(1 << (operand[1] % operand[0].size))
il.AddInstruction(WriteILOperand(il, xedd, addr, 0, 0,
il.And(opOneLen,
ReadILOperand(il, xedd, addr, 0, 0),
il.Not(opOneLen,
il.ShiftLeft(opOneLen,
il.Const(opOneLen, 1),
(opTwo_name == XED_OPERAND_IMM0) ?
ReadILOperand(il, xedd, addr, 1, 1) :
il.ModUnsigned(opTwoLen,
ReadILOperand(il, xedd, addr, 1, 1),
il.Const(1, opOneLen * 8)))))));
break;
case XED_ICLASS_BTS_LOCK:
case XED_ICLASS_BTS:
// TODO: Handle lock prefix
il.AddInstruction(il.SetFlag(IL_FLAG_C,
il.TestBit(opOneLen,
ReadILOperand(il, xedd, addr, 0, 0),
ReadILOperand(il, xedd, addr, 1, 1))));
// Complement the bit specified by operand[1] in operand[0]
// operand[0] = operand[0] | (1 << operand[1])
// or in the case operand[1] is a register
// operand[0] = operand[0] | (1 << (operand[1] % operand[0].size))
il.AddInstruction(WriteILOperand(il, xedd, addr, 0, 0,
il.Or(opOneLen,
ReadILOperand(il, xedd, addr, 0, 0),
il.ShiftLeft(opOneLen,
il.Const(opOneLen, 1),
(opTwo_name == XED_OPERAND_IMM0) ?
ReadILOperand(il, xedd, addr, 1, 1) :
il.ModUnsigned(opTwoLen,
ReadILOperand(il, xedd, addr, 1, 1),
il.Const(1, opOneLen * 8))))));
break;
case XED_ICLASS_ADDSS:
{
il.AddInstruction(WriteILOperand(il, xedd, addr, 0, 0,
il.FloatAdd(4,
ReadFloatILOperand(il, xedd, addr, 0, 0, 4),
ReadFloatILOperand(il, xedd, addr, 1, 1, 4)
)));
break;
}
case XED_ICLASS_VADDSS:
{
if (xed_classify_avx512(xedd))
{
LiftAsIntrinsic();
break;
}
il.AddInstruction(WriteILOperand(il, xedd, addr, 0, 0,
il.FloatAdd(4,
ReadFloatILOperand(il, xedd, addr, 1, 1, 4),
ReadFloatILOperand(il, xedd, addr, 2, 2, 4)
)));
break;
}
case XED_ICLASS_ADDSD:
{
il.AddInstruction(WriteILOperand(il, xedd, addr, 0, 0,
il.FloatAdd(8,
ReadFloatILOperand(il, xedd, addr, 0, 0, 8),
ReadFloatILOperand(il, xedd, addr, 1, 1, 8)
)));
break;
}
case XED_ICLASS_VADDSD:
{
if (xed_classify_avx512(xedd))
{
LiftAsIntrinsic();
break;
}
il.AddInstruction(WriteILOperand(il, xedd, addr, 0, 0,
il.FloatAdd(8,
ReadFloatILOperand(il, xedd, addr, 1, 1, 8),
ReadFloatILOperand(il, xedd, addr, 2, 2, 8)
)));
break;
}
case XED_ICLASS_SUBSS:
{
il.AddInstruction(WriteILOperand(il, xedd, addr, 0, 0,
il.FloatSub(4,
ReadFloatILOperand(il, xedd, addr, 0, 0, 4),
ReadFloatILOperand(il, xedd, addr, 1, 1, 4)
)));
break;
}
case XED_ICLASS_VSUBSS:
{
if (xed_classify_avx512(xedd))
{
LiftAsIntrinsic();
break;
}
il.AddInstruction(WriteILOperand(il, xedd, addr, 0, 0,
il.FloatSub(4,
ReadFloatILOperand(il, xedd, addr, 1, 1, 4),
ReadFloatILOperand(il, xedd, addr, 2, 2, 4)
)));
break;
}
case XED_ICLASS_SUBSD:
{
il.AddInstruction(WriteILOperand(il, xedd, addr, 0, 0,
il.FloatSub(8,
ReadFloatILOperand(il, xedd, addr, 0, 0, 8),
ReadFloatILOperand(il, xedd, addr, 1, 1, 8)
)));
break;
}
case XED_ICLASS_VSUBSD:
{
if (xed_classify_avx512(xedd))
{
LiftAsIntrinsic();
break;
}
il.AddInstruction(WriteILOperand(il, xedd, addr, 0, 0,
il.FloatSub(8,
ReadFloatILOperand(il, xedd, addr, 1, 1, 8),
ReadFloatILOperand(il, xedd, addr, 2, 2, 8
)))
);
break;
}
case XED_ICLASS_MULSS:
{
il.AddInstruction(WriteILOperand(il, xedd, addr, 0, 0,
il.FloatMult(4,
ReadFloatILOperand(il, xedd, addr, 0, 0, 4),
ReadFloatILOperand(il, xedd, addr, 1, 1, 4)
)));
break;
}
case XED_ICLASS_VMULSS:
{
if (xed_classify_avx512(xedd))
{
LiftAsIntrinsic();
break;
}
il.AddInstruction(WriteILOperand(il, xedd, addr, 0, 0,
il.FloatMult(4,
ReadFloatILOperand(il, xedd, addr, 1, 1, 4),
ReadFloatILOperand(il, xedd, addr, 2, 2, 4)
)));
break;
}
case XED_ICLASS_MULSD:
{
il.AddInstruction(WriteILOperand(il, xedd, addr, 0, 0,
il.FloatMult(8,
ReadFloatILOperand(il, xedd, addr, 0, 0, 8),
ReadFloatILOperand(il, xedd, addr, 1, 1, 8)
)));
break;
}
case XED_ICLASS_VMULSD:
{
if (xed_classify_avx512(xedd))
{
LiftAsIntrinsic();
break;
}
il.AddInstruction(WriteILOperand(il, xedd, addr, 0, 0,
il.FloatMult(8,
ReadFloatILOperand(il, xedd, addr, 1, 1, 8),
ReadFloatILOperand(il, xedd, addr, 2, 2, 8)
)));
break;
}
case XED_ICLASS_DIVSS:
{
il.AddInstruction(WriteILOperand(il, xedd, addr, 0, 0,
il.FloatDiv(4,
ReadFloatILOperand(il, xedd, addr, 0, 0, 4),
ReadFloatILOperand(il, xedd, addr, 1, 1, 4)
)));
break;
}
case XED_ICLASS_VDIVSS:
{
if (xed_classify_avx512(xedd))
{
LiftAsIntrinsic();
break;
}
il.AddInstruction(WriteILOperand(il, xedd, addr, 0, 0,
il.FloatDiv(4,
ReadFloatILOperand(il, xedd, addr, 1, 1, 4),
ReadFloatILOperand(il, xedd, addr, 2, 2, 4)
)));
break;