This repository contains a collection of Verilog-based digital design projects, ranging from fundamental logic gates to complex hardware modules. Ideal for learning RTL design, synthesis, and FPGA implementation.

Projects Included
✔️ Basic Logic Gates
✔️ Multiplexers & Demultiplexers
✔️ Flip-Flops & Registers
✔️ ALU (Arithmetic Logic Unit)
✔️ FSM (Finite State Machines)
✔️ Memory Modules & More!

🔹 Tools Used: Icarus Verilog, ModelSim, Xilinx Vivado, GTKWave
🔹 For Beginners & Enthusiasts

💡 Contributions are welcome!