From 90902d3d5cf1ff6109f3fffd2be150b23300b8aa Mon Sep 17 00:00:00 2001 From: Lars Asplund Date: Sun, 17 Nov 2024 20:42:22 +0100 Subject: [PATCH] Updated run script to emulate support for post-simulation Visualizer --- examples/vhdl/three_step_flow/run.py | 57 +++++++++++++++++-- .../vhdl/three_step_flow/sub_module/tb_a.vhd | 21 ++++--- examples/vhdl/three_step_flow/tb_b.vhd | 21 ++++--- examples/vhdl/three_step_flow/tb_example.vhd | 22 ++++--- 4 files changed, 86 insertions(+), 35 deletions(-) diff --git a/examples/vhdl/three_step_flow/run.py b/examples/vhdl/three_step_flow/run.py index 63d62ec65..51e4b28c8 100644 --- a/examples/vhdl/three_step_flow/run.py +++ b/examples/vhdl/three_step_flow/run.py @@ -8,19 +8,56 @@ from pathlib import Path from vunit import VUnit, VUnitCLI from os import environ +from subprocess import run import logging logging.basicConfig( level=logging.DEBUG, format="%(asctime)s.%(msecs)03d - %(levelname)7s - %(message)s", datefmt="%H:%M:%S" ) -cli = VUnitCLI() - environ["VUNIT_SIMULATOR"] = "modelsim" -vu = VUnit.from_argv() +cli = VUnitCLI() +args = cli.parse_args() +gui = args.gui +args.gui = False +vu = VUnit.from_args(args=args) vu.add_vhdl_builtins() + +# Support functions for setting up post-simulation Visualizer +def fix_path(path): + return str(path).replace("\\", "/").replace(" ", "\\ ") + + +def save_design_file(obj, design_file_path): + obj.set_sim_option("modelsim.vopt_flags", ["-debug", "-designfile", fix_path(design_file_path)]) + + +def save_db_sim_option(db_file_path): + return {"modelsim.vsim_flags": [f"-qwavedb=+signal+memory+wavefile={fix_path(db_file_path)}"]} + + +def save_db(obj, db_file_path): + sim_option = save_db_sim_option(db_file_path) + obj.set_sim_option("modelsim.vsim_flags", sim_option["modelsim.vsim_flags"]) + + +def post_check(design_file_path, db_file_path): + def func(output_path): + run(["visualizer", "-designfile", fix_path(design_file_path), "-wavefile", fix_path(db_file_path)]) + + return True + + return func + + +def setup_visualizer(obj, design_file_path, db_file_path): + save_design_file(obj, design_file_path) + save_db(obj, db_file_path) + obj.set_post_check(post_check(design_file_path, db_file_path)) + + root = Path(__file__).parent lib1 = vu.add_library("lib1") @@ -29,11 +66,23 @@ lib2 = vu.add_library("lib2") lib2.add_source_files(root / "*.vhd") +if gui: + setup_visualizer(lib1.test_bench("tb_a"), root / "lib1.tb_a.bin", root / "lib1.tb_a.db") + setup_visualizer(lib2.test_bench("tb_b"), root / "lib2.tb_b.bin", root / "lib2.tb_b.db") + tb = lib2.test_bench("tb_example") +design_file_path = root / "lib2.tb_example.bin" +save_design_file(tb, design_file_path) test = tb.test("test") for value in range(5): - test.add_config(name=f"{value}", generics=dict(value=value)) + db_file_path = root / f"lib2.tb_example.{value}.test.db" + test.add_config( + name=f"{value}", + generics=dict(value=value), + sim_options=save_db_sim_option(db_file_path) if gui else None, + post_check=post_check(design_file_path, db_file_path) if gui else None, + ) vu.set_sim_option("modelsim.three_step_flow", True) diff --git a/examples/vhdl/three_step_flow/sub_module/tb_a.vhd b/examples/vhdl/three_step_flow/sub_module/tb_a.vhd index b4f0748c8..5425a3ade 100644 --- a/examples/vhdl/three_step_flow/sub_module/tb_a.vhd +++ b/examples/vhdl/three_step_flow/sub_module/tb_a.vhd @@ -13,23 +13,22 @@ entity tb_a is end entity; architecture tb of tb_a is + signal clk : bit; + signal message : string(1 to 7); begin main : process - function recurse(value : integer) return integer is - begin - if value <= 0 then - return 0; - elsif value mod 2 = 0 then - return 1 + recurse(value - 1); - else - return recurse(value - 1); - end if; - end; begin test_runner_setup(runner, runner_cfg); - info("Running tb_a: " & to_string(recurse(17))); + info("Running tb_a"); + + message <= "Running"; + wait until rising_edge(clk); + message <= "tb_a "; + wait until rising_edge(clk); test_runner_cleanup(runner); end process; + + clk <= not clk after 100 ns; end architecture; diff --git a/examples/vhdl/three_step_flow/tb_b.vhd b/examples/vhdl/three_step_flow/tb_b.vhd index 61bd84976..cdc85134c 100644 --- a/examples/vhdl/three_step_flow/tb_b.vhd +++ b/examples/vhdl/three_step_flow/tb_b.vhd @@ -13,23 +13,22 @@ entity tb_b is end entity; architecture tb of tb_b is + signal clk : bit; + signal message : string(1 to 7); begin main : process - function recurse(value : integer) return integer is - begin - if value <= 0 then - return 0; - elsif value mod 2 = 0 then - return 1 + recurse(value - 1); - else - return recurse(value - 1); - end if; - end; begin test_runner_setup(runner, runner_cfg); - info("Running tb_b: " & to_string(recurse(17))); + info("Running tb_b"); + + message <= "Running"; + wait until rising_edge(clk); + message <= "tb_b "; + wait until rising_edge(clk); test_runner_cleanup(runner); end process; + + clk <= not clk after 100 ns; end architecture; diff --git a/examples/vhdl/three_step_flow/tb_example.vhd b/examples/vhdl/three_step_flow/tb_example.vhd index eda9eae57..a68fab5da 100644 --- a/examples/vhdl/three_step_flow/tb_example.vhd +++ b/examples/vhdl/three_step_flow/tb_example.vhd @@ -14,16 +14,10 @@ entity tb_example is end entity; architecture tb of tb_example is + signal clk : bit; + signal message : string(1 to 7); begin main : process - function recurse(value : integer) return integer is - begin - if value <= 0 then - return 0; - else - return 1 + recurse(value - 1); - end if; - end; begin test_runner_setup(runner, runner_cfg); @@ -32,9 +26,19 @@ begin end if; info("Running " & running_test_case & " with generic value = " & to_string(value)); - info("Recurse = " & to_string(recurse(value))); + + message <= "Running"; + wait until rising_edge(clk); + message <= "test "; + wait until rising_edge(clk); + message(1 to 1) <= to_string(value); + message(2 to 7) <= " "; + wait until rising_edge(clk); + end loop; test_runner_cleanup(runner); end process; + + clk <= not clk after 100 ns; end architecture;