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Add SystemVerilog support using Google's Verible project #294

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mithro opened this issue Jun 11, 2021 · 0 comments

mithro commented Jun 11, 2021

Beautifier Details
Name: Verible
Link to project/homepage: https://github.com/google/verible and https://google.github.io/verible/verilog_format.html

If this is a new beautifier, please fill out the below
Languages Supported: SystemVerilog
How is it run (node, terminal, etc): terminal

If this is to update an existing beautifier, please describe what should be updated

Additional context

Verible is a parser for creating developer tooling for the SystemVerilog language. It also includes a number of tools like linters and autoformatters. See https://google.github.io/verible/verilog_format.html

mithro mentioned this issue

Add verible formatter to unibeautify chipsalliance/verible#856

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