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Password for ECAD archives

Status: Open.

#116 In Time-Appliances-Project/Time-Card;

· SiwaNetwork opened on Jan 6, 2025

GPS module UART baud mismatch in code and TimeCard on sale?

Status: Open.

#113 In Time-Appliances-Project/Time-Card;

· regymm opened on Oct 6, 2024

R6 Placement Interferes with Y3 (Abracon AOCJYR) on OCXO Daughter Card

Status: Open.

#108 In Time-Appliances-Project/Time-Card;

· skear opened on May 29, 2024

OCXO Daughter Card V4 - Silkscreen Designator Mismatch for R8 and R33

Status: Open.

#107 In Time-Appliances-Project/Time-Card;

· skear opened on May 23, 2024

Connecting 1PPS and 10MHz outputs with 50 Ohm termination to another TimeCard 1PPS and 10MHz inputs

Status: Open.

#105 In Time-Appliances-Project/Time-Card;

· vlvassilev opened on Mar 15, 2024

Should the version numbers in the CoreList be the same as the version registers?

Status: Open.

#104 In Time-Appliances-Project/Time-Card;

· JohnHay opened on Nov 18, 2023

Time Card PCB queries from PCBway regarding vias in pad.

Status: Open.

#96 In Time-Appliances-Project/Time-Card;

· ghost opened on Jul 28, 2023

Production Timecard: mismatch between board and FPGA PCIe lane counts

Status: Open.

#92 In Time-Appliances-Project/Time-Card;

· wisxxx opened on Mar 7, 2023

SMA TVS not connected to +3.3V

Status: Open.

#91 In Time-Appliances-Project/Time-Card;

· wisxxx opened on Mar 5, 2023

Production Timecard: bad termination on FPGA JTAG with USB

Status: Open.

#90 In Time-Appliances-Project/Time-Card;

· wisxxx opened on Mar 1, 2023

SA45 osc daughtercard does not bring out LOCK signal

Status: Open.

#88 In Time-Appliances-Project/Time-Card;

· wisxxx opened on Feb 2, 2023

LOF (ver 0.1) mechanical drawing is incomplete

Status: Open.

#87 In Time-Appliances-Project/Time-Card;

· wisxxx opened on Jan 30, 2023