-
Notifications
You must be signed in to change notification settings - Fork 2
/
ucode.c
2075 lines (1772 loc) · 71.7 KB
/
ucode.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/***********************************************************************************************************************
*
* 6502 / 65C02 Microcode
*
* by Thuffir
*
* This is free and unencumbered software released into the public domain.
*
* Anyone is free to copy, modify, publish, use, compile, sell, or
* distribute this software, either in source code form or as a compiled
* binary, for any purpose, commercial or non-commercial, and by any
* means.
*
* In jurisdictions that recognize copyright laws, the author or authors
* of this software dedicate any and all copyright interest in the
* software to the public domain. We make this dedication for the benefit
* of the public at large and to the detriment of our heirs and
* successors. We intend this dedication to be an overt act of
* relinquishment in perpetuity of all present and future rights to this
* software under copyright law.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* For more information, please refer to <http://unlicense.org/>
*
**********************************************************************************************************************/
#include <stdint.h>
#include <stdio.h>
#include <string.h>
/***********************************************************************************************************************
* Control logic input and output signals
**********************************************************************************************************************/
// Source select (4 bits)
#define SRC_POS 0
#define OE_PCL ( 1 << SRC_POS)
#define OE_PCH ( 2 << SRC_POS)
#define OE_ADDRL ( 3 << SRC_POS)
#define OE_ADDRH ( 4 << SRC_POS)
#define OE_RAM ( 5 << SRC_POS)
#define OE_ACC ( 6 << SRC_POS)
#define OE_X ( 7 << SRC_POS)
#define OE_Y ( 8 << SRC_POS)
#define OE_SP ( 9 << SRC_POS)
#define OE_ALU_A (10 << SRC_POS)
#define OE_ALU_B (11 << SRC_POS)
#define OE_FLAGS (12 << SRC_POS)
#define OE_ALU (13 << SRC_POS)
#define OE_CONST (14 << SRC_POS)
// Destination select (4 bits)
#define DST_POS 4
#define WR_PCL ( 1 << DST_POS)
#define WR_PCH ( 2 << DST_POS)
#define WR_ADDRL ( 3 << DST_POS)
#define WR_ADDRH ( 4 << DST_POS)
#define WR_RAM ( 5 << DST_POS)
#define WR_ACC ( 6 << DST_POS)
#define WR_X ( 7 << DST_POS)
#define WR_Y ( 8 << DST_POS)
#define WR_SP ( 9 << DST_POS)
#define WR_ALU_A (10 << DST_POS)
#define WR_ALU_B (11 << DST_POS)
#define WR_FLAGS (12 << DST_POS)
#define WR_INST (13 << DST_POS)
// ALU operations (4 Bits, shared input with constant register input)
#define ALU_POS 8
#define ALU_ADD ( 0 << ALU_POS) // Binary add
#define ALU_SUB ( 1 << ALU_POS) // Binary subtract
#define ALU_DADD ( 2 << ALU_POS) // Binary or BCD add
#define ALU_DSUB ( 3 << ALU_POS) // Binary or BCD subtract
#define ALU_AND ( 4 << ALU_POS) // ALU AND
#define ALU_OR ( 5 << ALU_POS) // ALU OR
#define ALU_XOR ( 6 << ALU_POS) // ALU XOR
#define ALU_SHR ( 7 << ALU_POS) // ALU Shift Right
#define ALU_CLRBIT ( 8 << ALU_POS) // ALU Clear Bit
#define ALU_SETBIT ( 9 << ALU_POS) // ALU Set Bit
#define ALU_TSTBIT (10 << ALU_POS) // ALU Test Bit
#define ALU_INVA (11 << ALU_POS) // ALU Invert A
// Constant register output (4 Bits, shared input with ALU operation)
#define CONST_POS 8
#define CONST_0 ( 0 << CONST_POS)
#define CONST_1 ( 1 << CONST_POS)
#define CONST_2 ( 2 << CONST_POS)
#define CONST_3 ( 3 << CONST_POS)
#define CONST_4 ( 4 << CONST_POS)
#define CONST_5 ( 5 << CONST_POS)
#define CONST_6 ( 6 << CONST_POS)
#define CONST_7 ( 7 << CONST_POS)
#define CONST_F8 ( 8 << CONST_POS)
#define CONST_F9 ( 9 << CONST_POS)
#define CONST_FA (10 << CONST_POS)
#define CONST_FB (11 << CONST_POS)
#define CONST_FC (12 << CONST_POS)
#define CONST_FD (13 << CONST_POS)
#define CONST_FE (14 << CONST_POS)
#define CONST_FF (15 << CONST_POS)
// Break opcode as constant for interrupt opcode injection
#define CONST_BRK (CONST_0)
// Flags input to uCode ROM (4 bits)
#define FLAGIN_POS 12
#define FLAGIN_C ( 0 << FLAGIN_POS) // Carry flag
#define FLAGIN_Z ( 1 << FLAGIN_POS) // Zero flag
#define FLAGIN_V ( 2 << FLAGIN_POS) // Overflow flag
#define FLAGIN_N ( 3 << FLAGIN_POS) // Negative flag
#define FLAGIN_CALU ( 4 << FLAGIN_POS) // Carry of the last ALU output
#define FLAGIN_NB ( 5 << FLAGIN_POS) // Actual sign bit of the B register
#define FLAGIN_INTR ( 6 << FLAGIN_POS) // Signal for all interrupts (INT, NMI, RST)
#define FLAGIN_NMI ( 7 << FLAGIN_POS) // NMI
#define FLAGIN_RST ( 8 << FLAGIN_POS) // Reset
#define FLAGIN_WAK ( 9 << FLAGIN_POS) // Wake-up
#define FLAGIN_ALOV (10 << FLAGIN_POS) // ADDRL overflow signal
#define FLAGIN_ZALU (11 << FLAGIN_POS) // Zero of the last ALU output
// Address output select (2 bits)
#define SELADDR_POS 16
#define ADDR_PC ( 0 << SELADDR_POS) // Address is driven by the PC registers
#define ADDR_FULL ( 1 << SELADDR_POS) // Address is driven by the ADDR registers
#define ADDR_ZP ( 2 << SELADDR_POS) // Address is driven by ADDRL in ZERO page
#define ADDR_SP ( 3 << SELADDR_POS) // Address is driven by the SP register in the stack page
// Other signals
#define CI_ALU ( 1 << 18) // ALU Carry Input
#define INC_PC ( 1 << 19) // PC register increment enable
#define RST_USTEP ( 1 << 20) // End of uSteps, reset uStep counter
#define UPD_C ( 1 << 21) // Update the Carry flag in the PS register
#define UPD_Z ( 1 << 22) // Update the Zero flag in the PS register
#define UPD_I ( 1 << 23) // Update the Interrupt Disable flag in the PS register
#define UPD_D ( 1 << 24) // Update the Decimal flag in the PS register
#define UPD_V ( 1 << 25) // Update the Overflow flag in the PS register
#define UPD_N ( 1 << 26) // Update the Negative flag in the PS register
#define INC_ADDRL ( 1 << 27) // ADDRL register increment enable
#define INC_ADDRH ( 1 << 28) // ADDRH register increment enable
#define CNT_SP ( 1 << 29) // SP register increment or decrement enable
#define DIR_SP ( 1 << 30) // SP register increment (0) or decrement (1)
#define INT_HOLD ( 1 << 31) // Hold the interrupt signals so they do not change
// Update Negative and Zero flags
#define UPD_NZ (UPD_N | UPD_Z)
// SP Operations
#define DEC_SP (CNT_SP | DIR_SP) // Decrement SP
#define INC_SP (CNT_SP) // Increment SP
// uCode ROM input bit positions
#define ROM_USTEP_POS 0 // uStep counter position (4 bits)
#define ROM_INSTR_POS 4 // Opcode position (8 bits)
#define ROM_FLAGS_POS 12 // Multiplexed flags input (1 bit)
// Max numbers
#define INSTR_MAX ( 1 << (ROM_FLAGS_POS - ROM_INSTR_POS)) // Number of maximum opcodes (256)
#define USTEP_MAX ( 1 << (ROM_INSTR_POS - ROM_USTEP_POS)) // Number of maximum uSteps (16)
#define UCODE_SIZE ( 1 << (ROM_FLAGS_POS + 1)) // Size of the uCode ROM (8k * 32 bits)
// Type of the uCode variable, make sure it can hold all signals
typedef uint32_t UcodeType;
// Opcode nmemonics as strings
char *instr[INSTR_MAX];
// Number of uSteps used for a specific opcode
uint8_t uStep[INSTR_MAX];
// uCode rom content
UcodeType rom[UCODE_SIZE];
// Define an opcode and begin the first uStep
#define USTEP_DEFINE(inst) { \
unsigned int _inst = (inst); \
uStep[_inst] = 1; \
instr[inst] = #inst
// Set an uStep for one flag input position
#define USTEP_FLAG_STEP(flag, ucode) \
rom[((flag) << ROM_FLAGS_POS) | (_inst << ROM_INSTR_POS) | (uStep[_inst] << ROM_USTEP_POS)] = (ucode)
// Set different uSteps for both flag input positions
#define USTEP_FLAG(ucodeFlagZero, ucodeFlagOne) \
USTEP_FLAG_STEP(0, ucodeFlagZero); \
USTEP_FLAG_STEP(1, ucodeFlagOne); \
uStep[_inst]++
// Set the same uStep for both flag input positions
#define USTEP_STEP(ucode) USTEP_FLAG(ucode, ucode)
// Last uStep (sets RST_USTEP)
#define USTEP_LAST(ucode) USTEP_STEP((ucode) | RST_USTEP); }
// Last uSteps for different flag input positions (sets RST_USTEP)
#define USTEP_FLST(ucodeFlagZero, ucodeFlagOne) USTEP_FLAG(ucodeFlagZero | RST_USTEP, ucodeFlagOne | RST_USTEP); }
/***********************************************************************************************************************
* uCode step templates for different addressing modes
**********************************************************************************************************************/
// Zero-Page Addressing
#define USTEP_ADDR_Z \
/* Load ZP address to ADDRL */ \
USTEP_STEP(OE_RAM | INC_PC | WR_ADDRL)
// Indexed Addressing: Zero-Page,X and Zero-Page,Y
#define USTEP_ADDR_Z_IDX(oe) \
/* Load ZP address to A */ \
USTEP_STEP(OE_RAM | INC_PC | WR_ALU_A); \
/* Load X or Y to B */ \
USTEP_STEP(oe | WR_ALU_B); \
/* Add the together into ADDRL*/ \
USTEP_STEP(OE_ALU | ALU_ADD | WR_ADDRL)
// Load indirect address from Zero-Page pointed by ADDRL
#define USTEP_ADDR_INDZ \
/* Put address low byte into A temporarily */ \
USTEP_STEP(OE_RAM | ADDR_ZP | WR_ALU_A | INC_ADDRL);\
/* Load address high byte into ADDRH */ \
USTEP_STEP(OE_RAM | ADDR_ZP | WR_ADDRH); \
/* Load saved address low byte into ADDRL */ \
USTEP_STEP(OE_ALU_A | WR_ADDRL)
// Zero-Page Indirect (65C02)
#define USTEP_ADDR_Z_IND \
/* Load zero page address into ADDRL */ \
USTEP_ADDR_Z; \
/* Put indirect address into ADDRL and ADDRH from zero page */ \
USTEP_ADDR_INDZ;
// Pre-Indexed Indirect, "(Zero-Page,X)"
#define USTEP_ADDR_ZX_IND \
/* Load zero page base address + X into ADDRL */ \
USTEP_ADDR_Z_IDX(OE_X); \
/* Put indirect address into ADDRL and ADDRH from zero page */ \
USTEP_ADDR_INDZ;
// Absolute Addressing
#define USTEP_ADDR_ABS \
/* Load address into ADDR registers */ \
USTEP_STEP(OE_RAM | INC_PC | WR_ADDRL); \
USTEP_STEP(OE_RAM | INC_PC | WR_ADDRH)
// Indexed Addressing: Absolute,X and Absolute,Y
#define USTEP_ADDR_ABS_IDX(oe) \
/* Load base address low byte into A */ \
USTEP_STEP(OE_RAM | INC_PC | WR_ALU_A); \
/* Load base address high byte into ADDRH */ \
USTEP_STEP(OE_RAM | INC_PC | WR_ADDRH); \
/* Load X or Y into B */ \
USTEP_STEP(oe | WR_ALU_B); \
/* ADDRL + X/Y -> ADDRL */ \
USTEP_STEP(OE_ALU | ALU_ADD | WR_ADDRL); \
/* Increment ADDRH if page boundary has been crossed */ \
USTEP_FLAG( \
FLAGIN_CALU, \
FLAGIN_CALU | INC_ADDRH \
)
// Post-Indexed Indirect, "(Zero-Page),Y"
#define USTEP_ADDR_ZY_IND \
/* Load zero page address into ADDRL */ \
USTEP_STEP(OE_RAM | INC_PC | WR_ADDRL); \
/* Load base address low byte from zero page into A */ \
USTEP_STEP(OE_RAM | ADDR_ZP | WR_ALU_A | INC_ADDRL); \
/* Load base address high byte from zero page into ADDRH */ \
USTEP_STEP(OE_RAM | ADDR_ZP | WR_ADDRH); \
/* Y -> B */ \
USTEP_STEP(OE_Y | WR_ALU_B); \
/* Base address low byte + Y -> ADDRL */ \
USTEP_STEP(OE_ALU | ALU_ADD | WR_ADDRL); \
/* Increment ADDRH if page boundary has been crossed */ \
USTEP_FLAG( \
FLAGIN_CALU, \
FLAGIN_CALU | INC_ADDRH \
)
// Load data into a register updating N and Z flags
#define LD_NZ(addr, wr) USTEP_LAST(OE_RAM | addr | UPD_NZ | wr)
// Supported CPU types
enum {
CPU_6502,
CPU_65C02
} cpuType = CPU_6502;
/***********************************************************************************************************************
* Generate 6502 microcode
**********************************************************************************************************************/
static void GenerateUcode6502(void)
{
// All valid 6502 instruction opcodes (151)
enum {
// Legend:
// * - add 1 to cycles if page boundary is crossed
// The number of cycles here are the original 6502 cycles and included only for reference.
// ADC - Add Memory to Accumulator with Carry (A + M + C -> A, C)
// N Z C I D V
// + + + - - +
// ENUM = Opcode | Addressing | Assembler | B | Cycles
ADC_IMM = 0x69, // | immediate | ADC #oper | 2 | 2
ADC_Z = 0x65, // | zeropage | ADC oper | 2 | 3
ADC_ZX = 0x75, // | zeropage,X | ADC oper,X | 2 | 4
ADC_ABS = 0x6D, // | absolute | ADC oper | 3 | 4
ADC_ABSX = 0x7D, // | absolute,X | ADC oper,X | 3 | 4*
ADC_ABSY = 0x79, // | absolute,Y | ADC oper,Y | 3 | 4*
ADC_INDX = 0x61, // | (indirect,X) | ADC (oper,X) | 2 | 6
ADC_INDY = 0x71, // | (indirect),Y | ADC (oper),Y | 2 | 5*
// AND - AND Memory with Accumulator (A AND M -> A)
// N Z C I D V
// + + - - - -
// ENUM = Opcode | Addressing | Assembler | B | Cycles
AND_IMM = 0x29, // | immediate | AND #oper | 2 | 2
AND_Z = 0x25, // | zeropage | AND oper | 2 | 3
AND_ZX = 0x35, // | zeropage,X | AND oper,X | 2 | 4
AND_ABS = 0x2D, // | absolute | AND oper | 3 | 4
AND_ABSX = 0x3D, // | absolute,X | AND oper,X | 3 | 4*
AND_ABSY = 0x39, // | absolute,Y | AND oper,Y | 3 | 4*
AND_INDX = 0x21, // | (indirect,X) | AND (oper,X) | 2 | 6
AND_INDY = 0x31, // | (indirect),Y | AND (oper),Y | 2 | 5*
// ASL - Shift Left One Bit (Memory or Accumulator) (C <- [76543210] <- 0)
// N Z C I D V
// + + + - - -
// ENUM = Opcode | Addressing | Assembler | B | Cycles
ASL_A = 0x0A, // | accumulator | ASL A | 1 | 2
ASL_Z = 0x06, // | zeropage | ASL oper | 2 | 5
ASL_ZX = 0x16, // | zeropage,X | ASL oper,X | 2 | 6
ASL_ABS = 0x0E, // | absolute | ASL oper | 3 | 6
ASL_ABSX = 0x1E, // | absolute,X | ASL oper,X | 3 | 7
// Branch on flag clear oder set
// N Z C I D V
// - - - - - -
// ** - add 1 to cycles if branch occurs on same page, add 2 to cycles if branch occurs to different page
// ENUM = Opcode | Addressing | Assembler | B | Cyc | Operation
BCC = 0x90, // | relative | BCC oper | 2 | 2** | branch on C = 0
BCS = 0xB0, // | relative | BCS oper | 2 | 2** | branch on C = 1
BNE = 0xD0, // | relative | BNE oper | 2 | 2** | branch on Z = 0
BEQ = 0xF0, // | relative | BEQ oper | 2 | 2** | branch on Z = 1
BPL = 0x10, // | relative | BPL oper | 2 | 2** | branch on N = 0
BMI = 0x30, // | relative | BMI oper | 2 | 2** | branch on N = 1
BVC = 0x50, // | relative | BVC oper | 2 | 2** | branch on V = 0
BVS = 0x70, // | relative | BVS oper | 2 | 2** | branch on V = 1
// BI T- Test Bits in Memory with Accumulator (A AND M, M7 -> N, M6 -> V)
// N Z C I D V
// M7 + - - - M6
// ENUM = Opcode | Addressing | Assembler | B | Cycles
BIT_Z = 0x24, // | zeropage | BIT oper | 2 | 3
BIT_ABS = 0x2C, // | absolute | BIT oper | 3 | 4
// BRK - Force Break (push PC+2, push SR)
// N Z C I D V
// - - - + - -
// ENUM = Opcode | Addressing | Assembler | B | Cycles
BRK = 0x00, // | implied | BRK | 1 | 7
// Flag Instructions
// N Z C I D V
// - - + + + +
// ENUM = Opcode | Addressing | Assembler | B | C | Operation
CLC = 0x18, // | implied | CLC | 1 | 2 | 0 -> C
SEC = 0x38, // | implied | SEC | 1 | 2 | 1 -> C
CLD = 0xD8, // | implied | CLD | 1 | 2 | 0 -> D
SED = 0xF8, // | implied | SED | 1 | 2 | 1 -> D
CLI = 0x58, // | implied | CLI | 1 | 2 | 0 -> I
SEI = 0x78, // | implied | SEI | 1 | 2 | 1 -> I
CLV = 0xB8, // | implied | CLV | 1 | 2 | 0 -> V
// Compare Memory with Accumulator (A - M)
// N Z C I D V
// + + + - - -
// ENUM = Opcode | Addressing | Assembler | B | Cycles
CMP_IMM = 0xC9, // | immediate | CMP #oper | 2 | 2
CMP_Z = 0xC5, // | zeropage | CMP oper | 2 | 3
CMP_ZX = 0xD5, // | zeropage,X | CMP oper,X | 2 | 4
CMP_ABS = 0xCD, // | absolute | CMP oper | 3 | 4
CMP_ABSX = 0xDD, // | absolute,X | CMP oper,X | 3 | 4*
CMP_ABSY = 0xD9, // | absolute,Y | CMP oper,Y | 3 | 4*
CMP_INDX = 0xC1, // | (indirect,X) | CMP (oper,X) | 2 | 6
CMP_INDY = 0xD1, // | (indirect),Y | CMP (oper),Y | 2 | 5*
// CPX - Compare Memory and Index X (X - M)
// N Z C I D V
// + + + - - -
// ENUM = Opcode | Addressing | Assembler | B | Cycles
CPX_IMM = 0xE0, // | immediate | CPX #oper | 2 | 2
CPX_Z = 0xE4, // | zeropage | CPX oper | 2 | 3
CPX_ABS = 0xEC, // | absolute | CPX oper | 3 | 4
// CPY - Compare Memory and Index Y (Y - M)
// N Z C I D V
// + + + - - -
// ENUM = Opcode | Addressing | Assembler | B | Cycles
CPY_IMM = 0xC0, // | immediate | CPY #oper | 2 | 2
CPY_Z = 0xC4, // | zeropage | CPY oper | 2 | 3
CPY_ABS = 0xCC, // | absolute | CPY oper | 3 | 4
// DEC - Decrement Memory by One (M - 1 -> M)
// N Z C I D V
// + + - - - -
DEC_Z = 0xC6, // | zeropage | DEC oper | 2 | 5
DEC_ZX = 0xD6, // | zeropage,X | DEC oper,X | 2 | 6
DEC_ABS = 0xCE, // | absolute | DEC oper | 3 | 6
DEC_ABSX = 0xDE, // | absolute,X | DEC oper,X | 3 | 7
// INC - Increment Memory by One (M + 1 -> M)
// N Z C I D V
// + + - - - -
// ENUM = Opcode | Addressing | Assembler | B | Cycles
INC_Z = 0xE6, // | zeropage | INC oper | 2 | 5
INC_ZX = 0xF6, // | zeropage,X | INC oper,X | 2 | 6
INC_ABS = 0xEE, // | absolute | INC oper | 3 | 6
INC_ABSX = 0xFE, // | absolute,X | INC oper,X | 3 | 7
// Register increment / decrement
// N Z C I D V
// + + - - - -
// ENUM = Opcode | Addressing | Assembler | B | C | Operation
INX = 0xE8, // | implied | INX | 1 | 2 | X + 1 -> X
DEX = 0xCA, // | implied | DEX | 1 | 2 | X - 1 -> X
INY = 0xC8, // | implied | INY | 1 | 2 | Y + 1 -> Y
DEY = 0x88, // | implied | DEY | 1 | 2 | Y - 1 -> Y
// EOR - Exclusive-OR Memory with Accumulator (A EOR M -> A)
// N Z C I D V
// + + - - - -
// ENUM = Opcode | Addressing | Assembler | B | Cycles
EOR_IMM = 0x49, // | immediate | EOR #oper | 2 | 2
EOR_Z = 0x45, // | zeropage | EOR oper | 2 | 3
EOR_ZX = 0x55, // | zeropage,X | EOR oper,X | 2 | 4
EOR_ABS = 0x4D, // | absolute | EOR oper | 3 | 4
EOR_ABSX = 0x5D, // | absolute,X | EOR oper,X | 3 | 4*
EOR_ABSY = 0x59, // | absolute,Y | EOR oper,Y | 3 | 4*
EOR_INDX = 0x41, // | (indirect,X) | EOR (oper,X) | 2 | 6
EOR_INDY = 0x51, // | (indirect),Y | EOR (oper),Y | 2 | 5*
// JMP - Jump to New Location ((PC+1) -> PCL, (PC+2) -> PCH)
// N Z C I D V
// - - - - - -
// ENUM = Opcode | Addressing | Assembler | B | Cycles
JMP_ABS = 0x4C, // | absolute | JMP oper | 3 | 3
JMP_IND = 0x6C, // | indirect | JMP (oper) | 3 | 5
// JSR - Jump to New Location Saving Return Address (push (PC+2), (PC+1) -> PCL, (PC+2) -> PCH)
// N Z C I D V
// - - - - - -
// ENUM = Opcode | Addressing | Assembler | B | Cycles
JSR = 0x20, // | absolute | JSR oper | 3 | 6
// LDA - Load Accumulator with Memory (M -> A)
// N Z C I D V
// + + - - - -
// ENUM = Opcode | Addressing | Assembler | B | Cycles
LDA_IMM = 0xA9, // | immediate | LDA #oper | 2 | 2
LDA_Z = 0xA5, // | zeropage | LDA oper | 2 | 3
LDA_ZX = 0xB5, // | zeropage,X | LDA oper,X | 2 | 4
LDA_ABS = 0xAD, // | absolute | LDA oper | 3 | 4
LDA_ABSX = 0xBD, // | absolute,X | LDA oper,X | 3 | 4*
LDA_ABSY = 0xB9, // | absolute,Y | LDA oper,Y | 3 | 4*
LDA_INDX = 0xA1, // | (indirect,X) | LDA (oper,X) | 2 | 6
LDA_INDY = 0xB1, // | (indirect),Y | LDA (oper),Y | 2 | 5*
// LDX - Load Index X with Memory (M -> X)
// N Z C I D V
// + + - - - -
// ENUM = Opcode | Addressing | Assembler | B | Cycles
LDX_IMM = 0xA2, // | immediate | LDX #oper | 2 | 2
LDX_Z = 0xA6, // | zeropage | LDX oper | 2 | 3
LDX_ZY = 0xB6, // | zeropage,Y | LDX oper,Y | 2 | 4
LDX_ABS = 0xAE, // | absolute | LDX oper | 3 | 4
LDX_ABSY = 0xBE, // | absolute,Y | LDX oper,Y | 3 | 4*
// LDY - Load Index Y with Memory (M -> Y)
// N Z C I D V
// + + - - - -
// ENUM = Opcode | Addressing | Assembler | B | Cycles
LDY_IMM = 0xA0, // | immediate | LDY #oper | 2 | 2
LDY_Z = 0xA4, // | zeropage | LDY oper | 2 | 3
LDY_ZX = 0xB4, // | zeropage,X | LDY oper,X | 2 | 4
LDY_ABS = 0xAC, // | absolute | LDY oper | 3 | 4
LDY_ABSX = 0xBC, // | absolute,X | LDY oper,X | 3 | 4*
// LSR - Shift One Bit Right (Memory or Accumulator) (0 -> [76543210] -> C)
// N Z C I D V
// 0 + + - - -
// ENUM = Opcode | Addressing | Assembler | B | Cycles
LSR_A = 0x4A, // | accumulator | LSR A | 1 | 2
LSR_Z = 0x46, // | zeropage | LSR oper | 2 | 5
LSR_ZX = 0x56, // | zeropage,X | LSR oper,X | 2 | 6
LSR_ABS = 0x4E, // | absolute | LSR oper | 3 | 6
LSR_ABSX = 0x5E, // | absolute,X | LSR oper,X | 3 | 7
// NOP - No Operation
// N Z C I D V
// - - - - - -
// ENUM = Opcode | Addressing | Assembler | B | Cycles
NOP = 0xEA, // | implied | NOP | 1 | 2
// ORA - OR Memory with Accumulator (A OR M -> A)
// N Z C I D V
// + + - - - -
// ENUM = Opcode | Addressing | Assembler | B | Cycles
ORA_IMM = 0x09, // | immediate | ORA #oper | 2 | 2
ORA_Z = 0x05, // | zeropage | ORA oper | 2 | 3
ORA_ZX = 0x15, // | zeropage,X | ORA oper,X | 2 | 4
ORA_ABS = 0x0D, // | absolute | ORA oper | 3 | 4
ORA_ABSX = 0x1D, // | absolute,X | ORA oper,X | 3 | 4*
ORA_ABSY = 0x19, // | absolute,Y | ORA oper,Y | 3 | 4*
ORA_INDX = 0x01, // | (indirect,X) | ORA (oper,X) | 2 | 6
ORA_INDY = 0x11, // | (indirect),Y | ORA (oper),Y | 2 | 5*
// Stack Instructions
// ENUM = Opcode | Addressing | Assembler | B | C | Operation | N Z C I D V
PHA = 0x48, // | implied | PHA | 1 | 3 | push A | - - - - - -
PLA = 0x68, // | implied | PLA | 1 | 4 | pull A | + + - - - -
PHP = 0x08, // | implied | PHP | 1 | 3 | push SR | - - - - - -
PLP = 0x28, // | implied | PLP | 1 | 4 | pull SR | + + + + + +
// ROL - Rotate One Bit Left (Memory or Accumulator) (C <- [76543210] <- C)
// N Z C I D V
// + + + - - -
// ENUM = Opcode | Addressing | Assembler | B | Cycles
ROL_A = 0x2A, // | accumulator | ROL A | 1 | 2
ROL_Z = 0x26, // | zeropage | ROL oper | 2 | 5
ROL_ZX = 0x36, // | zeropage,X | ROL oper,X | 2 | 6
ROL_ABS = 0x2E, // | absolute | ROL oper | 3 | 6
ROL_ABSX = 0x3E, // | absolute,X | ROL oper,X | 3 | 7
// ROR - Rotate One Bit Right (Memory or Accumulator) (C -> [76543210] -> C)
// N Z C I D V
// + + + - - -
// ENUM = Opcode | Addressing | Assembler | B | Cycles
ROR_A = 0x6A, // | accumulator | ROR A | 1 | 2
ROR_Z = 0x66, // | zeropage | ROR oper | 2 | 5
ROR_ZX = 0x76, // | zeropage,X | ROR oper,X | 2 | 6
ROR_ABS = 0x6E, // | absolute | ROR oper | 3 | 6
ROR_ABSX = 0x7E, // | absolute,X | ROR oper,X | 3 | 7
// RTI - Return from Interrupt (pull SR, pull PC)
// N Z C I D V
// + + + + + +
// ENUM = Opcode | Addressing | Assembler | B | Cycles
RTI = 0x40, // | implied | RTI | 1 | 6
// RTS - Return from Subroutine (pull PC, PC+1 -> PC)
// N Z C I D V
// - - - - - -
// ENUM = Opcode | Addressing | Assembler | B | Cycles
RTS = 0x60, // | implied | RTS | 1 | 6
// SBC - Subtract Memory from Accumulator with Borrow (A - M - /C -> A)
// N Z C I D V
// + + + - - +
// ENUM = Opcode | Addressing | Assembler | B | Cycles
SBC_IMM = 0xE9, // | immediate | SBC #oper | 2 | 2
SBC_Z = 0xE5, // | zeropage | SBC oper | 2 | 3
SBC_ZX = 0xF5, // | zeropage,X | SBC oper,X | 2 | 4
SBC_ABS = 0xED, // | absolute | SBC oper | 3 | 4
SBC_ABSX = 0xFD, // | absolute,X | SBC oper,X | 3 | 4*
SBC_ABSY = 0xF9, // | absolute,Y | SBC oper,Y | 3 | 4*
SBC_INDX = 0xE1, // | (indirect,X) | SBC (oper,X) | 2 | 6
SBC_INDY = 0xF1, // | (indirect),Y | SBC (oper),Y | 2 | 5*
// STA - Store Accumulator in Memory (A -> M)
// N Z C I D V
// - - - - - -
// ENUM = Opcode | Addressing | Assembler | B | Cycles
STA_Z = 0x85, // | zeropage | STA oper | 2 | 3
STA_ZX = 0x95, // | zeropage,X | STA oper,X | 2 | 4
STA_ABS = 0x8D, // | absolute | STA oper | 3 | 4
STA_ABSX = 0x9D, // | absolute,X | STA oper,X | 3 | 5
STA_ABSY = 0x99, // | absolute,Y | STA oper,Y | 3 | 5
STA_INDX = 0x81, // | (indirect,X) | STA (oper,X) | 2 | 6
STA_INDY = 0x91, // | (indirect),Y | STA (oper),Y | 2 | 6
// STX - Store Index X in Memory (X -> M)
// N Z C I D V
// - - - - - -
// ENUM = Opcode | Addressing | Assembler | B | Cycles
STX_Z = 0x86, // | zeropage | STX oper | 2 | 3
STX_ZY = 0x96, // | zeropage,Y | STX oper,Y | 2 | 4
STX_ABS = 0x8E, // | absolute | STX oper | 3 | 4
// STY - Sore Index Y in Memory (Y -> M)
// N Z C I D V
// - - - - - -
// ENUM = Opcode | Addressing | Assembler | B | Cycles
STY_Z = 0x84, // | zeropage | STY oper | 2 | 3
STY_ZX = 0x94, // | zeropage,X | STY oper,X | 2 | 4
STY_ABS = 0x8C, // | absolute | STY oper | 3 | 4
// Register to register transfer
// ENUM = Opcode | Addressing | Assembler | B | C | Operation | N Z C I D V
TAX = 0xAA, // | implied | TAX | 1 | 2 | A -> X | + + - - - -
TXA = 0x8A, // | implied | TXA | 1 | 2 | X -> A | + + - - - -
TAY = 0xA8, // | implied | TAY | 1 | 2 | A -> Y | + + - - - -
TYA = 0x98, // | implied | TYA | 1 | 2 | Y -> A | + + - - - -
TSX = 0xBA, // | implied | TSX | 1 | 2 | SP -> X | + + - - - -
TXS = 0x9A, // | implied | TXS | 1 | 2 | X -> SP | - - - - - -
};
/*********************************************************************************************************************
* ADC - Add Memory to Accumulator with Carry (A + M + C -> A, C)
*
* N Z C I D V
* + + + - - +
********************************************************************************************************************/
// ALU add or subtract with carry flag
#define ALU_ADD_SUB(addr, aluop) \
/* ACC -> A */ \
USTEP_STEP(OE_ACC | WR_ALU_A); \
/* Operand from memory -> B */ \
USTEP_STEP(OE_RAM | addr | WR_ALU_B); \
/* Add or subtract with carry */ \
USTEP_FLST( \
FLAGIN_C | OE_ALU | aluop | UPD_NZ | UPD_C | UPD_V | WR_ACC, \
FLAGIN_C | OE_ALU | aluop | UPD_NZ | UPD_C | UPD_V | WR_ACC | CI_ALU \
)
// Add with carry and according to decimal flag
#define ADD_ACC(addr) ALU_ADD_SUB(addr, ALU_DADD)
USTEP_DEFINE(ADC_IMM);
ADD_ACC(INC_PC);
USTEP_DEFINE(ADC_Z);
USTEP_ADDR_Z;
ADD_ACC(ADDR_ZP);
USTEP_DEFINE(ADC_ZX);
USTEP_ADDR_Z_IDX(OE_X);
ADD_ACC(ADDR_ZP);
USTEP_DEFINE(ADC_ABS);
USTEP_ADDR_ABS;
ADD_ACC(ADDR_FULL);
USTEP_DEFINE(ADC_ABSX);
USTEP_ADDR_ABS_IDX(OE_X);
ADD_ACC(ADDR_FULL);
USTEP_DEFINE(ADC_ABSY);
USTEP_ADDR_ABS_IDX(OE_Y);
ADD_ACC(ADDR_FULL);
USTEP_DEFINE(ADC_INDX);
USTEP_ADDR_ZX_IND;
ADD_ACC(ADDR_FULL);
USTEP_DEFINE(ADC_INDY);
USTEP_ADDR_ZY_IND;
ADD_ACC(ADDR_FULL);
/*********************************************************************************************************************
* SBC - Subtract Memory from Accumulator with Borrow (A - M - /C -> A)
*
* N Z C I D V
* + + + - - +
********************************************************************************************************************/
#define SUB_ACC(addr) ALU_ADD_SUB(addr, ALU_DSUB)
USTEP_DEFINE(SBC_IMM);
SUB_ACC(INC_PC);
USTEP_DEFINE(SBC_Z);
USTEP_ADDR_Z;
SUB_ACC(ADDR_ZP);
USTEP_DEFINE(SBC_ZX);
USTEP_ADDR_Z_IDX(OE_X);
SUB_ACC(ADDR_ZP);
USTEP_DEFINE(SBC_ABS);
USTEP_ADDR_ABS;
SUB_ACC(ADDR_FULL);
USTEP_DEFINE(SBC_ABSX);
USTEP_ADDR_ABS_IDX(OE_X);
SUB_ACC(ADDR_FULL);
USTEP_DEFINE(SBC_ABSY);
USTEP_ADDR_ABS_IDX(OE_Y);
SUB_ACC(ADDR_FULL);
USTEP_DEFINE(SBC_INDX);
USTEP_ADDR_ZX_IND;
SUB_ACC(ADDR_FULL);
USTEP_DEFINE(SBC_INDY);
USTEP_ADDR_ZY_IND;
SUB_ACC(ADDR_FULL);
/*********************************************************************************************************************
* AND - AND Memory with Accumulator (A AND M -> A)
*
* N Z C I D V
* + + - - - -
********************************************************************************************************************/
// ALU AND / OR / XOR
#define ALU_LOGIC_OP(addr, aluop) \
/* ACC -> A */ \
USTEP_STEP(OE_ACC | WR_ALU_A); \
/* Operand from memory -> B */ \
USTEP_STEP(OE_RAM | addr | WR_ALU_B); \
/* Result of logic operation -> ACC */ \
USTEP_LAST(OE_ALU | aluop | UPD_NZ | WR_ACC)
// AND
#define AND_ACC(addr) ALU_LOGIC_OP(addr, ALU_AND)
USTEP_DEFINE(AND_IMM);
AND_ACC(INC_PC);
USTEP_DEFINE(AND_Z);
USTEP_ADDR_Z;
AND_ACC(ADDR_ZP);
USTEP_DEFINE(AND_ZX);
USTEP_ADDR_Z_IDX(OE_X);
AND_ACC(ADDR_ZP);
USTEP_DEFINE(AND_ABS);
USTEP_ADDR_ABS;
AND_ACC(ADDR_FULL);
USTEP_DEFINE(AND_ABSX);
USTEP_ADDR_ABS_IDX(OE_X);
AND_ACC(ADDR_FULL);
USTEP_DEFINE(AND_ABSY);
USTEP_ADDR_ABS_IDX(OE_Y);
AND_ACC(ADDR_FULL);
USTEP_DEFINE(AND_INDX);
USTEP_ADDR_ZX_IND;
AND_ACC(ADDR_FULL);
USTEP_DEFINE(AND_INDY);
USTEP_ADDR_ZY_IND;
AND_ACC(ADDR_FULL);
/*********************************************************************************************************************
* ORA - OR Memory with Accumulator (A OR M -> A)
*
* N Z C I D V
* + + - - - -
********************************************************************************************************************/
#define ORA_ACC(addr) ALU_LOGIC_OP(addr, ALU_OR)
USTEP_DEFINE(ORA_IMM);
ORA_ACC(INC_PC);
USTEP_DEFINE(ORA_Z);
USTEP_ADDR_Z;
ORA_ACC(ADDR_ZP);
USTEP_DEFINE(ORA_ZX);
USTEP_ADDR_Z_IDX(OE_X);
ORA_ACC(ADDR_ZP);
USTEP_DEFINE(ORA_ABS);
USTEP_ADDR_ABS;
ORA_ACC(ADDR_FULL);
USTEP_DEFINE(ORA_ABSX);
USTEP_ADDR_ABS_IDX(OE_X);
ORA_ACC(ADDR_FULL);
USTEP_DEFINE(ORA_ABSY);
USTEP_ADDR_ABS_IDX(OE_Y);
ORA_ACC(ADDR_FULL);
USTEP_DEFINE(ORA_INDX);
USTEP_ADDR_ZX_IND;
ORA_ACC(ADDR_FULL);
USTEP_DEFINE(ORA_INDY);
USTEP_ADDR_ZY_IND;
ORA_ACC(ADDR_FULL);
/*********************************************************************************************************************
* EOR - Exclusive-OR Memory with Accumulator (A EOR M -> A)
*
* N Z C I D V
* + + - - - -
********************************************************************************************************************/
#define EOR_ACC(addr) ALU_LOGIC_OP(addr, ALU_XOR)
USTEP_DEFINE(EOR_IMM);
EOR_ACC(INC_PC);
USTEP_DEFINE(EOR_Z);
USTEP_ADDR_Z;
EOR_ACC(ADDR_ZP);
USTEP_DEFINE(EOR_ZX);
USTEP_ADDR_Z_IDX(OE_X);
EOR_ACC(ADDR_ZP);
USTEP_DEFINE(EOR_ABS);
USTEP_ADDR_ABS;
EOR_ACC(ADDR_FULL);
USTEP_DEFINE(EOR_ABSX);
USTEP_ADDR_ABS_IDX(OE_X);
EOR_ACC(ADDR_FULL);
USTEP_DEFINE(EOR_ABSY);
USTEP_ADDR_ABS_IDX(OE_Y);
EOR_ACC(ADDR_FULL);
USTEP_DEFINE(EOR_INDX);
USTEP_ADDR_ZX_IND;
EOR_ACC(ADDR_FULL);
USTEP_DEFINE(EOR_INDY);
USTEP_ADDR_ZY_IND;
EOR_ACC(ADDR_FULL);
/*********************************************************************************************************************
* ASL - Shift Left One Bit (Memory or Accumulator) (C <- [76543210] <- 0)
*
* N Z C I D V
* + + + - - -
********************************************************************************************************************/
#define ASL(src, dst) \
/* src -> A */ \
USTEP_STEP(src | WR_ALU_A); \
/* A -> B */ \
USTEP_STEP(OE_ALU_A | WR_ALU_B); \
/* src + src -> dst */ \
USTEP_LAST(OE_ALU | ALU_ADD | UPD_NZ | UPD_C | dst)
USTEP_DEFINE(ASL_A);
ASL(OE_ACC, WR_ACC);
USTEP_DEFINE(ASL_Z);
USTEP_ADDR_Z;
ASL(OE_RAM | ADDR_ZP, WR_RAM | ADDR_ZP);
USTEP_DEFINE(ASL_ZX);
USTEP_ADDR_Z_IDX(OE_X);
ASL(OE_RAM | ADDR_ZP, WR_RAM | ADDR_ZP);
USTEP_DEFINE(ASL_ABS);
USTEP_ADDR_ABS;
ASL(OE_RAM | ADDR_FULL, WR_RAM | ADDR_FULL);
USTEP_DEFINE(ASL_ABSX);
USTEP_ADDR_ABS_IDX(OE_X);
ASL(OE_RAM | ADDR_FULL, WR_RAM | ADDR_FULL);
/*********************************************************************************************************************
* ROL - Rotate One Bit Left (Memory or Accumulator) (C <- [76543210] <- C)
*
* N Z C I D V
* + + + - - -
********************************************************************************************************************/
#define ROL(src, dst) \
/* src -> A */ \
USTEP_STEP(src | WR_ALU_A); \
/* A -> B */ \
USTEP_STEP(OE_ALU_A | WR_ALU_B); \
/* src + src + C -> dst */ \
USTEP_FLST( \
FLAGIN_C | OE_ALU | ALU_ADD | UPD_NZ | UPD_C | dst, \
FLAGIN_C | OE_ALU | ALU_ADD | UPD_NZ | UPD_C | dst | CI_ALU \
)
USTEP_DEFINE(ROL_A);
ROL(OE_ACC, WR_ACC);
USTEP_DEFINE(ROL_Z);
USTEP_ADDR_Z;
ROL(OE_RAM | ADDR_ZP, WR_RAM | ADDR_ZP);
USTEP_DEFINE(ROL_ZX);
USTEP_ADDR_Z_IDX(OE_X);
ROL(OE_RAM | ADDR_ZP, WR_RAM | ADDR_ZP);
USTEP_DEFINE(ROL_ABS);
USTEP_ADDR_ABS;
ROL(OE_RAM | ADDR_FULL, WR_RAM | ADDR_FULL);
USTEP_DEFINE(ROL_ABSX);
USTEP_ADDR_ABS_IDX(OE_X);
ROL(OE_RAM | ADDR_FULL, WR_RAM | ADDR_FULL);
/*********************************************************************************************************************
* LSR - Shift One Bit Right (Memory or Accumulator) (0 -> [76543210] -> C)
*
* N Z C I D V
* 0 + + - - -
********************************************************************************************************************/
#define LSR(src, dst) \
USTEP_STEP(src | WR_ALU_A); \
USTEP_LAST(OE_ALU | ALU_SHR | UPD_NZ | UPD_C | dst)
USTEP_DEFINE(LSR_A);
LSR(OE_ACC, WR_ACC);
USTEP_DEFINE(LSR_Z);
USTEP_ADDR_Z;
LSR(OE_RAM | ADDR_ZP, WR_RAM | ADDR_ZP);
USTEP_DEFINE(LSR_ZX);
USTEP_ADDR_Z_IDX(OE_X);
LSR(OE_RAM | ADDR_ZP, WR_RAM | ADDR_ZP);
USTEP_DEFINE(LSR_ABS);
USTEP_ADDR_ABS;
LSR(OE_RAM | ADDR_FULL, WR_RAM | ADDR_FULL);
USTEP_DEFINE(LSR_ABSX);
USTEP_ADDR_ABS_IDX(OE_X);
LSR(OE_RAM | ADDR_FULL, WR_RAM | ADDR_FULL);
/*********************************************************************************************************************
* ROR - Rotate One Bit Right (Memory or Accumulator) (C -> [76543210] -> C)
*
* N Z C I D V
* + + + - - -
********************************************************************************************************************/
#define ROR(src, dst) \
USTEP_STEP(src | WR_ALU_A); \
USTEP_FLST( \
FLAGIN_C | OE_ALU | ALU_SHR | UPD_NZ | UPD_C | dst, \
FLAGIN_C | OE_ALU | ALU_SHR | UPD_NZ | UPD_C | dst | CI_ALU \
)
USTEP_DEFINE(ROR_A);
ROR(OE_ACC, WR_ACC);
USTEP_DEFINE(ROR_Z);
USTEP_ADDR_Z;
ROR(OE_RAM | ADDR_ZP, WR_RAM | ADDR_ZP);
USTEP_DEFINE(ROR_ZX);
USTEP_ADDR_Z_IDX(OE_X);
ROR(OE_RAM | ADDR_ZP, WR_RAM | ADDR_ZP);
USTEP_DEFINE(ROR_ABS);
USTEP_ADDR_ABS;
ROR(OE_RAM | ADDR_FULL, WR_RAM | ADDR_FULL);
USTEP_DEFINE(ROR_ABSX);
USTEP_ADDR_ABS_IDX(OE_X);
ROR(OE_RAM | ADDR_FULL, WR_RAM | ADDR_FULL);
/*********************************************************************************************************************
* BIT - Test Bits in Memory with Accumulator (A AND M, M7 -> N, M6 -> V)
*
* N Z C I D V
* M7 + - - - M6
*
* bits 7 and 6 of operand are transfered to bit 7 and 6 of SR (N,V);
* the zero-flag is set according to the result of the operand AND
* the accumulator (set, if the result is zero, unset otherwise).
* This allows a quick check of a few bits at once without affecting
* any of the registers, other than the status register (SR).
*
********************************************************************************************************************/
#define BIT(addr) \
/* Memory -> A */ \
USTEP_STEP(OE_RAM | addr | WR_ALU_A); \
/* Bit 6 -> V, Bit 7 -> N */ \
USTEP_STEP(OE_ALU_A | WR_FLAGS | UPD_N | UPD_V); \
/* ACC -> B */ \
USTEP_STEP(OE_ACC | WR_ALU_B); \
/* ACC AND Memory -> Z */ \
USTEP_LAST(OE_ALU | ALU_AND | UPD_Z)
USTEP_DEFINE(BIT_Z);
USTEP_ADDR_Z;
BIT(ADDR_ZP);
USTEP_DEFINE(BIT_ABS);
USTEP_ADDR_ABS;
BIT(ADDR_FULL);
/*********************************************************************************************************************
* Comparisons
*
* Generally, comparison instructions subtract the operand from the given register without affecting this register.
* Flags are still set as with a normal subtraction and thus the relation of the two values becomes accessible by the
* Zero, Carry and Negative flags.
* (See the branch instructions below for how to evaluate flags.)
*
* Relation R - Op | Z | C | N
* Register < Operand | 0 | 0 | sign bit of result
* Register = Operand | 1 | 1 | 0
* Register > Operand | 0 | 1 | sign bit of result
********************************************************************************************************************/
#define CMP(reg, addr) \
/* Register -> A */ \
USTEP_STEP(reg | WR_ALU_A); \