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ERROR: Can't open ABC output file `/tmp/yosys-abc-usQczk/output.blif'. #123
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Another data point is that my design uses Also, the github repo link changed per mpw-one guidelines of caravel_ prefix. Github will redirect, but for reference, it is now https://github.com/SweeperAA/caravel_skywater130_decred_miner |
In the mean time, I've updated my repo for a smaller design to get around this issue. If you need to recreate it with the repo I listed, let me know and I'll provide you the changes to do so. |
@SweeperAA: Usually, when this error happens:
Since you already tried the other synthesis strategies and they worked. I believe your problem is solved. |
@agorararmard I am working around this issue by changing the |
Using openlane mpw-one-a branch and in the early stages of the flow for my design, I get the following error:
This error occurs on the full up version of my design that as about 282K cells (as reported just before the "Executing ABC pass (technology mapping using ABC)" step). If I reduce my design to 107K cells, it still occurs. Only if I reduce the design down to 72K cells, I don't get this error. I don't believe this is a RAM limitation as the memory usage was very low during this part of the process (and I have 24G of RAM).
Repo is at: https://github.com/SweeperAA/skywater130_decred_miner
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