grlib-gpl-2025.2-b4298

----------------------- Release 2025.2-b4298 ---------------------------

2025-06-30	NOEL-V updates:
		- Update interrupt port definition (new record type)
		- Prevent H-extension to be enabled for RV32 (currently
		  not supported)
		- MC standard configuration has been updated to increase L1
		  to 4-way and remove double-precision floating-point (only
		  supporting F extension)
		- The double-trap extension (smdbltr and ssdbltrp) have been
		  updated version 1.0
		- Update to CSR handling (illegal checks, and exceptions)
		- Added shlcofideleg and smcdeleg extension
		- Added SVADU extension
		- PLIC now supports more then 31 interrupt sources
		- Custom FEATURE CSR updated (bits has been redefined)
		- Added support for Svnapot extension and Sv48
		- Update illegal checks for CBO instructions
		- APLIC: base_ppn field was not shifted 12 bits to the left
		  to calculate the IMSIC base address.
		- G-stage access fault was raised instead of page fault for
		  some cases
		- Fixed issue with PMA/PMP check during page-walk
		- Fix to not update m/htinst on shadowstack push/pop
		  exceptions
		- Fixed incorrect fault for CFI landing pad faults
		- Executing ssamoswap in machine mode was not handled
		  correctly
		- Update Smstateen extension to incorporate the bits
		  p1p13 & C.
		- Modify write behavior of bits in hstateen/sstateen, if
		  mstateen.bit is 0 then hstateen.bit/sstateen.bit is no
		  longer writeable and previous bits are preserved.
		- Update envcfg to incorporate read-only behavior for bits
		  not set in higher privilege mode envcfg. Example) if
		  menvcfg.sse = 0 => RO (s/h)envcfg.sse. Previous bits
		  preserved.
		- Update CBO and ssamoswap exception behavior, these
		  instructions could previously throw a virtual instruction
		  exception even if its menvcfg bit was 0.

2025-06-25	TECHMAP: Add UltraScale/UltraScale-Plus mapping for DDR_OREG

2025-06-24	AHB2AXIB: new generic to support AMBA address widths of more
		than 32 bits (not compatible yet with PnP scanning).

2025-06-17	APBUART: Added break character support
		- Increased APBUART revision to 2
		- Updated the core to support transmission and detection
		  of break characters within a configurable range of
		  10-16 zeroes. Break operation is managed via the control
		  register of the apb bus.
		- Enabled break handling in loop-back operation
		- Added a capability register that reports the values
		  for certain RTL instantiation generics, including
		  FIFO size and flow
		- The debug bit in the control register is now read-only.
		  Read/write access for debug functionality has been
		  relocated to the FIFO debug control register.

2025-06-16	GRGPIO: Added set and clear register support to facilitate
		atomic accesses to selected registers.

2025-06-10	BCC: BCC1 to BCC2 migration
		- Affects systest in designs directory

2025-06-09	LEON5: Fix issue on LDSTUB/LDSTUBA opcode check

2025-05-23	LEON5: DTCM Fixes
		- Fix an issue where ASI accesses where triggering unwanted
		  dtcmhit.

2025-04-16	AXI2AHB: fix simultaneous read and write accesses

2025-04-03	GRDMAC2: Incorrect calculation of the burst_chop_mask generic
		value in generic_bm instantiation is fixed. generic_bm_ahb
		instantiation in the grdmac2 has the default value 1024 for
		burst_chop_mask	generic.

grlib-gpl-2025.1-b4296

----------------------- Release 2025.1-b4296 ---------------------------

2025-03-21	New AHBJTAG_EXTTAP IP. Modified version of AHBJTAG where
		the TAP module is instantiated externally.
		Especially suitable for technologies where the TAP cannot
		be instantiated standalone, such as AMD Versal.

2025-03-21	Added support for Versal memories, including ECC (FT = 5)

2025-03-21	NOELV: Workaround for Cadence synthesis issues

2025-03-13	LEON5: Fix issue when building with the global async reset
		setting in the grlib config package.

2025-01-16	AXI: Add new modules
		- AXI4 to AHB2 bridge
		- AXI4-Stream skidbuffer
		- AXI4-Stream gearbox
		- AXI4 transaction resizer

grlib-gpl-2024.4-b4295

----------------------- Release 2024.4-b4295 ---------------------------

2024-12-18	NOEL-V updates
		- Internal APB bus in noelvsys has been moved from
		  0xFC0000000 to 0xFF9000000 and some devices has been
		  reorganized. New UART address is now 0xFF900000.
		- Added option in noelvsys to include PLIC and APLIC
		- Workaround tool issues for Design-compiler and formality
		- Added NOEL-V template design for the ZCU102 board
		- Updated BF16 support (Zfbfmin now ratified)
		- B in MISA is now set when zba, zbb, zbs are implemented
		- Improved access and fixed issues with access to IMSIC CSRs
		- Trigger update to support CBO instructions
		- Updated Smrnmi implementation to support CFI
		- Updated interrupt prioritization according to AIA
		- Removed workaround to allow 64-bit debug-module abstract
		  command on RV32
		- Bug fixes:
		  - CBO.inval and CBO.flush could incorrectly update the TAG
		    and cause duplicated data tags.
		  - mstatush was only available when H-extension was enabled
		  - exception generated for the SSTC extension was incorrect
		  - ePMP bit in mseccfg was writable when PMP was not
		    implemented
		  - updating these CSRs (menvcfgh, frm/fcsr, xtvec, stateen,
		    mideleg/hideleg) should not be dual-issued with other
		    instructions
		  - incorrect exception when an address in a PTE failed PMA
		    check
		  - SIP.lcof was always read zero
		  - sfence.w.inval and sfence.inval.ir weren't trapping in
		    U/VU mode and generating virtual instruction exception
		    correctly
		  - APLIC interrupt source was shifted by one bit.
		  - a hit in BTB was not check to actually be a branch/jal
		    instruction
		  - SLLI >31 bit shift was not marked as illegal for RV32
		  - medeleg and hedeleg to incorporate hw-fault exception
		  - address translation was not enabled for the instruction
		    following enabling MMU
		  - VSATP had the same number of PPN bits as SATP and not
		    all 41 bits of GPA could be used
		  - fix for a CFI landing pad corner case
		  - data cache was flushed when executing a fence instruction
		  - PTE with D = 1 and A = 0 did not result in page-fault
		  - LWU could be executed on RV32
		  - issue with tval for mcontrol6 trigger
		  - SSRDP was not checked for regarding pairing with
		    instruction using destination
		  - PMP check for hlvx and  hypervisor fetch and store was
		    incorrect (when allowed in PTE)
		  - wrong fault on W-only pages with ext_zicfiss but SS
		    disabled
		  - no illegal instruction exception for sfence.vma and
		    reading satp when supervisor mode not implemented
		  - CSR stimecmp was readable when not implemented

2024-11-05	SPIMCTRL: Input signal 'RSTADDRM' added which can be used
		to select the reset value of the extended address mode
		configuration.

2024-10-11	SPIMCTRL: 'allow_writes' configuration now set as register
        	bit. Old VHDL generic is kept and is instead used as reset
		value for the new register bit.

2024-10-04	SPIMCTRL: support for several SPI memories
		The core now supports the use of up to four chip select
		signals. It can either be configured to always communicate
		with one out of the four devices, or instead use bit pairs
		from the address to select which device to use. The second
		approach allows a continuous view into the four memories
		in the SPIMCTRL ROM address region.

grlib-gpl-2024.2-b4293

----------------------- Release 2024.2-b4293 ---------------------------

2024-07-09	Added support for Lattice Nexus FPGAs.
		- Techmap support for nexus primitives.
		- Template designs for LEON3, LEON5 and NOEL-V targeting
		  CrossLink, Certus and CertusPro FPGAs.

2024-06-30	NOEL-V:
		- Writes to HPMCOUNTERs are now single-issued
		- MCONTROL6: The 32 MSBs of the address were masked when
		  setting a breakpoint
		- Accessing htimedeltah, henvcfgh and stimecmph could
		  generate incorrect exception code
		- HGATP: change to not clear all fields when illegal
		  mode is set
		- Update fence instruction to stall until write-buffer
		  and current snoop access has completed
		- hfence instruction did not cause illegal instruction
		  exception when executed in U-mode
		- PMPCFG: change behavior on illegal NA4 mode
		- CBO: did not stall until tag update was completed.
		  Forwarding for address generation was not correct
		- SC: returned incorrect value is some corner cases
		- Some code rewrite to workaround issues with some
		  version of the DC tool
		- The extra two bits in guest physical addresses was not
		  stored in the TLB
		- APLIC: when interrupt was delegated to S-mode it was
		  also forwarded to M-mode

2024-06-24	APBUART16550 documentation added to grip.pdf

grlib-gpl-2024.2-b4293

----------------------- Release 2024.2-b4293 ---------------------------

2024-07-09	Added support for Lattice Nexus FPGAs.
		- Techmap support for nexus primitives.
		- Template designs for LEON3, LEON5 and NOEL-V targeting
		  CrossLink, Certus and CertusPro FPGAs.

2024-06-30	NOEL-V:
		- Writes to HPMCOUNTERs are now single-issued
		- MCONTROL6: The 32 MSBs of the address were masked when
		  setting a breakpoint
		- Accessing htimedeltah, henvcfgh and stimecmph could
		  generate incorrect exception code
		- HGATP: change to not clear all fields when illegal
		  mode is set
		- Update fence instruction to stall until write-buffer
		  and current snoop access has completed
		- hfence instruction did not cause illegal instruction
		  exception when executed in U-mode
		- PMPCFG: change behavior on illegal NA4 mode
		- CBO: did not stall until tag update was completed.
		  Forwarding for address generation was not correct
		- SC: returned incorrect value is some corner cases
		- Some code rewrite to workaround issues with some
		  version of the DC tool
		- The extra two bits in guest physical addresses was not
		  stored in the TLB
		- APLIC: when interrupt was delegated to S-mode it was
		  also forwarded to M-mode

2024-06-24	APBUART16550 documentation added to grip.pdf

grlib-gpl-2024.1-b4292

----------------------- Release 2024.1-b4292 ---------------------------

2024-04-18	L2C_LITE: Fixed backend io address to provide an AMBA
		AHB BAR that can be scanned for PnP information of the
		bus behind the L2C_LITE.
		Fixed the index addressing bug introduced in the
		2024.1-b4291 release.

2024-04-15	LEON5: Fixed bus access corner case where HBUSREQ was
		deasserted too early if wbmask=0 was combined with
		busw>32.
		Fixed bus access corner case where HTRANS(0) would
		remain asserted if bus grant was lost in the middle of
		a burst fetch of a cache line. The AHBCTRL would never
		have rearbitrated the bus in this instance since HBUSREQ
		remained asserted, but AMBA 2.0 compliant AHB arbiters
		are allowed to do this.

2024-04-15	NOEL-V updates
		- Fixed minor issue with instret CSR
		- Code rework to fix tool issues with single-issue
		  configuration

grlib-gpl-2024.1-b4291

----------------------- Release 2024.1-b4291 ---------------------------

2024-03-21	NOEL-V updates
		- Added system bus access support for debug-module
		- Now interrupt is allowed on CSR writes
		- Fixed issue with ICOUNT trigger and CSR VSATP, INSTRET
		- Improve branch prediction when C-extension is disabled
		- CSR read with debug-module can now return error
		- Only supported values can now be written to DCSR
		- BTB is not flushed when entering debug mode
		- NOEL-V subsystem: added 16550UART and removed dummy
		  AHB bridge

2024-03-19	LEON5: Fix for MMU probe ASI, could perform unnecessary
		read access during table walk when set to stop at PTD.

2024-02-22	leon5-xilinx-vcu128: Leon5 template design for Xilinx
		VCU128 added.

2024-01-30	LEON5/TECHMAP: Added new mapping for syncram with
		built in data loop back to allow for large TCM timing
		optimizations.

2024-01-25	Documentation updates.
		IRQMP:
		- Added interrupt remapping and extended interrupts to block
		  diagram.
		- Added software usage note on level interrupts.
		GPTIMER:
		- Clarified additional consequences of the shared decrementer.

2024-01-18	LEON5: Add support for TCM with non power-of-two size,
		where only a fraction of the TCM space is backed by
		memory. This is to allow finer control of TCM size.

2024-01-18	LEON5: Bugfix for data_store_error trap delivery
		introduced in release 2023.2.

grlib-gpl-2023.4-b4288

----------------------- Release 2023.4-b4288 ---------------------------

2023-11-28	NOEL-V: updates
		- Trigger updates:
		  - Added interrupt and exception triggers
		  - Update to mcontrol6
		  - Fixed watchpoint triggering on sfence instructions
		- Debug module: Added halt and resume groups
		- Misaligned load/stores didn't write a transformed instruction
		  into [mh]tinst
		- Updated performance counter event encoding

2023-11-06	LEON3,LEON5: Allow clearing high bits of time stamp
		counter through debug interface to allow clean restart
		through GRMON.

2023-11-06	LEON5: Support 63-bit wide time stamp counter in HP
		configuration (perfcfg=0).

2023-10-27	NOEL-V: updates
		- Reenable RAS
		- Added Svinval extension
		- Instruction trace updated
		- Fixed half-persision fsqrt inexact issue
		- Fixed minor issue related to H extension (HIE, GVA, MVP, HGEIP, HGSATP)
		- Fault type could be wrong related to page-tables
		- Fixed access issue for Sstc CSRs

2023-10-27	APLIC: Added support for interrupt domains

2023-10-23	GRDMAC2: Issue fix for timeout mechanism checking TRST register
		even when TE bit is not set in CTRL register.

2023-10-02	LEON5-ALTERA-C5EKIT: Set edclsepahb signal to Ethernet
		cores to route EDCL accesses to debug module.

2023-10-02	LEON5: Instruction TCM bugfixes.

		Under some conditions following a pipeline stall when executing
		out of ITCM, the cache controller could deliver stale data
		from the Icache RAMs instead of from the ITCM data memories.

		Write to ASI 0x26 could in some cases also cause a write into
		instruction cache data RAMs.

2023-10-02	LEON5: Code reorganization. Move decoding of perfcfg generic
		up to leon5sys level.

2023-10-02	LEON3/LEON5-ALTERA-C5EKIT: Change default IRQ assignment of
		Ethernet cores.

2023-09-29	NOEL-V: updates
		- Code rewrite to support Synopsys DC and FM better.

2023-08-15	L2C-Lite: Major architectural update. Backends available:
		AHB, AXI3, AXI4. Functional updates:
		- Turn on/off Cache.
		- Select replacement policy, 0 -> random, 1 -> psuedo LRU
		  (Probe bit to see if pLRU can enabled).
		- New flush modes: Flush, Flush+Invalidate, Invalidate,
		  Flush address, Flush+Invalidate address.
		- Diagnostics interface: Read/write cachelines and tag+v+d
		  data.

2023-08-15	AHB2AXIB: Added support for BUSY HTRANS.

2023-07-25	AHBCTRL simulation trace:
		Added option to select between printing either full HWDATA/
		HRDATA contents, or the subword selected by HSIZE/HADDR/
		ahbendian.

grlib-gpl-2023.2-b4283

----------------------- Release 2023.2-b4283 ---------------------------

2023-06-09	LEON5 updates:
		- Implemented data_store_error trap with configurable handling
		  of special cases (such as interrupt between store and error)
		- Implemented internal cache error trap for critical errors
		  (duplicated tags detected)
		- Add cache trap register to record delivered and pending and
		  traps from cache controller.
		- Support write combining mode based on explicit hint
		  instructions instead of always waiting for following store
		- Add full barrier and write combining hint using existing
		  STBAR opcode (consistent with SPARC V9 MEMBAR)

2023-05-25	AHBCTRL simulation trace updates:
		- Print correct slice for narrow accesses on little endian
		  buses.
		- Trace SPLIT and RETRY responses in addition to OKAY and ERROR.
		- Optionally prefix each trace line with bus index and/or a
		  custom debug tag provided as a generic. Intended for
		  multi-bus systems.

2023-05-25	AHBJTAG and TAP techmap:
		- TAP techmap now uses BSCANE2_TAP for all Xilinx technologies
		  where the built-in TAP is accessed using a BSCANE2 primitive.
		- Added new generic taptecharg in AHBJTAG which is passed to
		  the TAP techmap. Currently used only by BSCANE2_TAP to
		  select an alternate user scan chain.
		- JTAGTST jread procedure now supports custom ainst/dinst/isize.
		- AHBJTAG documentation updated.

grlib-gpl-2023.1-b4282

----------------------- Release 2023.1-b4282 ---------------------------

2023-04-27	LEON5: Minor fix to snooping on stores. Stores and atomics to
		ASI 1 activated the snooping and caused the cache line to be
		invalidated unnecessarily.

2023-04-27	LEON5: Bug fix for diagnostic data cache tag access (ASI 0x0E).
		Valid bits could be read out incorrectly in configurations
		where the valid bits are held in flip flops (cmemconf=2).

2023-04-27	LEON5: Bug fixes for MMU TLB flush and probe (ASI 0x1B).

2023-04-18	LEON5: Bugfix for AHB retry corner case during DCache fetch

2023-04-11	LEON5: Bugfix for breaking execution from debug module while
		an atomic operation is in progress.

2023-04-06	NOEL-V: NOEL-V and RISC-V peripherals updates
		- Added AIA interrupt controller (disabled in default config.)
		- Added ACLINT to replacing CLINT
		- Added UART interface register compatible with 16550 spec.
		- Added RISC-V watchdog
		- Debug module updates (removed internal AHB2AHB bridge)
		- PnP for NOELVSYS is updated to place internal APB bus first.
		- TLB flush updates (separate flush for sTLB and hTLB,
		  Address/VMID/ASID matching)
		- Added Diagnostic access to TLBs
		- Update STVEC/VSTVEC to have 256 byte alignment in vectored mode.
		- Added ISA extensions:
		  - Zcb, Zfhmin, Zfh, Smstateen
		  - Smepmp, Zicond, Zfa, Smrnmi (experimental)
		- Bug fixes:
		  - Store byte followed by sfence.vma prevent update the cache
		  - Instruction c.zext.w was not illegal on 32-bit version
		  - Zicbom instructions could operate in incorrect cache line
		  - Incorrect mask for hedeleg
		  - Minor FPU updates

2023-03-30	LEON5: Minor fixes for debug module access while cache
		controller still has an ongoing access.

2023-03-27	SYNCFIFO_2P: Add scantest generic to propagate down to
		syncram_2p instances.

2023-03-06	LEON5: Increase number of timers in the gptimer in
		standard LEON5SYS configurations from 2 to 3.

2023-02-09	APBUART systest: Fix to the initial loop to fill the
		holding register to avoid X issues in simulation.

2023-02-07	LEON5: Bug fixes related to breaking/resuming execution
		and single stepping.

2023-01-30	APBUART: Modification of simulation mode (console=1)
		When console=1, reads of the status register now return
		values consistent with the transmitter shift register and
		transmitter FIFO being empty. This should make the console=1
		configuration compatible with existing software. Notably,
		BCC2 was not entirely compatible prior to this change.

2023-01-23	LEON5: Cache controller updates
		- Added write combining feature for double stores, enabled
		via LEON5 configuration register bit. Combines stores to
		consecutive addresses into larger bursts up to cache line
		boundary.
		- Minor change to debug access handling in order to remove
		some timing critical paths.
		- Fixes to HPROT generation for store accesses, bit 1 not
		always reflecting supervisor status correctly for that
		store.

2023-01-11	LEON5: Various improvements / fixes related to stores
		- Make stores propagate through to the AHB bus one cycle
		faster in some cases.
		- Make HBURST drive HBURST_SINGLE for MMU page table
		accesses (to allow for re-arbitration in the AHB arbiter).
		- Ensure bus lock is always dropped between locked store
		and any following regular stores.
		- Bug fixes to HBUSREQ signal generation and RETRY/SPLIT
		handling during 32-bit write burst (double store to narrow
		area functionality added recently).

2022-12-21	APBUART
		- Fixed bug where two stopbits were only sent when parity
		was enabled.
		- GRIP: stopbit setting has no effect on the receiver
		- GRIP: corrected description of receiver input filtering
		- GRIP: parity gen

2022-12-20	LEON5: Improved store performance when used with
		32-bit AHB buses. Stores to narrow (32-bit) areas
		now go through the store buffer/FIFO without blocking
		the pipeline similar to the wider case, with double
		stores performed as two-beat bursts.