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GaislerAleks-Daniel Jakimenko-Aleksejev
Gaisler
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Aleks-Daniel Jakimenko-Aleksejev
committed
grlib-gpl-2025.2-b4298
----------------------- Release 2025.2-b4298 --------------------------- 2025-06-30 NOEL-V updates: - Update interrupt port definition (new record type) - Prevent H-extension to be enabled for RV32 (currently not supported) - MC standard configuration has been updated to increase L1 to 4-way and remove double-precision floating-point (only supporting F extension) - The double-trap extension (smdbltr and ssdbltrp) have been updated version 1.0 - Update to CSR handling (illegal checks, and exceptions) - Added shlcofideleg and smcdeleg extension - Added SVADU extension - PLIC now supports more then 31 interrupt sources - Custom FEATURE CSR updated (bits has been redefined) - Added support for Svnapot extension and Sv48 - Update illegal checks for CBO instructions - APLIC: base_ppn field was not shifted 12 bits to the left to calculate the IMSIC base address. - G-stage access fault was raised instead of page fault for some cases - Fixed issue with PMA/PMP check during page-walk - Fix to not update m/htinst on shadowstack push/pop exceptions - Fixed incorrect fault for CFI landing pad faults - Executing ssamoswap in machine mode was not handled correctly - Update Smstateen extension to incorporate the bits p1p13 & C. - Modify write behavior of bits in hstateen/sstateen, if mstateen.bit is 0 then hstateen.bit/sstateen.bit is no longer writeable and previous bits are preserved. - Update envcfg to incorporate read-only behavior for bits not set in higher privilege mode envcfg. Example) if menvcfg.sse = 0 => RO (s/h)envcfg.sse. Previous bits preserved. - Update CBO and ssamoswap exception behavior, these instructions could previously throw a virtual instruction exception even if its menvcfg bit was 0. 2025-06-25 TECHMAP: Add UltraScale/UltraScale-Plus mapping for DDR_OREG 2025-06-24 AHB2AXIB: new generic to support AMBA address widths of more than 32 bits (not compatible yet with PnP scanning). 2025-06-17 APBUART: Added break character support - Increased APBUART revision to 2 - Updated the core to support transmission and detection of break characters within a configurable range of 10-16 zeroes. Break operation is managed via the control register of the apb bus. - Enabled break handling in loop-back operation - Added a capability register that reports the values for certain RTL instantiation generics, including FIFO size and flow - The debug bit in the control register is now read-only. Read/write access for debug functionality has been relocated to the FIFO debug control register. 2025-06-16 GRGPIO: Added set and clear register support to facilitate atomic accesses to selected registers. 2025-06-10 BCC: BCC1 to BCC2 migration - Affects systest in designs directory 2025-06-09 LEON5: Fix issue on LDSTUB/LDSTUBA opcode check 2025-05-23 LEON5: DTCM Fixes - Fix an issue where ASI accesses where triggering unwanted dtcmhit. 2025-04-16 AXI2AHB: fix simultaneous read and write accesses 2025-04-03 GRDMAC2: Incorrect calculation of the burst_chop_mask generic value in generic_bm instantiation is fixed. generic_bm_ahb instantiation in the grdmac2 has the default value 1024 for burst_chop_mask generic.
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‎README.md‎

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@@ -11,6 +11,7 @@ is available. This repository is an attempt to fix the situation.
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| Release name | Available? |
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|--------------------------|------------|
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| grlib-gpl-2025.2-b4298 | Yes |
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| grlib-gpl-2025.1-b4296 | Yes |
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| grlib-gpl-2024.4-b4295 | Yes |
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| grlib-gpl-2024.2-b4293 | Yes |

‎bin/Makefile‎

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VER=$(VNAME)2025.1
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BID=4296
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VER=$(VNAME)2025.2
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BID=4298
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CC=gcc
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SED=sed
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‎boards/lattice-lfcpnx-evn/lattice_ips/lifcl/osc/lattice_osc.cfg‎

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{
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"HF_OSC_EN": "DISABLED",
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"LF_OUTPUT_EN": "DISABLED",
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"SEDCLK_EN": 1,
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"SEDSEC_CLK_FREQ": 1.8,
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"LMMI_CLK_EN": "DISABLED"
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}

‎boards/lattice-lfcpnx-evn/lattice_ips/lifcl/osc/osc50.cfg‎

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{
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"HF_OSC_EN": "ENABLED",
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"HF_CLK_FREQ": 50.0,
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"LF_OUTPUT_EN": "DISABLED",
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"SEDCLK_EN": 1,
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"SEDSEC_CLK_FREQ": 50.0,
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"LMMI_CLK_EN": "DISABLED"
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}

‎boards/lattice-lfcpnx-evn/lattice_ips/lifcl/osc/osc_cram_sedc_25o.cfg‎

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{
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"HF_OSC_EN": "DISABLED",
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"LF_OUTPUT_EN": "DISABLED",
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"SEDCLK_EN": 1,
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"SEDSEC_CLK_FREQ": 25.0,
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"LMMI_CLK_EN": "DISABLED"
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}

‎boards/lattice-lfcpnx-evn/lattice_ips/lifcl/osc/osc_cram_sedc_50o.cfg‎

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{
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"HF_OSC_EN": "DISABLED",
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"LF_OUTPUT_EN": "DISABLED",
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"SEDCLK_EN": 1,
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"SEDSEC_CLK_FREQ": 50.0,
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"LMMI_CLK_EN": "DISABLED"
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}

‎boards/lattice-lfcpnx-evn/lattice_ips/lifcl/sedc/cram_sedc.cfg‎

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{}

‎designs/leon3-digilent-arty-a7/systest.c‎

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#include <report.h>
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#include <gpio.h>
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#include <spictrl.h>
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main()
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int __bcc_cfg_skip_clear_bss;
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static const uintptr_t GPIO1_REGS = 0x80000a00u;
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static const uintptr_t GPIO1_PIRQ = 6;
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static const uintptr_t SPICTRL0_REGS = 0x80000600u;
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static const uintptr_t SPICTRL0_PIRQ = 5;
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int main(void)
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{
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report_start();
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gpio_test(GPIO1_REGS);
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gpio_test_irq(GPIO1_REGS, GPIO1_PIRQ);
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spictrl_test(SPICTRL0_REGS, 0);
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spictrl_test(SPICTRL0_REGS, 1);
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spictrl_irqtest(SPICTRL0_REGS, SPICTRL0_PIRQ);
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base_test();
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report_end();
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return 0;
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}
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‎designs/leon3-digilent-arty-a7/testbench.vhd‎

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signal cpu_resetn : std_ulogic;
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-- Switches
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signal sw : std_logic_vector(3 downto 0);
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-- PMOD
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signal jabcd : std_logic_vector(31 downto 0);
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-- Arduino/ChipKit SPI
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signal ck_miso : std_ulogic;
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signal ck_mosi : std_ulogic;
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-- USB-RS232 interface
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signal uart_tx_in : std_logic;
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signal uart_rx_out : std_logic;
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-- dsui.enable
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sw(3) <= '1';
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jabcd <= (others => 'H');
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ck_miso <= ck_mosi;
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d3 : entity work.leon3mp
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generic map (fabtech, memtech, padtech, clktech, disas, dbguart, pclow,
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SIM_BYPASS_INIT_CAL, SIMULATION, USE_MIG_INTERFACE_MODEL)
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ck_rst => ck_rst,
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btn => btn,
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sw => sw,
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ck_miso => '1',
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ja => jabcd( 7 downto 0),
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jb => jabcd(15 downto 8),
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jc => jabcd(23 downto 16),
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jd => jabcd(31 downto 24),
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ck_miso => ck_miso,
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ck_mosi => ck_mosi,
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uart_txd_in => '1',
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uart_rxd_out => open,
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qspi_sck => qspi_sck,

‎designs/leon3-gr-xc3s-1500/Makefile‎

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LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
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tmtc openchip hynix cypress ihp gsi fmf spansion
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DIRSKIP = b1553 pci/pcif leon2 leon2ft crypto satcan pci leon3ft ambatest ddr \
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leon4v0 l2cache/v2 l2cache/v3 gr1553b iommu ascs slink pwm \
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leon4v0 l2cache/v2 l2cache/v3 l2cache/str gr1553b iommu ascs slink pwm \
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ge_1000baseX canfd \
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leon5v0 leon5v0/blockred grfpu5 noelv noelv/subsys riscv
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FILESKIP = grcan.vhd adapters/sgmii.vhd \

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