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grlib-gpl-2023.2-b4283
----------------------- Release 2023.2-b4283 --------------------------- 2023-06-09 LEON5 updates: - Implemented data_store_error trap with configurable handling of special cases (such as interrupt between store and error) - Implemented internal cache error trap for critical errors (duplicated tags detected) - Add cache trap register to record delivered and pending and traps from cache controller. - Support write combining mode based on explicit hint instructions instead of always waiting for following store - Add full barrier and write combining hint using existing STBAR opcode (consistent with SPARC V9 MEMBAR) 2023-05-25 AHBCTRL simulation trace updates: - Print correct slice for narrow accesses on little endian buses. - Trace SPLIT and RETRY responses in addition to OKAY and ERROR. - Optionally prefix each trace line with bus index and/or a custom debug tag provided as a generic. Intended for multi-bus systems. 2023-05-25 AHBJTAG and TAP techmap: - TAP techmap now uses BSCANE2_TAP for all Xilinx technologies where the built-in TAP is accessed using a BSCANE2 primitive. - Added new generic taptecharg in AHBJTAG which is passed to the TAP techmap. Currently used only by BSCANE2_TAP to select an alternate user scan chain. - JTAGTST jread procedure now supports custom ainst/dinst/isize. - AHBJTAG documentation updated.
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README.md

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| Release name | Available? |
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|--------------------------|------------|
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| grlib-gpl-2023.2-b4283 | Yes |
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| grlib-gpl-2023.1-b4282 | Yes |
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| grlib-gpl-2022.4-b4280 | Yes |
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| grlib-gpl-2022.2-b4274 | Yes |

bin/Makefile

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VER=$(VNAME)2023.1
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BID=4282
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VER=$(VNAME)2023.2
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BID=4283
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CC=gcc
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SED=sed
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designs/leon3-digilent-arty-a7/.config

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# CONFIG_SYN_INFER_PADS is not set
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# CONFIG_SYN_NO_ASYNC is not set
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# CONFIG_SYN_SCAN is not set
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# CONFIG_FPGA_A100 is not set
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CONFIG_FPGA_A35=y
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# CONFIG_FPGA_A35 is not set
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CONFIG_FPGA_A100=y
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#
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# Clock generation

designs/leon3-digilent-arty-a7/Makefile

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TOP=leon3mp
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BOARD=digilent-arty-a7
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DESIGN=thesign
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DESIGN=leon3-digilent-arty-a7
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BOARDDIR=$(GRLIB)/boards/$(BOARD)
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include $(BOARDDIR)/Makefile.inc
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designs/leon3-digilent-arty-a7/README.txt

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interactive session with Vivado. To program the FPGA in batch mode, use
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'make vivprog'. To program the configuration flash, use 'make vivrom'.
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XC7A35T is the default target FPGA. To change the target to XC7A100T,
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XC7A100T is the default target FPGA. To change the target to XC7A35T,
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change FPGA type in xconfig in the "Synthesis" section.
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The design uses the Xilinx MIG memory interface with an AHB-2.0

designs/leon5-altera-c5ekit/Makefile

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GRLIB_CONFIG=grlib_config.vhd
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GRLIB=../..
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TOP=leon5mp
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BOARD=altera-c5ekit
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/*
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* BCC2 link-time configuration to speed up simulation:
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* - Disable all AMBA Plug&Play scanning
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*
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* See bcc/bcc_param.h for more information
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*/
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#include <bcc/bcc_param.h>
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#if 1
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/*
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* Define a global variable named __bcc_cfg_skip_clear_bss to prevent
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* initialize .bss section at BCC run-time initialization. The value of the
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* variable does not matter.
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*/
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int __bcc_cfg_skip_clear_bss;
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#endif
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int __bcc_con_init(void) {
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__bcc_con_handle = 0;
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return 0;
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}
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int __bcc_timer_init(void) {
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__bcc_timer_handle = 0;
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return 0;
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}
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int __bcc_int_init(void) {
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__bcc_int_handle = 0;
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__bcc_int_irqmp_eirq = 0;
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return 0;
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}
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designs/leon5-altera-c5ekit/config.vhd

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--LEON5 processor system
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constant CFG_NCPU : integer := (1);
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constant CFG_FPUTYPE : integer := 0;
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constant CFG_AHBW : integer := 32;
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constant CFG_BWMASK : integer := 16#0000#;
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constant CFG_AHBW : integer := 64;
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constant CFG_BWMASK : integer := 16#00f0#;
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constant CFG_DFIXED : integer := 16#0#;
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-- DSU UART
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constant CFG_AHB_UART : integer := 1;
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------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003 - 2008, Gaisler Research
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-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
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-- Copyright (C) 2015 - 2023, Cobham Gaisler
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-- Copyright (C) 2023, Frontgrade Gaisler
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; version 2.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-----------------------------------------------------------------------------
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-- Package: config
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-- File: config.vhd
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-- Description: GRLIB Global configuration package. Can be overriden
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-- by local config packages in template designs.
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library grlib;
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use grlib.config_types.all;
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package config is
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-- AHBDW - AHB data with
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--
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-- Valid values are 32, 64, 128 and 256
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--
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-- The value here sets the width of the AMBA AHB data vectors for all
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-- cores in the library.
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--
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constant CFG_AHBDW : integer := 64;
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-- CFG_AHB_ACDM - Enable AMBA Compliant Data Muxing in cores
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--
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-- Valid values are 0 and 1
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--
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-- 0: All GRLIB cores that use the ahbread* programs defined in the AMBA package
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-- will read their data from the low part of the AHB data vector.
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--
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-- 1: All GRLIB cores that use the ahbread* programs defined in the AMBA package
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-- will select valid data, as defined in the AMBA AHB standard, from the
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-- AHB data vectors based on the address input. If a core uses a function
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-- that does not have the address input, a failure will be asserted.
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--
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-- The value of CFG_AHB_ACDM is assigned to the constant CORE_ACDM in the
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-- grlib.amba package. Note that this setting is separate from the ACDM setting
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-- of the AHBCTRL core (which is set directly via a AHBCTRL VHDL generic).
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--
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constant CFG_AHB_ACDM : integer := 0;
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-- GRLIB_CONFIG_ARRAY - Array of configuration values
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--
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-- The length of this array and the meaning of different positions is defined
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-- in the grlib.config_types package.
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constant GRLIB_CONFIG_ARRAY : grlib_config_array_type := (
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grlib_debug_level => 0,
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grlib_debug_mask => 0,
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grlib_techmap_strict_ram => 0,
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grlib_techmap_testin_extra => 0,
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grlib_sync_reset_enable_all => 0,
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grlib_async_reset_enable => 0,
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grlib_amba_inc_nirq => 0,
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grlib_little_endian => 0,
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others => 0);
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end;
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