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fm801.c
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/*
* The driver for the ForteMedia FM801 based soundcards
* Copyright (c) by Jaroslav Kysela <perex@suse.cz>
*
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#include <sound/driver.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/moduleparam.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/ac97_codec.h>
#include <sound/mpu401.h>
#include <sound/opl3.h>
#include <sound/initval.h>
#include <asm/io.h>
#if (defined(CONFIG_SND_FM801_TEA575X) || defined(CONFIG_SND_FM801_TEA575X_MODULE)) && (defined(CONFIG_VIDEO_DEV) || defined(CONFIG_VIDEO_DEV_MODULE))
#include <sound/tea575x-tuner.h>
#define TEA575X_RADIO 1
#endif
MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>");
MODULE_DESCRIPTION("ForteMedia FM801");
MODULE_LICENSE("GPL");
MODULE_SUPPORTED_DEVICE("{{ForteMedia,FM801},"
"{Genius,SoundMaker Live 5.1}}");
static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
/*
* Enable TEA575x tuner
* 1 = MediaForte 256-PCS
* 2 = MediaForte 256-PCPR
* 3 = MediaForte 64-PCR
* High 16-bits are video (radio) device number + 1
*/
static int tea575x_tuner[SNDRV_CARDS] = { [0 ... (SNDRV_CARDS-1)] = 0 };
module_param_array(index, int, NULL, 0444);
MODULE_PARM_DESC(index, "Index value for the FM801 soundcard.");
module_param_array(id, charp, NULL, 0444);
MODULE_PARM_DESC(id, "ID string for the FM801 soundcard.");
module_param_array(enable, bool, NULL, 0444);
MODULE_PARM_DESC(enable, "Enable FM801 soundcard.");
module_param_array(tea575x_tuner, int, NULL, 0444);
MODULE_PARM_DESC(tea575x_tuner, "Enable TEA575x tuner.");
/*
* Direct registers
*/
#define FM801_REG(chip, reg) (chip->port + FM801_##reg)
#define FM801_PCM_VOL 0x00 /* PCM Output Volume */
#define FM801_FM_VOL 0x02 /* FM Output Volume */
#define FM801_I2S_VOL 0x04 /* I2S Volume */
#define FM801_REC_SRC 0x06 /* Record Source */
#define FM801_PLY_CTRL 0x08 /* Playback Control */
#define FM801_PLY_COUNT 0x0a /* Playback Count */
#define FM801_PLY_BUF1 0x0c /* Playback Bufer I */
#define FM801_PLY_BUF2 0x10 /* Playback Buffer II */
#define FM801_CAP_CTRL 0x14 /* Capture Control */
#define FM801_CAP_COUNT 0x16 /* Capture Count */
#define FM801_CAP_BUF1 0x18 /* Capture Buffer I */
#define FM801_CAP_BUF2 0x1c /* Capture Buffer II */
#define FM801_CODEC_CTRL 0x22 /* Codec Control */
#define FM801_I2S_MODE 0x24 /* I2S Mode Control */
#define FM801_VOLUME 0x26 /* Volume Up/Down/Mute Status */
#define FM801_I2C_CTRL 0x29 /* I2C Control */
#define FM801_AC97_CMD 0x2a /* AC'97 Command */
#define FM801_AC97_DATA 0x2c /* AC'97 Data */
#define FM801_MPU401_DATA 0x30 /* MPU401 Data */
#define FM801_MPU401_CMD 0x31 /* MPU401 Command */
#define FM801_GPIO_CTRL 0x52 /* General Purpose I/O Control */
#define FM801_GEN_CTRL 0x54 /* General Control */
#define FM801_IRQ_MASK 0x56 /* Interrupt Mask */
#define FM801_IRQ_STATUS 0x5a /* Interrupt Status */
#define FM801_OPL3_BANK0 0x68 /* OPL3 Status Read / Bank 0 Write */
#define FM801_OPL3_DATA0 0x69 /* OPL3 Data 0 Write */
#define FM801_OPL3_BANK1 0x6a /* OPL3 Bank 1 Write */
#define FM801_OPL3_DATA1 0x6b /* OPL3 Bank 1 Write */
#define FM801_POWERDOWN 0x70 /* Blocks Power Down Control */
#define FM801_AC97_ADDR_SHIFT 10
/* playback and record control register bits */
#define FM801_BUF1_LAST (1<<1)
#define FM801_BUF2_LAST (1<<2)
#define FM801_START (1<<5)
#define FM801_PAUSE (1<<6)
#define FM801_IMMED_STOP (1<<7)
#define FM801_RATE_SHIFT 8
#define FM801_RATE_MASK (15 << FM801_RATE_SHIFT)
#define FM801_CHANNELS_4 (1<<12) /* playback only */
#define FM801_CHANNELS_6 (2<<12) /* playback only */
#define FM801_CHANNELS_6MS (3<<12) /* playback only */
#define FM801_CHANNELS_MASK (3<<12)
#define FM801_16BIT (1<<14)
#define FM801_STEREO (1<<15)
/* IRQ status bits */
#define FM801_IRQ_PLAYBACK (1<<8)
#define FM801_IRQ_CAPTURE (1<<9)
#define FM801_IRQ_VOLUME (1<<14)
#define FM801_IRQ_MPU (1<<15)
/* GPIO control register */
#define FM801_GPIO_GP0 (1<<0) /* read/write */
#define FM801_GPIO_GP1 (1<<1)
#define FM801_GPIO_GP2 (1<<2)
#define FM801_GPIO_GP3 (1<<3)
#define FM801_GPIO_GP(x) (1<<(0+(x)))
#define FM801_GPIO_GD0 (1<<8) /* directions: 1 = input, 0 = output*/
#define FM801_GPIO_GD1 (1<<9)
#define FM801_GPIO_GD2 (1<<10)
#define FM801_GPIO_GD3 (1<<11)
#define FM801_GPIO_GD(x) (1<<(8+(x)))
#define FM801_GPIO_GS0 (1<<12) /* function select: */
#define FM801_GPIO_GS1 (1<<13) /* 1 = GPIO */
#define FM801_GPIO_GS2 (1<<14) /* 0 = other (S/PDIF, VOL) */
#define FM801_GPIO_GS3 (1<<15)
#define FM801_GPIO_GS(x) (1<<(12+(x)))
/*
*/
typedef struct _snd_fm801 fm801_t;
struct _snd_fm801 {
int irq;
unsigned long port; /* I/O port number */
unsigned int multichannel: 1, /* multichannel support */
secondary: 1; /* secondary codec */
unsigned char secondary_addr; /* address of the secondary codec */
unsigned short ply_ctrl; /* playback control */
unsigned short cap_ctrl; /* capture control */
unsigned long ply_buffer;
unsigned int ply_buf;
unsigned int ply_count;
unsigned int ply_size;
unsigned int ply_pos;
unsigned long cap_buffer;
unsigned int cap_buf;
unsigned int cap_count;
unsigned int cap_size;
unsigned int cap_pos;
ac97_bus_t *ac97_bus;
ac97_t *ac97;
ac97_t *ac97_sec;
struct pci_dev *pci;
snd_card_t *card;
snd_pcm_t *pcm;
snd_rawmidi_t *rmidi;
snd_pcm_substream_t *playback_substream;
snd_pcm_substream_t *capture_substream;
unsigned int p_dma_size;
unsigned int c_dma_size;
spinlock_t reg_lock;
snd_info_entry_t *proc_entry;
#ifdef TEA575X_RADIO
tea575x_t tea;
#endif
};
static struct pci_device_id snd_fm801_ids[] = {
{ 0x1319, 0x0801, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0, }, /* FM801 */
{ 0, }
};
MODULE_DEVICE_TABLE(pci, snd_fm801_ids);
/*
* common I/O routines
*/
static int snd_fm801_update_bits(fm801_t *chip, unsigned short reg,
unsigned short mask, unsigned short value)
{
int change;
unsigned long flags;
unsigned short old, new;
spin_lock_irqsave(&chip->reg_lock, flags);
old = inw(chip->port + reg);
new = (old & ~mask) | value;
change = old != new;
if (change)
outw(new, chip->port + reg);
spin_unlock_irqrestore(&chip->reg_lock, flags);
return change;
}
static void snd_fm801_codec_write(ac97_t *ac97,
unsigned short reg,
unsigned short val)
{
fm801_t *chip = ac97->private_data;
int idx;
/*
* Wait until the codec interface is not ready..
*/
for (idx = 0; idx < 100; idx++) {
if (!(inw(FM801_REG(chip, AC97_CMD)) & (1<<9)))
goto ok1;
udelay(10);
}
snd_printk("AC'97 interface is busy (1)\n");
return;
ok1:
/* write data and address */
outw(val, FM801_REG(chip, AC97_DATA));
outw(reg | (ac97->addr << FM801_AC97_ADDR_SHIFT), FM801_REG(chip, AC97_CMD));
/*
* Wait until the write command is not completed..
*/
for (idx = 0; idx < 1000; idx++) {
if (!(inw(FM801_REG(chip, AC97_CMD)) & (1<<9)))
return;
udelay(10);
}
snd_printk("AC'97 interface #%d is busy (2)\n", ac97->num);
}
static unsigned short snd_fm801_codec_read(ac97_t *ac97, unsigned short reg)
{
fm801_t *chip = ac97->private_data;
int idx;
/*
* Wait until the codec interface is not ready..
*/
for (idx = 0; idx < 100; idx++) {
if (!(inw(FM801_REG(chip, AC97_CMD)) & (1<<9)))
goto ok1;
udelay(10);
}
snd_printk("AC'97 interface is busy (1)\n");
return 0;
ok1:
/* read command */
outw(reg | (ac97->addr << FM801_AC97_ADDR_SHIFT) | (1<<7), FM801_REG(chip, AC97_CMD));
for (idx = 0; idx < 100; idx++) {
if (!(inw(FM801_REG(chip, AC97_CMD)) & (1<<9)))
goto ok2;
udelay(10);
}
snd_printk("AC'97 interface #%d is busy (2)\n", ac97->num);
return 0;
ok2:
for (idx = 0; idx < 1000; idx++) {
if (inw(FM801_REG(chip, AC97_CMD)) & (1<<8))
goto ok3;
udelay(10);
}
snd_printk("AC'97 interface #%d is not valid (2)\n", ac97->num);
return 0;
ok3:
return inw(FM801_REG(chip, AC97_DATA));
}
static unsigned int rates[] = {
5500, 8000, 9600, 11025,
16000, 19200, 22050, 32000,
38400, 44100, 48000
};
static snd_pcm_hw_constraint_list_t hw_constraints_rates = {
.count = ARRAY_SIZE(rates),
.list = rates,
.mask = 0,
};
static unsigned int channels[] = {
2, 4, 6
};
#define CHANNELS sizeof(channels) / sizeof(channels[0])
static snd_pcm_hw_constraint_list_t hw_constraints_channels = {
.count = CHANNELS,
.list = channels,
.mask = 0,
};
/*
* Sample rate routines
*/
static unsigned short snd_fm801_rate_bits(unsigned int rate)
{
unsigned int idx;
for (idx = 0; idx < ARRAY_SIZE(rates); idx++)
if (rates[idx] == rate)
return idx;
snd_BUG();
return ARRAY_SIZE(rates) - 1;
}
/*
* PCM part
*/
static int snd_fm801_playback_trigger(snd_pcm_substream_t * substream,
int cmd)
{
fm801_t *chip = snd_pcm_substream_chip(substream);
spin_lock(&chip->reg_lock);
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
chip->ply_ctrl &= ~(FM801_BUF1_LAST |
FM801_BUF2_LAST |
FM801_PAUSE);
chip->ply_ctrl |= FM801_START |
FM801_IMMED_STOP;
break;
case SNDRV_PCM_TRIGGER_STOP:
chip->ply_ctrl &= ~(FM801_START | FM801_PAUSE);
break;
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
chip->ply_ctrl |= FM801_PAUSE;
break;
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
chip->ply_ctrl &= ~FM801_PAUSE;
break;
default:
spin_unlock(&chip->reg_lock);
snd_BUG();
return -EINVAL;
}
outw(chip->ply_ctrl, FM801_REG(chip, PLY_CTRL));
spin_unlock(&chip->reg_lock);
return 0;
}
static int snd_fm801_capture_trigger(snd_pcm_substream_t * substream,
int cmd)
{
fm801_t *chip = snd_pcm_substream_chip(substream);
spin_lock(&chip->reg_lock);
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
chip->cap_ctrl &= ~(FM801_BUF1_LAST |
FM801_BUF2_LAST |
FM801_PAUSE);
chip->cap_ctrl |= FM801_START |
FM801_IMMED_STOP;
break;
case SNDRV_PCM_TRIGGER_STOP:
chip->cap_ctrl &= ~(FM801_START | FM801_PAUSE);
break;
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
chip->cap_ctrl |= FM801_PAUSE;
break;
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
chip->cap_ctrl &= ~FM801_PAUSE;
break;
default:
spin_unlock(&chip->reg_lock);
snd_BUG();
return -EINVAL;
}
outw(chip->cap_ctrl, FM801_REG(chip, CAP_CTRL));
spin_unlock(&chip->reg_lock);
return 0;
}
static int snd_fm801_hw_params(snd_pcm_substream_t * substream,
snd_pcm_hw_params_t * hw_params)
{
return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
}
static int snd_fm801_hw_free(snd_pcm_substream_t * substream)
{
return snd_pcm_lib_free_pages(substream);
}
static int snd_fm801_playback_prepare(snd_pcm_substream_t * substream)
{
fm801_t *chip = snd_pcm_substream_chip(substream);
snd_pcm_runtime_t *runtime = substream->runtime;
chip->ply_size = snd_pcm_lib_buffer_bytes(substream);
chip->ply_count = snd_pcm_lib_period_bytes(substream);
spin_lock_irq(&chip->reg_lock);
chip->ply_ctrl &= ~(FM801_START | FM801_16BIT |
FM801_STEREO | FM801_RATE_MASK |
FM801_CHANNELS_MASK);
if (snd_pcm_format_width(runtime->format) == 16)
chip->ply_ctrl |= FM801_16BIT;
if (runtime->channels > 1) {
chip->ply_ctrl |= FM801_STEREO;
if (runtime->channels == 4)
chip->ply_ctrl |= FM801_CHANNELS_4;
else if (runtime->channels == 6)
chip->ply_ctrl |= FM801_CHANNELS_6;
}
chip->ply_ctrl |= snd_fm801_rate_bits(runtime->rate) << FM801_RATE_SHIFT;
chip->ply_buf = 0;
outw(chip->ply_ctrl, FM801_REG(chip, PLY_CTRL));
outw(chip->ply_count - 1, FM801_REG(chip, PLY_COUNT));
chip->ply_buffer = runtime->dma_addr;
chip->ply_pos = 0;
outl(chip->ply_buffer, FM801_REG(chip, PLY_BUF1));
outl(chip->ply_buffer + (chip->ply_count % chip->ply_size), FM801_REG(chip, PLY_BUF2));
spin_unlock_irq(&chip->reg_lock);
return 0;
}
static int snd_fm801_capture_prepare(snd_pcm_substream_t * substream)
{
fm801_t *chip = snd_pcm_substream_chip(substream);
snd_pcm_runtime_t *runtime = substream->runtime;
chip->cap_size = snd_pcm_lib_buffer_bytes(substream);
chip->cap_count = snd_pcm_lib_period_bytes(substream);
spin_lock_irq(&chip->reg_lock);
chip->cap_ctrl &= ~(FM801_START | FM801_16BIT |
FM801_STEREO | FM801_RATE_MASK);
if (snd_pcm_format_width(runtime->format) == 16)
chip->cap_ctrl |= FM801_16BIT;
if (runtime->channels > 1)
chip->cap_ctrl |= FM801_STEREO;
chip->cap_ctrl |= snd_fm801_rate_bits(runtime->rate) << FM801_RATE_SHIFT;
chip->cap_buf = 0;
outw(chip->cap_ctrl, FM801_REG(chip, CAP_CTRL));
outw(chip->cap_count - 1, FM801_REG(chip, CAP_COUNT));
chip->cap_buffer = runtime->dma_addr;
chip->cap_pos = 0;
outl(chip->cap_buffer, FM801_REG(chip, CAP_BUF1));
outl(chip->cap_buffer + (chip->cap_count % chip->cap_size), FM801_REG(chip, CAP_BUF2));
spin_unlock_irq(&chip->reg_lock);
return 0;
}
static snd_pcm_uframes_t snd_fm801_playback_pointer(snd_pcm_substream_t * substream)
{
fm801_t *chip = snd_pcm_substream_chip(substream);
size_t ptr;
if (!(chip->ply_ctrl & FM801_START))
return 0;
spin_lock(&chip->reg_lock);
ptr = chip->ply_pos + (chip->ply_count - 1) - inw(FM801_REG(chip, PLY_COUNT));
if (inw(FM801_REG(chip, IRQ_STATUS)) & FM801_IRQ_PLAYBACK) {
ptr += chip->ply_count;
ptr %= chip->ply_size;
}
spin_unlock(&chip->reg_lock);
return bytes_to_frames(substream->runtime, ptr);
}
static snd_pcm_uframes_t snd_fm801_capture_pointer(snd_pcm_substream_t * substream)
{
fm801_t *chip = snd_pcm_substream_chip(substream);
size_t ptr;
if (!(chip->cap_ctrl & FM801_START))
return 0;
spin_lock(&chip->reg_lock);
ptr = chip->cap_pos + (chip->cap_count - 1) - inw(FM801_REG(chip, CAP_COUNT));
if (inw(FM801_REG(chip, IRQ_STATUS)) & FM801_IRQ_CAPTURE) {
ptr += chip->cap_count;
ptr %= chip->cap_size;
}
spin_unlock(&chip->reg_lock);
return bytes_to_frames(substream->runtime, ptr);
}
static irqreturn_t snd_fm801_interrupt(int irq, void *dev_id, struct pt_regs *regs)
{
fm801_t *chip = dev_id;
unsigned short status;
unsigned int tmp;
status = inw(FM801_REG(chip, IRQ_STATUS));
status &= FM801_IRQ_PLAYBACK|FM801_IRQ_CAPTURE|FM801_IRQ_MPU|FM801_IRQ_VOLUME;
if (! status)
return IRQ_NONE;
/* ack first */
outw(status, FM801_REG(chip, IRQ_STATUS));
if (chip->pcm && (status & FM801_IRQ_PLAYBACK) && chip->playback_substream) {
spin_lock(&chip->reg_lock);
chip->ply_buf++;
chip->ply_pos += chip->ply_count;
chip->ply_pos %= chip->ply_size;
tmp = chip->ply_pos + chip->ply_count;
tmp %= chip->ply_size;
outl(chip->ply_buffer + tmp,
(chip->ply_buf & 1) ?
FM801_REG(chip, PLY_BUF1) :
FM801_REG(chip, PLY_BUF2));
spin_unlock(&chip->reg_lock);
snd_pcm_period_elapsed(chip->playback_substream);
}
if (chip->pcm && (status & FM801_IRQ_CAPTURE) && chip->capture_substream) {
spin_lock(&chip->reg_lock);
chip->cap_buf++;
chip->cap_pos += chip->cap_count;
chip->cap_pos %= chip->cap_size;
tmp = chip->cap_pos + chip->cap_count;
tmp %= chip->cap_size;
outl(chip->cap_buffer + tmp,
(chip->cap_buf & 1) ?
FM801_REG(chip, CAP_BUF1) :
FM801_REG(chip, CAP_BUF2));
spin_unlock(&chip->reg_lock);
snd_pcm_period_elapsed(chip->capture_substream);
}
if (chip->rmidi && (status & FM801_IRQ_MPU))
snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data, regs);
if (status & FM801_IRQ_VOLUME)
;/* TODO */
return IRQ_HANDLED;
}
static snd_pcm_hardware_t snd_fm801_playback =
{
.info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_BLOCK_TRANSFER |
SNDRV_PCM_INFO_PAUSE |
SNDRV_PCM_INFO_MMAP_VALID),
.formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
.rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000,
.rate_min = 5500,
.rate_max = 48000,
.channels_min = 1,
.channels_max = 2,
.buffer_bytes_max = (128*1024),
.period_bytes_min = 64,
.period_bytes_max = (128*1024),
.periods_min = 1,
.periods_max = 1024,
.fifo_size = 0,
};
static snd_pcm_hardware_t snd_fm801_capture =
{
.info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_BLOCK_TRANSFER |
SNDRV_PCM_INFO_PAUSE |
SNDRV_PCM_INFO_MMAP_VALID),
.formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
.rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000,
.rate_min = 5500,
.rate_max = 48000,
.channels_min = 1,
.channels_max = 2,
.buffer_bytes_max = (128*1024),
.period_bytes_min = 64,
.period_bytes_max = (128*1024),
.periods_min = 1,
.periods_max = 1024,
.fifo_size = 0,
};
static int snd_fm801_playback_open(snd_pcm_substream_t * substream)
{
fm801_t *chip = snd_pcm_substream_chip(substream);
snd_pcm_runtime_t *runtime = substream->runtime;
int err;
chip->playback_substream = substream;
runtime->hw = snd_fm801_playback;
snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
if (chip->multichannel) {
runtime->hw.channels_max = 6;
snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels);
}
if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
return err;
return 0;
}
static int snd_fm801_capture_open(snd_pcm_substream_t * substream)
{
fm801_t *chip = snd_pcm_substream_chip(substream);
snd_pcm_runtime_t *runtime = substream->runtime;
int err;
chip->capture_substream = substream;
runtime->hw = snd_fm801_capture;
snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
return err;
return 0;
}
static int snd_fm801_playback_close(snd_pcm_substream_t * substream)
{
fm801_t *chip = snd_pcm_substream_chip(substream);
chip->playback_substream = NULL;
return 0;
}
static int snd_fm801_capture_close(snd_pcm_substream_t * substream)
{
fm801_t *chip = snd_pcm_substream_chip(substream);
chip->capture_substream = NULL;
return 0;
}
static snd_pcm_ops_t snd_fm801_playback_ops = {
.open = snd_fm801_playback_open,
.close = snd_fm801_playback_close,
.ioctl = snd_pcm_lib_ioctl,
.hw_params = snd_fm801_hw_params,
.hw_free = snd_fm801_hw_free,
.prepare = snd_fm801_playback_prepare,
.trigger = snd_fm801_playback_trigger,
.pointer = snd_fm801_playback_pointer,
};
static snd_pcm_ops_t snd_fm801_capture_ops = {
.open = snd_fm801_capture_open,
.close = snd_fm801_capture_close,
.ioctl = snd_pcm_lib_ioctl,
.hw_params = snd_fm801_hw_params,
.hw_free = snd_fm801_hw_free,
.prepare = snd_fm801_capture_prepare,
.trigger = snd_fm801_capture_trigger,
.pointer = snd_fm801_capture_pointer,
};
static void snd_fm801_pcm_free(snd_pcm_t *pcm)
{
fm801_t *chip = pcm->private_data;
chip->pcm = NULL;
snd_pcm_lib_preallocate_free_for_all(pcm);
}
static int __devinit snd_fm801_pcm(fm801_t *chip, int device, snd_pcm_t ** rpcm)
{
snd_pcm_t *pcm;
int err;
if (rpcm)
*rpcm = NULL;
if ((err = snd_pcm_new(chip->card, "FM801", device, 1, 1, &pcm)) < 0)
return err;
snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_fm801_playback_ops);
snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_fm801_capture_ops);
pcm->private_data = chip;
pcm->private_free = snd_fm801_pcm_free;
pcm->info_flags = 0;
strcpy(pcm->name, "FM801");
chip->pcm = pcm;
snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
snd_dma_pci_data(chip->pci),
chip->multichannel ? 128*1024 : 64*1024, 128*1024);
if (rpcm)
*rpcm = pcm;
return 0;
}
/*
* TEA5757 radio
*/
#ifdef TEA575X_RADIO
/* 256PCS GPIO numbers */
#define TEA_256PCS_DATA 1
#define TEA_256PCS_WRITE_ENABLE 2 /* inverted */
#define TEA_256PCS_BUS_CLOCK 3
static void snd_fm801_tea575x_256pcs_write(tea575x_t *tea, unsigned int val)
{
fm801_t *chip = tea->private_data;
unsigned short reg;
int i = 25;
spin_lock_irq(&chip->reg_lock);
reg = inw(FM801_REG(chip, GPIO_CTRL));
/* use GPIO lines and set write enable bit */
reg |= FM801_GPIO_GS(TEA_256PCS_DATA) |
FM801_GPIO_GS(TEA_256PCS_WRITE_ENABLE) |
FM801_GPIO_GS(TEA_256PCS_BUS_CLOCK);
/* all of lines are in the write direction */
/* clear data and clock lines */
reg &= ~(FM801_GPIO_GD(TEA_256PCS_DATA) |
FM801_GPIO_GD(TEA_256PCS_WRITE_ENABLE) |
FM801_GPIO_GD(TEA_256PCS_BUS_CLOCK) |
FM801_GPIO_GP(TEA_256PCS_DATA) |
FM801_GPIO_GP(TEA_256PCS_BUS_CLOCK) |
FM801_GPIO_GP(TEA_256PCS_WRITE_ENABLE));
outw(reg, FM801_REG(chip, GPIO_CTRL));
udelay(1);
while (i--) {
if (val & (1 << i))
reg |= FM801_GPIO_GP(TEA_256PCS_DATA);
else
reg &= ~FM801_GPIO_GP(TEA_256PCS_DATA);
outw(reg, FM801_REG(chip, GPIO_CTRL));
udelay(1);
reg |= FM801_GPIO_GP(TEA_256PCS_BUS_CLOCK);
outw(reg, FM801_REG(chip, GPIO_CTRL));
reg &= ~FM801_GPIO_GP(TEA_256PCS_BUS_CLOCK);
outw(reg, FM801_REG(chip, GPIO_CTRL));
udelay(1);
}
/* and reset the write enable bit */
reg |= FM801_GPIO_GP(TEA_256PCS_WRITE_ENABLE) |
FM801_GPIO_GP(TEA_256PCS_DATA);
outw(reg, FM801_REG(chip, GPIO_CTRL));
spin_unlock_irq(&chip->reg_lock);
}
static unsigned int snd_fm801_tea575x_256pcs_read(tea575x_t *tea)
{
fm801_t *chip = tea->private_data;
unsigned short reg;
unsigned int val = 0;
int i;
spin_lock_irq(&chip->reg_lock);
reg = inw(FM801_REG(chip, GPIO_CTRL));
/* use GPIO lines, set data direction to input */
reg |= FM801_GPIO_GS(TEA_256PCS_DATA) |
FM801_GPIO_GS(TEA_256PCS_WRITE_ENABLE) |
FM801_GPIO_GS(TEA_256PCS_BUS_CLOCK) |
FM801_GPIO_GD(TEA_256PCS_DATA) |
FM801_GPIO_GP(TEA_256PCS_DATA) |
FM801_GPIO_GP(TEA_256PCS_WRITE_ENABLE);
/* all of lines are in the write direction, except data */
/* clear data, write enable and clock lines */
reg &= ~(FM801_GPIO_GD(TEA_256PCS_WRITE_ENABLE) |
FM801_GPIO_GD(TEA_256PCS_BUS_CLOCK) |
FM801_GPIO_GP(TEA_256PCS_BUS_CLOCK));
for (i = 0; i < 24; i++) {
reg &= ~FM801_GPIO_GP(TEA_256PCS_BUS_CLOCK);
outw(reg, FM801_REG(chip, GPIO_CTRL));
udelay(1);
reg |= FM801_GPIO_GP(TEA_256PCS_BUS_CLOCK);
outw(reg, FM801_REG(chip, GPIO_CTRL));
udelay(1);
val <<= 1;
if (inw(FM801_REG(chip, GPIO_CTRL)) & FM801_GPIO_GP(TEA_256PCS_DATA))
val |= 1;
}
spin_unlock_irq(&chip->reg_lock);
return val;
}
/* 256PCPR GPIO numbers */
#define TEA_256PCPR_BUS_CLOCK 0
#define TEA_256PCPR_DATA 1
#define TEA_256PCPR_WRITE_ENABLE 2 /* inverted */
static void snd_fm801_tea575x_256pcpr_write(tea575x_t *tea, unsigned int val)
{
fm801_t *chip = tea->private_data;
unsigned short reg;
int i = 25;
spin_lock_irq(&chip->reg_lock);
reg = inw(FM801_REG(chip, GPIO_CTRL));
/* use GPIO lines and set write enable bit */
reg |= FM801_GPIO_GS(TEA_256PCPR_DATA) |
FM801_GPIO_GS(TEA_256PCPR_WRITE_ENABLE) |
FM801_GPIO_GS(TEA_256PCPR_BUS_CLOCK);
/* all of lines are in the write direction */
/* clear data and clock lines */
reg &= ~(FM801_GPIO_GD(TEA_256PCPR_DATA) |
FM801_GPIO_GD(TEA_256PCPR_WRITE_ENABLE) |
FM801_GPIO_GD(TEA_256PCPR_BUS_CLOCK) |
FM801_GPIO_GP(TEA_256PCPR_DATA) |
FM801_GPIO_GP(TEA_256PCPR_BUS_CLOCK) |
FM801_GPIO_GP(TEA_256PCPR_WRITE_ENABLE));
outw(reg, FM801_REG(chip, GPIO_CTRL));
udelay(1);
while (i--) {
if (val & (1 << i))
reg |= FM801_GPIO_GP(TEA_256PCPR_DATA);
else
reg &= ~FM801_GPIO_GP(TEA_256PCPR_DATA);
outw(reg, FM801_REG(chip, GPIO_CTRL));
udelay(1);
reg |= FM801_GPIO_GP(TEA_256PCPR_BUS_CLOCK);
outw(reg, FM801_REG(chip, GPIO_CTRL));
reg &= ~FM801_GPIO_GP(TEA_256PCPR_BUS_CLOCK);
outw(reg, FM801_REG(chip, GPIO_CTRL));
udelay(1);
}
/* and reset the write enable bit */
reg |= FM801_GPIO_GP(TEA_256PCPR_WRITE_ENABLE) |
FM801_GPIO_GP(TEA_256PCPR_DATA);
outw(reg, FM801_REG(chip, GPIO_CTRL));
spin_unlock_irq(&chip->reg_lock);
}
static unsigned int snd_fm801_tea575x_256pcpr_read(tea575x_t *tea)
{
fm801_t *chip = tea->private_data;
unsigned short reg;
unsigned int val = 0;
int i;
spin_lock_irq(&chip->reg_lock);
reg = inw(FM801_REG(chip, GPIO_CTRL));
/* use GPIO lines, set data direction to input */
reg |= FM801_GPIO_GS(TEA_256PCPR_DATA) |
FM801_GPIO_GS(TEA_256PCPR_WRITE_ENABLE) |
FM801_GPIO_GS(TEA_256PCPR_BUS_CLOCK) |
FM801_GPIO_GD(TEA_256PCPR_DATA) |
FM801_GPIO_GP(TEA_256PCPR_DATA) |
FM801_GPIO_GP(TEA_256PCPR_WRITE_ENABLE);
/* all of lines are in the write direction, except data */
/* clear data, write enable and clock lines */
reg &= ~(FM801_GPIO_GD(TEA_256PCPR_WRITE_ENABLE) |
FM801_GPIO_GD(TEA_256PCPR_BUS_CLOCK) |
FM801_GPIO_GP(TEA_256PCPR_BUS_CLOCK));
for (i = 0; i < 24; i++) {
reg &= ~FM801_GPIO_GP(TEA_256PCPR_BUS_CLOCK);
outw(reg, FM801_REG(chip, GPIO_CTRL));
udelay(1);
reg |= FM801_GPIO_GP(TEA_256PCPR_BUS_CLOCK);
outw(reg, FM801_REG(chip, GPIO_CTRL));
udelay(1);
val <<= 1;
if (inw(FM801_REG(chip, GPIO_CTRL)) & FM801_GPIO_GP(TEA_256PCPR_DATA))
val |= 1;
}
spin_unlock_irq(&chip->reg_lock);
return val;
}
/* 64PCR GPIO numbers */
#define TEA_64PCR_BUS_CLOCK 0
#define TEA_64PCR_WRITE_ENABLE 1 /* inverted */
#define TEA_64PCR_DATA 2
static void snd_fm801_tea575x_64pcr_write(tea575x_t *tea, unsigned int val)
{
fm801_t *chip = tea->private_data;
unsigned short reg;
int i = 25;
spin_lock_irq(&chip->reg_lock);
reg = inw(FM801_REG(chip, GPIO_CTRL));
/* use GPIO lines and set write enable bit */
reg |= FM801_GPIO_GS(TEA_64PCR_DATA) |
FM801_GPIO_GS(TEA_64PCR_WRITE_ENABLE) |
FM801_GPIO_GS(TEA_64PCR_BUS_CLOCK);
/* all of lines are in the write direction */
/* clear data and clock lines */
reg &= ~(FM801_GPIO_GD(TEA_64PCR_DATA) |
FM801_GPIO_GD(TEA_64PCR_WRITE_ENABLE) |
FM801_GPIO_GD(TEA_64PCR_BUS_CLOCK) |
FM801_GPIO_GP(TEA_64PCR_DATA) |
FM801_GPIO_GP(TEA_64PCR_BUS_CLOCK) |
FM801_GPIO_GP(TEA_64PCR_WRITE_ENABLE));
outw(reg, FM801_REG(chip, GPIO_CTRL));
udelay(1);
while (i--) {
if (val & (1 << i))
reg |= FM801_GPIO_GP(TEA_64PCR_DATA);
else
reg &= ~FM801_GPIO_GP(TEA_64PCR_DATA);
outw(reg, FM801_REG(chip, GPIO_CTRL));
udelay(1);
reg |= FM801_GPIO_GP(TEA_64PCR_BUS_CLOCK);
outw(reg, FM801_REG(chip, GPIO_CTRL));
reg &= ~FM801_GPIO_GP(TEA_64PCR_BUS_CLOCK);
outw(reg, FM801_REG(chip, GPIO_CTRL));
udelay(1);
}
/* and reset the write enable bit */
reg |= FM801_GPIO_GP(TEA_64PCR_WRITE_ENABLE) |
FM801_GPIO_GP(TEA_64PCR_DATA);
outw(reg, FM801_REG(chip, GPIO_CTRL));
spin_unlock_irq(&chip->reg_lock);
}
static unsigned int snd_fm801_tea575x_64pcr_read(tea575x_t *tea)
{
fm801_t *chip = tea->private_data;
unsigned short reg;
unsigned int val = 0;
int i;
spin_lock_irq(&chip->reg_lock);
reg = inw(FM801_REG(chip, GPIO_CTRL));
/* use GPIO lines, set data direction to input */
reg |= FM801_GPIO_GS(TEA_64PCR_DATA) |
FM801_GPIO_GS(TEA_64PCR_WRITE_ENABLE) |
FM801_GPIO_GS(TEA_64PCR_BUS_CLOCK) |
FM801_GPIO_GD(TEA_64PCR_DATA) |
FM801_GPIO_GP(TEA_64PCR_DATA) |
FM801_GPIO_GP(TEA_64PCR_WRITE_ENABLE);
/* all of lines are in the write direction, except data */
/* clear data, write enable and clock lines */
reg &= ~(FM801_GPIO_GD(TEA_64PCR_WRITE_ENABLE) |
FM801_GPIO_GD(TEA_64PCR_BUS_CLOCK) |
FM801_GPIO_GP(TEA_64PCR_BUS_CLOCK));
for (i = 0; i < 24; i++) {
reg &= ~FM801_GPIO_GP(TEA_64PCR_BUS_CLOCK);
outw(reg, FM801_REG(chip, GPIO_CTRL));
udelay(1);
reg |= FM801_GPIO_GP(TEA_64PCR_BUS_CLOCK);
outw(reg, FM801_REG(chip, GPIO_CTRL));
udelay(1);
val <<= 1;
if (inw(FM801_REG(chip, GPIO_CTRL)) & FM801_GPIO_GP(TEA_64PCR_DATA))
val |= 1;
}
spin_unlock_irq(&chip->reg_lock);
return val;
}
static struct snd_tea575x_ops snd_fm801_tea_ops[3] = {
{
/* 1 = MediaForte 256-PCS */
.write = snd_fm801_tea575x_256pcs_write,
.read = snd_fm801_tea575x_256pcs_read,
},
{
/* 2 = MediaForte 256-PCPR */
.write = snd_fm801_tea575x_256pcpr_write,
.read = snd_fm801_tea575x_256pcpr_read,
},
{
/* 3 = MediaForte 64-PCR */
.write = snd_fm801_tea575x_64pcr_write,
.read = snd_fm801_tea575x_64pcr_read,
}
};
#endif
/*
* Mixer routines
*/
#define FM801_SINGLE(xname, reg, shift, mask, invert) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .info = snd_fm801_info_single, \
.get = snd_fm801_get_single, .put = snd_fm801_put_single, \
.private_value = reg | (shift << 8) | (mask << 16) | (invert << 24) }
static int snd_fm801_info_single(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)