From d1e34a8abfd6c5ac196f278ac2c5633e3e35ee22 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 22 Nov 2022 11:21:18 +0100 Subject: [PATCH] ARM: tegra: Sort nodes by unit-address, then alphabetically Nodes in device tree should be sorted by unit-address, followed by nodes without a unit-address, sorted alphabetically. Some exceptions are the top-level aliases, chosen, firmware, memory and reserved-memory nodes, which are expected to come first. These rules apply recursively with some exceptions, such as pinmux nodes or regulator nodes, which often follow more complicated ordering (often by "importance"). While at it, change the name of some of the nodes to follow standard naming conventions, which helps with the sorting order and reduces the amount of warnings from the DT validation tools. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra114-asus-tf701t.dts | 240 ++-- arch/arm/boot/dts/tegra114-dalmore.dts | 26 +- arch/arm/boot/dts/tegra124-apalis-emc.dtsi | 14 +- arch/arm/boot/dts/tegra124-apalis-eval.dts | 20 +- .../boot/dts/tegra124-apalis-v1.2-eval.dts | 20 +- arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi | 60 +- arch/arm/boot/dts/tegra124-apalis.dtsi | 60 +- .../arm/boot/dts/tegra124-jetson-tk1-emc.dtsi | 15 +- arch/arm/boot/dts/tegra124-jetson-tk1.dts | 8 +- arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi | 27 +- arch/arm/boot/dts/tegra124-nyan-big.dts | 22 +- .../arm/boot/dts/tegra124-nyan-blaze-emc.dtsi | 19 +- arch/arm/boot/dts/tegra124-nyan-blaze.dts | 14 +- arch/arm/boot/dts/tegra124-nyan.dtsi | 71 +- arch/arm/boot/dts/tegra124.dtsi | 20 +- .../boot/dts/tegra20-acer-a500-picasso.dts | 1257 +++++++++-------- arch/arm/boot/dts/tegra20-asus-tf101.dts | 114 +- arch/arm/boot/dts/tegra20-colibri-eval-v3.dts | 38 +- arch/arm/boot/dts/tegra20-colibri-iris.dts | 12 +- arch/arm/boot/dts/tegra20-colibri.dtsi | 60 +- arch/arm/boot/dts/tegra20-medcom-wide.dts | 8 +- arch/arm/boot/dts/tegra20-paz00.dts | 130 +- arch/arm/boot/dts/tegra20-seaboard.dts | 72 +- arch/arm/boot/dts/tegra20-tamonten.dtsi | 58 +- arch/arm/boot/dts/tegra20-trimslice.dts | 20 +- arch/arm/boot/dts/tegra20-ventana.dts | 58 +- arch/arm/boot/dts/tegra20.dtsi | 70 +- arch/arm/boot/dts/tegra30-apalis-eval.dts | 20 +- .../arm/boot/dts/tegra30-apalis-v1.1-eval.dts | 20 +- arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi | 20 +- arch/arm/boot/dts/tegra30-apalis.dtsi | 20 +- .../boot/dts/tegra30-asus-lvds-display.dtsi | 2 + .../tegra30-asus-nexus7-grouper-common.dtsi | 82 +- ...egra30-asus-nexus7-grouper-maxim-pmic.dtsi | 14 +- ...30-asus-nexus7-grouper-memory-timings.dtsi | 20 +- .../boot/dts/tegra30-asus-nexus7-grouper.dtsi | 28 +- .../boot/dts/tegra30-asus-nexus7-tilapia.dtsi | 32 +- arch/arm/boot/dts/tegra30-asus-tf201.dts | 34 +- arch/arm/boot/dts/tegra30-asus-tf300t.dts | 24 +- arch/arm/boot/dts/tegra30-asus-tf300tg.dts | 20 +- arch/arm/boot/dts/tegra30-asus-tf700t.dts | 52 +- .../dts/tegra30-asus-transformer-common.dtsi | 54 +- arch/arm/boot/dts/tegra30-beaver.dts | 44 +- arch/arm/boot/dts/tegra30-cardhu.dtsi | 54 +- arch/arm/boot/dts/tegra30-colibri-eval-v3.dts | 2 +- arch/arm/boot/dts/tegra30-colibri.dtsi | 30 +- arch/arm/boot/dts/tegra30-ouya.dts | 207 ++- .../arm/boot/dts/tegra30-pegatron-chagall.dts | 130 +- arch/arm/boot/dts/tegra30.dtsi | 88 +- 49 files changed, 1770 insertions(+), 1760 deletions(-) diff --git a/arch/arm/boot/dts/tegra114-asus-tf701t.dts b/arch/arm/boot/dts/tegra114-asus-tf701t.dts index 9279d24db009c5..84a3eb38e71d21 100644 --- a/arch/arm/boot/dts/tegra114-asus-tf701t.dts +++ b/arch/arm/boot/dts/tegra114-asus-tf701t.dts @@ -25,6 +25,14 @@ serial2 = &uartb; /* GPS */ }; + firmware { + trusted-foundations { + compatible = "tlm,trusted-foundations"; + tlm,version-major = <2>; + tlm,version-minor = <8>; + }; + }; + memory@80000000 { reg = <0x80000000 0x80000000>; }; @@ -109,6 +117,15 @@ }; codec_default: pinmux-codec-default { + interrupt { + nvidia,pins = "gpio_w2_aud_pw2", + "gpio_w3_aud_pw3"; + nvidia,function = "spi6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ldo1-en { nvidia,pins = "sdmmc1_wp_n_pv3"; nvidia,function = "sdmmc1"; @@ -116,11 +133,12 @@ nvidia,tristate = ; nvidia,enable-input = ; }; + }; - interrupt { - nvidia,pins = "gpio_w2_aud_pw2", - "gpio_w3_aud_pw3"; - nvidia,function = "spi6"; + gpio_hall_sensor_default: pinmux-gpio-hall-sensor-default { + ulpi_data4_po5 { + nvidia,pins = "ulpi_data4_po5"; + nvidia,function = "spi2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; @@ -146,16 +164,6 @@ }; }; - gpio_hall_sensor_default: pinmux-gpio-hall-sensor-default { - ulpi_data4_po5 { - nvidia,pins = "ulpi_data4_po5"; - nvidia,function = "spi2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - }; - hp_det_default: pinmux-hp-det-default { gmi_iordy_pi5 { nvidia,pins = "kb_row7_pr7"; @@ -198,6 +206,16 @@ }; sdmmc3_default: pinmux-sdmmc3-default { + drive_sdio3 { + nvidia,pins = "drive_sdio3"; + nvidia,high-speed-mode = ; + nvidia,schmitt = ; + nvidia,pull-down-strength = <22>; + nvidia,pull-up-strength = <36>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + sdmmc3_clk_pa6 { nvidia,pins = "sdmmc3_clk_pa6"; nvidia,function = "sdmmc3"; @@ -221,16 +239,6 @@ nvidia,tristate = ; nvidia,enable-input = ; }; - - drive_sdio3 { - nvidia,pins = "drive_sdio3"; - nvidia,high-speed-mode = ; - nvidia,schmitt = ; - nvidia,pull-down-strength = <22>; - nvidia,pull-up-strength = <36>; - nvidia,slew-rate-rising = ; - nvidia,slew-rate-falling = ; - }; }; sdmmc3_vdd_default: pinmux-sdmmc3-vdd-default { @@ -298,6 +306,14 @@ pinctrl-0 = <&codec_default>; }; + temp_sensor: temperature-sensor@4c { + compatible = "onnn,nct1008"; + reg = <0x4c>; + + vcc-supply = <&vdd_3v3_sys>; + #thermal-sensor-cells = <1>; + }; + motion-tracker@68 { compatible = "invensense,mpu6500"; reg = <0x68>; @@ -312,14 +328,6 @@ pinctrl-names = "default"; pinctrl-0 = <&imu_default>; }; - - temp_sensor: temperature-sensor@4c { - compatible = "onnn,nct1008"; - reg = <0x4c>; - - vcc-supply = <&vdd_3v3_sys>; - #thermal-sensor-cells = <1>; - }; }; i2c@7000c400 { @@ -368,6 +376,66 @@ #gpio-cells = <2>; }; + pinmux { + compatible = "ti,tps65913-pinctrl"; + ti,palmas-enable-dvfs1; + + pinctrl-names = "default"; + pinctrl-0 = <&palmas_default>; + + palmas_default: pinmux { + pin_gpio0 { + pins = "gpio0"; + function = "gpio"; + }; + + pin_gpio1 { + pins = "gpio1"; + function = "gpio"; + }; + + pin_gpio2 { + pins = "gpio2"; + function = "gpio"; + }; + + pin_gpio3 { + pins = "gpio3"; + function = "gpio"; + }; + + pin_gpio4 { + pins = "gpio4"; + function = "gpio"; + }; + + pin_gpio5 { + pins = "gpio5"; + function = "gpio"; + }; + + pin_gpio6 { + pins = "gpio6"; + function = "gpio"; + }; + + pin_gpio7 { + pins = "gpio7"; + function = "gpio"; + }; + + pin_powergood { + pins = "powergood"; + function = "powergood"; + }; + + pin_vac { + pins = "vac"; + function = "vac"; + }; + }; + }; + pmic { compatible = "ti,tps65913-pmic", "ti,palmas-pmic"; @@ -528,66 +596,6 @@ interrupt-parent = <&palmas>; interrupts = <8 0>; }; - - pinmux { - compatible = "ti,tps65913-pinctrl"; - ti,palmas-enable-dvfs1; - - pinctrl-names = "default"; - pinctrl-0 = <&palmas_default>; - - palmas_default: pinmux { - pin_powergood { - pins = "powergood"; - function = "powergood"; - }; - - pin_vac { - pins = "vac"; - function = "vac"; - }; - - pin_gpio0 { - pins = "gpio0"; - function = "gpio"; - }; - - pin_gpio1 { - pins = "gpio1"; - function = "gpio"; - }; - - pin_gpio2 { - pins = "gpio2"; - function = "gpio"; - }; - - pin_gpio3 { - pins = "gpio3"; - function = "gpio"; - }; - - pin_gpio4 { - pins = "gpio4"; - function = "gpio"; - }; - - pin_gpio5 { - pins = "gpio5"; - function = "gpio"; - }; - - pin_gpio6 { - pins = "gpio6"; - function = "gpio"; - }; - - pin_gpio7 { - pins = "gpio7"; - function = "gpio"; - }; - }; - }; }; }; @@ -668,11 +676,21 @@ clock-output-names = "pmic-oscillator"; }; - firmware { - trusted-foundations { - compatible = "tlm,trusted-foundations"; - tlm,version-major = <2>; - tlm,version-minor = <8>; + gpio-hall-sensor { + compatible = "gpio-keys"; + + label = "GPIO Hall Effect Sensor"; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_hall_sensor_default>; + + switch-hall-sensor { + label = "Hall Effect Sensor"; + gpios = <&gpio TEGRA_GPIO(O, 5) GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + linux,can-disable; + wakeup-source; }; }; @@ -692,36 +710,18 @@ wakeup-source; }; - button-volume-up { - label = "Volume Up"; - gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <10>; - }; - button-volume-down { label = "Volume Down"; gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>; linux,code = ; debounce-interval = <10>; }; - }; - - gpio-hall-sensor { - compatible = "gpio-keys"; - - label = "GPIO Hall Effect Sensor"; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_hall_sensor_default>; - - switch-hall-sensor { - label = "Hall Effect Sensor"; - gpios = <&gpio TEGRA_GPIO(O, 5) GPIO_ACTIVE_LOW>; - linux,input-type = ; - linux,code = ; - linux,can-disable; - wakeup-source; + button-volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; }; }; diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts index fffd62bcea6a9b..a685fcb129d009 100644 --- a/arch/arm/boot/dts/tegra114-dalmore.dts +++ b/arch/arm/boot/dts/tegra114-dalmore.dts @@ -909,6 +909,19 @@ #gpio-cells = <2>; }; + pinmux { + compatible = "ti,tps65913-pinctrl"; + pinctrl-names = "default"; + pinctrl-0 = <&palmas_default>; + + palmas_default: pinmux { + pin_gpio6 { + pins = "gpio6"; + function = "gpio"; + }; + }; + }; + pmic { compatible = "ti,tps65913-pmic", "ti,palmas-pmic"; smps1-in-supply = <&tps65090_dcdc3_reg>; @@ -1065,19 +1078,6 @@ interrupt-parent = <&palmas>; interrupts = <8 0>; }; - - pinmux { - compatible = "ti,tps65913-pinctrl"; - pinctrl-names = "default"; - pinctrl-0 = <&palmas_default>; - - palmas_default: pinmux { - pin_gpio6 { - pins = "gpio6"; - function = "gpio"; - }; - }; - }; }; }; diff --git a/arch/arm/boot/dts/tegra124-apalis-emc.dtsi b/arch/arm/boot/dts/tegra124-apalis-emc.dtsi index 7143c6b2ec3ed8..970f33dd9101ef 100644 --- a/arch/arm/boot/dts/tegra124-apalis-emc.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis-emc.dtsi @@ -4,6 +4,8 @@ * */ +#include + / { clock@60006000 { emc-timings-1 { @@ -1474,12 +1476,12 @@ }; }; }; -}; -&emc_icc_dvfs_opp_table { - /delete-node/ opp-1200000000-1100; -}; + opp-table-actmon { + /delete-node/ opp-1200000000; + }; -&emc_bw_dfs_opp_table { - /delete-node/ opp-1200000000; + opp-table-emc { + /delete-node/ opp-1200000000-1100; + }; }; diff --git a/arch/arm/boot/dts/tegra124-apalis-eval.dts b/arch/arm/boot/dts/tegra124-apalis-eval.dts index bce12b3411fc78..2df2d8a6b552d9 100644 --- a/arch/arm/boot/dts/tegra124-apalis-eval.dts +++ b/arch/arm/boot/dts/tegra124-apalis-eval.dts @@ -40,6 +40,16 @@ }; }; + gpio: gpio@6000d000 { + /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */ + pex-perst-n-hog { + gpio-hog; + gpios = ; + output-high; + line-name = "PEX_PERST_N"; + }; + }; + /* Apalis UART1 */ serial@70006000 { status = "okay"; @@ -243,13 +253,3 @@ vin-supply = <®_5v0>; }; }; - -&gpio { - /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */ - pex-perst-n-hog { - gpio-hog; - gpios = ; - output-high; - line-name = "PEX_PERST_N"; - }; -}; diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts b/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts index 800283ad6bdc77..f4521fd15f6ad7 100644 --- a/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts +++ b/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts @@ -41,6 +41,16 @@ }; }; + gpio@6000d000 { + /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */ + pex-perst-n-hog { + gpio-hog; + gpios = ; + output-high; + line-name = "PEX_PERST_N"; + }; + }; + /* Apalis UART1 */ serial@70006000 { status = "okay"; @@ -245,13 +255,3 @@ vin-supply = <®_5v0>; }; }; - -&gpio { - /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */ - pex-perst-n-hog { - gpio-hog; - gpios = ; - output-high; - line-name = "PEX_PERST_N"; - }; -}; diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi index dbb0da08cb95d6..75cfe718737cda 100644 --- a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi @@ -65,6 +65,24 @@ vdd-supply = <®_vdd_gpu>; }; + gpio@6000d000 { + /* I210 Gigabit Ethernet Controller Reset */ + lan-reset-n-hog { + gpio-hog; + gpios = ; + output-high; + line-name = "LAN_RESET_N"; + }; + + /* Control MXM3 pin 26 Reset Module Output Carrier Input */ + reset-moci-ctrl-hog { + gpio-hog; + gpios = ; + output-high; + line-name = "RESET_MOCI_CTRL"; + }; + }; + pinmux@70000868 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; @@ -1585,18 +1603,18 @@ pinctrl-0 = <&as3722_default>; as3722_default: pinmux { + gpio0-1-3-4-5-6 { + pins = "gpio0", "gpio1", "gpio3", + "gpio4", "gpio5", "gpio6"; + bias-high-impedance; + }; + gpio2-7 { pins = "gpio2", /* PWR_EN_+V3.3 */ "gpio7"; /* +V1.6_LPO */ function = "gpio"; bias-pull-up; }; - - gpio0-1-3-4-5-6 { - pins = "gpio0", "gpio1", "gpio3", - "gpio4", "gpio5", "gpio6"; - bias-high-impedance; - }; }; regulators { @@ -1943,18 +1961,18 @@ }; }; - clk32k_in: osc3 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - cpus { cpu@0 { vdd-cpu-supply = <®_vdd_cpu>; }; }; + clk32k_in: osc3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + reg_1v05_avdd_hdmi_pll: regulator-1v05-avdd-hdmi-pll { compatible = "regulator-fixed"; regulator-name = "+V1.05_AVDD_HDMI_PLL"; @@ -2056,21 +2074,3 @@ }; }; }; - -&gpio { - /* I210 Gigabit Ethernet Controller Reset */ - lan-reset-n-hog { - gpio-hog; - gpios = ; - output-high; - line-name = "LAN_RESET_N"; - }; - - /* Control MXM3 pin 26 Reset Module Output Carrier Input */ - reset-moci-ctrl-hog { - gpio-hog; - gpios = ; - output-high; - line-name = "RESET_MOCI_CTRL"; - }; -}; diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi index d3f16c117b0ca2..554c8089491c95 100644 --- a/arch/arm/boot/dts/tegra124-apalis.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis.dtsi @@ -64,6 +64,24 @@ vdd-supply = <®_vdd_gpu>; }; + gpio@6000d000 { + /* I210 Gigabit Ethernet Controller Reset */ + lan-reset-n-hog { + gpio-hog; + gpios = ; + output-high; + line-name = "LAN_RESET_N"; + }; + + /* Control MXM3 pin 26 Reset Module Output Carrier Input */ + reset-moci-ctrl-hog { + gpio-hog; + gpios = ; + output-high; + line-name = "RESET_MOCI_CTRL"; + }; + }; + pinmux@70000868 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; @@ -1578,18 +1596,18 @@ pinctrl-0 = <&as3722_default>; as3722_default: pinmux { + gpio0-1-3-4-5-6 { + pins = "gpio0", "gpio1", "gpio3", + "gpio4", "gpio5", "gpio6"; + bias-high-impedance; + }; + gpio2-7 { pins = "gpio2", /* PWR_EN_+V3.3 */ "gpio7"; /* +V1.6_LPO */ function = "gpio"; bias-pull-up; }; - - gpio0-1-3-4-5-6 { - pins = "gpio0", "gpio1", "gpio3", - "gpio4", "gpio5", "gpio6"; - bias-high-impedance; - }; }; regulators { @@ -1935,18 +1953,18 @@ }; }; - clk32k_in: osc3 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - cpus { cpu@0 { vdd-cpu-supply = <®_vdd_cpu>; }; }; + clk32k_in: osc3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + reg_1v05_avdd_hdmi_pll: regulator-1v05-avdd-hdmi-pll { compatible = "regulator-fixed"; regulator-name = "+V1.05_AVDD_HDMI_PLL"; @@ -2048,21 +2066,3 @@ }; }; }; - -&gpio { - /* I210 Gigabit Ethernet Controller Reset */ - lan-reset-n-hog { - gpio-hog; - gpios = ; - output-high; - line-name = "LAN_RESET_N"; - }; - - /* Control MXM3 pin 26 Reset Module Output Carrier Input */ - reset-moci-ctrl-hog { - gpio-hog; - gpios = ; - output-high; - line-name = "RESET_MOCI_CTRL"; - }; -}; diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi b/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi index 79e776db5f3752..d10e5334a6c67f 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi +++ b/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi @@ -1,4 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 + +#include + / { clock@60006000 { emc-timings-3 { @@ -2429,12 +2432,12 @@ }; }; }; -}; -&emc_icc_dvfs_opp_table { - /delete-node/ opp-1200000000-1100; -}; + opp-table-actmon { + /delete-node/ opp-1200000000; + }; -&emc_bw_dfs_opp_table { - /delete-node/ opp-1200000000; + opp-table-emc { + /delete-node/ opp-1200000000-1100; + }; }; diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts index f41dd4039c07bb..4196f2401c90f1 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts @@ -68,10 +68,6 @@ }; }; - cec@70015000 { - status = "okay"; - }; - gpu@57000000 { /* * Node left disabled on purpose - the bootloader will enable @@ -1683,6 +1679,10 @@ }; }; + cec@70015000 { + status = "okay"; + }; + /* Serial ATA */ sata@70020000 { status = "okay"; diff --git a/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi b/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi index 31b2e26c69d46d..cadb1969f1ccea 100644 --- a/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi +++ b/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi @@ -1,9 +1,8 @@ // SPDX-License-Identifier: GPL-2.0 -/ { - apbmisc@70000800 { - nvidia,long-ram-code; - }; +#include + +/ { clock@60006000 { emc-timings-1 { nvidia,ram-code = <1>; @@ -249,6 +248,10 @@ }; }; + apbmisc@70000800 { + nvidia,long-ram-code; + }; + memory-controller@70019000 { emc-timings-1 { nvidia,ram-code = <1>; @@ -6678,14 +6681,14 @@ }; }; }; -}; -&emc_icc_dvfs_opp_table { - /delete-node/ opp-924000000-1100; - /delete-node/ opp-1200000000-1100; -}; + opp-table-actmon { + /delete-node/ opp-924000000; + /delete-node/ opp-1200000000; + }; -&emc_bw_dfs_opp_table { - /delete-node/ opp-924000000; - /delete-node/ opp-1200000000; + opp-table-emc { + /delete-node/ opp-924000000-1100; + /delete-node/ opp-1200000000-1100; + }; }; diff --git a/arch/arm/boot/dts/tegra124-nyan-big.dts b/arch/arm/boot/dts/tegra124-nyan-big.dts index 9a01dfed137910..8bca9599ad6ec6 100644 --- a/arch/arm/boot/dts/tegra124-nyan-big.dts +++ b/arch/arm/boot/dts/tegra124-nyan-big.dts @@ -25,17 +25,6 @@ }; }; - mmc@700b0400 { /* SD Card on this bus */ - wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; - }; - - sound { - compatible = "nvidia,tegra-audio-max98090-nyan-big", - "nvidia,tegra-audio-max98090-nyan", - "nvidia,tegra-audio-max98090"; - nvidia,model = "GoogleNyanBig"; - }; - pinmux@70000868 { pinctrl-names = "default"; pinctrl-0 = <&pinmux_default>; @@ -1345,4 +1334,15 @@ }; }; }; + + mmc@700b0400 { /* SD Card on this bus */ + wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; + }; + + sound { + compatible = "nvidia,tegra-audio-max98090-nyan-big", + "nvidia,tegra-audio-max98090-nyan", + "nvidia,tegra-audio-max98090"; + nvidia,model = "GoogleNyanBig"; + }; }; diff --git a/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi b/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi index 2ce1b12be44d22..e8dcc4f51fc591 100644 --- a/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi +++ b/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi @@ -1,4 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 + +#include + / { clock@60006000 { emc-timings-1 { @@ -2055,14 +2058,14 @@ }; }; }; -}; -&emc_icc_dvfs_opp_table { - /delete-node/ opp-924000000-1100; - /delete-node/ opp-1200000000-1100; -}; + opp-table-actmon { + /delete-node/ opp-924000000; + /delete-node/ opp-1200000000; + }; -&emc_bw_dfs_opp_table { - /delete-node/ opp-924000000; - /delete-node/ opp-1200000000; + opp-table-emc { + /delete-node/ opp-924000000-1100; + /delete-node/ opp-1200000000-1100; + }; }; diff --git a/arch/arm/boot/dts/tegra124-nyan-blaze.dts b/arch/arm/boot/dts/tegra124-nyan-blaze.dts index 0beef1c03ff333..432540c1006534 100644 --- a/arch/arm/boot/dts/tegra124-nyan-blaze.dts +++ b/arch/arm/boot/dts/tegra124-nyan-blaze.dts @@ -27,13 +27,6 @@ }; }; - sound { - compatible = "nvidia,tegra-audio-max98090-nyan-blaze", - "nvidia,tegra-audio-max98090-nyan", - "nvidia,tegra-audio-max98090"; - nvidia,model = "GoogleNyanBlaze"; - }; - pinmux@70000868 { pinctrl-names = "default"; pinctrl-0 = <&pinmux_default>; @@ -1343,4 +1336,11 @@ }; }; }; + + sound { + compatible = "nvidia,tegra-audio-max98090-nyan-blaze", + "nvidia,tegra-audio-max98090-nyan", + "nvidia,tegra-audio-max98090"; + nvidia,model = "GoogleNyanBlaze"; + }; }; diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi index 13061ab5247b36..56952333ae2856 100644 --- a/arch/arm/boot/dts/tegra124-nyan.dtsi +++ b/arch/arm/boot/dts/tegra124-nyan.dtsi @@ -498,12 +498,6 @@ }; }; - sdhci0_pwrseq: sdhci0_pwrseq { - compatible = "mmc-pwrseq-simple"; - - reset-gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>; - }; - mmc@700b0000 { /* WiFi/BT on this bus */ status = "okay"; bus-width = <4>; @@ -595,14 +589,35 @@ }; cpus { - cpu@0 { + cpu0: cpu@0 { + #cooling-cells = <2>; vdd-cpu-supply = <&vdd_cpu>; }; + + cpu1: cpu@1 { + #cooling-cells = <2>; + }; + + cpu2: cpu@2 { + #cooling-cells = <2>; + }; + + cpu3: cpu@3 { + #cooling-cells = <2>; + }; }; gpio-keys { compatible = "gpio-keys"; + key-power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <30>; + wakeup-source; + }; + switch-lid { label = "Lid"; gpios = <&gpio TEGRA_GPIO(R, 4) GPIO_ACTIVE_LOW>; @@ -611,14 +626,18 @@ debounce-interval = <1>; wakeup-source; }; + }; - key-power { - label = "Power"; - gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <30>; - wakeup-source; - }; + gpio-restart { + compatible = "gpio-restart"; + gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; + priority = <200>; + }; + + sdhci0_pwrseq: pwrseq-sdhci0 { + compatible = "mmc-pwrseq-simple"; + + reset-gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>; }; vdd_mux: regulator-mux { @@ -785,30 +804,6 @@ <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>; }; - gpio-restart { - compatible = "gpio-restart"; - gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; - priority = <200>; - }; - - cpus { - cpu0: cpu@0 { - #cooling-cells = <2>; - }; - - cpu1: cpu@1 { - #cooling-cells = <2>; - }; - - cpu2: cpu@2 { - #cooling-cells = <2>; - }; - - cpu3: cpu@3 { - #cooling-cells = <2>; - }; - }; - thermal-zones { cpu-skin-thermal { polling-delay-passive = <1000>; /* milliseconds */ diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index a9ab548781e1c2..b3fbecf5c81882 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -639,6 +639,16 @@ reset-names = "fuse"; }; + cec@70015000 { + compatible = "nvidia,tegra124-cec"; + reg = <0x0 0x70015000 0x0 0x00001000>; + interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_CEC>; + clock-names = "cec"; + status = "disabled"; + hdmi-phandle = <&hdmi>; + }; + mc: memory-controller@70019000 { compatible = "nvidia,tegra124-mc"; reg = <0x0 0x70019000 0x0 0x1000>; @@ -906,16 +916,6 @@ status = "disabled"; }; - cec@70015000 { - compatible = "nvidia,tegra124-cec"; - reg = <0x0 0x70015000 0x0 0x00001000>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_CEC>; - clock-names = "cec"; - status = "disabled"; - hdmi-phandle = <&hdmi>; - }; - soctherm: thermal-sensor@700e2000 { compatible = "nvidia,tegra124-soctherm"; reg = <0x0 0x700e2000 0x0 0x600>, /* SOC_THERM reg_base */ diff --git a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts index 17afc2c7cb37b7..08b42952f4de39 100644 --- a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts +++ b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts @@ -347,31 +347,34 @@ nvidia,pins = "ddc"; nvidia,function = "i2c2"; }; + pta { nvidia,pins = "pta"; nvidia,function = "rsvd4"; }; }; - state_i2cmux_pta: pinmux-i2cmux-pta { + state_i2cmux_idle: pinmux-i2cmux-idle { ddc { nvidia,pins = "ddc"; nvidia,function = "rsvd4"; }; + pta { nvidia,pins = "pta"; - nvidia,function = "i2c2"; + nvidia,function = "rsvd4"; }; }; - state_i2cmux_idle: pinmux-i2cmux-idle { + state_i2cmux_pta: pinmux-i2cmux-pta { ddc { nvidia,pins = "ddc"; nvidia,function = "rsvd4"; }; + pta { nvidia,pins = "pta"; - nvidia,function = "rsvd4"; + nvidia,function = "i2c2"; }; }; }; @@ -425,6 +428,10 @@ /* Docking station */ }; + pwm: pwm@7000a000 { + status = "okay"; + }; + i2c@7000c000 { clock-frequency = <400000>; status = "okay"; @@ -512,45 +519,6 @@ status = "okay"; }; - i2cmux { - compatible = "i2c-mux-pinctrl"; - #address-cells = <1>; - #size-cells = <0>; - - i2c-parent = <&{/i2c@7000c400}>; - - pinctrl-names = "ddc", "pta", "idle"; - pinctrl-0 = <&state_i2cmux_ddc>; - pinctrl-1 = <&state_i2cmux_pta>; - pinctrl-2 = <&state_i2cmux_idle>; - - hdmi_ddc: i2c@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - }; - - panel_ddc: i2c@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - embedded-controller@58 { - compatible = "acer,a500-iconia-ec", "ene,kb930"; - reg = <0x58>; - - system-power-controller; - - monitored-battery = <&bat1010>; - power-supplies = <&mains>; - }; - }; - }; - - pwm: pwm@7000a000 { - status = "okay"; - }; - i2c@7000d000 { clock-frequency = <100000>; status = "okay"; @@ -729,71 +697,456 @@ core-supply = <&vdd_core>; }; - usb@c5000000 { - compatible = "nvidia,tegra20-udc"; - status = "okay"; - dr_mode = "peripheral"; - }; + memory-controller@7000f400 { + nvidia,use-ram-code; - usb-phy@c5000000 { - status = "okay"; - dr_mode = "peripheral"; - nvidia,xcvr-setup-use-fuses; - nvidia,xcvr-lsfslew = <2>; - nvidia,xcvr-lsrslew = <2>; - }; + emc-tables@0 { + nvidia,ram-code = <0>; /* elpida-8gb */ + reg = <0>; - usb@c5008000 { - status = "okay"; - }; + #address-cells = <1>; + #size-cells = <0>; - usb-phy@c5008000 { - status = "okay"; - nvidia,xcvr-setup-use-fuses; - nvidia,xcvr-lsfslew = <2>; - nvidia,xcvr-lsrslew = <2>; - vbus-supply = <&vdd_5v0_sys>; - }; + emc-table@25000 { + reg = <25000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <25000>; + nvidia,emc-registers = <0x00000002 0x00000006 + 0x00000003 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000004 + 0x00000003 0x00000008 0x0000000b 0x0000004d + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x00000004 + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x00000068 0x00000000 0x00000003 + 0x00000000 0x00000000 0x00000282 0xa0ae04ae + 0x00070000 0x00000000 0x00000000 0x00000003 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; - brcm_wifi_pwrseq: wifi-pwrseq { - compatible = "mmc-pwrseq-simple"; + emc-table@50000 { + reg = <50000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <50000>; + nvidia,emc-registers = <0x00000003 0x00000007 + 0x00000003 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000005 + 0x00000003 0x00000008 0x0000000b 0x0000009f + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x00000007 + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x000000d0 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000282 0xa0ae04ae + 0x00070000 0x00000000 0x00000000 0x00000005 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; - clocks = <&rtc_32k_wifi>; - clock-names = "ext_clock"; + emc-table@75000 { + reg = <75000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <75000>; + nvidia,emc-registers = <0x00000005 0x0000000a + 0x00000004 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000005 + 0x00000003 0x00000008 0x0000000b 0x000000ff + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x0000000b + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x00000138 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000282 0xa0ae04ae + 0x00070000 0x00000000 0x00000000 0x00000007 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; - reset-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_LOW>; - post-power-on-delay-ms = <300>; - power-off-delay-us = <300>; - }; + emc-table@150000 { + reg = <150000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <150000>; + nvidia,emc-registers = <0x00000009 0x00000014 + 0x00000007 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000005 + 0x00000003 0x00000008 0x0000000b 0x0000021f + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x00000015 + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x00000270 0x00000000 0x00000001 + 0x00000000 0x00000000 0x00000282 0xa07c04ae + 0x007dd510 0x00000000 0x00000000 0x0000000e + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; - sdmmc1: mmc@c8000000 { - status = "okay"; + emc-table@300000 { + reg = <300000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <300000>; + nvidia,emc-registers = <0x00000012 0x00000027 + 0x0000000d 0x00000006 0x00000007 0x00000005 + 0x00000003 0x00000009 0x00000006 0x00000006 + 0x00000003 0x00000003 0x00000002 0x00000006 + 0x00000003 0x00000009 0x0000000c 0x0000045f + 0x00000000 0x00000004 0x00000004 0x00000006 + 0x00000008 0x00000001 0x0000000e 0x0000002a + 0x00000003 0x0000000f 0x00000007 0x00000005 + 0x00000002 0x000004e1 0x00000005 0x00000002 + 0x00000000 0x00000000 0x00000282 0xe059048b + 0x007e1510 0x00000000 0x00000000 0x0000001b + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + }; - #address-cells = <1>; - #size-cells = <0>; + emc-tables@1 { + nvidia,ram-code = <1>; /* elpida-4gb */ + reg = <1>; - assigned-clocks = <&tegra_car TEGRA20_CLK_SDMMC1>; - assigned-clock-parents = <&tegra_car TEGRA20_CLK_PLL_C>; - assigned-clock-rates = <50000000>; + #address-cells = <1>; + #size-cells = <0>; - max-frequency = <50000000>; - keep-power-in-suspend; - bus-width = <4>; - non-removable; + emc-table@25000 { + reg = <25000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <25000>; + nvidia,emc-registers = <0x00000002 0x00000006 + 0x00000003 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000004 + 0x00000003 0x00000008 0x0000000b 0x0000004d + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x00000004 + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x00000068 0x00000000 0x00000003 + 0x00000000 0x00000000 0x00000282 0xa0ae04ae + 0x0007c000 0x00000000 0x00000000 0x00000003 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; - mmc-pwrseq = <&brcm_wifi_pwrseq>; - vmmc-supply = <&vdd_3v3_sys>; - vqmmc-supply = <&vdd_1v8_sys>; + emc-table@50000 { + reg = <50000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <50000>; + nvidia,emc-registers = <0x00000003 0x00000007 + 0x00000003 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000005 + 0x00000003 0x00000008 0x0000000b 0x0000009f + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x00000007 + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x000000d0 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000282 0xa0ae04ae + 0x0007c000 0x00000000 0x00000000 0x00000005 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; - /* Azurewave AW-NH611 BCM4329 */ - wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&gpio>; - interrupts = ; - interrupt-names = "host-wake"; - }; - }; + emc-table@75000 { + reg = <75000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <75000>; + nvidia,emc-registers = <0x00000005 0x0000000a + 0x00000004 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000005 + 0x00000003 0x00000008 0x0000000b 0x000000ff + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x0000000b + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x00000138 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000282 0xa0ae04ae + 0x0007c000 0x00000000 0x00000000 0x00000007 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@150000 { + reg = <150000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <150000>; + nvidia,emc-registers = <0x00000009 0x00000014 + 0x00000007 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000005 + 0x00000003 0x00000008 0x0000000b 0x0000021f + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x00000015 + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x00000270 0x00000000 0x00000001 + 0x00000000 0x00000000 0x00000282 0xa07c04ae + 0x007e4010 0x00000000 0x00000000 0x0000000e + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@300000 { + reg = <300000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <300000>; + nvidia,emc-registers = <0x00000012 0x00000027 + 0x0000000d 0x00000006 0x00000007 0x00000005 + 0x00000003 0x00000009 0x00000006 0x00000006 + 0x00000003 0x00000003 0x00000002 0x00000006 + 0x00000003 0x00000009 0x0000000c 0x0000045f + 0x00000000 0x00000004 0x00000004 0x00000006 + 0x00000008 0x00000001 0x0000000e 0x0000002a + 0x00000003 0x0000000f 0x00000007 0x00000005 + 0x00000002 0x000004e1 0x00000005 0x00000002 + 0x00000000 0x00000000 0x00000282 0xe059048b + 0x007e0010 0x00000000 0x00000000 0x0000001b + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + }; + + emc-tables@2 { + nvidia,ram-code = <2>; /* hynix-8gb */ + reg = <2>; + + #address-cells = <1>; + #size-cells = <0>; + + emc-table@25000 { + reg = <25000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <25000>; + nvidia,emc-registers = <0x00000002 0x00000006 + 0x00000003 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000004 + 0x00000003 0x00000008 0x0000000b 0x0000004d + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x00000004 + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x00000068 0x00000000 0x00000003 + 0x00000000 0x00000000 0x00000282 0xa0ae04ae + 0x00070000 0x00000000 0x00000000 0x00000003 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@50000 { + reg = <50000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <50000>; + nvidia,emc-registers = <0x00000003 0x00000007 + 0x00000003 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000005 + 0x00000003 0x00000008 0x0000000b 0x0000009f + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x00000007 + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x000000d0 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000282 0xa0ae04ae + 0x00070000 0x00000000 0x00000000 0x00000005 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@75000 { + reg = <75000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <75000>; + nvidia,emc-registers = <0x00000005 0x0000000a + 0x00000004 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000005 + 0x00000003 0x00000008 0x0000000b 0x000000ff + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x0000000b + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x00000138 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000282 0xa0ae04ae + 0x00070000 0x00000000 0x00000000 0x00000007 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@150000 { + reg = <150000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <150000>; + nvidia,emc-registers = <0x00000009 0x00000014 + 0x00000007 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000005 + 0x00000003 0x00000008 0x0000000b 0x0000021f + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x00000015 + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x00000270 0x00000000 0x00000001 + 0x00000000 0x00000000 0x00000282 0xa07c04ae + 0x007dd010 0x00000000 0x00000000 0x0000000e + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@300000 { + reg = <300000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <300000>; + nvidia,emc-registers = <0x00000012 0x00000027 + 0x0000000d 0x00000006 0x00000007 0x00000005 + 0x00000003 0x00000009 0x00000006 0x00000006 + 0x00000003 0x00000003 0x00000002 0x00000006 + 0x00000003 0x00000009 0x0000000c 0x0000045f + 0x00000000 0x00000004 0x00000004 0x00000006 + 0x00000008 0x00000001 0x0000000e 0x0000002a + 0x00000003 0x0000000f 0x00000007 0x00000005 + 0x00000002 0x000004e1 0x00000005 0x00000002 + 0x00000000 0x00000000 0x00000282 0xe059048b + 0x007e2010 0x00000000 0x00000000 0x0000001b + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + }; + + emc-tables@3 { + nvidia,ram-code = <3>; /* hynix-4gb */ + reg = <3>; + + #address-cells = <1>; + #size-cells = <0>; + + emc-table@25000 { + reg = <25000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <25000>; + nvidia,emc-registers = <0x00000002 0x00000006 + 0x00000003 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000004 + 0x00000003 0x00000008 0x0000000b 0x0000004d + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x00000004 + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x00000068 0x00000000 0x00000003 + 0x00000000 0x00000000 0x00000282 0xa0ae04ae + 0x0007c000 0x00000000 0x00000000 0x00000003 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@50000 { + reg = <50000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <50000>; + nvidia,emc-registers = <0x00000003 0x00000007 + 0x00000003 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000005 + 0x00000003 0x00000008 0x0000000b 0x0000009f + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x00000007 + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x000000d0 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000282 0xa0ae04ae + 0x0007c000 0x00078000 0x00000000 0x00000005 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@75000 { + reg = <75000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <75000>; + nvidia,emc-registers = <0x00000005 0x0000000a + 0x00000004 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000005 + 0x00000003 0x00000008 0x0000000b 0x000000ff + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x0000000b + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x00000138 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000282 0xa0ae04ae + 0x0007c000 0x00000000 0x00000000 0x00000007 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@150000 { + reg = <150000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <150000>; + nvidia,emc-registers = <0x00000009 0x00000014 + 0x00000007 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000005 + 0x00000003 0x00000008 0x0000000b 0x0000021f + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x00000015 + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x00000270 0x00000000 0x00000001 + 0x00000000 0x00000000 0x00000282 0xa07c04ae + 0x007e4010 0x00000000 0x00000000 0x0000000e + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@300000 { + reg = <300000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <300000>; + nvidia,emc-registers = <0x00000012 0x00000027 + 0x0000000d 0x00000006 0x00000007 0x00000005 + 0x00000003 0x00000009 0x00000006 0x00000006 + 0x00000003 0x00000003 0x00000002 0x00000006 + 0x00000003 0x00000009 0x0000000c 0x0000045f + 0x00000000 0x00000004 0x00000004 0x00000006 + 0x00000008 0x00000001 0x0000000e 0x0000002a + 0x00000003 0x0000000f 0x00000007 0x00000005 + 0x00000002 0x000004e1 0x00000005 0x00000002 + 0x00000000 0x00000000 0x00000282 0xe059048b + 0x007e0010 0x00000000 0x00000000 0x0000001b + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + }; + }; + + usb@c5000000 { + compatible = "nvidia,tegra20-udc"; + status = "okay"; + dr_mode = "peripheral"; + }; + + usb-phy@c5000000 { + status = "okay"; + dr_mode = "peripheral"; + nvidia,xcvr-setup-use-fuses; + nvidia,xcvr-lsfslew = <2>; + nvidia,xcvr-lsrslew = <2>; + }; + + usb@c5008000 { + status = "okay"; + }; + + usb-phy@c5008000 { + status = "okay"; + nvidia,xcvr-setup-use-fuses; + nvidia,xcvr-lsfslew = <2>; + nvidia,xcvr-lsrslew = <2>; + vbus-supply = <&vdd_5v0_sys>; + }; + + sdmmc1: mmc@c8000000 { + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + assigned-clocks = <&tegra_car TEGRA20_CLK_SDMMC1>; + assigned-clock-parents = <&tegra_car TEGRA20_CLK_PLL_C>; + assigned-clock-rates = <50000000>; + + max-frequency = <50000000>; + keep-power-in-suspend; + bus-width = <4>; + non-removable; + + mmc-pwrseq = <&brcm_wifi_pwrseq>; + vmmc-supply = <&vdd_3v3_sys>; + vqmmc-supply = <&vdd_1v8_sys>; + + /* Azurewave AW-NH611 BCM4329 */ + wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&gpio>; + interrupts = ; + interrupt-names = "host-wake"; + }; + }; sdmmc3: mmc@c8000400 { status = "okay"; @@ -922,19 +1275,19 @@ debounce-interval = <10>; }; - key-volume-up { - label = "Volume Up"; - gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; - linux,code = ; + key-volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(Q, 5) GPIO_ACTIVE_LOW>; + linux,code = ; debounce-interval = <10>; wakeup-event-action = ; wakeup-source; }; - key-volume-down { - label = "Volume Down"; - gpios = <&gpio TEGRA_GPIO(Q, 5) GPIO_ACTIVE_LOW>; - linux,code = ; + key-volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; + linux,code = ; debounce-interval = <10>; wakeup-event-action = ; wakeup-source; @@ -947,576 +1300,226 @@ vcc-supply = <&vdd_3v3_sys>; }; - lvds-encoder { - compatible = "ti,sn75lvds83", "lvds-encoder"; + i2cmux { + compatible = "i2c-mux-pinctrl"; + #address-cells = <1>; + #size-cells = <0>; - powerdown-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_LOW>; - power-supply = <&vdd_3v3_sys>; + i2c-parent = <&{/i2c@7000c400}>; - ports { + pinctrl-names = "ddc", "pta", "idle"; + pinctrl-0 = <&state_i2cmux_ddc>; + pinctrl-1 = <&state_i2cmux_pta>; + pinctrl-2 = <&state_i2cmux_idle>; + + hdmi_ddc: i2c@0 { + reg = <0>; #address-cells = <1>; #size-cells = <0>; - - port@0 { - reg = <0>; - - lvds_encoder_input: endpoint { - remote-endpoint = <&lcd_output>; - }; - }; - - port@1 { - reg = <1>; - - lvds_encoder_output: endpoint { - remote-endpoint = <&panel_input>; - }; - }; }; - }; - - vdd_5v0_sys: regulator-5v0 { - compatible = "regulator-fixed"; - regulator-name = "vdd_5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - vdd_3v3_sys: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "vdd_3v3_vs"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - vin-supply = <&vdd_5v0_sys>; - }; - vdd_1v8_sys: regulator-1v8 { - compatible = "regulator-fixed"; - regulator-name = "vdd_1v8_vs"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - vin-supply = <&vdd_5v0_sys>; - }; - - vdd_pnl: regulator-panel { - compatible = "regulator-fixed"; - regulator-name = "vdd_panel"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <300000>; - gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_5v0_sys>; - }; - - sound { - compatible = "nvidia,tegra-audio-wm8903-picasso", - "nvidia,tegra-audio-wm8903"; - nvidia,model = "Acer Iconia Tab A500 WM8903"; - - nvidia,audio-routing = - "Headphone Jack", "HPOUTR", - "Headphone Jack", "HPOUTL", - "Int Spk", "LINEOUTL", - "Int Spk", "LINEOUTR", - "Mic Jack", "MICBIAS", - "IN2L", "Mic Jack", - "IN2R", "Mic Jack", - "IN1L", "Int Mic", - "IN1R", "Int Mic"; - - nvidia,i2s-controller = <&tegra_i2s1>; - nvidia,audio-codec = <&wm8903>; - - nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; - nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; - nvidia,int-mic-en-gpios = <&wm8903 1 GPIO_ACTIVE_HIGH>; - nvidia,headset; - - clocks = <&tegra_car TEGRA20_CLK_PLL_A>, - <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA20_CLK_CDEV1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; - }; - - thermal-zones { - /* - * NCT1008 has two sensors: - * - * 0: internal that monitors ambient/skin temperature - * 1: external that is connected to the CPU's diode - * - * Ideally we should use userspace thermal governor, - * but it's a much more complex solution. The "skin" - * zone is a simpler solution which prevents A500 from - * getting too hot from a user's tactile perspective. - * The CPU zone is intended to protect silicon from damage. - */ - - skin-thermal { - polling-delay-passive = <1000>; /* milliseconds */ - polling-delay = <5000>; /* milliseconds */ - - thermal-sensors = <&nct1008 0>; - - trips { - trip0: skin-alert { - /* start throttling at 60C */ - temperature = <60000>; - hysteresis = <200>; - type = "passive"; - }; - - trip1: skin-crit { - /* shut down at 70C */ - temperature = <70000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&trip0>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu-thermal { - polling-delay-passive = <1000>; /* milliseconds */ - polling-delay = <5000>; /* milliseconds */ - - thermal-sensors = <&nct1008 1>; - - trips { - trip2: cpu-alert { - /* throttle at 85C until temperature drops to 84.8C */ - temperature = <85000>; - hysteresis = <200>; - type = "passive"; - }; - - trip3: cpu-crit { - /* shut down at 90C */ - temperature = <90000>; - hysteresis = <2000>; - type = "critical"; - }; - }; + panel_ddc: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; - cooling-maps { - map1 { - trip = <&trip2>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; + embedded-controller@58 { + compatible = "acer,a500-iconia-ec", "ene,kb930"; + reg = <0x58>; + + system-power-controller; + + monitored-battery = <&bat1010>; + power-supplies = <&mains>; }; }; }; - memory-controller@7000f400 { - nvidia,use-ram-code; + lvds-encoder { + compatible = "ti,sn75lvds83", "lvds-encoder"; - emc-tables@0 { - nvidia,ram-code = <0>; /* elpida-8gb */ - reg = <0>; + powerdown-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_LOW>; + power-supply = <&vdd_3v3_sys>; + ports { #address-cells = <1>; #size-cells = <0>; - emc-table@25000 { - reg = <25000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <25000>; - nvidia,emc-registers = <0x00000002 0x00000006 - 0x00000003 0x00000003 0x00000006 0x00000004 - 0x00000002 0x00000009 0x00000003 0x00000003 - 0x00000002 0x00000002 0x00000002 0x00000004 - 0x00000003 0x00000008 0x0000000b 0x0000004d - 0x00000000 0x00000003 0x00000003 0x00000003 - 0x00000008 0x00000001 0x0000000a 0x00000004 - 0x00000003 0x00000008 0x00000004 0x00000006 - 0x00000002 0x00000068 0x00000000 0x00000003 - 0x00000000 0x00000000 0x00000282 0xa0ae04ae - 0x00070000 0x00000000 0x00000000 0x00000003 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; - - emc-table@50000 { - reg = <50000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <50000>; - nvidia,emc-registers = <0x00000003 0x00000007 - 0x00000003 0x00000003 0x00000006 0x00000004 - 0x00000002 0x00000009 0x00000003 0x00000003 - 0x00000002 0x00000002 0x00000002 0x00000005 - 0x00000003 0x00000008 0x0000000b 0x0000009f - 0x00000000 0x00000003 0x00000003 0x00000003 - 0x00000008 0x00000001 0x0000000a 0x00000007 - 0x00000003 0x00000008 0x00000004 0x00000006 - 0x00000002 0x000000d0 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000282 0xa0ae04ae - 0x00070000 0x00000000 0x00000000 0x00000005 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; + port@0 { + reg = <0>; - emc-table@75000 { - reg = <75000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <75000>; - nvidia,emc-registers = <0x00000005 0x0000000a - 0x00000004 0x00000003 0x00000006 0x00000004 - 0x00000002 0x00000009 0x00000003 0x00000003 - 0x00000002 0x00000002 0x00000002 0x00000005 - 0x00000003 0x00000008 0x0000000b 0x000000ff - 0x00000000 0x00000003 0x00000003 0x00000003 - 0x00000008 0x00000001 0x0000000a 0x0000000b - 0x00000003 0x00000008 0x00000004 0x00000006 - 0x00000002 0x00000138 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000282 0xa0ae04ae - 0x00070000 0x00000000 0x00000000 0x00000007 - 0x00000000 0x00000000 0x00000000 0x00000000>; + lvds_encoder_input: endpoint { + remote-endpoint = <&lcd_output>; + }; }; - emc-table@150000 { - reg = <150000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <150000>; - nvidia,emc-registers = <0x00000009 0x00000014 - 0x00000007 0x00000003 0x00000006 0x00000004 - 0x00000002 0x00000009 0x00000003 0x00000003 - 0x00000002 0x00000002 0x00000002 0x00000005 - 0x00000003 0x00000008 0x0000000b 0x0000021f - 0x00000000 0x00000003 0x00000003 0x00000003 - 0x00000008 0x00000001 0x0000000a 0x00000015 - 0x00000003 0x00000008 0x00000004 0x00000006 - 0x00000002 0x00000270 0x00000000 0x00000001 - 0x00000000 0x00000000 0x00000282 0xa07c04ae - 0x007dd510 0x00000000 0x00000000 0x0000000e - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; + port@1 { + reg = <1>; - emc-table@300000 { - reg = <300000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <300000>; - nvidia,emc-registers = <0x00000012 0x00000027 - 0x0000000d 0x00000006 0x00000007 0x00000005 - 0x00000003 0x00000009 0x00000006 0x00000006 - 0x00000003 0x00000003 0x00000002 0x00000006 - 0x00000003 0x00000009 0x0000000c 0x0000045f - 0x00000000 0x00000004 0x00000004 0x00000006 - 0x00000008 0x00000001 0x0000000e 0x0000002a - 0x00000003 0x0000000f 0x00000007 0x00000005 - 0x00000002 0x000004e1 0x00000005 0x00000002 - 0x00000000 0x00000000 0x00000282 0xe059048b - 0x007e1510 0x00000000 0x00000000 0x0000001b - 0x00000000 0x00000000 0x00000000 0x00000000>; + lvds_encoder_output: endpoint { + remote-endpoint = <&panel_input>; + }; }; }; + }; - emc-tables@1 { - nvidia,ram-code = <1>; /* elpida-4gb */ - reg = <1>; + opp-table-emc { + /delete-node/ opp-666000000; + /delete-node/ opp-760000000; + }; - #address-cells = <1>; - #size-cells = <0>; + vdd_5v0_sys: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; - emc-table@25000 { - reg = <25000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <25000>; - nvidia,emc-registers = <0x00000002 0x00000006 - 0x00000003 0x00000003 0x00000006 0x00000004 - 0x00000002 0x00000009 0x00000003 0x00000003 - 0x00000002 0x00000002 0x00000002 0x00000004 - 0x00000003 0x00000008 0x0000000b 0x0000004d - 0x00000000 0x00000003 0x00000003 0x00000003 - 0x00000008 0x00000001 0x0000000a 0x00000004 - 0x00000003 0x00000008 0x00000004 0x00000006 - 0x00000002 0x00000068 0x00000000 0x00000003 - 0x00000000 0x00000000 0x00000282 0xa0ae04ae - 0x0007c000 0x00000000 0x00000000 0x00000003 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; + vdd_3v3_sys: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3_vs"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + vin-supply = <&vdd_5v0_sys>; + }; - emc-table@50000 { - reg = <50000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <50000>; - nvidia,emc-registers = <0x00000003 0x00000007 - 0x00000003 0x00000003 0x00000006 0x00000004 - 0x00000002 0x00000009 0x00000003 0x00000003 - 0x00000002 0x00000002 0x00000002 0x00000005 - 0x00000003 0x00000008 0x0000000b 0x0000009f - 0x00000000 0x00000003 0x00000003 0x00000003 - 0x00000008 0x00000001 0x0000000a 0x00000007 - 0x00000003 0x00000008 0x00000004 0x00000006 - 0x00000002 0x000000d0 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000282 0xa0ae04ae - 0x0007c000 0x00000000 0x00000000 0x00000005 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; + vdd_1v8_sys: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vdd_1v8_vs"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + vin-supply = <&vdd_5v0_sys>; + }; - emc-table@75000 { - reg = <75000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <75000>; - nvidia,emc-registers = <0x00000005 0x0000000a - 0x00000004 0x00000003 0x00000006 0x00000004 - 0x00000002 0x00000009 0x00000003 0x00000003 - 0x00000002 0x00000002 0x00000002 0x00000005 - 0x00000003 0x00000008 0x0000000b 0x000000ff - 0x00000000 0x00000003 0x00000003 0x00000003 - 0x00000008 0x00000001 0x0000000a 0x0000000b - 0x00000003 0x00000008 0x00000004 0x00000006 - 0x00000002 0x00000138 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000282 0xa0ae04ae - 0x0007c000 0x00000000 0x00000000 0x00000007 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; + vdd_pnl: regulator-panel { + compatible = "regulator-fixed"; + regulator-name = "vdd_panel"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <300000>; + gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; + }; - emc-table@150000 { - reg = <150000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <150000>; - nvidia,emc-registers = <0x00000009 0x00000014 - 0x00000007 0x00000003 0x00000006 0x00000004 - 0x00000002 0x00000009 0x00000003 0x00000003 - 0x00000002 0x00000002 0x00000002 0x00000005 - 0x00000003 0x00000008 0x0000000b 0x0000021f - 0x00000000 0x00000003 0x00000003 0x00000003 - 0x00000008 0x00000001 0x0000000a 0x00000015 - 0x00000003 0x00000008 0x00000004 0x00000006 - 0x00000002 0x00000270 0x00000000 0x00000001 - 0x00000000 0x00000000 0x00000282 0xa07c04ae - 0x007e4010 0x00000000 0x00000000 0x0000000e - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; + sound { + compatible = "nvidia,tegra-audio-wm8903-picasso", + "nvidia,tegra-audio-wm8903"; + nvidia,model = "Acer Iconia Tab A500 WM8903"; - emc-table@300000 { - reg = <300000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <300000>; - nvidia,emc-registers = <0x00000012 0x00000027 - 0x0000000d 0x00000006 0x00000007 0x00000005 - 0x00000003 0x00000009 0x00000006 0x00000006 - 0x00000003 0x00000003 0x00000002 0x00000006 - 0x00000003 0x00000009 0x0000000c 0x0000045f - 0x00000000 0x00000004 0x00000004 0x00000006 - 0x00000008 0x00000001 0x0000000e 0x0000002a - 0x00000003 0x0000000f 0x00000007 0x00000005 - 0x00000002 0x000004e1 0x00000005 0x00000002 - 0x00000000 0x00000000 0x00000282 0xe059048b - 0x007e0010 0x00000000 0x00000000 0x0000001b - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; - }; + nvidia,audio-routing = + "Headphone Jack", "HPOUTR", + "Headphone Jack", "HPOUTL", + "Int Spk", "LINEOUTL", + "Int Spk", "LINEOUTR", + "Mic Jack", "MICBIAS", + "IN2L", "Mic Jack", + "IN2R", "Mic Jack", + "IN1L", "Int Mic", + "IN1R", "Int Mic"; + + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,audio-codec = <&wm8903>; + + nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; + nvidia,int-mic-en-gpios = <&wm8903 1 GPIO_ACTIVE_HIGH>; + nvidia,headset; - emc-tables@2 { - nvidia,ram-code = <2>; /* hynix-8gb */ - reg = <2>; + clocks = <&tegra_car TEGRA20_CLK_PLL_A>, + <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA20_CLK_CDEV1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; + }; - #address-cells = <1>; - #size-cells = <0>; + thermal-zones { + /* + * NCT1008 has two sensors: + * + * 0: internal that monitors ambient/skin temperature + * 1: external that is connected to the CPU's diode + * + * Ideally we should use userspace thermal governor, + * but it's a much more complex solution. The "skin" + * zone is a simpler solution which prevents A500 from + * getting too hot from a user's tactile perspective. + * The CPU zone is intended to protect silicon from damage. + */ - emc-table@25000 { - reg = <25000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <25000>; - nvidia,emc-registers = <0x00000002 0x00000006 - 0x00000003 0x00000003 0x00000006 0x00000004 - 0x00000002 0x00000009 0x00000003 0x00000003 - 0x00000002 0x00000002 0x00000002 0x00000004 - 0x00000003 0x00000008 0x0000000b 0x0000004d - 0x00000000 0x00000003 0x00000003 0x00000003 - 0x00000008 0x00000001 0x0000000a 0x00000004 - 0x00000003 0x00000008 0x00000004 0x00000006 - 0x00000002 0x00000068 0x00000000 0x00000003 - 0x00000000 0x00000000 0x00000282 0xa0ae04ae - 0x00070000 0x00000000 0x00000000 0x00000003 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; + skin-thermal { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ - emc-table@50000 { - reg = <50000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <50000>; - nvidia,emc-registers = <0x00000003 0x00000007 - 0x00000003 0x00000003 0x00000006 0x00000004 - 0x00000002 0x00000009 0x00000003 0x00000003 - 0x00000002 0x00000002 0x00000002 0x00000005 - 0x00000003 0x00000008 0x0000000b 0x0000009f - 0x00000000 0x00000003 0x00000003 0x00000003 - 0x00000008 0x00000001 0x0000000a 0x00000007 - 0x00000003 0x00000008 0x00000004 0x00000006 - 0x00000002 0x000000d0 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000282 0xa0ae04ae - 0x00070000 0x00000000 0x00000000 0x00000005 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; + thermal-sensors = <&nct1008 0>; - emc-table@75000 { - reg = <75000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <75000>; - nvidia,emc-registers = <0x00000005 0x0000000a - 0x00000004 0x00000003 0x00000006 0x00000004 - 0x00000002 0x00000009 0x00000003 0x00000003 - 0x00000002 0x00000002 0x00000002 0x00000005 - 0x00000003 0x00000008 0x0000000b 0x000000ff - 0x00000000 0x00000003 0x00000003 0x00000003 - 0x00000008 0x00000001 0x0000000a 0x0000000b - 0x00000003 0x00000008 0x00000004 0x00000006 - 0x00000002 0x00000138 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000282 0xa0ae04ae - 0x00070000 0x00000000 0x00000000 0x00000007 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; + trips { + trip0: skin-alert { + /* start throttling at 60C */ + temperature = <60000>; + hysteresis = <200>; + type = "passive"; + }; - emc-table@150000 { - reg = <150000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <150000>; - nvidia,emc-registers = <0x00000009 0x00000014 - 0x00000007 0x00000003 0x00000006 0x00000004 - 0x00000002 0x00000009 0x00000003 0x00000003 - 0x00000002 0x00000002 0x00000002 0x00000005 - 0x00000003 0x00000008 0x0000000b 0x0000021f - 0x00000000 0x00000003 0x00000003 0x00000003 - 0x00000008 0x00000001 0x0000000a 0x00000015 - 0x00000003 0x00000008 0x00000004 0x00000006 - 0x00000002 0x00000270 0x00000000 0x00000001 - 0x00000000 0x00000000 0x00000282 0xa07c04ae - 0x007dd010 0x00000000 0x00000000 0x0000000e - 0x00000000 0x00000000 0x00000000 0x00000000>; + trip1: skin-crit { + /* shut down at 70C */ + temperature = <70000>; + hysteresis = <2000>; + type = "critical"; + }; }; - emc-table@300000 { - reg = <300000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <300000>; - nvidia,emc-registers = <0x00000012 0x00000027 - 0x0000000d 0x00000006 0x00000007 0x00000005 - 0x00000003 0x00000009 0x00000006 0x00000006 - 0x00000003 0x00000003 0x00000002 0x00000006 - 0x00000003 0x00000009 0x0000000c 0x0000045f - 0x00000000 0x00000004 0x00000004 0x00000006 - 0x00000008 0x00000001 0x0000000e 0x0000002a - 0x00000003 0x0000000f 0x00000007 0x00000005 - 0x00000002 0x000004e1 0x00000005 0x00000002 - 0x00000000 0x00000000 0x00000282 0xe059048b - 0x007e2010 0x00000000 0x00000000 0x0000001b - 0x00000000 0x00000000 0x00000000 0x00000000>; + cooling-maps { + map0 { + trip = <&trip0>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; }; }; - emc-tables@3 { - nvidia,ram-code = <3>; /* hynix-4gb */ - reg = <3>; - - #address-cells = <1>; - #size-cells = <0>; - - emc-table@25000 { - reg = <25000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <25000>; - nvidia,emc-registers = <0x00000002 0x00000006 - 0x00000003 0x00000003 0x00000006 0x00000004 - 0x00000002 0x00000009 0x00000003 0x00000003 - 0x00000002 0x00000002 0x00000002 0x00000004 - 0x00000003 0x00000008 0x0000000b 0x0000004d - 0x00000000 0x00000003 0x00000003 0x00000003 - 0x00000008 0x00000001 0x0000000a 0x00000004 - 0x00000003 0x00000008 0x00000004 0x00000006 - 0x00000002 0x00000068 0x00000000 0x00000003 - 0x00000000 0x00000000 0x00000282 0xa0ae04ae - 0x0007c000 0x00000000 0x00000000 0x00000003 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; + cpu-thermal { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ - emc-table@50000 { - reg = <50000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <50000>; - nvidia,emc-registers = <0x00000003 0x00000007 - 0x00000003 0x00000003 0x00000006 0x00000004 - 0x00000002 0x00000009 0x00000003 0x00000003 - 0x00000002 0x00000002 0x00000002 0x00000005 - 0x00000003 0x00000008 0x0000000b 0x0000009f - 0x00000000 0x00000003 0x00000003 0x00000003 - 0x00000008 0x00000001 0x0000000a 0x00000007 - 0x00000003 0x00000008 0x00000004 0x00000006 - 0x00000002 0x000000d0 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000282 0xa0ae04ae - 0x0007c000 0x00078000 0x00000000 0x00000005 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; + thermal-sensors = <&nct1008 1>; - emc-table@75000 { - reg = <75000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <75000>; - nvidia,emc-registers = <0x00000005 0x0000000a - 0x00000004 0x00000003 0x00000006 0x00000004 - 0x00000002 0x00000009 0x00000003 0x00000003 - 0x00000002 0x00000002 0x00000002 0x00000005 - 0x00000003 0x00000008 0x0000000b 0x000000ff - 0x00000000 0x00000003 0x00000003 0x00000003 - 0x00000008 0x00000001 0x0000000a 0x0000000b - 0x00000003 0x00000008 0x00000004 0x00000006 - 0x00000002 0x00000138 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000282 0xa0ae04ae - 0x0007c000 0x00000000 0x00000000 0x00000007 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; + trips { + trip2: cpu-alert { + /* throttle at 85C until temperature drops to 84.8C */ + temperature = <85000>; + hysteresis = <200>; + type = "passive"; + }; - emc-table@150000 { - reg = <150000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <150000>; - nvidia,emc-registers = <0x00000009 0x00000014 - 0x00000007 0x00000003 0x00000006 0x00000004 - 0x00000002 0x00000009 0x00000003 0x00000003 - 0x00000002 0x00000002 0x00000002 0x00000005 - 0x00000003 0x00000008 0x0000000b 0x0000021f - 0x00000000 0x00000003 0x00000003 0x00000003 - 0x00000008 0x00000001 0x0000000a 0x00000015 - 0x00000003 0x00000008 0x00000004 0x00000006 - 0x00000002 0x00000270 0x00000000 0x00000001 - 0x00000000 0x00000000 0x00000282 0xa07c04ae - 0x007e4010 0x00000000 0x00000000 0x0000000e - 0x00000000 0x00000000 0x00000000 0x00000000>; + trip3: cpu-crit { + /* shut down at 90C */ + temperature = <90000>; + hysteresis = <2000>; + type = "critical"; + }; }; - emc-table@300000 { - reg = <300000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <300000>; - nvidia,emc-registers = <0x00000012 0x00000027 - 0x0000000d 0x00000006 0x00000007 0x00000005 - 0x00000003 0x00000009 0x00000006 0x00000006 - 0x00000003 0x00000003 0x00000002 0x00000006 - 0x00000003 0x00000009 0x0000000c 0x0000045f - 0x00000000 0x00000004 0x00000004 0x00000006 - 0x00000008 0x00000001 0x0000000e 0x0000002a - 0x00000003 0x0000000f 0x00000007 0x00000005 - 0x00000002 0x000004e1 0x00000005 0x00000002 - 0x00000000 0x00000000 0x00000282 0xe059048b - 0x007e0010 0x00000000 0x00000000 0x0000001b - 0x00000000 0x00000000 0x00000000 0x00000000>; + cooling-maps { + map1 { + trip = <&trip2>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; }; }; }; -}; -&emc_icc_dvfs_opp_table { - /delete-node/ opp-666000000; - /delete-node/ opp-760000000; + brcm_wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + + clocks = <&rtc_32k_wifi>; + clock-names = "ext_clock"; + + reset-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_LOW>; + post-power-on-delay-ms = <300>; + power-off-delay-us = <300>; + }; }; diff --git a/arch/arm/boot/dts/tegra20-asus-tf101.dts b/arch/arm/boot/dts/tegra20-asus-tf101.dts index c39ddb462ad01b..7b2969656ec964 100644 --- a/arch/arm/boot/dts/tegra20-asus-tf101.dts +++ b/arch/arm/boot/dts/tegra20-asus-tf101.dts @@ -411,7 +411,7 @@ }; }; - state_i2cmux_pta: pinmux-i2cmux-pta { + state_i2cmux_idle: pinmux-i2cmux-idle { ddc { nvidia,pins = "ddc"; nvidia,function = "rsvd4"; @@ -419,11 +419,11 @@ pta { nvidia,pins = "pta"; - nvidia,function = "i2c2"; + nvidia,function = "rsvd4"; }; }; - state_i2cmux_idle: pinmux-i2cmux-idle { + state_i2cmux_pta: pinmux-i2cmux-pta { ddc { nvidia,pins = "ddc"; nvidia,function = "rsvd4"; @@ -431,7 +431,7 @@ pta { nvidia,pins = "pta"; - nvidia,function = "rsvd4"; + nvidia,function = "i2c2"; }; }; }; @@ -764,13 +764,6 @@ #address-cells = <1>; #size-cells = <0>; - lpddr2 { - compatible = "elpida,B8132B2PB-6D-F", "jedec,lpddr2-s4"; - revision-id = <1 0>; - density = <2048>; - io-width = <16>; - }; - emc-table@25000 { reg = <25000>; compatible = "nvidia,tegra20-emc-table"; @@ -860,6 +853,13 @@ 0x007e0010 0x00000000 0x00000000 0x0000001b 0x00000000 0x00000000 0x00000000 0x00000000>; }; + + lpddr2 { + compatible = "elpida,B8132B2PB-6D-F", "jedec,lpddr2-s4"; + revision-id = <1 0>; + density = <2048>; + io-width = <16>; + }; }; }; @@ -977,47 +977,6 @@ }; }; - gpio-keys { - compatible = "gpio-keys"; - - switch-dock-hall-sensor { - label = "Lid"; - gpios = <&gpio TEGRA_GPIO(S, 4) GPIO_ACTIVE_LOW>; - linux,input-type = ; - linux,code = ; - debounce-interval = <500>; - wakeup-event-action = ; - wakeup-source; - }; - - key-power { - label = "Power"; - gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <10>; - wakeup-event-action = ; - wakeup-source; - }; - - key-volume-up { - label = "Volume Up"; - gpios = <&gpio TEGRA_GPIO(Q, 5) GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <10>; - wakeup-event-action = ; - wakeup-source; - }; - - key-volume-down { - label = "Volume Down"; - gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <10>; - wakeup-event-action = ; - wakeup-source; - }; - }; - display-panel { compatible = "auo,b101ew05", "panel-lvds"; @@ -1051,6 +1010,47 @@ }; }; + gpio-keys { + compatible = "gpio-keys"; + + key-power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + wakeup-event-action = ; + wakeup-source; + }; + + key-volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + wakeup-event-action = ; + wakeup-source; + }; + + key-volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(Q, 5) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + wakeup-event-action = ; + wakeup-source; + }; + + switch-dock-hall-sensor { + label = "Lid"; + gpios = <&gpio TEGRA_GPIO(S, 4) GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + debounce-interval = <500>; + wakeup-event-action = ; + wakeup-source; + }; + }; + i2cmux { compatible = "i2c-mux-pinctrl"; #address-cells = <1>; @@ -1112,6 +1112,11 @@ }; }; + opp-table-emc { + /delete-node/ opp-666000000; + /delete-node/ opp-760000000; + }; + vdd_5v0_sys: regulator-5v0 { compatible = "regulator-fixed"; regulator-name = "vdd_5v0"; @@ -1283,8 +1288,3 @@ power-off-delay-us = <200>; }; }; - -&emc_icc_dvfs_opp_table { - /delete-node/ opp-666000000; - /delete-node/ opp-760000000; -}; diff --git a/arch/arm/boot/dts/tegra20-colibri-eval-v3.dts b/arch/arm/boot/dts/tegra20-colibri-eval-v3.dts index cb1190b77db353..612f4e54cb2028 100644 --- a/arch/arm/boot/dts/tegra20-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/tegra20-colibri-eval-v3.dts @@ -143,6 +143,24 @@ status = "okay"; }; + /* SPI4: Colibri SSP */ + spi@7000da00 { + status = "okay"; + spi-max-frequency = <25000000>; + + can@0 { + compatible = "microchip,mcp2515"; + reg = <0>; + clocks = <&clk16m>; + interrupt-parent = <&gpio>; + /* CAN_INT */ + interrupts = ; + spi-max-frequency = <10000000>; + vdd-supply = <®_3v3>; + xceiver-supply = <®_5v0>; + }; + }; + /* EHCI instance 0: USB1_DP/N -> USBC_P/N */ usb@c5000000 { status = "okay"; @@ -164,24 +182,6 @@ vbus-supply = <®_usbh_vbus>; }; - /* SPI4: Colibri SSP */ - spi@7000da00 { - status = "okay"; - spi-max-frequency = <25000000>; - - can@0 { - compatible = "microchip,mcp2515"; - reg = <0>; - clocks = <&clk16m>; - interrupt-parent = <&gpio>; - /* CAN_INT */ - interrupts = ; - spi-max-frequency = <10000000>; - vdd-supply = <®_3v3>; - xceiver-supply = <®_5v0>; - }; - }; - /* SD/MMC */ mmc@c8000600 { status = "okay"; @@ -200,7 +200,7 @@ pwms = <&pwm 0 5000000>; /* PWM */ }; - clk16m: osc3 { + clk16m: clock-osc3 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <16000000>; diff --git a/arch/arm/boot/dts/tegra20-colibri-iris.dts b/arch/arm/boot/dts/tegra20-colibri-iris.dts index 53487cc2151380..25a9f5dfe62d00 100644 --- a/arch/arm/boot/dts/tegra20-colibri-iris.dts +++ b/arch/arm/boot/dts/tegra20-colibri-iris.dts @@ -143,6 +143,12 @@ status = "okay"; }; + /* SPI4: Colibri SSP */ + spi@7000da00 { + status = "okay"; + spi-max-frequency = <25000000>; + }; + /* EHCI instance 0: USB1_DP/N -> USBC_P/N */ usb@c5000000 { status = "okay"; @@ -164,12 +170,6 @@ vbus-supply = <®_usbh_vbus>; }; - /* SPI4: Colibri SSP */ - spi@7000da00 { - status = "okay"; - spi-max-frequency = <25000000>; - }; - /* SD/MMC */ mmc@c8000600 { status = "okay"; diff --git a/arch/arm/boot/dts/tegra20-colibri.dtsi b/arch/arm/boot/dts/tegra20-colibri.dtsi index 8ebd8afc857da3..0e03910abbe640 100644 --- a/arch/arm/boot/dts/tegra20-colibri.dtsi +++ b/arch/arm/boot/dts/tegra20-colibri.dtsi @@ -27,6 +27,31 @@ }; }; + gpio@6000d000 { + lan-reset-n-hog { + gpio-hog; + gpios = ; + output-high; + line-name = "LAN_RESET#"; + }; + + /* Tri-stating GMI_WR_N on SODIMM pin 99 nPWE */ + npwe-hog { + gpio-hog; + gpios = ; + output-high; + line-name = "Tri-state nPWE"; + }; + + /* Not tri-stating GMI_WR_N on SODIMM pin 93 RDnWR */ + rdnwr-hog { + gpio-hog; + gpios = ; + output-low; + line-name = "Not tri-state RDnWR"; + }; + }; + pinmux@70000014 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; @@ -705,12 +730,16 @@ vbus-supply = <®_lan_v_bus>; }; - clk32k_in: xtal3 { + clk32k_in: clock-xtal3 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; }; + opp-table-emc { + /delete-node/ opp-760000000; + }; + reg_lan_v_bus: regulator-lan-v-bus { compatible = "regulator-fixed"; regulator-name = "LAN_V_BUS"; @@ -745,32 +774,3 @@ clock-names = "pll_a", "pll_a_out0", "mclk"; }; }; - -&emc_icc_dvfs_opp_table { - /delete-node/ opp-760000000; -}; - -&gpio { - lan-reset-n-hog { - gpio-hog; - gpios = ; - output-high; - line-name = "LAN_RESET#"; - }; - - /* Tri-stating GMI_WR_N on SODIMM pin 99 nPWE */ - npwe-hog { - gpio-hog; - gpios = ; - output-high; - line-name = "Tri-state nPWE"; - }; - - /* Not tri-stating GMI_WR_N on SODIMM pin 93 RDnWR */ - rdnwr-hog { - gpio-hog; - gpios = ; - output-low; - line-name = "Not tri-state RDnWR"; - }; -}; diff --git a/arch/arm/boot/dts/tegra20-medcom-wide.dts b/arch/arm/boot/dts/tegra20-medcom-wide.dts index f144487c5da3c1..8c657182fff32c 100644 --- a/arch/arm/boot/dts/tegra20-medcom-wide.dts +++ b/arch/arm/boot/dts/tegra20-medcom-wide.dts @@ -15,10 +15,6 @@ stdout-path = "serial0:115200n8"; }; - pwm@7000a000 { - status = "okay"; - }; - host1x@50000000 { dc@54200000 { rgb { @@ -28,6 +24,10 @@ }; }; + pwm@7000a000 { + status = "okay"; + }; + i2c@7000c000 { wm8903: wm8903@1a { compatible = "wlf,wm8903"; diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index 48fe628c6d8752..e995f428dc2eae 100644 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts @@ -323,53 +323,6 @@ reset-names = "i2c"; }; - memory-controller@7000f400 { - nvidia,use-ram-code; - - emc-tables@0 { - nvidia,ram-code = <0x0>; - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - emc-table@166500 { - reg = <166500>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <166500>; - nvidia,emc-registers = <0x0000000a 0x00000016 - 0x00000008 0x00000003 0x00000004 0x00000004 - 0x00000002 0x0000000c 0x00000003 0x00000003 - 0x00000002 0x00000001 0x00000004 0x00000005 - 0x00000004 0x00000009 0x0000000d 0x000004df - 0x00000000 0x00000003 0x00000003 0x00000003 - 0x00000003 0x00000001 0x0000000a 0x000000c8 - 0x00000003 0x00000006 0x00000004 0x00000008 - 0x00000002 0x00000000 0x00000000 0x00000002 - 0x00000000 0x00000000 0x00000083 0xe03b0323 - 0x007fe010 0x00001414 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; - - emc-table@333000 { - reg = <333000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <333000>; - nvidia,emc-registers = <0x00000018 0x00000033 - 0x00000012 0x00000004 0x00000004 0x00000005 - 0x00000003 0x0000000c 0x00000006 0x00000006 - 0x00000003 0x00000001 0x00000004 0x00000005 - 0x00000004 0x00000009 0x0000000d 0x00000bff - 0x00000000 0x00000003 0x00000003 0x00000006 - 0x00000006 0x00000001 0x00000011 0x000000c8 - 0x00000003 0x0000000e 0x00000007 0x00000008 - 0x00000002 0x00000000 0x00000000 0x00000002 - 0x00000000 0x00000000 0x00000083 0xf0440303 - 0x007fe010 0x00001414 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; - }; - }; - i2c@7000d000 { status = "okay"; clock-frequency = <400000>; @@ -532,6 +485,53 @@ core-supply = <&core_vdd_reg>; }; + memory-controller@7000f400 { + nvidia,use-ram-code; + + emc-tables@0 { + nvidia,ram-code = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + emc-table@166500 { + reg = <166500>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <166500>; + nvidia,emc-registers = <0x0000000a 0x00000016 + 0x00000008 0x00000003 0x00000004 0x00000004 + 0x00000002 0x0000000c 0x00000003 0x00000003 + 0x00000002 0x00000001 0x00000004 0x00000005 + 0x00000004 0x00000009 0x0000000d 0x000004df + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000003 0x00000001 0x0000000a 0x000000c8 + 0x00000003 0x00000006 0x00000004 0x00000008 + 0x00000002 0x00000000 0x00000000 0x00000002 + 0x00000000 0x00000000 0x00000083 0xe03b0323 + 0x007fe010 0x00001414 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@333000 { + reg = <333000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <333000>; + nvidia,emc-registers = <0x00000018 0x00000033 + 0x00000012 0x00000004 0x00000004 0x00000005 + 0x00000003 0x0000000c 0x00000006 0x00000006 + 0x00000003 0x00000001 0x00000004 0x00000005 + 0x00000004 0x00000009 0x0000000d 0x00000bff + 0x00000000 0x00000003 0x00000003 0x00000006 + 0x00000006 0x00000001 0x00000011 0x000000c8 + 0x00000003 0x0000000e 0x00000007 0x00000008 + 0x00000002 0x00000000 0x00000000 0x00000002 + 0x00000000 0x00000000 0x00000083 0xf0440303 + 0x007fe010 0x00001414 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + }; + }; + usb@c5000000 { compatible = "nvidia,tegra20-udc"; status = "okay"; @@ -593,6 +593,20 @@ #clock-cells = <0>; }; + cpus { + cpu0: cpu@0 { + cpu-supply = <&cpu_vdd_reg>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + + cpu1: cpu@1 { + cpu-supply = <&cpu_vdd_reg>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + }; + gpio-keys { compatible = "gpio-keys"; @@ -614,6 +628,10 @@ }; }; + opp-table-emc { + /delete-node/ opp-760000000; + }; + panel: panel { compatible = "samsung,ltn101nt05"; @@ -668,20 +686,6 @@ clock-names = "pll_a", "pll_a_out0", "mclk"; }; - cpus { - cpu0: cpu@0 { - cpu-supply = <&cpu_vdd_reg>; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; - }; - - cpu1: cpu@1 { - cpu-supply = <&cpu_vdd_reg>; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; - }; - }; - thermal-zones { cpu-thermal { polling-delay-passive = <500>; /* milliseconds */ @@ -715,7 +719,3 @@ }; }; }; - -&emc_icc_dvfs_opp_table { - /delete-node/ opp-760000000; -}; diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts index ab33ff67fdb9dc..bd4ff8b40b208f 100644 --- a/arch/arm/boot/dts/tegra20-seaboard.dts +++ b/arch/arm/boot/dts/tegra20-seaboard.dts @@ -296,25 +296,25 @@ }; }; - state_i2cmux_pta: pinmux-i2cmux-pta { + state_i2cmux_idle: pinmux-i2cmux-idle { ddc { nvidia,pins = "ddc"; nvidia,function = "rsvd4"; }; pta { nvidia,pins = "pta"; - nvidia,function = "i2c2"; + nvidia,function = "rsvd4"; }; }; - state_i2cmux_idle: pinmux-i2cmux-idle { + state_i2cmux_pta: pinmux-i2cmux-pta { ddc { nvidia,pins = "ddc"; nvidia,function = "rsvd4"; }; pta { nvidia,pins = "pta"; - nvidia,function = "rsvd4"; + nvidia,function = "i2c2"; }; }; }; @@ -370,38 +370,6 @@ clock-frequency = <100000>; }; - i2cmux { - compatible = "i2c-mux-pinctrl"; - #address-cells = <1>; - #size-cells = <0>; - - i2c-parent = <&{/i2c@7000c400}>; - - pinctrl-names = "ddc", "pta", "idle"; - pinctrl-0 = <&state_i2cmux_ddc>; - pinctrl-1 = <&state_i2cmux_pta>; - pinctrl-2 = <&state_i2cmux_idle>; - - hdmi_ddc: i2c@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - }; - - lvds_ddc: i2c@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - smart-battery@b { - compatible = "ti,bq20z75", "sbs,sbs-battery"; - reg = <0xb>; - sbs,i2c-retry-count = <2>; - sbs,poll-retry-count = <10>; - }; - }; - }; - i2c@7000c500 { status = "okay"; clock-frequency = <400000>; @@ -817,6 +785,38 @@ }; }; + i2cmux { + compatible = "i2c-mux-pinctrl"; + #address-cells = <1>; + #size-cells = <0>; + + i2c-parent = <&{/i2c@7000c400}>; + + pinctrl-names = "ddc", "pta", "idle"; + pinctrl-0 = <&state_i2cmux_ddc>; + pinctrl-1 = <&state_i2cmux_pta>; + pinctrl-2 = <&state_i2cmux_idle>; + + hdmi_ddc: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + lvds_ddc: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + smart-battery@b { + compatible = "ti,bq20z75", "sbs,sbs-battery"; + reg = <0xb>; + sbs,i2c-retry-count = <2>; + sbs,poll-retry-count = <10>; + }; + }; + }; + panel: panel { compatible = "chunghwa,claa101wa01a"; diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi index 980272ad59a412..ddb84e4a9f8b69 100644 --- a/arch/arm/boot/dts/tegra20-tamonten.dtsi +++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi @@ -260,25 +260,25 @@ }; }; - state_i2cmux_pta: pinmux-i2cmux-pta { + state_i2cmux_idle: pinmux-i2cmux-idle { ddc { nvidia,pins = "ddc"; nvidia,function = "rsvd4"; }; pta { nvidia,pins = "pta"; - nvidia,function = "i2c2"; + nvidia,function = "rsvd4"; }; }; - state_i2cmux_idle: pinmux-i2cmux-idle { + state_i2cmux_pta: pinmux-i2cmux-pta { ddc { nvidia,pins = "ddc"; nvidia,function = "rsvd4"; }; pta { nvidia,pins = "pta"; - nvidia,function = "rsvd4"; + nvidia,function = "i2c2"; }; }; }; @@ -301,31 +301,6 @@ status = "okay"; }; - i2cmux { - compatible = "i2c-mux-pinctrl"; - #address-cells = <1>; - #size-cells = <0>; - - i2c-parent = <&{/i2c@7000c400}>; - - pinctrl-names = "ddc", "pta", "idle"; - pinctrl-0 = <&state_i2cmux_ddc>; - pinctrl-1 = <&state_i2cmux_pta>; - pinctrl-2 = <&state_i2cmux_idle>; - - hdmi_ddc: i2c@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - i2c@7000d000 { clock-frequency = <400000>; status = "okay"; @@ -509,6 +484,31 @@ #clock-cells = <0>; }; + i2cmux { + compatible = "i2c-mux-pinctrl"; + #address-cells = <1>; + #size-cells = <0>; + + i2c-parent = <&{/i2c@7000c400}>; + + pinctrl-names = "ddc", "pta", "idle"; + pinctrl-0 = <&state_i2cmux_ddc>; + pinctrl-1 = <&state_i2cmux_pta>; + pinctrl-2 = <&state_i2cmux_idle>; + + hdmi_ddc: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + pci_vdd_reg: regulator-1v05 { compatible = "regulator-fixed"; regulator-name = "vdd_1v05"; diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts index dc51835423a9e7..1944121e2dd6b7 100644 --- a/arch/arm/boot/dts/tegra20-trimslice.dts +++ b/arch/arm/boot/dts/tegra20-trimslice.dts @@ -385,6 +385,16 @@ #clock-cells = <0>; }; + cpus { + cpu0: cpu@0 { + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@1 { + operating-points-v2 = <&cpu0_opp_table>; + }; + }; + gpio-keys { compatible = "gpio-keys"; @@ -462,14 +472,4 @@ <&tegra_car TEGRA20_CLK_CDEV1>; clock-names = "pll_a", "pll_a_out0", "mclk"; }; - - cpus { - cpu0: cpu@0 { - operating-points-v2 = <&cpu0_opp_table>; - }; - - cpu@1 { - operating-points-v2 = <&cpu0_opp_table>; - }; - }; }; diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts index 2d7bb442d6b6a0..433575a6ad38fe 100644 --- a/arch/arm/boot/dts/tegra20-ventana.dts +++ b/arch/arm/boot/dts/tegra20-ventana.dts @@ -295,25 +295,25 @@ }; }; - state_i2cmux_pta: pinmux-i2cmux-pta { + state_i2cmux_idle: pinmux-i2cmux-idle { ddc { nvidia,pins = "ddc"; nvidia,function = "rsvd4"; }; pta { nvidia,pins = "pta"; - nvidia,function = "i2c2"; + nvidia,function = "rsvd4"; }; }; - state_i2cmux_idle: pinmux-i2cmux-idle { + state_i2cmux_pta: pinmux-i2cmux-pta { ddc { nvidia,pins = "ddc"; nvidia,function = "rsvd4"; }; pta { nvidia,pins = "pta"; - nvidia,function = "rsvd4"; + nvidia,function = "i2c2"; }; }; }; @@ -362,31 +362,6 @@ clock-frequency = <100000>; }; - i2cmux { - compatible = "i2c-mux-pinctrl"; - #address-cells = <1>; - #size-cells = <0>; - - i2c-parent = <&{/i2c@7000c400}>; - - pinctrl-names = "ddc", "pta", "idle"; - pinctrl-0 = <&state_i2cmux_ddc>; - pinctrl-1 = <&state_i2cmux_pta>; - pinctrl-2 = <&state_i2cmux_idle>; - - hdmi_ddc: i2c@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - }; - - lvds_ddc: i2c@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - i2c@7000c500 { status = "okay"; clock-frequency = <400000>; @@ -636,6 +611,31 @@ }; }; + i2cmux { + compatible = "i2c-mux-pinctrl"; + #address-cells = <1>; + #size-cells = <0>; + + i2c-parent = <&{/i2c@7000c400}>; + + pinctrl-names = "ddc", "pta", "idle"; + pinctrl-0 = <&state_i2cmux_ddc>; + pinctrl-1 = <&state_i2cmux_pta>; + pinctrl-2 = <&state_i2cmux_idle>; + + hdmi_ddc: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + lvds_ddc: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + panel: panel { compatible = "chunghwa,claa101wa01a"; diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 62bf0b30647214..4177d04265d83f 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -356,12 +356,6 @@ operating-points-v2 = <&vde_dvfs_opp_table>; }; - apbmisc@70000800 { - compatible = "nvidia,tegra20-apbmisc"; - reg = <0x70000800 0x64>, /* Chip revision */ - <0x70000008 0x04>; /* Strapping options */ - }; - pinmux: pinmux@70000014 { compatible = "nvidia,tegra20-pinmux"; reg = <0x70000014 0x10>, /* Tri-state registers */ @@ -370,6 +364,12 @@ <0x70000868 0xa8>; /* Pad control registers */ }; + apbmisc@70000800 { + compatible = "nvidia,tegra20-apbmisc"; + reg = <0x70000800 0x64>, /* Chip revision */ + <0x70000008 0x04>; /* Strapping options */ + }; + das@70000c00 { compatible = "nvidia,tegra20-das"; reg = <0x70000c00 0x80>; @@ -542,13 +542,6 @@ status = "disabled"; }; - rtc@7000e000 { - compatible = "nvidia,tegra20-rtc"; - reg = <0x7000e000 0x100>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_RTC>; - }; - i2c@7000c000 { compatible = "nvidia,tegra20-i2c"; reg = <0x7000c000 0x100>; @@ -683,6 +676,13 @@ status = "disabled"; }; + rtc@7000e000 { + compatible = "nvidia,tegra20-rtc"; + reg = <0x7000e000 0x100>; + interrupts = ; + clocks = <&tegra_car TEGRA20_CLK_RTC>; + }; + kbc@7000e200 { compatible = "nvidia,tegra20-kbc"; reg = <0x7000e200 0x100>; @@ -706,6 +706,16 @@ }; powergates { + pd_mpe: mpe { + clocks = <&tegra_car TEGRA20_CLK_MPE>; + resets = <&mc TEGRA20_MC_RESET_MPEA>, + <&mc TEGRA20_MC_RESET_MPEB>, + <&mc TEGRA20_MC_RESET_MPEC>, + <&tegra_car TEGRA20_CLK_MPE>; + power-domains = <&pd_core>; + #power-domain-cells = <0>; + }; + pd_3d: td { clocks = <&tegra_car TEGRA20_CLK_GR3D>; resets = <&mc TEGRA20_MC_RESET_3D>, @@ -714,6 +724,14 @@ #power-domain-cells = <0>; }; + pd_vde: vdec { + clocks = <&tegra_car TEGRA20_CLK_VDE>; + resets = <&mc TEGRA20_MC_RESET_VDE>, + <&tegra_car TEGRA20_CLK_VDE>; + power-domains = <&pd_core>; + #power-domain-cells = <0>; + }; + pd_venc: venc { clocks = <&tegra_car TEGRA20_CLK_ISP>, <&tegra_car TEGRA20_CLK_VI>, @@ -726,24 +744,6 @@ power-domains = <&pd_core>; #power-domain-cells = <0>; }; - - pd_vde: vdec { - clocks = <&tegra_car TEGRA20_CLK_VDE>; - resets = <&mc TEGRA20_MC_RESET_VDE>, - <&tegra_car TEGRA20_CLK_VDE>; - power-domains = <&pd_core>; - #power-domain-cells = <0>; - }; - - pd_mpe: mpe { - clocks = <&tegra_car TEGRA20_CLK_MPE>; - resets = <&mc TEGRA20_MC_RESET_MPEA>, - <&mc TEGRA20_MC_RESET_MPEB>, - <&mc TEGRA20_MC_RESET_MPEC>, - <&tegra_car TEGRA20_CLK_MPE>; - power-domains = <&pd_core>; - #power-domain-cells = <0>; - }; }; }; @@ -1049,13 +1049,13 @@ simple-audio-card,dai-link@0 { reg = <0>; - cpu { - sound-dai = <&tegra_spdif>; - }; - codec { sound-dai = <&tegra_hdmi>; }; + + cpu { + sound-dai = <&tegra_spdif>; + }; }; }; }; diff --git a/arch/arm/boot/dts/tegra30-apalis-eval.dts b/arch/arm/boot/dts/tegra30-apalis-eval.dts index ad968ff968d77c..842b5faba28564 100644 --- a/arch/arm/boot/dts/tegra30-apalis-eval.dts +++ b/arch/arm/boot/dts/tegra30-apalis-eval.dts @@ -47,6 +47,16 @@ }; }; + gpio@6000d000 { + /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */ + pex-perst-n-hog { + gpio-hog; + gpios = ; + output-high; + line-name = "PEX_PERST_N"; + }; + }; + /* Apalis UART1 */ serial@70006000 { status = "okay"; @@ -236,13 +246,3 @@ vin-supply = <®_5v0>; }; }; - -&gpio { - /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */ - pex-perst-n-hog { - gpio-hog; - gpios = ; - output-high; - line-name = "PEX_PERST_N"; - }; -}; diff --git a/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts b/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts index c172fdb5e1aeb2..ca277bf1df7840 100644 --- a/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts +++ b/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts @@ -48,6 +48,16 @@ }; }; + gpio@6000d000 { + /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */ + pex-perst-n-hog { + gpio-hog; + gpios = ; + output-high; + line-name = "PEX_PERST_N"; + }; + }; + /* Apalis UART1 */ serial@70006000 { status = "okay"; @@ -254,13 +264,3 @@ vin-supply = <&vddio_sdmmc_1v8_reg>; }; }; - -&gpio { - /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */ - pex-perst-n-hog { - gpio-hog; - gpios = ; - output-high; - line-name = "PEX_PERST_N"; - }; -}; diff --git a/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi b/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi index a1bcd67fa50591..a4b7fe5c3d2369 100644 --- a/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi +++ b/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi @@ -1007,6 +1007,12 @@ /* ADC converstion time: 80 clocks */ st,sample-time = <4>; + stmpe_adc { + compatible = "st,stmpe-adc"; + /* forbid to use ADC channels 3-0 (touch) */ + st,norequest-mask = <0x0F>; + }; + stmpe_touchscreen { compatible = "st,stmpe-ts"; /* 8 sample average control */ @@ -1023,12 +1029,6 @@ /* 5 ms touch detect interrupt delay */ st,touch-det-delay = <5>; }; - - stmpe_adc { - compatible = "st,stmpe-adc"; - /* forbid to use ADC channels 3-0 (touch) */ - st,norequest-mask = <0x0F>; - }; }; /* @@ -1122,16 +1122,16 @@ mmc-ddr-1_8v; }; - clk32k_in: xtal1 { + clk16m: clock-osc4 { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <32768>; + clock-frequency = <16000000>; }; - clk16m: osc4 { + clk32k_in: clock-xtal1 { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <16000000>; + clock-frequency = <32768>; }; reg_1v8_avdd_hdmi_pll: regulator-1v8-avdd-hdmi-pll { diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi index 99d7dad72d2917..d731038840008c 100644 --- a/arch/arm/boot/dts/tegra30-apalis.dtsi +++ b/arch/arm/boot/dts/tegra30-apalis.dtsi @@ -990,6 +990,12 @@ /* ADC converstion time: 80 clocks */ st,sample-time = <4>; + stmpe_adc { + compatible = "st,stmpe-adc"; + /* forbid to use ADC channels 3-0 (touch) */ + st,norequest-mask = <0x0F>; + }; + stmpe_touchscreen { compatible = "st,stmpe-ts"; /* 8 sample average control */ @@ -1006,12 +1012,6 @@ /* 5 ms touch detect interrupt delay */ st,touch-det-delay = <5>; }; - - stmpe_adc { - compatible = "st,stmpe-adc"; - /* forbid to use ADC channels 3-0 (touch) */ - st,norequest-mask = <0x0F>; - }; }; /* @@ -1105,16 +1105,16 @@ mmc-ddr-1_8v; }; - clk32k_in: xtal1 { + clk16m: clock-osc4 { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <32768>; + clock-frequency = <16000000>; }; - clk16m: osc4 { + clk32k_in: clock-xtal1 { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <16000000>; + clock-frequency = <32768>; }; reg_1v8_avdd_hdmi_pll: regulator-1v8-avdd-hdmi-pll { diff --git a/arch/arm/boot/dts/tegra30-asus-lvds-display.dtsi b/arch/arm/boot/dts/tegra30-asus-lvds-display.dtsi index a047abfa636921..bae09d82594d3d 100644 --- a/arch/arm/boot/dts/tegra30-asus-lvds-display.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-lvds-display.dtsi @@ -2,6 +2,8 @@ /* This dtsi file describes parts common for Asus T30 devices with a LVDS panel. */ +#include + / { host1x@50000000 { lcd: dc@54200000 { diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi index ee683c5a9c6242..c0062353c1f192 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi @@ -29,6 +29,14 @@ */ chosen {}; + firmware { + trusted-foundations { + compatible = "tlm,trusted-foundations"; + tlm,version-major = <0x0>; + tlm,version-minor = <0x0>; + }; + }; + memory@80000000 { reg = <0x80000000 0x40000000>; }; @@ -61,6 +69,12 @@ }; gpio@6000d000 { + init-low-power-mode-hog { + gpio-hog; + gpios = ; + input; + }; + init-mode-hog { gpio-hog; gpios = , @@ -68,12 +82,6 @@ ; output-low; }; - - init-low-power-mode-hog { - gpio-hog; - gpios = ; - input; - }; }; pinmux@70000868 { @@ -977,17 +985,6 @@ }; }; - brcm_wifi_pwrseq: wifi-pwrseq { - compatible = "mmc-pwrseq-simple"; - - clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; - clock-names = "ext_clock"; - - reset-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_LOW>; - post-power-on-delay-ms = <300>; - power-off-delay-us = <300>; - }; - sdmmc3: mmc@78000400 { status = "okay"; @@ -1113,27 +1110,9 @@ /delete-property/ ddc-i2c-bus; }; - firmware { - trusted-foundations { - compatible = "tlm,trusted-foundations"; - tlm,version-major = <0x0>; - tlm,version-minor = <0x0>; - }; - }; - gpio-keys { compatible = "gpio-keys"; - switch-hall-sensor { - label = "Lid"; - gpios = <&gpio TEGRA_GPIO(S, 6) GPIO_ACTIVE_LOW>; - linux,input-type = ; - linux,code = ; - debounce-interval = <500>; - wakeup-event-action = ; - wakeup-source; - }; - key-power { label = "Power"; gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; @@ -1143,6 +1122,15 @@ wakeup-source; }; + key-volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(Q, 3) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + wakeup-event-action = ; + wakeup-source; + }; + key-volume-up { label = "Volume Up"; gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_LOW>; @@ -1152,16 +1140,28 @@ wakeup-source; }; - key-volume-down { - label = "Volume Down"; - gpios = <&gpio TEGRA_GPIO(Q, 3) GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <10>; - wakeup-event-action = ; + switch-hall-sensor { + label = "Lid"; + gpios = <&gpio TEGRA_GPIO(S, 6) GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + debounce-interval = <500>; + wakeup-event-action = ; wakeup-source; }; }; + brcm_wifi_pwrseq: pwrseq-wifi { + compatible = "mmc-pwrseq-simple"; + + clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; + clock-names = "ext_clock"; + + reset-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_LOW>; + post-power-on-delay-ms = <300>; + power-off-delay-us = <300>; + }; + vdd_5v0_sys: regulator-5v0 { compatible = "regulator-fixed"; regulator-name = "vdd_5v0"; diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi index cd28e8782f7db1..694c7fe37eb880 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi @@ -22,13 +22,6 @@ pinctrl-names = "default"; pinctrl-0 = <&max77620_default>; - max77620_default: pinmux { - gpio4 { - pins = "gpio4"; - function = "32k-out1"; - }; - }; - cpu-pwr-req-hog { gpio-hog; gpios = <6 GPIO_ACTIVE_HIGH>; @@ -49,6 +42,13 @@ }; }; + max77620_default: pinmux { + gpio4 { + pins = "gpio4"; + function = "32k-out1"; + }; + }; + regulators { in-sd0-supply = <&vdd_5v0_sys>; in-sd1-supply = <&vdd_5v0_sys>; diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-memory-timings.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-memory-timings.dtsi index 6c229e1d67e718..8944a4a5a8d7df 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-memory-timings.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-memory-timings.dtsi @@ -1562,16 +1562,16 @@ }; }; }; -}; -&emc_icc_dvfs_opp_table { - /delete-node/ opp-750000000-1300; - /delete-node/ opp-800000000-1300; - /delete-node/ opp-900000000-1350; -}; + opp-table-actmon { + /delete-node/ opp-750000000; + /delete-node/ opp-800000000; + /delete-node/ opp-900000000; + }; -&emc_bw_dfs_opp_table { - /delete-node/ opp-750000000; - /delete-node/ opp-800000000; - /delete-node/ opp-900000000; + opp-table-emc { + /delete-node/ opp-750000000-1300; + /delete-node/ opp-800000000-1300; + /delete-node/ opp-900000000-1350; + }; }; diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper.dtsi index 564cfcde21a9c8..c19a0419112a59 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper.dtsi @@ -6,20 +6,6 @@ / { compatible = "asus,grouper", "nvidia,tegra30"; - display-panel { - panel-timing { - clock-frequency = <68000000>; - hactive = <800>; - vactive = <1280>; - hfront-porch = <24>; - hback-porch = <32>; - hsync-len = <24>; - vsync-len = <1>; - vfront-porch = <5>; - vback-porch = <32>; - }; - }; - pinmux@70000868 { state_default: pinmux { lcd_dc1_pd2 { @@ -145,4 +131,18 @@ firmware-gpios = <&gpio TEGRA_GPIO(R, 3) GPIO_ACTIVE_HIGH>; }; }; + + display-panel { + panel-timing { + clock-frequency = <68000000>; + hactive = <800>; + vactive = <1280>; + hfront-porch = <24>; + hback-porch = <32>; + hsync-len = <24>; + vsync-len = <1>; + vfront-porch = <5>; + vback-porch = <32>; + }; + }; }; diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia.dtsi index 1b241f0542b89f..94c80134574e95 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia.dtsi @@ -6,22 +6,6 @@ / { compatible = "asus,tilapia", "asus,grouper", "nvidia,tegra30"; - display-panel { - enable-gpios = <&gpio TEGRA_GPIO(V, 6) GPIO_ACTIVE_HIGH>; - - panel-timing { - clock-frequency = <81750000>; - hactive = <800>; - vactive = <1280>; - hfront-porch = <64>; - hback-porch = <128>; - hsync-len = <64>; - vsync-len = <1>; - vfront-porch = <5>; - vback-porch = <2>; - }; - }; - gpio@6000d000 { init-mode-3g-hog { gpio-hog; @@ -230,4 +214,20 @@ firmware-gpios = <&gpio TEGRA_GPIO(P, 3) GPIO_ACTIVE_HIGH>; }; }; + + display-panel { + enable-gpios = <&gpio TEGRA_GPIO(V, 6) GPIO_ACTIVE_HIGH>; + + panel-timing { + clock-frequency = <81750000>; + hactive = <800>; + vactive = <1280>; + hfront-porch = <64>; + hback-porch = <128>; + hsync-len = <64>; + vsync-len = <1>; + vfront-porch = <5>; + vback-porch = <2>; + }; + }; }; diff --git a/arch/arm/boot/dts/tegra30-asus-tf201.dts b/arch/arm/boot/dts/tegra30-asus-tf201.dts index 315c6dc068c5f2..3c2b9e93e02835 100644 --- a/arch/arm/boot/dts/tegra30-asus-tf201.dts +++ b/arch/arm/boot/dts/tegra30-asus-tf201.dts @@ -605,23 +605,23 @@ enable-gpios = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_HIGH>; vcc-supply = <&vdd_3v3_sys>; }; -}; -&emc_icc_dvfs_opp_table { - /delete-node/ opp-533000000-1200; - /delete-node/ opp-625000000-1200; - /delete-node/ opp-625000000-1250; - /delete-node/ opp-667000000-1200; - /delete-node/ opp-750000000-1300; - /delete-node/ opp-800000000-1300; - /delete-node/ opp-900000000-1350; -}; + opp-table-actmon { + /delete-node/ opp-533000000; + /delete-node/ opp-625000000; + /delete-node/ opp-667000000; + /delete-node/ opp-750000000; + /delete-node/ opp-800000000; + /delete-node/ opp-900000000; + }; -&emc_bw_dfs_opp_table { - /delete-node/ opp-533000000; - /delete-node/ opp-625000000; - /delete-node/ opp-667000000; - /delete-node/ opp-750000000; - /delete-node/ opp-800000000; - /delete-node/ opp-900000000; + opp-table-emc { + /delete-node/ opp-533000000-1200; + /delete-node/ opp-625000000-1200; + /delete-node/ opp-625000000-1250; + /delete-node/ opp-667000000-1200; + /delete-node/ opp-750000000-1300; + /delete-node/ opp-800000000-1300; + /delete-node/ opp-900000000-1350; + }; }; diff --git a/arch/arm/boot/dts/tegra30-asus-tf300t.dts b/arch/arm/boot/dts/tegra30-asus-tf300t.dts index f47434871a5c81..506ae3626731b8 100644 --- a/arch/arm/boot/dts/tegra30-asus-tf300t.dts +++ b/arch/arm/boot/dts/tegra30-asus-tf300t.dts @@ -999,6 +999,18 @@ compatible = "innolux,g101ice-l01"; }; + opp-table-emc { + /delete-node/ opp-750000000-1300; + /delete-node/ opp-800000000-1300; + /delete-node/ opp-900000000-1350; + }; + + opp-table-actmon { + /delete-node/ opp-750000000; + /delete-node/ opp-800000000; + /delete-node/ opp-900000000; + }; + sound { compatible = "asus,tegra-audio-wm8903-tf300t", "nvidia,tegra-audio-wm8903"; @@ -1020,15 +1032,3 @@ nvidia,headset; }; }; - -&emc_icc_dvfs_opp_table { - /delete-node/ opp-750000000-1300; - /delete-node/ opp-800000000-1300; - /delete-node/ opp-900000000-1350; -}; - -&emc_bw_dfs_opp_table { - /delete-node/ opp-750000000; - /delete-node/ opp-800000000; - /delete-node/ opp-900000000; -}; diff --git a/arch/arm/boot/dts/tegra30-asus-tf300tg.dts b/arch/arm/boot/dts/tegra30-asus-tf300tg.dts index 96345f821c3d2b..573deeafb7baae 100644 --- a/arch/arm/boot/dts/tegra30-asus-tf300tg.dts +++ b/arch/arm/boot/dts/tegra30-asus-tf300tg.dts @@ -1072,16 +1072,16 @@ display-panel { compatible = "innolux,g101ice-l01"; }; -}; -&emc_icc_dvfs_opp_table { - /delete-node/ opp-750000000-1300; - /delete-node/ opp-800000000-1300; - /delete-node/ opp-900000000-1350; -}; + opp-table-emc { + /delete-node/ opp-750000000-1300; + /delete-node/ opp-800000000-1300; + /delete-node/ opp-900000000-1350; + }; -&emc_bw_dfs_opp_table { - /delete-node/ opp-750000000; - /delete-node/ opp-800000000; - /delete-node/ opp-900000000; + opp-table-actmon { + /delete-node/ opp-750000000; + /delete-node/ opp-800000000; + /delete-node/ opp-900000000; + }; }; diff --git a/arch/arm/boot/dts/tegra30-asus-tf700t.dts b/arch/arm/boot/dts/tegra30-asus-tf700t.dts index 1a331dec3cfede..e7fe8c7a74351c 100644 --- a/arch/arm/boot/dts/tegra30-asus-tf700t.dts +++ b/arch/arm/boot/dts/tegra30-asus-tf700t.dts @@ -758,6 +758,24 @@ vddio-supply = <&vdd_1v8_vio>; vddmipi-supply = <&vdd_1v2_mipi>; + /* + * Panasonic VVX10F004B00 or HYDIS HV101WU1-1E1 + * LCD SuperIPS+ Full HD panel. + */ + panel@1 { + compatible = "panasonic,vvx10f004b00"; + reg = <1>; + + power-supply = <&vdd_pnl>; + backlight = <&backlight>; + + port { + panel_input: endpoint { + remote-endpoint = <&bridge_output>; + }; + }; + }; + ports { #address-cells = <1>; #size-cells = <0>; @@ -779,28 +797,18 @@ }; }; }; - - /* - * Panasonic VVX10F004B00 or HYDIS HV101WU1-1E1 - * LCD SuperIPS+ Full HD panel. - */ - panel@1 { - compatible = "panasonic,vvx10f004b00"; - reg = <1>; - - power-supply = <&vdd_pnl>; - backlight = <&backlight>; - - port { - panel_input: endpoint { - remote-endpoint = <&bridge_output>; - }; - }; - }; }; }; }; + opp-table-actmon { + /delete-node/ opp-900000000; + }; + + opp-table-emc { + /delete-node/ opp-900000000-1350; + }; + vdd_1v2_mipi: regulator-mipi { compatible = "regulator-fixed"; regulator-name = "tc358768_1v2_vdd"; @@ -813,11 +821,3 @@ vin-supply = <&vdd_3v3_sys>; }; }; - -&emc_icc_dvfs_opp_table { - /delete-node/ opp-900000000-1350; -}; - -&emc_bw_dfs_opp_table { - /delete-node/ opp-900000000; -}; diff --git a/arch/arm/boot/dts/tegra30-asus-transformer-common.dtsi b/arch/arm/boot/dts/tegra30-asus-transformer-common.dtsi index 08ea9cb32d0ea2..1861b2de2dc3d4 100644 --- a/arch/arm/boot/dts/tegra30-asus-transformer-common.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-transformer-common.dtsi @@ -33,6 +33,14 @@ */ chosen {}; + firmware { + trusted-foundations { + compatible = "tlm,trusted-foundations"; + tlm,version-major = <2>; + tlm,version-minor = <8>; + }; + }; + memory@80000000 { reg = <0x80000000 0x40000000>; }; @@ -1187,17 +1195,6 @@ status = "okay"; clock-frequency = <400000>; - nct72: temperature-sensor@4c { - compatible = "onnn,nct1008"; - reg = <0x4c>; - - interrupt-parent = <&gpio>; - interrupts = ; - - vcc-supply = <&vdd_3v3_sys>; - #thermal-sensor-cells = <1>; - }; - /* Texas Instruments TPS659110 PMIC */ pmic: pmic@2d { compatible = "ti,tps65911"; @@ -1323,6 +1320,17 @@ }; }; + nct72: temperature-sensor@4c { + compatible = "onnn,nct1008"; + reg = <0x4c>; + + interrupt-parent = <&gpio>; + interrupts = ; + + vcc-supply = <&vdd_3v3_sys>; + #thermal-sensor-cells = <1>; + }; + vdd_core: core-regulator@60 { compatible = "ti,tps62361"; reg = <0x60>; @@ -1531,14 +1539,6 @@ }; }; - firmware { - trusted-foundations { - compatible = "tlm,trusted-foundations"; - tlm,version-major = <2>; - tlm,version-minor = <8>; - }; - }; - gpio-keys { compatible = "gpio-keys"; @@ -1551,19 +1551,19 @@ wakeup-source; }; - key-volume-up { - label = "Volume Up"; - gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_LOW>; - linux,code = ; + key-volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(Q, 3) GPIO_ACTIVE_LOW>; + linux,code = ; debounce-interval = <10>; wakeup-event-action = ; wakeup-source; }; - key-volume-down { - label = "Volume Down"; - gpios = <&gpio TEGRA_GPIO(Q, 3) GPIO_ACTIVE_LOW>; - linux,code = ; + key-volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_LOW>; + linux,code = ; debounce-interval = <10>; wakeup-event-action = ; wakeup-source; diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts index 5ad62b567d3285..51769d5132aec4 100644 --- a/arch/arm/boot/dts/tegra30-beaver.dts +++ b/arch/arm/boot/dts/tegra30-beaver.dts @@ -1974,6 +1974,28 @@ #clock-cells = <0>; }; + cpus { + cpu0: cpu@0 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@1 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@2 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@3 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + }; + gpio-leds { compatible = "gpio-leds"; @@ -2113,26 +2135,4 @@ assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, <&tegra_car TEGRA30_CLK_EXTERN1>; }; - - cpus { - cpu0: cpu@0 { - cpu-supply = <&vddctrl_reg>; - operating-points-v2 = <&cpu0_opp_table>; - }; - - cpu@1 { - cpu-supply = <&vddctrl_reg>; - operating-points-v2 = <&cpu0_opp_table>; - }; - - cpu@2 { - cpu-supply = <&vddctrl_reg>; - operating-points-v2 = <&cpu0_opp_table>; - }; - - cpu@3 { - cpu-supply = <&vddctrl_reg>; - operating-points-v2 = <&cpu0_opp_table>; - }; - }; }; diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi index 540530c983ff56..37a9c5a0ca3034 100644 --- a/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi @@ -468,6 +468,33 @@ }; }; + gpio-keys { + compatible = "gpio-keys"; + + key-power { + label = "Power"; + interrupt-parent = <&pmic>; + interrupts = <2 0>; + linux,code = ; + debounce-interval = <100>; + wakeup-source; + }; + + key-volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + }; + + key-volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + }; + }; + panel: panel { compatible = "chunghwa,claa101wb01"; ddc-i2c-bus = <&panelddc>; @@ -681,31 +708,4 @@ }; }; }; - - gpio-keys { - compatible = "gpio-keys"; - - key-power { - label = "Power"; - interrupt-parent = <&pmic>; - interrupts = <2 0>; - linux,code = ; - debounce-interval = <100>; - wakeup-source; - }; - - key-volume-down { - label = "Volume Down"; - gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <10>; - }; - - key-volume-up { - label = "Volume Up"; - gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <10>; - }; - }; }; diff --git a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts index 8dbc15f9a9e4f2..36615c5fda2cb8 100644 --- a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts @@ -136,7 +136,7 @@ pwms = <&pwm 0 5000000>; /* PWM */ }; - clk16m: osc3 { + clk16m: clock-osc3 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <16000000>; diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi index 2867a138e011fc..ed6106f1bea115 100644 --- a/arch/arm/boot/dts/tegra30-colibri.dtsi +++ b/arch/arm/boot/dts/tegra30-colibri.dtsi @@ -20,6 +20,15 @@ }; }; + gpio: gpio@6000d000 { + lan-reset-n-hog { + gpio-hog; + gpios = ; + output-high; + line-name = "LAN_RESET#"; + }; + }; + pinmux@70000868 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; @@ -864,6 +873,11 @@ st,sample-time = <4>; /* forbid to use ADC channels 3-0 (touch) */ + stmpe_adc { + compatible = "st,stmpe-adc"; + st,norequest-mask = <0x0F>; + }; + stmpe_touchscreen { compatible = "st,stmpe-ts"; /* 8 sample average control */ @@ -880,11 +894,6 @@ /* 5 ms touch detect interrupt delay */ st,touch-det-delay = <5>; }; - - stmpe_adc { - compatible = "st,stmpe-adc"; - st,norequest-mask = <0x0F>; - }; }; /* @@ -972,7 +981,7 @@ vbus-supply = <®_lan_v_bus>; }; - clk32k_in: xtal1 { + clk32k_in: clock-xtal1 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; @@ -1053,12 +1062,3 @@ <&tegra_car TEGRA30_CLK_EXTERN1>; }; }; - -&gpio { - lan-reset-n-hog { - gpio-hog; - gpios = ; - output-high; - line-name = "LAN_RESET#"; - }; -}; diff --git a/arch/arm/boot/dts/tegra30-ouya.dts b/arch/arm/boot/dts/tegra30-ouya.dts index b7acea39b94225..eef27c82987b33 100644 --- a/arch/arm/boot/dts/tegra30-ouya.dts +++ b/arch/arm/boot/dts/tegra30-ouya.dts @@ -26,6 +26,14 @@ stdout-path = "serial0:115200n8"; }; + firmware { + trusted-foundations { + compatible = "tlm,trusted-foundations"; + tlm,version-major = <0x0>; + tlm,version-minor = <0x0>; + }; + }; + memory@80000000 { reg = <0x80000000 0x40000000>; }; @@ -2037,17 +2045,6 @@ status = "okay"; clock-frequency = <400000>; - cpu_temp: nct1008@4c { - compatible = "onnn,nct1008"; - reg = <0x4c>; - vcc-supply = <&sys_3v3_reg>; - - interrupt-parent = <&gpio>; - interrupts = ; - - #thermal-sensor-cells = <1>; - }; - pmic: pmic@2d { compatible = "ti,tps65911"; reg = <0x2d>; @@ -2161,6 +2158,17 @@ }; }; + cpu_temp: nct1008@4c { + compatible = "onnn,nct1008"; + reg = <0x4c>; + vcc-supply = <&sys_3v3_reg>; + + interrupt-parent = <&gpio>; + interrupts = ; + + #thermal-sensor-cells = <1>; + }; + vdd_core: tps62361@60 { compatible = "ti,tps62361"; reg = <0x60>; @@ -4485,17 +4493,6 @@ status = "okay"; }; - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - - clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; - clock-names = "ext_clock"; - - reset-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_LOW>; - post-power-on-delay-ms = <300>; - power-off-delay-us = <300>; - }; - sdmmc3: mmc@78000400 { status = "okay"; @@ -4608,15 +4605,7 @@ }; }; - firmware { - trusted-foundations { - compatible = "tlm,trusted-foundations"; - tlm,version-major = <0x0>; - tlm,version-minor = <0x0>; - }; - }; - - fan: gpio_fan { + fan: fan { compatible = "gpio-fan"; gpios = <&gpio TEGRA_GPIO(J, 2) GPIO_ACTIVE_HIGH>; gpio-fan,speed-map = <0 0 @@ -4624,50 +4613,50 @@ #cooling-cells = <2>; }; - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay = <5000>; - polling-delay-passive = <5000>; + gpio-keys { + compatible = "gpio-keys"; - thermal-sensors = <&cpu_temp 1>; + key-power { + gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; + debounce-interval = <10>; + linux,code = ; + wakeup-event-action = ; + wakeup-source; + }; + }; - trips { - cpu_alert0: cpu-alert0 { - temperature = <50000>; - hysteresis = <10000>; - type = "active"; - }; - cpu_alert1: cpu-alert1 { - temperature = <70000>; - hysteresis = <5000>; - type = "passive"; - }; - cpu_crit: cpu-crit { - temperature = <90000>; - hysteresis = <2000>; - type = "critical"; - }; - }; + leds { + compatible = "gpio-leds"; - cooling-maps { - map0 { - trip = <&cpu_alert0>; - cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu_alert1>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&actmon THERMAL_NO_LIMIT - THERMAL_NO_LIMIT>; - }; - }; + led-power { + label = "power-led"; + gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + retain-state-suspended; }; }; - vdd_12v_in: vdd_12v_in { + opp-table-actmon { + /delete-node/ opp-900000000; + }; + + opp-table-emc { + /delete-node/ opp-900000000-1350; + }; + + wifi_pwrseq: pwrseq-wifi { + compatible = "mmc-pwrseq-simple"; + + clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; + clock-names = "ext_clock"; + + reset-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_LOW>; + post-power-on-delay-ms = <300>; + power-off-delay-us = <300>; + }; + + vdd_12v_in: regulator-vdd-12v-in { compatible = "regulator-fixed"; regulator-name = "vdd_12v_in"; regulator-min-microvolt = <12000000>; @@ -4675,7 +4664,7 @@ regulator-always-on; }; - sdmmc_3v3_reg: sdmmc_3v3_reg { + sdmmc_3v3_reg: regulator-sdmmc-3v3 { compatible = "regulator-fixed"; regulator-name = "sdmmc_3v3"; regulator-min-microvolt = <3300000>; @@ -4686,7 +4675,7 @@ vin-supply = <&sys_3v3_reg>; }; - vdd_fuse_3v3_reg: vdd_fuse_3v3_reg { + vdd_fuse_3v3_reg: regulator-vdd-fuse-3v3 { compatible = "regulator-fixed"; regulator-name = "vdd_fuse_3v3"; regulator-min-microvolt = <3300000>; @@ -4697,7 +4686,7 @@ regulator-always-on; }; - vdd_vid_reg: vdd_vid_reg { + vdd_vid_reg: regulator-vdd-vid { compatible = "regulator-fixed"; regulator-name = "vddio_vid"; regulator-min-microvolt = <5000000>; @@ -4708,7 +4697,7 @@ regulator-boot-on; }; - ddr_reg: ddr_reg { + ddr_reg: regulator-ddr { compatible = "regulator-fixed"; regulator-name = "vdd_ddr"; regulator-min-microvolt = <1500000>; @@ -4720,7 +4709,7 @@ vin-supply = <&vdd_12v_in>; }; - sys_3v3_reg: sys_3v3_reg { + sys_3v3_reg: regulator-sys-3v3 { compatible = "regulator-fixed"; regulator-name = "sys_3v3"; regulator-min-microvolt = <3300000>; @@ -4732,7 +4721,7 @@ vin-supply = <&vdd_12v_in>; }; - vdd_5v0_reg: vdd_5v0_reg { + vdd_5v0_reg: regulator-vdd-5v0 { compatible = "regulator-fixed"; regulator-name = "vdd_5v0"; regulator-min-microvolt = <5000000>; @@ -4744,14 +4733,14 @@ vin-supply = <&vdd_12v_in>; }; - vdd_smsc: vdd_smsc { + vdd_smsc: regulator-vdd-smsc { compatible = "regulator-fixed"; regulator-name = "vdd_smsc"; enable-active-high; gpio = <&gpio TEGRA_GPIO(DD, 5) GPIO_ACTIVE_HIGH>; }; - usb3_vbus_reg: usb3_vbus_reg { + usb3_vbus_reg: regulator-usb3-vbus { compatible = "regulator-fixed"; regulator-name = "usb3_vbus"; regulator-min-microvolt = <5000000>; @@ -4761,36 +4750,46 @@ vin-supply = <&vdd_5v0_reg>; }; - gpio-keys { - compatible = "gpio-keys"; - - key-power { - gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; - debounce-interval = <10>; - linux,code = ; - wakeup-event-action = ; - wakeup-source; - }; - }; + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay = <5000>; + polling-delay-passive = <5000>; + thermal-sensors = <&cpu_temp 1>; - leds { - compatible = "gpio-leds"; + trips { + cpu_alert0: cpu-alert0 { + temperature = <50000>; + hysteresis = <10000>; + type = "active"; + }; + cpu_alert1: cpu-alert1 { + temperature = <70000>; + hysteresis = <5000>; + type = "passive"; + }; + cpu_crit: cpu-crit { + temperature = <90000>; + hysteresis = <2000>; + type = "critical"; + }; + }; - led-power { - label = "power-led"; - gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - retain-state-suspended; + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu_alert1>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&actmon THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; }; }; }; - -&emc_icc_dvfs_opp_table { - /delete-node/ opp-900000000-1350; -}; - -&emc_bw_dfs_opp_table { - /delete-node/ opp-900000000; -}; diff --git a/arch/arm/boot/dts/tegra30-pegatron-chagall.dts b/arch/arm/boot/dts/tegra30-pegatron-chagall.dts index d9408a90653a2a..8d10eb8b48b952 100644 --- a/arch/arm/boot/dts/tegra30-pegatron-chagall.dts +++ b/arch/arm/boot/dts/tegra30-pegatron-chagall.dts @@ -37,6 +37,14 @@ */ chosen {}; + firmware { + trusted-foundations { + compatible = "tlm,trusted-foundations"; + tlm,version-major = <2>; + tlm,version-minor = <8>; + }; + }; + memory@80000000 { reg = <0x80000000 0x40000000>; }; @@ -1190,16 +1198,6 @@ status = "okay"; clock-frequency = <400000>; - light-sensor@44 { - compatible = "isil,isl29023"; - reg = <0x44>; - - interrupt-parent = <&gpio>; - interrupts = ; - - vcc-supply = <&vdd_3v3_sen>; - }; - /* AsahiKASEI AK8975 magnetometer sensor */ magnetometer@c { compatible = "asahi-kasei,ak8975"; @@ -1213,6 +1211,16 @@ "0", "0", "-1"; }; + light-sensor@44 { + compatible = "isil,isl29023"; + reg = <0x44>; + + interrupt-parent = <&gpio>; + interrupts = ; + + vcc-supply = <&vdd_3v3_sen>; + }; + gyroscope@68 { compatible = "invensense,mpu3050"; reg = <0x68>; @@ -1259,17 +1267,6 @@ status = "okay"; clock-frequency = <400000>; - nct72: temperature-sensor@4c { - compatible = "onnn,nct1008"; - reg = <0x4c>; - - interrupt-parent = <&gpio>; - interrupts = ; - - vcc-supply = <&vdd_3v3_sys>; - #thermal-sensor-cells = <1>; - }; - /* Texas Instruments TPS659110 PMIC */ pmic: pmic@2d { compatible = "ti,tps65911"; @@ -1400,6 +1397,17 @@ }; }; + nct72: temperature-sensor@4c { + compatible = "onnn,nct1008"; + reg = <0x4c>; + + interrupt-parent = <&gpio>; + interrupts = ; + + vcc-supply = <&vdd_3v3_sys>; + #thermal-sensor-cells = <1>; + }; + vdd_core: core-regulator@60 { compatible = "ti,tps62361"; reg = <0x60>; @@ -2506,17 +2514,6 @@ vqmmc-supply = <&vddio_usd>; /* ldo3 */ }; - brcm_wifi_pwrseq: wifi-pwrseq { - compatible = "mmc-pwrseq-simple"; - - clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; - clock-names = "ext_clock"; - - reset-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_LOW>; - post-power-on-delay-ms = <300>; - power-off-delay-us = <300>; - }; - sdmmc3: mmc@78000400 { status = "okay"; @@ -2674,14 +2671,6 @@ }; }; - firmware { - trusted-foundations { - compatible = "tlm,trusted-foundations"; - tlm,version-major = <2>; - tlm,version-minor = <8>; - }; - }; - gpio-keys { compatible = "gpio-keys"; @@ -2694,19 +2683,19 @@ wakeup-source; }; - key-volume-up { - label = "Volume Up"; - gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; - linux,code = ; + key-volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(Q, 1) GPIO_ACTIVE_LOW>; + linux,code = ; debounce-interval = <10>; wakeup-event-action = ; wakeup-source; }; - key-volume-down { - label = "Volume Down"; - gpios = <&gpio TEGRA_GPIO(Q, 1) GPIO_ACTIVE_LOW>; - linux,code = ; + key-volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; + linux,code = ; debounce-interval = <10>; wakeup-event-action = ; wakeup-source; @@ -2719,6 +2708,34 @@ vcc-supply = <&vdd_3v3_sys>; }; + opp-table-actmon { + /delete-node/ opp-625000000; + /delete-node/ opp-667000000; + /delete-node/ opp-750000000; + /delete-node/ opp-800000000; + /delete-node/ opp-900000000; + }; + + opp-table-emc { + /delete-node/ opp-625000000-1200; + /delete-node/ opp-625000000-1250; + /delete-node/ opp-667000000-1200; + /delete-node/ opp-750000000-1300; + /delete-node/ opp-800000000-1300; + /delete-node/ opp-900000000-1350; + }; + + brcm_wifi_pwrseq: pwrseq-wifi { + compatible = "mmc-pwrseq-simple"; + + clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; + clock-names = "ext_clock"; + + reset-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_LOW>; + post-power-on-delay-ms = <300>; + power-off-delay-us = <300>; + }; + sound { compatible = "pegatron,tegra-audio-wm8903-chagall", "nvidia,tegra-audio-wm8903"; @@ -2839,20 +2856,3 @@ }; }; }; - -&emc_icc_dvfs_opp_table { - /delete-node/ opp-625000000-1200; - /delete-node/ opp-625000000-1250; - /delete-node/ opp-667000000-1200; - /delete-node/ opp-750000000-1300; - /delete-node/ opp-800000000-1300; - /delete-node/ opp-900000000-1350; -}; - -&emc_bw_dfs_opp_table { - /delete-node/ opp-625000000; - /delete-node/ opp-667000000; - /delete-node/ opp-750000000; - /delete-node/ opp-800000000; - /delete-node/ opp-900000000; -}; diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 9dab8d2c158a7b..b6fcac6016e01d 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -397,13 +397,6 @@ #clock-cells = <1>; #reset-cells = <1>; - sclk { - compatible = "nvidia,tegra30-sclk"; - clocks = <&tegra_car TEGRA30_CLK_SCLK>; - power-domains = <&pd_core>; - operating-points-v2 = <&sclk_dvfs_opp_table>; - }; - pll-c { compatible = "nvidia,tegra30-pllc"; clocks = <&tegra_car TEGRA30_CLK_PLL_C>; @@ -424,6 +417,13 @@ power-domains = <&pd_core>; operating-points-v2 = <&pll_m_dvfs_opp_table>; }; + + sclk { + compatible = "nvidia,tegra30-sclk"; + clocks = <&tegra_car TEGRA30_CLK_SCLK>; + power-domains = <&pd_core>; + operating-points-v2 = <&sclk_dvfs_opp_table>; + }; }; flow-controller@60007000 { @@ -648,13 +648,6 @@ status = "disabled"; }; - rtc@7000e000 { - compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc"; - reg = <0x7000e000 0x100>; - interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_RTC>; - }; - i2c@7000c000 { compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; reg = <0x7000c000 0x100>; @@ -831,6 +824,13 @@ status = "disabled"; }; + rtc@7000e000 { + compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc"; + reg = <0x7000e000 0x100>; + interrupts = ; + clocks = <&tegra_car TEGRA30_CLK_RTC>; + }; + kbc@7000e200 { compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc"; reg = <0x7000e200 0x100>; @@ -854,6 +854,28 @@ }; powergates { + pd_heg: heg { + clocks = <&tegra_car TEGRA30_CLK_GR2D>, + <&tegra_car TEGRA30_CLK_EPP>, + <&tegra_car TEGRA30_CLK_HOST1X>; + resets = <&mc TEGRA30_MC_RESET_2D>, + <&mc TEGRA30_MC_RESET_EPP>, + <&mc TEGRA30_MC_RESET_HC>, + <&tegra_car TEGRA30_CLK_GR2D>, + <&tegra_car TEGRA30_CLK_EPP>, + <&tegra_car TEGRA30_CLK_HOST1X>; + power-domains = <&pd_core>; + #power-domain-cells = <0>; + }; + + pd_mpe: mpe { + clocks = <&tegra_car TEGRA30_CLK_MPE>; + resets = <&mc TEGRA30_MC_RESET_MPE>, + <&tegra_car TEGRA30_CLK_MPE>; + power-domains = <&pd_core>; + #power-domain-cells = <0>; + }; + pd_3d0: td { clocks = <&tegra_car TEGRA30_CLK_GR3D>; resets = <&mc TEGRA30_MC_RESET_3D>, @@ -870,6 +892,14 @@ #power-domain-cells = <0>; }; + pd_vde: vdec { + clocks = <&tegra_car TEGRA30_CLK_VDE>; + resets = <&mc TEGRA30_MC_RESET_VDE>, + <&tegra_car TEGRA30_CLK_VDE>; + power-domains = <&pd_core>; + #power-domain-cells = <0>; + }; + pd_venc: venc { clocks = <&tegra_car TEGRA30_CLK_ISP>, <&tegra_car TEGRA30_CLK_VI>, @@ -882,36 +912,6 @@ power-domains = <&pd_core>; #power-domain-cells = <0>; }; - - pd_vde: vdec { - clocks = <&tegra_car TEGRA30_CLK_VDE>; - resets = <&mc TEGRA30_MC_RESET_VDE>, - <&tegra_car TEGRA30_CLK_VDE>; - power-domains = <&pd_core>; - #power-domain-cells = <0>; - }; - - pd_mpe: mpe { - clocks = <&tegra_car TEGRA30_CLK_MPE>; - resets = <&mc TEGRA30_MC_RESET_MPE>, - <&tegra_car TEGRA30_CLK_MPE>; - power-domains = <&pd_core>; - #power-domain-cells = <0>; - }; - - pd_heg: heg { - clocks = <&tegra_car TEGRA30_CLK_GR2D>, - <&tegra_car TEGRA30_CLK_EPP>, - <&tegra_car TEGRA30_CLK_HOST1X>; - resets = <&mc TEGRA30_MC_RESET_2D>, - <&mc TEGRA30_MC_RESET_EPP>, - <&mc TEGRA30_MC_RESET_HC>, - <&tegra_car TEGRA30_CLK_GR2D>, - <&tegra_car TEGRA30_CLK_EPP>, - <&tegra_car TEGRA30_CLK_HOST1X>; - power-domains = <&pd_core>; - #power-domain-cells = <0>; - }; }; };