Hardware Architecture Lab

Lab Exercises for the Course CS6862 - Applied Hardware Architecture Lab (Spring Semester).

🎯 Exercises

Lab Session	Exercises	Notes
Lab 1	Verilog AND Gate Half Adder Full Adder	Notes
Lab 2	4-bit Adder	Notes
Lab 3	D-Flip Flop Gated Clock Flip Flop Synchronous and Asynchronous Reset	Notes
Lab 4	2-Bit Multiplicator and Divider	Notes
Lab 5	Traffic Light FSM	Notes
Lab 6	VHDL AND Gate 3-Input XOR Gate	Notes
Lab 7	Up Counter Down Counter	Notes
Lab 8	Up-Down Counter 2x2 Matrix Mulitplicator	Notes
Final Test	RFID Scanner using Verilog

📦 Setting up Environment

• Download the Icarus Verilog Compiler from this Icarus-Verilog. The installer is packaged with GTKWave.

  • Verify installation with iverilog -v and gtkwave --version.
  • Install Verilog-HDL for VS Code for Syntax Highlighting and Autocomplete.

• Download GHDL - VHDL Simulator from this GHDL.

  • Verify installation with ghdl help.
  • Install Awesome VHDL for Intellisense.

• VCDrom for viewing simulation dumpfiles (.vcd).

  • Link to the Repo: Wavedrom/vcdrom

🫥 How to Compile?

Compile Verilog Source Code using the commands:

iverilog -o out.vvp module_tb.v
vvp out.vvp

Compile VHDL Source Code using the commands:

for %f in (*.vhdl) do ghdl -a "%f"
ghdl -e module_tb
ghdl -r module_tb --vcd=test.vcd
gtkwave test.vcd

🚀 References

• Verilog Coding for Logic Synthesis
• The Verilog® Golden Reference Guide
• VHDL® Golden Reference Guide
• Verilog - Cheatsheet