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cascade_lake.json
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cascade_lake.json
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{"top":"global.cascade_lake",
"namespaces":{
"global":{
"modules":{
"buf1_ub":{
"type":["Record",[
["clk",["Named","coreir.clkIn"]],
["reset","BitIn"],
["conv_read",["Array",9,["Array",16,"Bit"]]],
["input_write",["Array",1,["Array",16,"BitIn"]]]
]],
"instances":{
"d_reg__U16":{
"genref":"mantle.reg",
"genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]},
"modargs":{"init":[["BitVector",16],"16'h0000"]}
},
"d_reg__U17":{
"genref":"mantle.reg",
"genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]},
"modargs":{"init":[["BitVector",16],"16'h0000"]}
},
"d_reg__U18":{
"genref":"mantle.reg",
"genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]},
"modargs":{"init":[["BitVector",16],"16'h0000"]}
},
"d_reg__U19":{
"genref":"mantle.reg",
"genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]},
"modargs":{"init":[["BitVector",16],"16'h0000"]}
},
"d_reg__U20":{
"genref":"mantle.reg",
"genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]},
"modargs":{"init":[["BitVector",16],"16'h0000"]}
},
"d_reg__U21":{
"genref":"mantle.reg",
"genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]},
"modargs":{"init":[["BitVector",16],"16'h0000"]}
},
"ub_buf1_input_10_to_buf1_conv_15":{
"genref":"cwlib.Mem",
"genargs":{"config":["Json",null], "has_flush":["Bool",true], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "num_input":["Int",1], "num_output":["Int",2], "width":["Int",16]},
"modargs":{"mode":["String","lake"]}
},
"ub_buf1_input_10_to_buf1_conv_15_clk_en_const":{
"modref":"corebit.const",
"modargs":{"value":["Bool",true]}
}
},
"connections":[
["self.clk","d_reg__U16.clk"],
["self.input_write.0","d_reg__U16.in"],
["d_reg__U17.in","d_reg__U16.out"],
["self.conv_read.7","d_reg__U16.out"],
["self.clk","d_reg__U17.clk"],
["self.conv_read.6","d_reg__U17.out"],
["self.clk","d_reg__U18.clk"],
["ub_buf1_input_10_to_buf1_conv_15.data_out_1","d_reg__U18.in"],
["d_reg__U19.in","d_reg__U18.out"],
["self.conv_read.4","d_reg__U18.out"],
["self.clk","d_reg__U19.clk"],
["self.conv_read.3","d_reg__U19.out"],
["self.clk","d_reg__U20.clk"],
["ub_buf1_input_10_to_buf1_conv_15.data_out_0","d_reg__U20.in"],
["d_reg__U21.in","d_reg__U20.out"],
["self.conv_read.1","d_reg__U20.out"],
["self.clk","d_reg__U21.clk"],
["self.conv_read.0","d_reg__U21.out"],
["ub_buf1_input_10_to_buf1_conv_15.clk","self.clk"],
["ub_buf1_input_10_to_buf1_conv_15.data_out_0","self.conv_read.2"],
["ub_buf1_input_10_to_buf1_conv_15.data_out_1","self.conv_read.5"],
["self.input_write.0","self.conv_read.8"],
["ub_buf1_input_10_to_buf1_conv_15.data_in_0","self.input_write.0"],
["ub_buf1_input_10_to_buf1_conv_15.flush","self.reset"],
["ub_buf1_input_10_to_buf1_conv_15_clk_en_const.out","ub_buf1_input_10_to_buf1_conv_15.clk_en"]
]
},
"buf2_ub":{
"type":["Record",[
["clk",["Named","coreir.clkIn"]],
["reset","BitIn"],
["conv_write",["Array",1,["Array",16,"BitIn"]]],
["output_read",["Array",9,["Array",16,"Bit"]]]
]],
"instances":{
"d_reg__U22":{
"genref":"mantle.reg",
"genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]},
"modargs":{"init":[["BitVector",16],"16'h0000"]}
},
"d_reg__U23":{
"genref":"mantle.reg",
"genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]},
"modargs":{"init":[["BitVector",16],"16'h0000"]}
},
"d_reg__U24":{
"genref":"mantle.reg",
"genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]},
"modargs":{"init":[["BitVector",16],"16'h0000"]}
},
"d_reg__U25":{
"genref":"mantle.reg",
"genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]},
"modargs":{"init":[["BitVector",16],"16'h0000"]}
},
"d_reg__U26":{
"genref":"mantle.reg",
"genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]},
"modargs":{"init":[["BitVector",16],"16'h0000"]}
},
"d_reg__U27":{
"genref":"mantle.reg",
"genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]},
"modargs":{"init":[["BitVector",16],"16'h0000"]}
},
"ub_buf2_conv_12_to_buf2_output_3":{
"genref":"cwlib.Mem",
"genargs":{"config":["Json",null], "has_flush":["Bool",true], "has_reset":["Bool",false], "has_stencil_valid":["Bool",false], "has_valid":["Bool",false], "num_input":["Int",1], "num_output":["Int",2], "width":["Int",16]},
"modargs":{"mode":["String","lake"]}
},
"ub_buf2_conv_12_to_buf2_output_3_clk_en_const":{
"modref":"corebit.const",
"modargs":{"value":["Bool",true]}
}
},
"connections":[
["self.clk","d_reg__U22.clk"],
["self.conv_write.0","d_reg__U22.in"],
["d_reg__U23.in","d_reg__U22.out"],
["self.output_read.7","d_reg__U22.out"],
["self.clk","d_reg__U23.clk"],
["self.output_read.6","d_reg__U23.out"],
["self.clk","d_reg__U24.clk"],
["ub_buf2_conv_12_to_buf2_output_3.data_out_1","d_reg__U24.in"],
["d_reg__U25.in","d_reg__U24.out"],
["self.output_read.4","d_reg__U24.out"],
["self.clk","d_reg__U25.clk"],
["self.output_read.3","d_reg__U25.out"],
["self.clk","d_reg__U26.clk"],
["ub_buf2_conv_12_to_buf2_output_3.data_out_0","d_reg__U26.in"],
["d_reg__U27.in","d_reg__U26.out"],
["self.output_read.1","d_reg__U26.out"],
["self.clk","d_reg__U27.clk"],
["self.output_read.0","d_reg__U27.out"],
["ub_buf2_conv_12_to_buf2_output_3.clk","self.clk"],
["self.output_read.8","self.conv_write.0"],
["ub_buf2_conv_12_to_buf2_output_3.data_in_0","self.conv_write.0"],
["ub_buf2_conv_12_to_buf2_output_3.data_out_0","self.output_read.2"],
["ub_buf2_conv_12_to_buf2_output_3.data_out_1","self.output_read.5"],
["ub_buf2_conv_12_to_buf2_output_3.flush","self.reset"],
["ub_buf2_conv_12_to_buf2_output_3_clk_en_const.out","ub_buf2_conv_12_to_buf2_output_3.clk_en"]
]
},
"cascade_lake":{
"type":["Record",[
["clk",["Named","coreir.clkIn"]],
["reset","BitIn"],
["in_input_read_en","Bit"],
["in_input_read",["Array",1,["Array",16,"BitIn"]]],
["out_output_write_valid","Bit"],
["out_output_write",["Array",1,["Array",16,"Bit"]]]
]],
"instances":{
"_U28":{
"genref":"mantle.reg",
"genargs":{"has_clr":["Bool",false], "has_en":["Bool",false], "has_rst":["Bool",false], "width":["Int",16]},
"modargs":{"init":[["BitVector",16],"16'h0000"]}
},
"buf1":{
"modref":"global.buf1_ub"
},
"buf2":{
"modref":"global.buf2_ub"
},
"conv":{
"modref":"global.cu_conv"
},
"input":{
"modref":"global.cu_input"
},
"output":{
"modref":"global.cu_output"
}
},
"connections":[
["self.clk","_U28.clk"],
["self.in_input_read.0","_U28.in"],
["self.clk","buf1.clk"],
["conv.buf1_conv_read","buf1.conv_read"],
["input.buf1_input_write","buf1.input_write"],
["self.reset","buf1.reset"],
["self.clk","buf2.clk"],
["conv.buf2_conv_write","buf2.conv_write"],
["output.buf2_output_read","buf2.output_read"],
["self.reset","buf2.reset"],
["self.clk","conv.clk"],
["self.clk","input.clk"],
["self.in_input_read.0","input.in_input_read.0"],
["self.clk","output.clk"],
["self.out_output_write","output.out_output_write"]
]
},
"cu_conv":{
"type":["Record",[
["clk",["Named","coreir.clkIn"]],
["buf1_conv_read",["Array",9,["Array",16,"BitIn"]]],
["buf2_conv_write",["Array",1,["Array",16,"Bit"]]]
]],
"instances":{
"add_all__U10":{
"genref":"coreir.add",
"genargs":{"width":["Int",16]}
},
"add_all__U11":{
"genref":"coreir.add",
"genargs":{"width":["Int",16]}
},
"add_all__U12":{
"genref":"coreir.add",
"genargs":{"width":["Int",16]}
},
"add_all__U13":{
"genref":"coreir.add",
"genargs":{"width":["Int",16]}
},
"add_all__U14":{
"genref":"coreir.add",
"genargs":{"width":["Int",16]}
},
"add_all__U15":{
"genref":"coreir.add",
"genargs":{"width":["Int",16]}
},
"add_all__U8":{
"genref":"coreir.add",
"genargs":{"width":["Int",16]}
},
"add_all__U9":{
"genref":"coreir.add",
"genargs":{"width":["Int",16]}
}
},
"connections":[
["add_all__U9.out","add_all__U10.in0"],
["self.buf1_conv_read.3","add_all__U10.in1"],
["add_all__U11.in0","add_all__U10.out"],
["self.buf1_conv_read.4","add_all__U11.in1"],
["add_all__U12.in0","add_all__U11.out"],
["self.buf1_conv_read.5","add_all__U12.in1"],
["add_all__U13.in0","add_all__U12.out"],
["self.buf1_conv_read.6","add_all__U13.in1"],
["add_all__U14.in0","add_all__U13.out"],
["self.buf1_conv_read.7","add_all__U14.in1"],
["add_all__U15.in0","add_all__U14.out"],
["self.buf1_conv_read.8","add_all__U15.in1"],
["self.buf2_conv_write.0","add_all__U15.out"],
["self.buf1_conv_read.0","add_all__U8.in0"],
["self.buf1_conv_read.1","add_all__U8.in1"],
["add_all__U9.in0","add_all__U8.out"],
["self.buf1_conv_read.2","add_all__U9.in1"]
]
},
"cu_input":{
"type":["Record",[
["clk",["Named","coreir.clkIn"]],
["in_input_read",["Array",1,["Array",16,"BitIn"]]],
["buf1_input_write",["Array",1,["Array",16,"Bit"]]]
]],
"connections":[
["self.in_input_read.0","self.buf1_input_write.0"]
]
},
"cu_output":{
"type":["Record",[
["clk",["Named","coreir.clkIn"]],
["buf2_output_read",["Array",9,["Array",16,"BitIn"]]],
["out_output_write",["Array",1,["Array",16,"Bit"]]]
]],
"instances":{
"add_all__U0":{
"genref":"coreir.add",
"genargs":{"width":["Int",16]}
},
"add_all__U1":{
"genref":"coreir.add",
"genargs":{"width":["Int",16]}
},
"add_all__U2":{
"genref":"coreir.add",
"genargs":{"width":["Int",16]}
},
"add_all__U3":{
"genref":"coreir.add",
"genargs":{"width":["Int",16]}
},
"add_all__U4":{
"genref":"coreir.add",
"genargs":{"width":["Int",16]}
},
"add_all__U5":{
"genref":"coreir.add",
"genargs":{"width":["Int",16]}
},
"add_all__U6":{
"genref":"coreir.add",
"genargs":{"width":["Int",16]}
},
"add_all__U7":{
"genref":"coreir.add",
"genargs":{"width":["Int",16]}
}
},
"connections":[
["self.buf2_output_read.0","add_all__U0.in0"],
["self.buf2_output_read.1","add_all__U0.in1"],
["add_all__U1.in0","add_all__U0.out"],
["self.buf2_output_read.2","add_all__U1.in1"],
["add_all__U2.in0","add_all__U1.out"],
["self.buf2_output_read.3","add_all__U2.in1"],
["add_all__U3.in0","add_all__U2.out"],
["self.buf2_output_read.4","add_all__U3.in1"],
["add_all__U4.in0","add_all__U3.out"],
["self.buf2_output_read.5","add_all__U4.in1"],
["add_all__U5.in0","add_all__U4.out"],
["self.buf2_output_read.6","add_all__U5.in1"],
["add_all__U6.in0","add_all__U5.out"],
["self.buf2_output_read.7","add_all__U6.in1"],
["add_all__U7.in0","add_all__U6.out"],
["self.buf2_output_read.8","add_all__U7.in1"],
["self.out_output_write.0","add_all__U7.out"]
]
}
},
"generators":{
"delay_tile":{
"typegen":"global.delay_tile_TG",
"genparams":{"delay":"Int"}
},
"raw_dual_port_sram_tile":{
"typegen":"global.raw_dual_port_sram_TG",
"genparams":{"depth":"Int"}
},
"raw_quad_port_memtile":{
"typegen":"global.raw_quad_port_memtile_TG",
"genparams":{"depth":"Int"}
},
"tahoe":{
"typegen":"global.tahoe_TG",
"genparams":{"depth":"Int"}
}
},
"typegens":{
"delay_tile_TG":[{"delay":"Int"},"implicit"],
"raw_dual_port_sram_TG":[{"depth":"Int"},"implicit"],
"raw_quad_port_memtile_TG":[{"depth":"Int"},"implicit"],
"tahoe_TG":[{"depth":"Int"},"implicit"]
}
}
}
}