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Building Unified Buffer Library in Vivado HLS #26

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6 of 8 tasks

joyliu37 opened this issue Jul 24, 2019 · 0 comments

Open

6 of 8 tasks

Building Unified Buffer Library in Vivado HLS #26

joyliu37 opened this issue Jul 24, 2019 · 0 comments

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joyliu37 commented Jul 24, 2019 •

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Improve Unified Buffer Library into template support up to 3D in Jing's line buffer style
Add testcase multiple channel convolution using circular line buffer as a real unified buffer
Line Buffer Lib support address stream
Address Generator
Bank selector support different I/O port
Psum Buffer with update state
VGGnet Pass
Mobilenet Pass

joyliu37 added this to the Compilation of Applications to FPGA milestone

joyliu37 modified the milestones: Compilation of Applications to FPGA, MICRO Poster

joyliu37 self-assigned this

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