Hardware Pin Mappings

[coburnw]

Anyone know where the pin manager of Microchip's Code Configurator gets its mapping of Package > PinNo > Function from? The snapshot is from page 19 of AN3417. Im looking for a parsable version, rather a human readable version such as found in the products datasheet.

DxCore's variant header files come close, but dont seem to map the hardware pin to the port number nor have power pins defined.

[SpenceKonde]

It gets it from the .atdf file in the .ATpack which supports that part. Search google for microchip atpack download, and grab the latest Dx-series package. Rename .ATpack file to a .zip file and extract it through your preferred method of .zip file extraction
Inside the archive will be a directory named 'atdf', which will contain a .atdf file named for each part.

It should be opened as text and parsed as xml.

Note that there is some tension between the atdf and the datasheet or silicon at times. Generally, the datasheet is less likely to be in error than the ATDF, though the silicon is often wrong too.

The core variants file is only concerned with things that are visible to the code and/or change how something is compiled; the mapping of physical pin numbers to logical (Pxn) numbering does not change that, because it is invisible to the code. Within the domain of the software, the most fundamental description of a pin is port X bit N. That translates to which registers to write to manipulate it. The compiler and code will work the same if your part with 17 logical I/O lines (ie, a DD20) looks like a real DD20, or is made on QFP-44 package so that they could connect every odd numbered pin to ground or something - the code doesn't care which package it came in. The designer of course cares, but that is beyond the scope of a core to care about, Since power and ground pins can't be interacted with, the variant has nothing to do with them.

(it's supporting documentation for the core - though because I'm not able to create pin mapping image I'm essentially at the mercy of others, and others have shown little interest in making pin diagrams since the 1.3.0 feature addition to allow the portmux to be changed at runtime for TCA and later TCD on the DD's, and at compile-time on mTC, probably in part because this means that the diagrams need to present more information (default pins for the timer as set by the core, and potential pins for the timer, ideally with a way to show that they act in groups)). I have a standing offer to anyone who can make such a generator that am happy to create the files that define the mappings if they tell me what format they want it in (I can do python tables, delimited text files (such as CSV) or json without that much pain - and can include most anything you request in the data - unless you want it in yaml, I can't do yaml. But I'm happy to do that part in exchange for a pinout generator that doesn't require me using a graphics editor.

[SpenceKonde]

Oh and also for example in the case of parts that exist in both pins-on-two-sides and pins-on-four-sides, those are identical from the perspective of the core and compiler. But the physical pin numbers aren't the same!