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SoCLabor.bib
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SoCLabor.bib
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@misc{noauthor_embedded_nodate,
title = {Embedded {IC} {Engine} {Control} {Unit} ({ECU}) {FPGA} {microBlaze} softcore {In} {Field} {Update}},
url = {https://www.elmgdigitalpower.com/products/embedded-applications/},
abstract = {FPGA microBlaze softcore In Field Update Control of the internal combustion engine in a motor vehicle presents a challenging embedded application. A great solution is an FPGA, microBlaze softcore, In Field Update system. The ELMG Digital Power embedded system for the vehicle engine control unit (ECU) meets this challenge by using a Xilinx FPGA to provides …},
language = {en-US},
urldate = {2018-10-09},
journal = {ELMG Digital Power- Power Electronics Digital Control},
file = {Snapshot:/home/consti/Zotero/storage/GBD3KYCR/embedded-applications.html:text/html}
}
@misc{noauthor_fpga_nodate,
title = {{FPGA} {Soft} {Core} – {Mikrocontroller}.net},
url = {https://www.mikrocontroller.net/articles/FPGA_Soft_Core},
urldate = {2018-10-09},
file = {FPGA Soft Core – Mikrocontroller.net:/home/consti/Zotero/storage/QP6NS2P2/FPGA_Soft_Core.html:text/html}
}
@article{shanker_enhancing_nodate,
title = {Enhancing {Automotive} {Embedded} {Systems} with {FPGAs}},
language = {en},
author = {Shanker, Shreejith},
pages = {249},
file = {Shanker - Enhancing Automotive Embedded Systems with FPGAs.pdf:/home/consti/Zotero/storage/DUZDR6FT/Shanker - Enhancing Automotive Embedded Systems with FPGAs.pdf:application/pdf}
}
@article{brungs_einsatz_nodate,
title = {Einsatz von dynamisch rekonfigurierbaren {FPGAs} in {Fahrzeugen}},
abstract = {Die Anforderungen zuku¨nftiger Fahrerassistenzsysteme (ADAS) an Konnektivita¨t, Flexibilita¨t und Verarbeitungsleistung werden immer ho¨her, sodass aktuelle Prozessoren (MCU/DSP) durch immer aufwendigere Algorithmen an ihre Grenzen stoûen. Die vorgestellte Arbeit zeigt ein Konzept, das durch eine ¯exible FPGA-Architektur eine rekon®gurierbare Hardwarebeschleunigung erlaubt. Statt komplexe Algorithmen weiterhin als Software fu¨r MCUs oder DSPs zu implementieren, werden partiell rekon®gurierbare Hardwarekomponenten in FPGAs realisiert. In verteilten Systemen dieser Art werden Daten u¨ber Kommunikationsschnittstellen mit anderen Hardwarekomponenten ausgetauscht, sodass eine ¯exible und skalierbare Architektur entsteht. Zusa¨tzlich gestattet das vorgestellte Konzept Spezialisierung und Redundanz kritischer Verarbeitungseinheiten hinsichtlich Performanz und Ausfallsicherheit. Die FPGA-Implementierung ist modular aufgebaut, sodass die Komponenten beliebig austauschbar und erweiterbar sind. Dies ermo¨glicht u.a. den Wechsel der Kommunikationsschnittstelle (z.B. von Ethernet nach CAN-Bus) oder die Erweiterung des Netzwerkprotokolls fu¨r zuku¨nftige Anforderungen.},
language = {de},
author = {Brungs, Peter and Baunach, Marcel},
pages = {13},
file = {Brungs and Baunach - Einsatz von dynamisch rekonfigurierbaren FPGAs in F.pdf:/home/consti/Zotero/storage/IIGIDLW6/Brungs and Baunach - Einsatz von dynamisch rekonfigurierbaren FPGAs in F.pdf:application/pdf}
}
@article{vipin_zycap:_2014,
title = {{ZyCAP}: {Efficient} {Partial} {Reconfiguration} {Management} on the {Xilinx} {Zynq}},
volume = {6},
issn = {1943-0663, 1943-0671},
shorttitle = {{ZyCAP}},
url = {http://ieeexplore.ieee.org/document/6780588/},
doi = {10.1109/LES.2014.2314390},
abstract = {New hybrid FPGA platforms that couple processors with a reconfigurable fabric, such as the Xilinx Zynq, offer an alternative view of reconfigurable computing where software applications leverage hardware resources through the use of often reconfigured accelerators. For this to be feasible, reconfiguration overheads must be reduced so that the processor is not burdened with managing the process. We discuss partial reconfiguration (PR) on these architectures, and present an open source controller, ZyCAP, that overcomes the limitations of existing methods, offering more effective use of hardware resources in such architectures. ZyCAP combines high-throughput configuration with a high-level software interface that frees the processor from detailed PR management, making PR on the Zynq easy and efficient.},
language = {en},
number = {3},
urldate = {2019-01-27},
journal = {IEEE Embedded Systems Letters},
author = {Vipin, Kizheppatt and Fahmy, Suhaib A.},
month = sep,
year = {2014},
pages = {41--44},
file = {Vipin and Fahmy - 2014 - ZyCAP Efficient Partial Reconfiguration Managemen.pdf:/home/consti/Zotero/storage/MC5PVGFK/Vipin and Fahmy - 2014 - ZyCAP Efficient Partial Reconfiguration Managemen.pdf:application/pdf}
}
@misc{arm_arm_2018,
title = {Arm® {Cortex}®‑{M}1 {DesignStart}™ {FPGA}-{Xilinx} edition {User} {Guide}},
url = {https://static.docs.arm.com/100211/0001/arm_cortex_m1_designstart_fpga_xilinx_edition_ug_100211_0001_00_en.pdf?_ga=2.121336076.523725493.1550477241-1711067005.1549732081},
language = {en},
author = {ARM},
year = {2018},
file = {2018 - Arm® Cortex®‑M1 DesignStart™ FPGA-Xilinx edition U.pdf:/home/consti/Zotero/storage/ZUHYLGT4/2018 - Arm® Cortex®‑M1 DesignStart™ FPGA-Xilinx edition U.pdf:application/pdf}
}
@misc{noauthor_getting_nodate,
title = {Getting {Started}},
url = {http://www2.keil.com/mdk5/install},
urldate = {2019-02-19},
file = {Getting Started:/home/consti/Zotero/storage/72IL83UX/install.html:text/html}
}
@misc{arm_cortex-m1_nodate,
title = {Cortex-{M}1 {Technical} {Reference} {Manual}},
url = {https://static.docs.arm.com/ddi0413/d/DDI0413D_cortexm1_r1p0_trm.pdf},
language = {en},
author = {ARM},
file = {Cortex-M1 Technical Reference Manual.pdf:/home/consti/Zotero/storage/LXW4UQB7/Cortex-M1 Technical Reference Manual.pdf:application/pdf}
}
@misc{xilinx_ug1118-vivado-creating-packaging-custom-ip.pdf_nodate,
title = {ug1118-vivado-creating-packaging-custom-ip.pdf},
url = {https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_2/ug1118-vivado-creating-packaging-custom-ip.pdf},
urldate = {2019-02-19},
author = {Xilinx},
file = {ug1118-vivado-creating-packaging-custom-ip.pdf:/home/consti/Zotero/storage/L74VGU4A/ug1118-vivado-creating-packaging-custom-ip.pdf:application/pdf}
}
@misc{xilinx_vivado_2018,
title = {Vivado {Design} {Suite} {Tutorial}: {Partial} {Reconfiguration} ({UG}947)},
url = {https://www.xilinx.com/content/dam/xilinx/support/documentation/sw_manuals/xilinx2018_3/ug947-vivado-partial-reconfiguration-tutorial.pdf},
language = {en},
author = {Xilinx},
year = {2018},
file = {2018 - Vivado Design Suite Tutorial Partial Reconfigurat.pdf:/home/consti/Zotero/storage/ZFCTPBMB/2018 - Vivado Design Suite Tutorial Partial Reconfigurat.pdf:application/pdf}
}
@misc{xilinx_vivado_2018-1,
title = {Vivado {Design} {Suite} {User} {Guide}: {Partial} {Reconfiguration} ({UG}909)},
url = {https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug909-vivado-partial-reconfiguration.pdf},
language = {en},
author = {Xilinx},
year = {2018},
file = {2018 - Vivado Design Suite User Guide Partial Reconfigur.pdf:/home/consti/Zotero/storage/AGDJI9W9/2018 - Vivado Design Suite User Guide Partial Reconfigur.pdf:application/pdf}
}
@misc{zynq_7000_technical_manual,
title = {Zynq {7000} {Technical} {Manual}},
url = {https://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf},
author = {Xilinx},
year = {2018}
}
@misc{7series_libraries_guide,
title = {7series {libraries} {guide}},
url = {https://www.xilinx.com/support/documentation/sw_manuals/xilinx2012_2/ug953-vivado-7series-libraries.pdf},
author = {Xilinx},
year = {2018}
}
@misc{firmware,
title = {{MCU Firmware Repository}},
url = {https://github.com/SoC-Lab/Firmware},
author = {{C. Schieber, R. Schorn, A. Hirtenlehner, P. Schober}},
year = {2019}
}
@misc{fpga_design,
title = {{FPGA Design Repository}},
url = {https://github.com/SoC-Lab/zedboard_cortex_m1},
author = {{C. Schieber, R. Schorn, A. Hirtenlehner, P. Schober}},
year = {2019}
}
@misc{mbed_port,
title = {{Mbed OS Port for Xilinx Cortex M1}},
url = {https://github.com/andi-h/mbed-os/tree/XC7Z020},
author = {A. Hirtenlehner},
year = {2019}
}
@misc{CANTransceiver,
title = {{CAN Bus transceiver}},
url = {https://www.ti.com/lit/ds/symlink/sn65hvd230.pdf},
author = {Texas Instruments},
year = {2018}
}
@misc{NucleoBoard,
title = {{STM32 Nucleo-64 F072RB/F103RB}},
url = {https://www.st.com/content/ccc/resource/technical/document/user_manual/98/2e/fa/4b/e0/82/43/b7/DM00105823.pdf/files/DM00105823.pdf/jcr:content/translations/en.DM00105823.pdf},
author = {STMicroelectronics},
year = {2017}
}
@misc{STM32F103RB,
title = {{STM32F103RB}},
url = {https://www.st.com/resource/en/datasheet/stm32f103rb.pdf},
author = {STMicroelectronics},
year = {2015}
}
@misc{STM32F072RB,
title = {{STM32F072RB}},
url = {https://www.st.com/resource/en/datasheet/stm32f072rb.pdf},
author = {STMicroelectronics},
year = {2017}
}
@misc{ZedBoard,
title = {{ZedBoard}},
url = {http://zedboard.org/sites/default/files/documentations/ZedBoard_HW_UG_v2_2.pdf},
author = {AvNet},
year = {2014}
}