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Merge pull request #946 from visr/wildcard
Support Moshi wildcards via dispatch
2 parents cc43377 + ac6180c commit 7771788

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2 files changed

+11
-4
lines changed

2 files changed

+11
-4
lines changed

src/clock.jl

Lines changed: 10 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -40,22 +40,28 @@ discrete-time systems that assume a fixed sample time, such as PID controllers a
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filters.
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""" SolverStepClock
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43-
isclock(c) = isa(c, TimeDomain) && @match c begin
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isclock(c::TimeDomain) = @match c begin
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PeriodicClock() => true
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_ => false
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end
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issolverstepclock(c) = isa(c, TimeDomain) && @match c begin
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issolverstepclock(c::TimeDomain) = @match c begin
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SolverStepClock() => true
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_ => false
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end
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53-
iscontinuous(c) = isa(c, TimeDomain) && @match c begin
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iscontinuous(c::TimeDomain) = @match c begin
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ContinuousClock() => true
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_ => false
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end
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58-
is_discrete_time_domain(c) = !iscontinuous(c)
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is_discrete_time_domain(c::TimeDomain) = !iscontinuous(c)
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# workaround for https://github.com/Roger-luo/Moshi.jl/issues/43
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isclock(::Any) = false
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issolverstepclock(::Any) = false
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iscontinuous(::Any) = false
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is_discrete_time_domain(::Any) = false
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function first_clock_tick_time(c, t0)
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@match c begin

test/clock.jl

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -34,6 +34,7 @@ using MLStyle: @match
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@test is_discrete_time_domain(PeriodicClock(; dt = 1.0))
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@test !is_discrete_time_domain(Continuous())
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@test is_discrete_time_domain(SolverStepClock())
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@test !is_discrete_time_domain(nothing)
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@test first_clock_tick_time(PeriodicClock(; dt = 2.0), 5.0) === 6.0
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@test_throws ErrorException first_clock_tick_time(Continuous(), 5.0)

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