correction(jugad) in lw,adz and ndz dependency

Author: kparth98

Project_2_RISC_Pipelined/IF_stage.vhd

@@ -9,7 +9,7 @@ entity memory_instruction is
 end entity;
 architecture mem of memory_instruction is
   type RAM_array is array (0 to 2**16-1) of std_logic_vector (15 downto 0);
-	signal RAM : RAM_array:= (X"3201",X"8205",X"0000",X"0000",X"3401",X"3601",X"3801",others=>X"0000");
+	signal RAM : RAM_array:= (X"3201",X"35ff",X"420f",X"2299",X"3801",X"3a01",others=>X"0000");
 begin
       data_out <= RAM(to_integer(unsigned(address)));
 end architecture mem;
@@ -138,7 +138,7 @@ d: IF_interface_reg port map(
 		ip(16 downto 1)=>mem_instr_out,
 		ip(0)=>validate_control,
 		op=>IF_reg_op);
-process(PC_control,ALU1_out,memd_out,alu2_out,alu3_out,RF_d2,memid_08)
+process(PC_control,ALU1_out,memd_out,alu2_out,alu3_out,RF_d2,memid_08,alu3_ex)
   begin
   if (PC_control = "000") then
     PC_in<=ALU1_out;

Project_2_RISC_Pipelined/Mem_stage.vhd

@@ -95,7 +95,21 @@ dummy_mem_write<=(EX_reg_op(60) and not(EX_reg_op(0)));
 
 a: memory_data port map(clk=>clock,mem_write=>dummy_mem_write,address=>mem_muxaddr_op,data_in=>mem_mux_datain_op,data_out=>mem_data_out_sig);
 
-b:mem_interface_reg port map(EN=>'1',CLK=>clock,reset=>reset,ip(76 downto 61)=>EX_reg_op(93 downto 78),ip(60 downto 45)=>EX_reg_op(77 downto 62),ip(44 downto 29)=>mem_data_out_sig,ip(28 downto 13)=>EX_reg_op(53 downto 38),ip(5 downto 3)=>EX_reg_op(5 downto 3),ip(2)=>EX_reg_op(2),ip(1)=>memd_muxz_output,ip(0)=>nullify_control_mem,ip(12)=>EX_reg_op(61),ip(11 downto 6)=>EX_reg_op(59 downto 54),op=>Mem_reg_op);
+b:mem_interface_reg port map(
+EN=>'1',
+CLK=>clock,
+reset=>reset,
+ip(76 downto 61)=>EX_reg_op(93 downto 78),
+ip(60 downto 45)=>EX_reg_op(77 downto 62),
+ip(44 downto 29)=>mem_data_out_sig,
+ip(28 downto 13)=>EX_reg_op(53 downto 38),
+ip(5 downto 3)=>EX_reg_op(5 downto 3),
+ip(2)=>EX_reg_op(2),
+ip(1)=>memd_muxz_output,
+ip(0)=>nullify_control_mem,
+ip(12)=>EX_reg_op(61),
+ip(11 downto 6)=>EX_reg_op(59 downto 54),
+op=>Mem_reg_op);
 
 memd_out<= mem_data_out_sig;
 load_flag_z<=memd_z_flag;
@@ -113,7 +127,7 @@ process(EX_reg_op,memd_z_flag)
 begin
 if((EX_reg_op(93 downto 90)="0100") and (EX_reg_op(0)='0')) then
   memd_muxz_output<=memd_z_flag;
-else 
+else
   memd_muxz_output<=EX_reg_op(1);
 end if;
 end process;

Project_2_RISC_Pipelined/write_control.vhd

@@ -19,16 +19,16 @@ begin
 authentic_c_op<=authentic_c;
 authentic_z_op<=authentic_z;
 -----------------------------------
-process(flag_z_ex,flag_z_mem,opcode_mem,opcode_EX,flagz_enable_ex,flagz_enable_mem,user_flagz)
+process(flag_z_ex,flag_z_mem,opcode_mem,opcode_EX,flagz_enable_ex,flagz_enable_mem,user_flagz,load_flag_z)
 begin
 	if(flagz_enable_ex = '0') then
 		if (flagz_enable_mem = '0') then
 			authentic_z<=user_flagz;
 		else
 			authentic_z<=flag_z_mem;
 		end if;
-	else
-		authentic_z<=flag_z_ex;
+  else
+	 authentic_z<=flag_z_ex;
 end if;
 end process;
 
@@ -47,7 +47,9 @@ end process;
 
 process(authentic_c,authentic_z,opcode_EX,opcode_OR,load_flag_z,nullify_ex,rf_write_or,flagc_write_or,flagz_write_or)
 begin
-	if((((opcode_OR = "000001") or (opcode_OR = "001001")) and (authentic_z = '0')) or (((opcode_OR = "000010") or (opcode_OR = "001010")) and (authentic_c = '0')) or ((opcode_EX(5 downto 2) = "0100") and ((opcode_OR = "000001") or (opcode_OR = "001001")) and (load_flag_z = '0') and (nullify_ex = '0'))) then
+	if((((opcode_OR = "000001") or (opcode_OR = "001001")) and (authentic_z = '0') and not (opcode_EX(5 downto 2) = "0100"))
+	or (((opcode_OR = "000010") or (opcode_OR = "001010")) and (authentic_c = '0'))
+	or ((opcode_EX(5 downto 2) = "0100") and ((opcode_OR = "000001") or (opcode_OR = "001001")) and (load_flag_z = '0') and (nullify_ex = '0'))) then
 		RF_write_out<='0';
 		flagc_write_out<='0';
 		flagz_write_out<='0';
@@ -58,6 +60,3 @@ begin
 	end if;
 end process;
 end Behave;
-
-
-