rtl bugs squashed

Author: SConsul

Project_2_RISC_Pipelined/EX_stage.vhd

@@ -228,6 +228,7 @@ signal se6_ex_op: std_logic_vector(15 downto 0);
 signal alu_flagz_sig, alu_flagc_sig: std_logic;
 signal PE1_addr_sig: std_logic_vector(2 downto 0);
 signal EX_reg_op_sig: std_logic_vector(93 downto 0);
+signal dummy_ip61, dummy_ip55, dummy_ip54: std_logic;
 begin
 
 a: ALU_2 port map(alu_op=>OR_reg_op(17 downto 16),alu_a=>alu_a_ip,alu_b=>OR_reg_op(51 downto 36),alu_c=>alu_flagc_sig,alu_z=>alu_flagz_sig,alu_out=>alu2_out_sig );
@@ -236,6 +237,10 @@ b: priority_encoder1 port map (ip=>OR_reg_op(7 downto 0),op_addr=>PE1_addr_sig,u
 
 c: SE6_ex port map (ip=>OR_reg_op(73 downto 68),op=>se6_ex_op);
 
+dummy_ip61 <=(RF_write_out and not(nullify_control_ex));
+dummy_ip55 <= (flagc_write_out and not(nullify_control_ex));
+dummy_ip54 <= (flagz_write_out and not(nullify_control_ex));
+
 d: EX_interface_reg port map(
   EN=>'1',
   CLK=>clock,
@@ -249,11 +254,11 @@ d: EX_interface_reg port map(
   ip(2)=>alu_flagc_sig,
   ip(1)=>alu_flagz_sig,
   ip(0)=>nullify_control_ex,
-  ip(61)=>(RF_write_out and not(nullify_control_ex)),
+  ip(61)=>dummy_ip61,
   ip(60)=>OR_reg_op(18),
   ip(59 downto 56)=>OR_reg_op(14 downto 11),
-  ip(55)=>(flagc_write_out and not(nullify_control_ex)),
-  ip(54)=>(flagz_write_out and not(nullify_control_ex)),
+  ip(55)=>dummy_ip55,
+  ip(54)=>dummy_ip54,
   op=>EX_reg_op_sig);
 
 PCtoR7 <= EX_reg_op_sig(93 downto 78);

Project_2_RISC_Pipelined/ID_stage.vhd

@@ -51,25 +51,33 @@ end component;
 signal RF_enable, mem_write, ALU2_a_mux,flagc_en,flagz_en: std_logic;
 signal ALU2_op,RF_D3_mux,RF_a3_mux: std_logic_vector(1 downto 0);
 signal PE2_mux_op: std_logic_vector(7 downto 0);
-
+signal dummy_ip8, dummy_ip19, dummy_ip18, dummy_ip10, dummy_ip9: std_logic;
 begin
+
+dummy_ip8 <= (nullify_ID_control or not(IF_reg_op(0)));
+dummy_ip19 <=(RF_enable and not(nullify_ID_control));
+dummy_ip18 <= (mem_write and not(nullify_ID_control));
+dummy_ip10 <= (flagc_en and not(nullify_ID_control));
+dummy_ip9 <= (flagz_en and not(nullify_ID_control));
+
 a: ID_interface_reg port map(
 		EN=>EN_id_control,
 		EN_8bits=>EN_8bits_control,
 		reset=>reset,
 		CLK=>clock,
 		ip(51 downto 20)=>IF_reg_op(32 downto 1),
-		ip(8)=>(nullify_ID_control or not(IF_reg_op(0))),
-		ip(7 downto 0)=>PE2_mux_op,
-		ip(19)=>(RF_enable and not(nullify_ID_control)),
-		ip(18)=>(mem_write and not(nullify_ID_control)),
+		ip(19)=>dummy_ip19,
+		ip(18)=>dummy_ip18,
 		ip(17 downto 16)=>ALU2_op,
 		ip(15)=>ALU2_a_mux,
 		ip(14 downto 13)=>RF_a3_mux,
 		ip(12 downto 11)=>RF_D3_mux,
-		op=>ID_reg_op,
-		ip(10)=>(flagc_en and not(nullify_ID_control)),
-		ip(9)=>(flagz_en and not(nullify_ID_control)));
+		ip(10)=>dummy_ip10,
+		ip(9)=>dummy_ip9,
+		ip(8)=>dummy_ip8,
+		ip(7 downto 0)=>PE2_mux_op,		
+		op=>ID_reg_op);
+		
 
 mem_id_08(15 downto 7)<=IF_reg_op(9 downto 1);
 mem_id_08(6 downto 0)<="0000000";

Project_2_RISC_Pipelined/Mem_stage.vhd

@@ -12,7 +12,7 @@ end entity;
 
 architecture mem of memory_data is
   type RAM_array is array (0 to 2**4-1) of std_logic_vector (15 downto 0);
-	signal RAM : RAM_array:= (X"3115",X"32C7",X"0050",X"039A",others=>X"0000");
+	signal RAM : RAM_array:= (X"3001",X"3203",X"3605",X"700A",X"6014",X"C283",others=>X"0000");
 begin
   process(clk, mem_write, data_in, address, RAM)
     begin
@@ -89,9 +89,11 @@ end component;
 
 signal memd_z_flag,memd_muxz_output: std_logic;
 signal mem_muxaddr_op ,mem_data_out_sig,mem_mux_datain_op: std_logic_vector(15 downto 0);
+signal dummy_mem_write: std_logic;
 begin
+dummy_mem_write<=(EX_reg_op(60) and not(EX_reg_op(0)));
 
-a: memory_data port map(clk=>clock,mem_write=>(EX_reg_op(60) and not(EX_reg_op(0))),address=>mem_muxaddr_op,data_in=>mem_mux_datain_op,data_out=>mem_data_out_sig);
+a: memory_data port map(clk=>clock,mem_write=>dummy_mem_write,address=>mem_muxaddr_op,data_in=>mem_mux_datain_op,data_out=>mem_data_out_sig);
 
 b:mem_interface_reg port map(EN=>'1',CLK=>clock,reset=>reset,ip(76 downto 61)=>EX_reg_op(93 downto 78),ip(60 downto 45)=>EX_reg_op(77 downto 62),ip(44 downto 29)=>mem_data_out_sig,ip(28 downto 13)=>EX_reg_op(53 downto 38),ip(5 downto 3)=>EX_reg_op(5 downto 3),ip(2)=>EX_reg_op(2),ip(1)=>memd_muxz_output,ip(0)=>nullify_control_mem,ip(12)=>EX_reg_op(61),ip(11 downto 6)=>EX_reg_op(59 downto 54),op=>Mem_reg_op);
 

Project_2_RISC_Pipelined/OR_stage.vhd

@@ -312,7 +312,7 @@ entity OR_stage is
     );
 end entity;
 
-architecture Behave of OR_stage is
+architecture ors of OR_stage is
 
 component R7 is
 Generic (NUM_BITS : INTEGER := 16);
@@ -374,14 +374,21 @@ end component;
 signal SE6_op,SE9_op,SE_mux_op,RF_D3_sig,alu3_op_sig,R7_op,rf_d1_sig,rf_d2_sig,rf_d1_mux_sig,rf_d2_mux_sig: std_logic_vector (15 downto 0);
 signal RF_a3_sig,RF_a2_sig,op_PE2: std_logic_vector (2 downto 0);
 signal PE1_mux_op: std_logic_vector(7 downto 0);
-
+signal not_nullify_ex: std_logic;
+signal dummy_ip19,dummy_ip18, dummy_ip10, dummy_ip9: std_logic;
 begin
 
+not_nullify_ex <= not(nullify_ex);
+dummy_ip19 <= (ID_reg_op(19) and not(nullify_control_OR));
+dummy_ip18 <= (ID_reg_op(18) and not(nullify_control_OR));
+dummy_ip10 <= (ID_reg_op(10) and not(nullify_control_OR));
+dummy_ip9 <= (ID_reg_op(9) and not(nullify_control_OR));
+
 a: SE6 port map (ip=>ID_reg_op(25 downto 20),op=>SE6_op);
 b: SE9 port map (ip=>ID_reg_op(28 downto 20),op=>SE9_op);
 c: ALU_3 port map (alu_a=>SE_mux_op,alu_b=>ID_reg_op(51 downto 36),alu_out=>alu3_op_sig);
 d: RegFile port map(CLK => clock, reset=>reset,rf_a1=>ID_reg_op(31 downto 29),rf_a2 => RF_a2_sig, rf_a3 =>RF_a3_sig,rf_d3=>RF_d3_sig,rf_d1=>rf_d1_sig,rf_d2=>rf_d2_sig,rf_wr =>mem_rf_en );
-e: R7 port map(EN=>not(nullify_ex),ip=>PC_ex,op=>R7_op,reset=>reset,clk=>clock);
+e: R7 port map(EN=>not_nullify_ex,ip=>PC_ex,op=>R7_op,reset=>reset,clk=>clock);
 f: priority_encoder2 port map(ip=>ID_reg_op(7 downto 0), op_addr=>op_PE2, update=> PE2_op);
 g: OR_interface_reg port map(
       EN=>'1',
@@ -392,11 +399,11 @@ g: OR_interface_reg port map(
       ip(67 downto 52)=>rf_d1_mux_sig,
       ip(51 downto 36)=>rf_d2_mux_sig,
       ip(35 downto 20)=>alu3_op_sig,
-      ip(19)=>(ID_reg_op(19) and not(nullify_control_OR)),
-      ip(18)=>(ID_reg_op(18) and not(nullify_control_OR)),
+      ip(19)=>dummy_ip19,
+      ip(18)=>dummy_ip18,
       ip(17 downto 11)=>ID_reg_op(17 downto 11),
-      ip(10)=>(ID_reg_op(10) and not(nullify_control_OR)),
-      ip(9)=>(ID_reg_op(9) and not(nullify_control_OR)),
+      ip(10)=>dummy_ip10,
+      ip(9)=>dummy_ip9,
       ip(8)=>nullify_control_OR,
       ip(7 downto 0)=>PE1_mux_op,
 		op=>OR_reg_op);
@@ -512,4 +519,4 @@ else
 end if;
 end process;
 
-end Behave;
+end architecture ors;

Project_2_RISC_Pipelined/WB_stage.vhd

@@ -5,9 +5,8 @@ use ieee.numeric_std.all;
 entity user_flagz is
 Generic (NUM_BITS : INTEGER :=1);
   port (EN, reset, CLK: in std_logic;
-        ip: in std_logic_vector(NUM_BITS-1 downto 0);
-        op: out std_logic_vector(NUM_BITS-1 downto 0)
-      );
+        ip: in std_logic;
+        op: out std_logic);
 end entity;
 
 architecture reg_arch of user_flagz is
@@ -16,7 +15,7 @@ reg1 : process(CLK, EN, ip)
 begin
   if CLK'event and CLK = '1' then
     if reset = '1' then
-      op(NUM_BITS-1 downto 0) <= (others=>'0');
+      op <= '0';
     elsif EN = '1' then
       op <= ip;
     end if;
@@ -34,9 +33,8 @@ use ieee.numeric_std.all;
 entity user_flagc is
 Generic (NUM_BITS : INTEGER :=1);
   port (EN, reset, CLK: in std_logic;
-        ip: in std_logic_vector(NUM_BITS-1 downto 0);
-        op: out std_logic_vector(NUM_BITS-1 downto 0)
-      );
+        ip: in std_logic;
+        op: out std_logic);
 end entity;
 
 architecture reg_arch of user_flagc is
@@ -45,7 +43,7 @@ reg1 : process(CLK, EN, ip)
 begin
   if CLK'event and CLK = '1' then
     if reset = '1' then
-      op(NUM_BITS-1 downto 0) <= (others=>'0');
+      op<= '0';
     elsif EN = '1' then
       op <= ip;
     end if;