squashed some more bugs

Author: kparth98

Project_2_RISC_Pipelined/EX_stage.vhd

@@ -156,6 +156,10 @@ end if;
 end process;
 end SignedExtender;
 ---------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
 entity EX_stage is 
 port (OR_reg_op: in std_logic_vector(99 downto 0);
 	 RF_write_out,flagc_write_out,flagz_write_out: in std_logic;

Project_2_RISC_Pipelined/ID_stage.vhd

@@ -31,7 +31,7 @@ library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 entity ID_stage is
-  port(reset,clock,nullify_ID_control,PE2_mux_control: in std_logic;
+  port(reset,clock,nullify_ID_control,PE2_mux_control,EN_id_control,EN_8bits_control: in std_logic;
   PE2_ip: std_logic_vector (7 downto 0);
   IF_reg_op :in std_logic_vector(32 downto 0);
   ID_reg_op : out std_logic_vector (51 downto 0);
@@ -42,7 +42,7 @@ architecture Behave of ID_stage is
 
 component ID_interface_reg is
 Generic (NUM_BITS : INTEGER := 52);
-  port (EN, reset, CLK,EN_id_control,EN_8bits_control: in std_logic;
+  port (EN, reset, CLK, EN_8bits: in std_logic;
         ip: in std_logic_vector(NUM_BITS-1 downto 0);
         op: out std_logic_vector(NUM_BITS-1 downto 0)
       );
@@ -53,7 +53,23 @@ signal ALU2_op,RF_D3_mux,RF_a3_mux: std_logic_vector(1 downto 0);
 signal PE2_mux_op: std_logic_vector(7 downto 0);
 
 begin
-a: ID_interface_reg(EN=>EN_id_control,EN_8bits=>EN_8bits_control,reset=>reset,CLK=>clock,ip(51 downto 20)=>IF_reg_op(32 downto 1),ip(8)=>(nullify_ID_control or not(IF_reg_op(0))),ip(7 downto 0)=>PE2_mux_op,ip(19)=>(RF_enable and not(nullify_ID_control)),ip(18)=>(mem_write and not(nullify_ID_control)),ip(17 downto 16)=>ALU2_op,ip(15)=>ALU2_a_mux,ip(14 downto 13)=>RF_a3_mux,ip(12 downto 11)=>RF_D3_mux,op=>ID_reg_op,ip(10)=>(flagc_en and not(nullify_ID_control)),ip(9)=>(flagz_en and not(nullify_ID_control)));
+a: ID_interface_reg port map(
+		EN=>EN_id_control,
+		EN_8bits=>EN_8bits_control,
+		reset=>reset,
+		CLK=>clock,
+		ip(51 downto 20)=>IF_reg_op(32 downto 1),
+		ip(8)=>(nullify_ID_control or not(IF_reg_op(0))),
+		ip(7 downto 0)=>PE2_mux_op,
+		ip(19)=>(RF_enable and not(nullify_ID_control)),
+		ip(18)=>(mem_write and not(nullify_ID_control)),
+		ip(17 downto 16)=>ALU2_op,
+		ip(15)=>ALU2_a_mux,
+		ip(14 downto 13)=>RF_a3_mux,
+		ip(12 downto 11)=>RF_D3_mux,
+		op=>ID_reg_op,
+		ip(10)=>(flagc_en and not(nullify_ID_control)),
+		ip(9)=>(flagz_en and not(nullify_ID_control)));
 
 mem_id_08(15 downto 7)<=IF_reg_op(9 downto 1);
 mem_id_08(6 downto 0)<="0000000";

Project_2_RISC_Pipelined/IF_stage.vhd

@@ -12,7 +12,7 @@ architecture mem of memory_instruction is
   type RAM_array is array (0 to 2**4-1) of std_logic_vector (15 downto 0);
 	signal RAM : RAM_array:= (X"3115",X"32C7",X"0050",X"039A",others=>X"0000");
 begin
-  process(clk,data_in, address, RAM)
+  process(clk, address, RAM)
     begin
     if rising_edge(clk) then
       data_out <= RAM(to_integer(unsigned(address)));
@@ -134,7 +134,7 @@ signal PC_out,PC_in: std_logic_vector(15 downto 0);
 signal ALU1_out,mem_instr_out: std_logic_vector(15 downto 0);
 begin
 a: PC port map(EN => PC_en_control,CLK=>clock,reset=>reset,ip=>PC_in,op=>PC_out);
-b: memory_instruction port map(clock=>clock,address=>PC_out,data_out=>mem_instr_out);
+b: memory_instruction port map(clk=>clock,address=>PC_out,data_out=>mem_instr_out);
 c: ALU_1 port map(alu_in=>PC_out,alu_out=>ALU1_out);
 d: IF_interface_reg port map(EN=>'1',reset=>reset,CLk=>clock,ip(32 downto 17)=>PC_out,ip(16 downto 1)=>mem_instr_out,ip(0)=>validate_control,op=>IF_reg_op);
 process(PC_control,ALU1_out)

Project_2_RISC_Pipelined/Mem_stage.vhd

@@ -55,6 +55,9 @@ end process;
 end reg_arch;
 
 -------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
 
 entity Mem_stage is
  port(

Project_2_RISC_Pipelined/OR_stage.vhd

@@ -343,21 +343,22 @@ component ALU_3 is
       alu_out: out std_logic_vector(15 downto 0));
 end component;
 
-signal SE6_op,SE9_op,SE_mux_op,RF_D3_sig,alu3_op,R7_op,rf_d1_sig,rf_d2_sig,rf_d1_mux_sig,rf_d2_mux_sig: std_logic_vector (15 downto 0);
+signal SE6_op,SE9_op,SE_mux_op,RF_D3_sig,alu3_op_sig,R7_op,rf_d1_sig,rf_d2_sig,rf_d1_mux_sig,rf_d2_mux_sig: std_logic_vector (15 downto 0);
 signal RF_a3_sig,RF_a2_sig,op_PE2: std_logic_vector (2 downto 0);
 signal PE1_mux_op: std_logic_vector(7 downto 0);
 
 begin
 
 a: SE6 port map (ip=>ID_reg_op(25 downto 20),op=>SE6_op);
 b: SE9 port map (ip=>ID_reg_op(28 downto 20),op=>SE9_op);
-c: ALU_3 port map (alu_a=>SE_mux_op,alu_b=>ID_reg_op(51 downto 36),alu_out=>alu3_op);
+c: ALU_3 port map (alu_a=>SE_mux_op,alu_b=>ID_reg_op(51 downto 36),alu_out=>alu3_op_sig);
 d: RegFile port map(CLK => clock, reset=>reset,rf_a1=>ID_reg_op(31 downto 29),rf_a2 => RF_a2_sig, rf_a3 =>RF_a3_sig,rf_d3=>RF_d3_sig,rf_d1=>rf_d1_sig,rf_d2=>rf_d2_sig,rf_wr =>mem_rf_en );
-e: R7 port map(EN=>not(nullify_ex),ip=>PC_ex,op=>R7_op);
+e: R7 port map(EN=>not(nullify_ex),ip=>PC_ex,op=>R7_op,reset=>reset,clk=>clock);
 f: priority_encoder2 port map(ip=>ID_reg_op(7 downto 0), op_addr=>op_PE2, update=> PE2_op);
-g: OR_interface_reg port map(EN=>'1',reset=>reset,CLK=>clock,ip(99 downto 84)=>ID_reg_op(51 downto 36),ip(83 downto 68)=>ID_reg_op(35 downto 20),ip(67 downto 52)=>rf_d1_mux_sig,ip(51 downto 34)=>rf_d2_mux_sig,ip(35 downto 20)=>alu3_op,ip(19)=>(ID_reg_op(19) and not(nullify_control_OR)),ip(18)=>(ID_reg_op(18) and not(nullify_control_OR)),ip(17 downto 11)=>ID_reg_op(17 downto 11),ip(10)=>(ID_reg_op(10) and not(nullify_control_OR)),ip(9)=>(ID_reg_op(9) and not(nullify_control_OR)),ip(8)=>nullify_control_OR,ip(7 downto 0)=>PE1_mux_op);
+g: OR_interface_reg port map(EN=>'1',reset=>reset,CLK=>clock,ip(99 downto 84)=>ID_reg_op(51 downto 36),ip(83 downto 68)=>ID_reg_op(35 downto 20),ip(67 downto 52)=>rf_d1_mux_sig,ip(51 downto 34)=>rf_d2_mux_sig,ip(35 downto 20)=>alu3_op_sig,ip(19)=>(ID_reg_op(19) and not(nullify_control_OR)),ip(18)=>(ID_reg_op(18) and not(nullify_control_OR)),ip(17 downto 11)=>ID_reg_op(17 downto 11),ip(10)=>(ID_reg_op(10) and not(nullify_control_OR)),ip(9)=>(ID_reg_op(9) and not(nullify_control_OR)),ip(8)=>nullify_control_OR,ip(7 downto 0)=>PE1_mux_op);
 
 RF_d2_or<=rf_d2_sig;
+ALU3_op<=alu3_op_sig;
 process(ID_reg_op)
 begin
 if (ID_reg_op(35 downto 32) ="1000") then
@@ -371,10 +372,10 @@ end process;
 
 process(ID_reg_op,op_PE2)
 begin
-if (ID_reg_op(35 downto 32) = "0111" and not(ID_reg_op(8))) then
-  rf_a2 <= op_PE2;
+if (ID_reg_op(35 downto 32) = "0111" and ID_reg_op(8)='0' ) then
+  rf_a2_sig <= op_PE2;
 else
-  rf_a2 <= ID_reg_op(28 downto 26);
+  rf_a2_sig <= ID_reg_op(28 downto 26);
 end if;
 end process;
 

Project_2_RISC_Pipelined/PE1_mux_control.vhd

@@ -14,10 +14,10 @@ architecture Behave of PE1_mux_control is
 	begin
 	process(OR_reg_opcode,nullified_or)
 	begin
-	if(OR_reg_opcode = "0110" and not(nullified_or)) then
-		PE1_mux_control<='1';
+	if(OR_reg_opcode = "0110" and nullified_or='0') then
+		PE1_mux_controller<='1';
 	else
-		PE1_mux_control<='0';
+		PE1_mux_controller<='0';
 end if;
 end process;
 end Behave;

Project_2_RISC_Pipelined/PE2_mux_control.vhd

@@ -14,7 +14,7 @@ architecture Behave of PE2_mux_control is
 	begin
 	process(ID_reg_opcode,nullified_id)
 	begin
-	if(ID_reg_opcode = "0111" and not(nullified_id)) then
+	if(ID_reg_opcode = "0111" and nullified_id='0') then
 		PE2_mux_controller<='1';
 	else
 		PE2_mux_controller<='0';

Project_2_RISC_Pipelined/RF_d1_control.vhd

@@ -16,7 +16,7 @@ end entity;
 
 architecture Behave of RF_d1_control is
 begin
-process(RS_id1,RD_or,RD_ex,RD_mem,ID_opcode,EX_opcode,OR_opcode,mem_opcode,cflag_ex,cflag_mem,zflag_ex,zflag_mem,nullify_or,nullify_id,nullify_ex,nullify_mem)
+process(RS_id1,RD_or,RD_ex,RD_mem,ID_opcode,EX_opcode,OR_opcode,mem_opcode,cflag_ex,cflag_mem,zflag_ex,zflag_mem,nullify_or,nullify_id,nullify_ex,nullify_mem,PE1_op,PE2_stored,user_cflag,user_zflag)
 begin
 if((OR_opcode(5 downto 2) = "0110" and nullify_or ='0' and PE1_op /= "00000000") or (OR_opcode(5 downto 2) = "0111" and nullify_or ='0' and PE2_stored /= "00000000")) then
 	RF_d1_mux_control<="0001";

Project_2_RISC_Pipelined/RF_d2_control.vhd

@@ -15,7 +15,7 @@ end entity;
 
 architecture Behave of RF_d2_control is
 begin
-process(RS_id2,RD_or,RD_ex,RD_mem,ID_opcode,EX_opcode,OR_opcode,mem_opcode,cflag_ex,cflag_mem,zflag_ex,zflag_mem,nullify_or,nullify_id,nullify_ex,nullify_mem)
+process(RS_id2,RD_or,RD_ex,RD_mem,ID_opcode,EX_opcode,OR_opcode,mem_opcode,cflag_ex,cflag_mem,zflag_ex,zflag_mem,nullify_or,nullify_id,nullify_ex,nullify_mem,user_zflag,user_cflag)
 begin
 if(((ID_opcode = "0000") or (ID_opcode = "0001") or
     (ID_opcode = "0010") or (ID_opcode = "0101") or

Project_2_RISC_Pipelined/write_control.vhd

@@ -33,7 +33,7 @@ begin
 end if;
 end process;
 
-process(authentic_c,authentic_z,opcode_EX,opcode_OR,load_flag_z,nullify_ex)
+process(authentic_c,authentic_z,opcode_EX,opcode_OR,load_flag_z,nullify_ex,rf_write_or,flagc_write_or,flagz_write_or)
 begin
 	if((((opcode_OR = "000001") or (opcode_OR = "001001")) and (authentic_z = '0')) or (((opcode_OR = "000010") or (opcode_OR = "001010")) and (authentic_c = '0')) or ((opcode_EX(5 downto 2) = "0100") and ((opcode_OR = "000001") or (opcode_OR = "001001")) and (load_flag_z = '0') and (nullify_ex = '0'))) then
 		RF_write_out<='0';