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StanleyYP Wangnbd168
StanleyYP Wang
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nbd168
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wifi: mt76: mt7996: rework register mapping for mt7990
Rework register offset and l1/l2/cbtop mapping for mt7990. This is a preliminary patch to support mt7990 chipset. Co-developed-by: Peter Chiu <chui-hao.chiu@mediatek.com> Signed-off-by: Peter Chiu <chui-hao.chiu@mediatek.com> Co-developed-by: Shayne Chen <shayne.chen@mediatek.com> Signed-off-by: Shayne Chen <shayne.chen@mediatek.com> Signed-off-by: StanleyYP Wang <StanleyYP.Wang@mediatek.com> Link: https://patch.msgid.link/20250409140750.724437-6-shayne.chen@mediatek.com Signed-off-by: Felix Fietkau <nbd@nbd.name>
1 parent 9ba4a76 commit f6c8741

2 files changed

Lines changed: 208 additions & 25 deletions

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‎drivers/net/wireless/mediatek/mt76/mt7996/mmio.c‎

Lines changed: 173 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -54,6 +54,17 @@ static const u32 mt7996_offs[] = {
5454
[MIB_BSCR7] = 0x9e8,
5555
[MIB_BSCR17] = 0xa10,
5656
[MIB_TRDR1] = 0xa28,
57+
[HIF_REMAP_L1] = 0x24,
58+
[HIF_REMAP_BASE_L1] = 0x130000,
59+
[HIF_REMAP_L2] = 0x1b4,
60+
[HIF_REMAP_BASE_L2] = 0x1000,
61+
[CBTOP1_PHY_END] = 0x77ffffff,
62+
[INFRA_MCU_END] = 0x7c3fffff,
63+
[WTBLON_WDUCR] = 0x370,
64+
[WTBL_UPDATE] = 0x380,
65+
[WTBL_ITCR] = 0x3b0,
66+
[WTBL_ITCR0] = 0x3b8,
67+
[WTBL_ITCR1] = 0x3bc,
5768
};
5869

5970
static const u32 mt7992_offs[] = {
@@ -80,6 +91,54 @@ static const u32 mt7992_offs[] = {
8091
[MIB_BSCR7] = 0xae4,
8192
[MIB_BSCR17] = 0xb0c,
8293
[MIB_TRDR1] = 0xb24,
94+
[HIF_REMAP_L1] = 0x8,
95+
[HIF_REMAP_BASE_L1] = 0x40000,
96+
[HIF_REMAP_L2] = 0x1b4,
97+
[HIF_REMAP_BASE_L2] = 0x1000,
98+
[CBTOP1_PHY_END] = 0x77ffffff,
99+
[INFRA_MCU_END] = 0x7c3fffff,
100+
[WTBLON_WDUCR] = 0x370,
101+
[WTBL_UPDATE] = 0x380,
102+
[WTBL_ITCR] = 0x3b0,
103+
[WTBL_ITCR0] = 0x3b8,
104+
[WTBL_ITCR1] = 0x3bc,
105+
};
106+
107+
static const u32 mt7990_offs[] = {
108+
[MIB_RVSR0] = 0x800,
109+
[MIB_RVSR1] = 0x804,
110+
[MIB_BTSCR5] = 0x868,
111+
[MIB_BTSCR6] = 0x878,
112+
[MIB_RSCR1] = 0x890,
113+
[MIB_RSCR27] = 0xa38,
114+
[MIB_RSCR28] = 0xa3c,
115+
[MIB_RSCR29] = 0xa40,
116+
[MIB_RSCR30] = 0xa44,
117+
[MIB_RSCR31] = 0xa48,
118+
[MIB_RSCR33] = 0xa50,
119+
[MIB_RSCR35] = 0xa58,
120+
[MIB_RSCR36] = 0xa5c,
121+
[MIB_BSCR0] = 0xbb8,
122+
[MIB_BSCR1] = 0xbbc,
123+
[MIB_BSCR2] = 0xbc0,
124+
[MIB_BSCR3] = 0xbc4,
125+
[MIB_BSCR4] = 0xbc8,
126+
[MIB_BSCR5] = 0xbcc,
127+
[MIB_BSCR6] = 0xbd0,
128+
[MIB_BSCR7] = 0xbd4,
129+
[MIB_BSCR17] = 0xbfc,
130+
[MIB_TRDR1] = 0xc14,
131+
[HIF_REMAP_L1] = 0x8,
132+
[HIF_REMAP_BASE_L1] = 0x40000,
133+
[HIF_REMAP_L2] = 0x1b8,
134+
[HIF_REMAP_BASE_L2] = 0x110000,
135+
[CBTOP1_PHY_END] = 0x7fffffff,
136+
[INFRA_MCU_END] = 0x7cffffff,
137+
[WTBLON_WDUCR] = 0x400,
138+
[WTBL_UPDATE] = 0x410,
139+
[WTBL_ITCR] = 0x440,
140+
[WTBL_ITCR0] = 0x448,
141+
[WTBL_ITCR1] = 0x44c,
83142
};
84143

85144
static const struct __map mt7996_reg_map[] = {
@@ -135,14 +194,83 @@ static const struct __map mt7996_reg_map[] = {
135194
{ 0x0, 0x0, 0x0 }, /* imply end of search */
136195
};
137196

197+
static const struct __map mt7990_reg_map[] = {
198+
{0x54000000, 0x02000, 0x1000}, /* WFDMA_0 (PCIE0 MCU DMA0) */
199+
{0x55000000, 0x03000, 0x1000}, /* WFDMA_1 (PCIE0 MCU DMA1) */
200+
{0x56000000, 0x04000, 0x1000}, /* WFDMA_2 (Reserved) */
201+
{0x57000000, 0x05000, 0x1000}, /* WFDMA_3 (MCU wrap CR) */
202+
{0x58000000, 0x06000, 0x1000}, /* WFDMA_4 (PCIE1 MCU DMA0 (MEM_DMA)) */
203+
{0x59000000, 0x07000, 0x1000}, /* WFDMA_5 (PCIE1 MCU DMA1) */
204+
{0x820c0000, 0x08000, 0x4000}, /* WF_UMAC_TOP (PLE) */
205+
{0x820c8000, 0x0c000, 0x2000}, /* WF_UMAC_TOP (PSE) */
206+
{0x820cc000, 0x0e000, 0x2000}, /* WF_UMAC_TOP (PP) */
207+
{0x820e0000, 0x20000, 0x0400}, /* WF_LMAC_TOP BN0 (WF_CFG) */
208+
{0x820e1000, 0x20400, 0x0200}, /* WF_LMAC_TOP BN0 (WF_TRB) */
209+
{0x820e2000, 0x20800, 0x0400}, /* WF_LMAC_TOP BN0 (WF_AGG) */
210+
{0x820e3000, 0x20c00, 0x0400}, /* WF_LMAC_TOP BN0 (WF_ARB) */
211+
{0x820e4000, 0x21000, 0x0400}, /* WF_LMAC_TOP BN0 (WF_TMAC) */
212+
{0x820e5000, 0x21400, 0x0800}, /* WF_LMAC_TOP BN0 (WF_RMAC) */
213+
{0x820ce000, 0x21c00, 0x0200}, /* WF_LMAC_TOP (WF_SEC) */
214+
{0x820e7000, 0x21e00, 0x0200}, /* WF_LMAC_TOP BN0 (WF_DMA) */
215+
{0x820cf000, 0x22000, 0x1000}, /* WF_LMAC_TOP (WF_PF) */
216+
{0x820e9000, 0x23400, 0x0200}, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */
217+
{0x820ea000, 0x24000, 0x0200}, /* WF_LMAC_TOP BN0 (WF_ETBF) */
218+
{0x820eb000, 0x24200, 0x0400}, /* WF_LMAC_TOP BN0 (WF_LPON) */
219+
{0x820ec000, 0x24600, 0x0200}, /* WF_LMAC_TOP BN0 (WF_INT) */
220+
{0x820ed000, 0x24800, 0x0800}, /* WF_LMAC_TOP BN0 (WF_MIB) */
221+
{0x820ca000, 0x26000, 0x2000}, /* WF_LMAC_TOP BN0 (WF_MUCOP) */
222+
{0x820d0000, 0x30000, 0x10000}, /* WF_LMAC_TOP (WF_WTBLON) */
223+
{0x00400000, 0x80000, 0x10000}, /* WF_MCU_SYSRAM */
224+
{0x820f0000, 0xa0000, 0x0400}, /* WF_LMAC_TOP BN1 (WF_CFG) */
225+
{0x820f1000, 0xa0600, 0x0200}, /* WF_LMAC_TOP BN1 (WF_TRB) */
226+
{0x820f2000, 0xa0800, 0x0400}, /* WF_LMAC_TOP BN1 (WF_AGG) */
227+
{0x820f3000, 0xa0c00, 0x0400}, /* WF_LMAC_TOP BN1 (WF_ARB) */
228+
{0x820f4000, 0xa1000, 0x0400}, /* WF_LMAC_TOP BN1 (WF_TMAC) */
229+
{0x820f5000, 0xa1400, 0x0800}, /* WF_LMAC_TOP BN1 (WF_RMAC) */
230+
{0x820f7000, 0xa1e00, 0x0200}, /* WF_LMAC_TOP BN1 (WF_DMA) */
231+
{0x820f9000, 0xa3400, 0x0200}, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */
232+
{0x820fa000, 0xa4000, 0x0200}, /* WF_LMAC_TOP BN1 (WF_ETBF) */
233+
{0x820fb000, 0xa4200, 0x0400}, /* WF_LMAC_TOP BN1 (WF_LPON) */
234+
{0x820fc000, 0xa4600, 0x0200}, /* WF_LMAC_TOP BN1 (WF_INT) */
235+
{0x820fd000, 0xa4800, 0x0800}, /* WF_LMAC_TOP BN1 (WF_MIB) */
236+
{0x820cc000, 0xa5000, 0x2000}, /* WF_LMAC_TOP BN1 (WF_MUCOP) */
237+
{0x820c4000, 0xa8000, 0x4000}, /* WF_LMAC_TOP (WF_UWTBL) */
238+
{0x81030000, 0xae000, 0x100}, /* WFSYS_AON part 1 */
239+
{0x81031000, 0xae100, 0x100}, /* WFSYS_AON part 2 */
240+
{0x81032000, 0xae200, 0x100}, /* WFSYS_AON part 3 */
241+
{0x81033000, 0xae300, 0x100}, /* WFSYS_AON part 4 */
242+
{0x81034000, 0xae400, 0x100}, /* WFSYS_AON part 5 */
243+
{0x80020000, 0xb0000, 0x10000}, /* WF_TOP_MISC_OFF */
244+
{0x81020000, 0xc0000, 0x10000}, /* WF_TOP_MISC_ON */
245+
{0x81040000, 0x120000, 0x1000}, /* WF_MCU_CFG_ON */
246+
{0x81050000, 0x121000, 0x1000}, /* WF_MCU_EINT */
247+
{0x81060000, 0x122000, 0x1000}, /* WF_MCU_GPT */
248+
{0x81070000, 0x123000, 0x1000}, /* WF_MCU_WDT */
249+
{0x80010000, 0x124000, 0x1000}, /* WF_AXIDMA */
250+
{0x7c020000, 0xd0000, 0x10000}, /* CONN_INFRA, wfdma for from CODA flow use */
251+
{0x7c060000, 0xe0000, 0x10000}, /* CONN_INFRA, conn_host_csr_top for from CODA flow use */
252+
{0x20020000, 0xd0000, 0x10000}, /* CONN_INFRA, wfdma */
253+
{0x20060000, 0xe0000, 0x10000}, /* CONN_INFRA, conn_host_csr_top */
254+
{0x7c000000, 0xf0000, 0x10000}, /* CONN_INFRA */
255+
{0x70020000, 0x1f0000, 0x9000}, /* PCIE remapping (AP2CONN) */
256+
{0x0, 0x0, 0x0}, /* imply end of search */
257+
};
258+
138259
static u32 mt7996_reg_map_l1(struct mt7996_dev *dev, u32 addr)
139260
{
140261
u32 offset = FIELD_GET(MT_HIF_REMAP_L1_OFFSET, addr);
141262
u32 base = FIELD_GET(MT_HIF_REMAP_L1_BASE, addr);
263+
u32 l1_mask, val;
264+
265+
if (is_mt7996(&dev->mt76)) {
266+
l1_mask = MT_HIF_REMAP_L1_MASK_7996;
267+
val = FIELD_PREP(MT_HIF_REMAP_L1_MASK_7996, base);
268+
} else {
269+
l1_mask = MT_HIF_REMAP_L1_MASK;
270+
val = FIELD_PREP(MT_HIF_REMAP_L1_MASK, base);
271+
}
142272

143-
dev->bus_ops->rmw(&dev->mt76, MT_HIF_REMAP_L1,
144-
MT_HIF_REMAP_L1_MASK,
145-
FIELD_PREP(MT_HIF_REMAP_L1_MASK, base));
273+
dev->bus_ops->rmw(&dev->mt76, MT_HIF_REMAP_L1, l1_mask, val);
146274
/* use read to push write */
147275
dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L1);
148276

@@ -151,18 +279,41 @@ static u32 mt7996_reg_map_l1(struct mt7996_dev *dev, u32 addr)
151279

152280
static u32 mt7996_reg_map_l2(struct mt7996_dev *dev, u32 addr)
153281
{
154-
u32 offset = FIELD_GET(MT_HIF_REMAP_L2_OFFSET, addr);
155-
u32 base = FIELD_GET(MT_HIF_REMAP_L2_BASE, addr);
282+
u32 offset, base, l2_mask, val;
156283

157-
dev->bus_ops->rmw(&dev->mt76, MT_HIF_REMAP_L2,
158-
MT_HIF_REMAP_L2_MASK,
159-
FIELD_PREP(MT_HIF_REMAP_L2_MASK, base));
284+
if (is_mt7990(&dev->mt76)) {
285+
offset = FIELD_GET(MT_HIF_REMAP_L2_OFFSET_7990, addr);
286+
base = FIELD_GET(MT_HIF_REMAP_L2_BASE_7990, addr);
287+
l2_mask = MT_HIF_REMAP_L2_MASK_7990;
288+
val = FIELD_PREP(MT_HIF_REMAP_L2_MASK_7990, base);
289+
} else {
290+
offset = FIELD_GET(MT_HIF_REMAP_L2_OFFSET, addr);
291+
base = FIELD_GET(MT_HIF_REMAP_L2_BASE, addr);
292+
l2_mask = MT_HIF_REMAP_L2_MASK;
293+
val = FIELD_PREP(MT_HIF_REMAP_L2_MASK, base);
294+
}
295+
296+
dev->bus_ops->rmw(&dev->mt76, MT_HIF_REMAP_L2, l2_mask, val);
160297
/* use read to push write */
161298
dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L2);
162299

163300
return MT_HIF_REMAP_BASE_L2 + offset;
164301
}
165302

303+
static u32 mt7996_reg_map_cbtop(struct mt7996_dev *dev, u32 addr)
304+
{
305+
u32 offset = FIELD_GET(MT_HIF_REMAP_CBTOP_OFFSET, addr);
306+
u32 base = FIELD_GET(MT_HIF_REMAP_CBTOP_BASE, addr);
307+
308+
dev->bus_ops->rmw(&dev->mt76, MT_HIF_REMAP_CBTOP,
309+
MT_HIF_REMAP_CBTOP_MASK,
310+
FIELD_PREP(MT_HIF_REMAP_CBTOP_MASK, base));
311+
/* use read to push write */
312+
dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_CBTOP);
313+
314+
return MT_HIF_REMAP_BASE_CBTOP + offset;
315+
}
316+
166317
static u32 __mt7996_reg_addr(struct mt7996_dev *dev, u32 addr)
167318
{
168319
int i;
@@ -193,17 +344,20 @@ static u32 __mt7996_reg_remap_addr(struct mt7996_dev *dev, u32 addr)
193344
(addr >= MT_WFSYS1_PHY_START && addr <= MT_WFSYS1_PHY_END))
194345
return mt7996_reg_map_l1(dev, addr);
195346

196-
if (dev_is_pci(dev->mt76.dev) &&
197-
((addr >= MT_CBTOP1_PHY_START && addr <= MT_CBTOP1_PHY_END) ||
198-
addr >= MT_CBTOP2_PHY_START))
199-
return mt7996_reg_map_l1(dev, addr);
200-
201347
/* CONN_INFRA: covert to phyiscal addr and use layer 1 remap */
202348
if (addr >= MT_INFRA_MCU_START && addr <= MT_INFRA_MCU_END) {
203349
addr = addr - MT_INFRA_MCU_START + MT_INFRA_BASE;
204350
return mt7996_reg_map_l1(dev, addr);
205351
}
206352

353+
if (dev_is_pci(dev->mt76.dev) &&
354+
((addr >= MT_CBTOP1_PHY_START && addr <= MT_CBTOP1_PHY_END) ||
355+
addr >= MT_CBTOP2_PHY_START)) {
356+
if (is_mt7990(&dev->mt76))
357+
return mt7996_reg_map_cbtop(dev, addr);
358+
return mt7996_reg_map_l1(dev, addr);
359+
}
360+
207361
return mt7996_reg_map_l2(dev, addr);
208362
}
209363

@@ -455,6 +609,12 @@ static int mt7996_mmio_init(struct mt76_dev *mdev,
455609
dev->reg.map = mt7996_reg_map;
456610
dev->reg.map_size = ARRAY_SIZE(mt7996_reg_map);
457611
break;
612+
case MT7990_DEVICE_ID:
613+
dev->reg.base = mt7996_reg_base;
614+
dev->reg.offs_rev = mt7990_offs;
615+
dev->reg.map = mt7990_reg_map;
616+
dev->reg.map_size = ARRAY_SIZE(mt7990_reg_map);
617+
break;
458618
default:
459619
return -EINVAL;
460620
}

‎drivers/net/wireless/mediatek/mt76/mt7996/regs.h‎

Lines changed: 35 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -64,6 +64,17 @@ enum offs_rev {
6464
MIB_BSCR7,
6565
MIB_BSCR17,
6666
MIB_TRDR1,
67+
HIF_REMAP_L1,
68+
HIF_REMAP_BASE_L1,
69+
HIF_REMAP_L2,
70+
HIF_REMAP_BASE_L2,
71+
CBTOP1_PHY_END,
72+
INFRA_MCU_END,
73+
WTBLON_WDUCR,
74+
WTBL_UPDATE,
75+
WTBL_ITCR,
76+
WTBL_ITCR0,
77+
WTBL_ITCR1,
6778
__MT_OFFS_MAX,
6879
};
6980

@@ -291,19 +302,19 @@ enum offs_rev {
291302
/* WTBLON TOP */
292303
#define MT_WTBLON_TOP_BASE 0x820d4000
293304
#define MT_WTBLON_TOP(ofs) (MT_WTBLON_TOP_BASE + (ofs))
294-
#define MT_WTBLON_TOP_WDUCR MT_WTBLON_TOP(0x370)
305+
#define MT_WTBLON_TOP_WDUCR MT_WTBLON_TOP(__OFFS(WTBLON_WDUCR))
295306
#define MT_WTBLON_TOP_WDUCR_GROUP GENMASK(4, 0)
296307

297-
#define MT_WTBL_UPDATE MT_WTBLON_TOP(0x380)
308+
#define MT_WTBL_UPDATE MT_WTBLON_TOP(__OFFS(WTBL_UPDATE))
298309
#define MT_WTBL_UPDATE_WLAN_IDX GENMASK(11, 0)
299310
#define MT_WTBL_UPDATE_ADM_COUNT_CLEAR BIT(14)
300311
#define MT_WTBL_UPDATE_BUSY BIT(31)
301312

302-
#define MT_WTBL_ITCR MT_WTBLON_TOP(0x3b0)
313+
#define MT_WTBL_ITCR MT_WTBLON_TOP(__OFFS(WTBL_ITCR))
303314
#define MT_WTBL_ITCR_WR BIT(16)
304315
#define MT_WTBL_ITCR_EXEC BIT(31)
305-
#define MT_WTBL_ITDR0 MT_WTBLON_TOP(0x3b8)
306-
#define MT_WTBL_ITDR1 MT_WTBLON_TOP(0x3bc)
316+
#define MT_WTBL_ITDR0 MT_WTBLON_TOP(__OFFS(WTBL_ITCR0))
317+
#define MT_WTBL_ITDR1 MT_WTBLON_TOP(__OFFS(WTBL_ITCR1))
307318
#define MT_WTBL_SPE_IDX_SEL BIT(6)
308319

309320
/* WTBL */
@@ -578,27 +589,39 @@ enum offs_rev {
578589
#define MT_MCU_CMD_WDT_MASK GENMASK(31, 30)
579590

580591
/* l1/l2 remap */
581-
#define MT_HIF_REMAP_L1 0x155024
582-
#define MT_HIF_REMAP_L1_MASK GENMASK(31, 16)
592+
#define CONN_BUS_CR_VON_BASE 0x155000
593+
#define MT_HIF_REMAP_L1 (CONN_BUS_CR_VON_BASE + __OFFS(HIF_REMAP_L1))
594+
#define MT_HIF_REMAP_L1_MASK_7996 GENMASK(31, 16)
595+
#define MT_HIF_REMAP_L1_MASK GENMASK(15, 0)
583596
#define MT_HIF_REMAP_L1_OFFSET GENMASK(15, 0)
584597
#define MT_HIF_REMAP_L1_BASE GENMASK(31, 16)
585-
#define MT_HIF_REMAP_BASE_L1 0x130000
598+
#define MT_HIF_REMAP_BASE_L1 __OFFS(HIF_REMAP_BASE_L1)
586599

587-
#define MT_HIF_REMAP_L2 0x1b4
600+
#define MT_HIF_REMAP_L2 __OFFS(HIF_REMAP_L2)
588601
#define MT_HIF_REMAP_L2_MASK GENMASK(19, 0)
589602
#define MT_HIF_REMAP_L2_OFFSET GENMASK(11, 0)
590603
#define MT_HIF_REMAP_L2_BASE GENMASK(31, 12)
591-
#define MT_HIF_REMAP_BASE_L2 0x1000
604+
#define MT_HIF_REMAP_L2_MASK_7990 GENMASK(15, 0)
605+
#define MT_HIF_REMAP_L2_OFFSET_7990 GENMASK(15, 0)
606+
#define MT_HIF_REMAP_L2_BASE_7990 GENMASK(31, 16)
607+
#define MT_HIF_REMAP_BASE_L2 __OFFS(HIF_REMAP_BASE_L2)
608+
609+
/* for mt7990 only */
610+
#define MT_HIF_REMAP_CBTOP 0x1f6554
611+
#define MT_HIF_REMAP_CBTOP_MASK GENMASK(15, 0)
612+
#define MT_HIF_REMAP_CBTOP_OFFSET GENMASK(15, 0)
613+
#define MT_HIF_REMAP_CBTOP_BASE GENMASK(31, 16)
614+
#define MT_HIF_REMAP_BASE_CBTOP 0x1c0000
592615

593616
#define MT_INFRA_BASE 0x18000000
594617
#define MT_WFSYS0_PHY_START 0x18400000
595618
#define MT_WFSYS1_PHY_START 0x18800000
596619
#define MT_WFSYS1_PHY_END 0x18bfffff
597620
#define MT_CBTOP1_PHY_START 0x70000000
598-
#define MT_CBTOP1_PHY_END 0x77ffffff
621+
#define MT_CBTOP1_PHY_END __OFFS(CBTOP1_PHY_END)
599622
#define MT_CBTOP2_PHY_START 0xf0000000
600623
#define MT_INFRA_MCU_START 0x7c000000
601-
#define MT_INFRA_MCU_END 0x7c3fffff
624+
#define MT_INFRA_MCU_END __OFFS(INFRA_MCU_END)
602625

603626
/* FW MODE SYNC */
604627
#define MT_FW_ASSERT_CNT 0x02208274

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