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seehearfeelgregkh
seehearfeel
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gregkh
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LoongArch: Change 8 to 14 for LOONGARCH_MAX_{BRP,WRP}
commit f502ea6 upstream. The maximum number of load/store watchpoints and fetch instruction watchpoints is 14 each according to LoongArch Reference Manual, so change 8 to 14 for the related code. Link: https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html#control-and-status-registers-related-to-watchpoints Cc: stable@vger.kernel.org Fixes: edffa33 ("LoongArch: Add hardware breakpoints/watchpoints support") Reviewed-by: WANG Xuerui <git@xen0n.name> Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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‎arch/loongarch/include/asm/hw_breakpoint.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -38,8 +38,8 @@ struct arch_hw_breakpoint {
3838
* Limits.
3939
* Changing these will require modifications to the register accessors.
4040
*/
41-
#define LOONGARCH_MAX_BRP 8
42-
#define LOONGARCH_MAX_WRP 8
41+
#define LOONGARCH_MAX_BRP 14
42+
#define LOONGARCH_MAX_WRP 14
4343

4444
/* Virtual debug register bases. */
4545
#define CSR_CFG_ADDR 0

‎arch/loongarch/include/asm/loongarch.h

Lines changed: 60 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -959,6 +959,36 @@
959959
#define LOONGARCH_CSR_DB7CTRL 0x34a /* data breakpoint 7 control */
960960
#define LOONGARCH_CSR_DB7ASID 0x34b /* data breakpoint 7 asid */
961961

962+
#define LOONGARCH_CSR_DB8ADDR 0x350 /* data breakpoint 8 address */
963+
#define LOONGARCH_CSR_DB8MASK 0x351 /* data breakpoint 8 mask */
964+
#define LOONGARCH_CSR_DB8CTRL 0x352 /* data breakpoint 8 control */
965+
#define LOONGARCH_CSR_DB8ASID 0x353 /* data breakpoint 8 asid */
966+
967+
#define LOONGARCH_CSR_DB9ADDR 0x358 /* data breakpoint 9 address */
968+
#define LOONGARCH_CSR_DB9MASK 0x359 /* data breakpoint 9 mask */
969+
#define LOONGARCH_CSR_DB9CTRL 0x35a /* data breakpoint 9 control */
970+
#define LOONGARCH_CSR_DB9ASID 0x35b /* data breakpoint 9 asid */
971+
972+
#define LOONGARCH_CSR_DB10ADDR 0x360 /* data breakpoint 10 address */
973+
#define LOONGARCH_CSR_DB10MASK 0x361 /* data breakpoint 10 mask */
974+
#define LOONGARCH_CSR_DB10CTRL 0x362 /* data breakpoint 10 control */
975+
#define LOONGARCH_CSR_DB10ASID 0x363 /* data breakpoint 10 asid */
976+
977+
#define LOONGARCH_CSR_DB11ADDR 0x368 /* data breakpoint 11 address */
978+
#define LOONGARCH_CSR_DB11MASK 0x369 /* data breakpoint 11 mask */
979+
#define LOONGARCH_CSR_DB11CTRL 0x36a /* data breakpoint 11 control */
980+
#define LOONGARCH_CSR_DB11ASID 0x36b /* data breakpoint 11 asid */
981+
982+
#define LOONGARCH_CSR_DB12ADDR 0x370 /* data breakpoint 12 address */
983+
#define LOONGARCH_CSR_DB12MASK 0x371 /* data breakpoint 12 mask */
984+
#define LOONGARCH_CSR_DB12CTRL 0x372 /* data breakpoint 12 control */
985+
#define LOONGARCH_CSR_DB12ASID 0x373 /* data breakpoint 12 asid */
986+
987+
#define LOONGARCH_CSR_DB13ADDR 0x378 /* data breakpoint 13 address */
988+
#define LOONGARCH_CSR_DB13MASK 0x379 /* data breakpoint 13 mask */
989+
#define LOONGARCH_CSR_DB13CTRL 0x37a /* data breakpoint 13 control */
990+
#define LOONGARCH_CSR_DB13ASID 0x37b /* data breakpoint 13 asid */
991+
962992
#define LOONGARCH_CSR_FWPC 0x380 /* instruction breakpoint config */
963993
#define LOONGARCH_CSR_FWPS 0x381 /* instruction breakpoint status */
964994

@@ -1002,6 +1032,36 @@
10021032
#define LOONGARCH_CSR_IB7CTRL 0x3ca /* inst breakpoint 7 control */
10031033
#define LOONGARCH_CSR_IB7ASID 0x3cb /* inst breakpoint 7 asid */
10041034

1035+
#define LOONGARCH_CSR_IB8ADDR 0x3d0 /* inst breakpoint 8 address */
1036+
#define LOONGARCH_CSR_IB8MASK 0x3d1 /* inst breakpoint 8 mask */
1037+
#define LOONGARCH_CSR_IB8CTRL 0x3d2 /* inst breakpoint 8 control */
1038+
#define LOONGARCH_CSR_IB8ASID 0x3d3 /* inst breakpoint 8 asid */
1039+
1040+
#define LOONGARCH_CSR_IB9ADDR 0x3d8 /* inst breakpoint 9 address */
1041+
#define LOONGARCH_CSR_IB9MASK 0x3d9 /* inst breakpoint 9 mask */
1042+
#define LOONGARCH_CSR_IB9CTRL 0x3da /* inst breakpoint 9 control */
1043+
#define LOONGARCH_CSR_IB9ASID 0x3db /* inst breakpoint 9 asid */
1044+
1045+
#define LOONGARCH_CSR_IB10ADDR 0x3e0 /* inst breakpoint 10 address */
1046+
#define LOONGARCH_CSR_IB10MASK 0x3e1 /* inst breakpoint 10 mask */
1047+
#define LOONGARCH_CSR_IB10CTRL 0x3e2 /* inst breakpoint 10 control */
1048+
#define LOONGARCH_CSR_IB10ASID 0x3e3 /* inst breakpoint 10 asid */
1049+
1050+
#define LOONGARCH_CSR_IB11ADDR 0x3e8 /* inst breakpoint 11 address */
1051+
#define LOONGARCH_CSR_IB11MASK 0x3e9 /* inst breakpoint 11 mask */
1052+
#define LOONGARCH_CSR_IB11CTRL 0x3ea /* inst breakpoint 11 control */
1053+
#define LOONGARCH_CSR_IB11ASID 0x3eb /* inst breakpoint 11 asid */
1054+
1055+
#define LOONGARCH_CSR_IB12ADDR 0x3f0 /* inst breakpoint 12 address */
1056+
#define LOONGARCH_CSR_IB12MASK 0x3f1 /* inst breakpoint 12 mask */
1057+
#define LOONGARCH_CSR_IB12CTRL 0x3f2 /* inst breakpoint 12 control */
1058+
#define LOONGARCH_CSR_IB12ASID 0x3f3 /* inst breakpoint 12 asid */
1059+
1060+
#define LOONGARCH_CSR_IB13ADDR 0x3f8 /* inst breakpoint 13 address */
1061+
#define LOONGARCH_CSR_IB13MASK 0x3f9 /* inst breakpoint 13 mask */
1062+
#define LOONGARCH_CSR_IB13CTRL 0x3fa /* inst breakpoint 13 control */
1063+
#define LOONGARCH_CSR_IB13ASID 0x3fb /* inst breakpoint 13 asid */
1064+
10051065
#define LOONGARCH_CSR_DEBUG 0x500 /* debug config */
10061066
#define LOONGARCH_CSR_DERA 0x501 /* debug era */
10071067
#define LOONGARCH_CSR_DESAVE 0x502 /* debug save */

‎arch/loongarch/kernel/hw_breakpoint.c

Lines changed: 14 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -51,7 +51,13 @@ int hw_breakpoint_slots(int type)
5151
READ_WB_REG_CASE(OFF, 4, REG, T, VAL); \
5252
READ_WB_REG_CASE(OFF, 5, REG, T, VAL); \
5353
READ_WB_REG_CASE(OFF, 6, REG, T, VAL); \
54-
READ_WB_REG_CASE(OFF, 7, REG, T, VAL);
54+
READ_WB_REG_CASE(OFF, 7, REG, T, VAL); \
55+
READ_WB_REG_CASE(OFF, 8, REG, T, VAL); \
56+
READ_WB_REG_CASE(OFF, 9, REG, T, VAL); \
57+
READ_WB_REG_CASE(OFF, 10, REG, T, VAL); \
58+
READ_WB_REG_CASE(OFF, 11, REG, T, VAL); \
59+
READ_WB_REG_CASE(OFF, 12, REG, T, VAL); \
60+
READ_WB_REG_CASE(OFF, 13, REG, T, VAL);
5561

5662
#define GEN_WRITE_WB_REG_CASES(OFF, REG, T, VAL) \
5763
WRITE_WB_REG_CASE(OFF, 0, REG, T, VAL); \
@@ -61,7 +67,13 @@ int hw_breakpoint_slots(int type)
6167
WRITE_WB_REG_CASE(OFF, 4, REG, T, VAL); \
6268
WRITE_WB_REG_CASE(OFF, 5, REG, T, VAL); \
6369
WRITE_WB_REG_CASE(OFF, 6, REG, T, VAL); \
64-
WRITE_WB_REG_CASE(OFF, 7, REG, T, VAL);
70+
WRITE_WB_REG_CASE(OFF, 7, REG, T, VAL); \
71+
WRITE_WB_REG_CASE(OFF, 8, REG, T, VAL); \
72+
WRITE_WB_REG_CASE(OFF, 9, REG, T, VAL); \
73+
WRITE_WB_REG_CASE(OFF, 10, REG, T, VAL); \
74+
WRITE_WB_REG_CASE(OFF, 11, REG, T, VAL); \
75+
WRITE_WB_REG_CASE(OFF, 12, REG, T, VAL); \
76+
WRITE_WB_REG_CASE(OFF, 13, REG, T, VAL);
6577

6678
static u64 read_wb_reg(int reg, int n, int t)
6779
{

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