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altairz80_cpu.c
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/* altairz80_cpu.c: MITS Altair CPU (8080 and Z80)
Copyright (c) 2002-2023, Peter Schorn
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
PETER SCHORN BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
Except as contained in this notice, the name of Peter Schorn shall not
be used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Peter Schorn.
Based on work by Charles E Owen (c) 1997
Code for Z80 CPU from Frank D. Cringle ((c) 1995 under GNU license)
*/
#include "m68k/m68k.h"
#define SWITCHCPU_DEFAULT 0xfd
/* Debug flags */
#define IN_MSG (1 << 0)
#define OUT_MSG (1 << 1)
#define INT_MSG (1 << 2)
#define PCQ_SIZE 64 /* must be 2**n */
#define PCQ_SIZE_LOG2 6 /* log2 of PCQ_SIZE */
#define PCQ_MASK (PCQ_SIZE - 1)
#define PCQ_ENTRY(PC) if (pcq[pcq_p] != (PC)) { pcq[pcq_p = (pcq_p - 1) & PCQ_MASK] = (PC); }
#define INST_MAX_BYTES 4 /* instruction max bytes */
#define IFF1 1 /* Interrupt flip-flop 1 */
#define IFF2 2 /* Interrupt flip-flop 2 */
#define FLAG_C 1
#define FLAG_N 2
#define FLAG_P 4
#define FLAG_H 16
#define FLAG_Z 64
#define FLAG_S 128
#define SETFLAG(f,c) AF = (c) ? AF | FLAG_ ## f : AF & ~FLAG_ ## f
#define TSTFLAG(f) ((AF & FLAG_ ## f) != 0)
#define TSTFLAG2(a, f) ((a & FLAG_ ## f) != 0)
#define LOW_DIGIT(x) ((x) & 0xf)
#define HIGH_DIGIT(x) (((x) >> 4) & 0xf)
#define LOW_REGISTER(x) ((x) & 0xff)
#define HIGH_REGISTER(x) (((x) >> 8) & 0xff)
#define SET_LOW_REGISTER(x, v) x = (((x) & 0xff00) | ((v) & 0xff))
#define SET_HIGH_REGISTER(x, v) x = (((x) & 0xff) | (((v) & 0xff) << 8))
#define PARITY(x) parityTable[(x) & 0xff]
/* SET_PV and SET_PV2 are used to provide correct PARITY flag semantics for the 8080 in cases
where the Z80 uses the overflow flag
*/
#define SET_PVS(s) ((chiptype == CHIP_TYPE_Z80) ? (((cbits >> 6) ^ (cbits >> 5)) & 4) : (PARITY(s)))
#define SET_PV (SET_PVS(sum))
#define SET_PV2(x) ((chiptype == CHIP_TYPE_Z80) ? (((temp == (x)) << 2)) : (PARITY(temp)))
/* CHECK_CPU_8080 must be invoked whenever a Z80 only instruction is executed
In case a Z80 instruction is executed on an 8080 the following two cases exist:
1) Trapping is enabled: execution stops
2) Trapping is not enabled: decoding continues with the next byte, i.e. interpret as NOP
Note: in some cases different instructions need to be chosen on 8080
*/
#define CHECK_CPU_8080 \
if ((chiptype == CHIP_TYPE_8080) && (cpu_unit.flags & UNIT_CPU_OPSTOP)) { \
reason = STOP_OPCODE; \
goto end_decode; \
}
/* CHECK_CPU_Z80 must be invoked whenever a non Z80 instruction is executed */
#define CHECK_CPU_Z80 \
if (cpu_unit.flags & UNIT_CPU_OPSTOP) { \
reason = STOP_OPCODE; \
goto end_decode; \
}
#define POP(x) { \
register uint32 y = RAM_PP(SP); \
x = y + (RAM_PP(SP) << 8); \
}
#define JPC(cond) { \
tStates += 10; \
if (cond) { \
PCQ_ENTRY(PCX); \
PC = GET_WORD(PC); \
} else { \
PC += 2; \
} \
}
#define CALLC(cond) { \
if (cond) { \
register uint32 adrr = GET_WORD(PC); \
CHECK_BREAK_WORD(SP - 2); \
PUSH(PC + 2); \
PCQ_ENTRY(PCX); \
PC = adrr; \
tStates += 17; \
} else { \
PC += 2; \
tStates += (chiptype == CHIP_TYPE_8080 ? 11 : 10); \
} \
}
/* increase R by val */
#define INCR(val) IR_S = (IR_S & ~0x7f) | ((IR_S + (val)) & 0x7f)
extern int32 sio0s (const int32 port, const int32 io, const int32 data);
extern int32 sio0d (const int32 port, const int32 io, const int32 data);
extern int32 sio1s (const int32 port, const int32 io, const int32 data);
extern int32 sio1d (const int32 port, const int32 io, const int32 data);
extern int32 dsk10 (const int32 port, const int32 io, const int32 data);
extern int32 dsk11 (const int32 port, const int32 io, const int32 data);
extern int32 dsk12 (const int32 port, const int32 io, const int32 data);
extern int32 netStatus (const int32 port, const int32 io, const int32 data);
extern int32 netData (const int32 port, const int32 io, const int32 data);
extern int32 nulldev (const int32 port, const int32 io, const int32 data);
extern int32 hdsk_io (const int32 port, const int32 io, const int32 data);
extern int32 simh_dev (const int32 port, const int32 io, const int32 data);
extern int32 sr_dev (const int32 port, const int32 io, const int32 data);
extern void install_ALTAIRbootROM(void);
extern void do_SIMH_sleep(void);
extern void prepareMemoryAccessMessage(const t_addr loc);
extern void prepareInstructionMessage(const t_addr loc, const uint32 op);
extern t_stat sim_instr_nommu(void);
extern uint8 MOPT[MAXBANKSIZE];
extern t_stat sim_instr_8086(void);
extern void cpu8086reset(void);
extern unsigned int m68k_cpu_read_byte_raw(unsigned int address);
void m68k_cpu_write_byte_raw(unsigned int address, unsigned int value);
/* function prototypes */
static t_stat cpu_set_switcher (UNIT *uptr, int32 value, CONST char *cptr, void *desc);
static t_stat cpu_reset_switcher(UNIT *uptr, int32 value, CONST char *cptr, void *desc);
static t_stat cpu_show_switcher (FILE *st, UNIT *uptr, int32 val, CONST void *desc);
static int32 switchcpu_io (const int32 port, const int32 io, CONST int32 data);
static t_stat cpu_set_altairrom (UNIT *uptr, int32 value, CONST char *cptr, void *desc);
static t_stat cpu_set_noaltairrom (UNIT *uptr, int32 value, CONST char *cptr, void *desc);
static t_stat cpu_set_nommu (UNIT *uptr, int32 value, CONST char *cptr, void *desc);
static t_stat cpu_set_banked (UNIT *uptr, int32 value, CONST char *cptr, void *desc);
static t_stat cpu_set_nonbanked (UNIT *uptr, int32 value, CONST char *cptr, void *desc);
static t_stat cpu_set_ramtype (UNIT *uptr, int32 value, CONST char *cptr, void *desc);
static t_stat cpu_set_chiptype (UNIT *uptr, int32 value, CONST char *cptr, void *desc);
static t_stat cpu_set_size (UNIT *uptr, int32 value, CONST char *cptr, void *desc);
static t_stat m68k_set_chiptype (UNIT * uptr, int32 value, CONST char* cptr, void* desc);
static t_stat cpu_set_memory (UNIT *uptr, int32 value, CONST char *cptr, void *desc);
static t_stat cpu_set_hist (UNIT *uptr, int32 val, CONST char *cptr, void *desc);
static t_stat cpu_show_hist (FILE *st, UNIT *uptr, int32 val, CONST void *desc);
static t_stat cpu_clear_command (UNIT *uptr, int32 value, CONST char *cptr, void *desc);
static void cpu_clear(void);
static t_stat cpu_show (FILE *st, UNIT *uptr, int32 val, CONST void *desc);
static t_stat chip_show (FILE *st, UNIT *uptr, int32 val, CONST void *desc);
static t_stat cpu_ex(t_value *vptr, t_addr addr, UNIT *uptr, int32 sw);
static t_stat cpu_dep(t_value val, t_addr addr, UNIT *uptr, int32 sw);
static t_stat cpu_reset(DEVICE *dptr);
static t_bool cpu_is_pc_a_subroutine_call (t_addr **ret_addrs);
static t_stat cpu_hex_load(FILE *fileref, CONST char *cptr, CONST char *fnam, int flag);
static t_stat sim_instr_mmu(void);
static uint32 GetBYTE(register uint32 Addr);
static void PutWORD(register uint32 Addr, const register uint32 Value);
static void PutBYTE(register uint32 Addr, const register uint32 Value);
static const char* cpu_description(DEVICE *dptr);
static t_stat cpu_cmd_memory(int32 flag, CONST char *cptr);
static t_stat cpu_cmd_reg(int32 flag, CONST char *cptr);
void out(const uint32 Port, const uint32 Value);
uint32 in(const uint32 Port);
void altairz80_init(void);
t_stat sim_instr(void);
t_stat install_bootrom(const int32 bootrom[], const int32 size, const int32 addr, const int32 makeROM);
uint8 GetBYTEWrapper(const uint32 Addr);
void PutBYTEWrapper(const uint32 Addr, const uint32 Value);
uint8 GetByteDMA(const uint32 Addr);
void PutByteDMA(const uint32 Addr, const uint32 Value);
int32 getBankSelect(void);
void setBankSelect(const int32 b);
uint32 getClockFrequency(void);
void setClockFrequency(const uint32 Value);
uint32 getCommon(void);
uint32 sim_map_resource(uint32 baseaddr, uint32 size, uint32 resource_type,
int32 (*routine)(const int32, const int32, const int32), const char* name, uint8 unmap);
void PutBYTEExtended(register uint32 Addr, const register uint32 Value);
uint32 GetBYTEExtended(register uint32 Addr);
void cpu_raise_interrupt(uint32 irq);
const char* handlerNameForPort(const int32 port);
/* CPU data structures
cpu_dev CPU device descriptor
cpu_unit CPU unit descriptor
cpu_reg CPU register list
cpu_mod CPU modifiers list
*/
UNIT cpu_unit = {
UDATA (NULL, UNIT_FIX | UNIT_BINK | UNIT_CPU_ALTAIRROM |
UNIT_CPU_STOPONHALT | UNIT_CPU_MMU, MAXBANKSIZE)
};
uint32 PCX = 0; /* external view of PC */
int32 AF_S; /* AF register */
int32 BC_S; /* BC register */
int32 DE_S; /* DE register */
int32 HL_S; /* HL register */
int32 IX_S; /* IX register */
int32 IY_S; /* IY register */
int32 PC_S = 0; /* 8080 / Z80 program counter */
int32 PCX_S = 0xFFFF0; /* 8086 program counter */
int32 SP_S; /* SP register */
int32 AF1_S; /* alternate AF register */
int32 BC1_S; /* alternate BC register */
int32 DE1_S; /* alternate DE register */
int32 HL1_S; /* alternate HL register */
int32 IFF_S; /* Interrupt Flip Flop */
int32 IM_S; /* Interrupt Mode register */
int32 IR_S; /* Interrupt (upper) / Refresh (lower) register */
int32 AX_S; /* AX register (8086) */
int32 BX_S; /* BX register (8086) */
int32 CX_S; /* CX register (8086) */
int32 DX_S; /* DX register (8086) */
int32 CS_S; /* CS register (8086) */
int32 DS_S; /* DS register (8086) */
int32 ES_S; /* ES register (8086) */
int32 SS_S; /* SS register (8086) */
int32 DI_S; /* DI register (8086) */
int32 SI_S; /* SI register (8086) */
int32 BP_S; /* BP register (8086) */
int32 SPX_S; /* SP register (8086) */
int32 IP_S; /* IP register (8086) */
int32 FLAGS_S; /* flags register (8086) */
int32 SR = 0; /* switch register */
uint32 nmiInterrupt = 0; /* Non-maskable Interrupt */
uint32 vectorInterrupt = 0; /* VI0-7 Vector Interrupt bitfield */
uint8 dataBus[MAX_INT_VECTORS]; /* Vector Interrupt data bus value */
static int32 bankSelect = 0; /* determines selected memory bank */
static uint32 common = 0xc000; /* addresses >= 'common' are in common memory */
static uint32 common_low = 0; /* Common area is in low memory */
static uint32 previousCapacity = MAXBANKSIZE; /* safe for previous memory capacity */
static uint32 clockFrequency = 0; /* in kHz, 0 means as fast as possible */
static uint32 sliceLength = 10; /* length of time-slice for CPU speed */
/* adjustment in milliseconds */
static uint32 executedTStates = 0; /* executed t-states */
static uint16 pcq[PCQ_SIZE] = { 0 }; /* PC queue */
static int32 pcq_p = 0; /* PC queue ptr */
static REG *pcq_r = NULL; /* PC queue reg ptr */
#define HIST_MIN 16
#define HIST_MAX 8192
typedef struct {
uint8 valid;
uint16 af;
uint16 bc;
uint16 de;
uint16 hl;
t_addr pc;
t_addr sp;
uint16 af1;
uint16 bc1;
uint16 de1;
uint16 hl1;
uint16 ix;
uint16 iy;
t_value op[INST_MAX_BYTES];
} insthist_t;
static uint32 hst_p = 0; /* history pointer */
static uint32 hst_lnt = 0; /* history length */
static insthist_t *hst = NULL; /* instruction history */
uint32 m68k_registers[M68K_REG_CPU_TYPE + 1]; /* M68K CPU registers */
uint32 mmiobase = 0xff0000; /* M68K MMIO base address */
uint32 mmiosize = 0x10000; /* M68K MMIO window size */
uint32 m68kvariant = M68K_CPU_TYPE_68000;
/* data structure for IN/OUT instructions */
struct idev {
int32 (*routine)(const int32, const int32, const int32);
const char* name;
};
static int32 switcherPort = SWITCHCPU_DEFAULT;
static struct idev oldSwitcherDevice = { NULL, NULL };
// CPU_INDEX_8080 is defined in altairz80_defs.h
#define CPU_INDEX_8086 27
#define CPU_INDEX_M68K 54
REG cpu_reg[] = {
// 8080 and Z80 registers
{ HRDATAD (AF, AF_S, 16, "8080 / Z80 Accumulator Flag register")
}, /* 0 */
{ HRDATAD (BC, BC_S, 16, "8080 / Z80 BC register")
}, /* 1 */
{ HRDATAD (DE, DE_S, 16, "8080 / Z80 DE register")
}, /* 2 */
{ HRDATAD (HL, HL_S, 16, "8080 / Z80 HL register")
}, /* 3 */
{ HRDATAD (PC, PC_S, 16 + MAXBANKSLOG2, "8080 / Z80 Program Counter register")
}, /* 4 8080 / Z80 */
{ HRDATAD (SP, SP_S, 16, "8080 / Z80 Stack Pointer register")
}, /* 5 */
// Z80 registers
{ HRDATAD (IX, IX_S, 16, "Z80 IX register")
}, /* 6 */
{ HRDATAD (IY, IY_S, 16, "Z80 IY register")
}, /* 7 */
{ HRDATAD (AF1, AF1_S, 16, "Z80 Alternate Accumulator Flag register")
}, /* 8 */
{ HRDATAD (BC1, BC1_S, 16, "Z80 Alternate BC register")
}, /* 9 */
{ HRDATAD (DE1, DE1_S, 16, "Z80 Alternate DE register")
}, /* 10 */
{ HRDATAD (HL1, HL1_S, 16, "Z80 Alternate HL register")
}, /* 11 */
{ GRDATAD (IFF, IFF_S, 2, 2, 0, "Z80 Interrupt Flip Flop register")
}, /* 12 */
{ HRDATAD (IM, IM_S, 2, "Z80 Interrupt Mode register")
}, /* 13 */
{ HRDATAD (IR, IR_S, 16, "Z80 Interrupt (upper) / Refresh (lower) register")
}, /* 14 */
// 8086 registers
{ HRDATAD (AX, AX_S, 16, "8086 AX register")
}, /* 15 8086 */
{ GRDATAD (AL, AX_S, 16, 8, 0, "8086 low bits of AX register")
}, /* 16 8086, low 8 bits of AX */
{ GRDATAD (AH, AX_S, 16, 8, 8, "8086 high bits of AX register")
}, /* 17 8086, high 8 bits of AX */
{ HRDATAD (BX, BX_S, 16, "8086 BX register")
}, /* 18 8086 */
{ GRDATAD (BL, BX_S, 16, 8, 0, "8086 low bits of BX register")
}, /* 19 8086, low 8 bits of BX */
{ GRDATAD (BH, BX_S, 16, 8, 8, "8086 high bits of BX register")
}, /* 20 8086, high 8 bits of BX */
{ HRDATAD (CX, CX_S, 16, "8086 CX register")
}, /* 21 8086 */
{ GRDATAD (CL, CX_S, 16, 8, 0, "8086 low bits of CX register")
}, /* 22 8086, low 8 bits of CX */
{ GRDATAD (CH, CX_S, 16, 8, 8, "8086 high bits of CX register")
}, /* 23 8086, high 8 bits of CX */
{ HRDATAD (DX, DX_S, 16, "8086 DX register")
}, /* 24 8086 */
{ GRDATAD (DL, DX_S, 16, 8, 0, "8086 low bits of DX register")
}, /* 25 8086, low 8 bits of DX */
{ GRDATAD (DH, DX_S, 16, 8, 8, "8086 high bits of DX register")
}, /* 26 8086, high 8 bits of DX */
{ HRDATAD (PCX, PCX_S, 16 + MAXBANKSLOG2, "8086 Program Counter register")
}, /* 27 8086, Program Counter */
{ HRDATAD (SPX, SPX_S, 16, "8086 Stack Pointer register")
}, /* 28 8086, Stack Pointer */
{ HRDATAD (BP, BP_S, 16, "8086 Base Pointer register")
}, /* 29 8086, Base Pointer */
{ HRDATAD (SI, SI_S, 16, "8086 Source Index register")
}, /* 30 8086, Source Index */
{ HRDATAD (DI, DI_S, 16, "8086 Destination Index register")
}, /* 31 8086, Destination Index */
{ HRDATAD (CS, CS_S, 16, "8086 Code Segment register")
}, /* 32 8086, Code Segment */
{ HRDATAD (DS, DS_S, 16, "8086 Data Segment register")
}, /* 33 8086, Data Segment */
{ HRDATAD (ES, ES_S, 16, "8086 Extra Segment register")
}, /* 34 8086, Extra Segment */
{ HRDATAD (SS, SS_S, 16, "8086 Stack Segment register")
}, /* 35 8086, Stack Segment */
{ HRDATAD (FLAGS, FLAGS_S, 16, "8086 Flag register")
}, /* 36 8086, FLAGS */
{ HRDATAD (IP, IP_S, 16, "8086 Instruction Pointer register"),
REG_RO }, /* 37 8086, set via PC */
// M68K registers
{ HRDATAD (M68K_D0, m68k_registers[M68K_REG_D0], 32, "M68K D0 register"),
}, /* 38 M68K, D0 */
{ HRDATAD (M68K_D1, m68k_registers[M68K_REG_D1], 32, "M68K D1 register"),
}, /* 39 M68K, D1 */
{ HRDATAD (M68K_D2, m68k_registers[M68K_REG_D2], 32, "M68K D2 register"),
}, /* 40 M68K, D2 */
{ HRDATAD (M68K_D3, m68k_registers[M68K_REG_D3], 32, "M68K D3 register"),
}, /* 41 M68K, D3 */
{ HRDATAD (M68K_D4, m68k_registers[M68K_REG_D4], 32, "M68K D4 register"),
}, /* 42 M68K, D4 */
{ HRDATAD (M68K_D5, m68k_registers[M68K_REG_D5], 32, "M68K D5 register"),
}, /* 43 M68K, D5 */
{ HRDATAD (M68K_D6, m68k_registers[M68K_REG_D6], 32, "M68K D6 register"),
}, /* 44 M68K, D6 */
{ HRDATAD (M68K_D7, m68k_registers[M68K_REG_D7], 32, "M68K D7 register"),
}, /* 45 M68K, D7 */
{ HRDATAD (M68K_A0, m68k_registers[M68K_REG_A0], 32, "M68K A0 register"),
}, /* 46 M68K, A0 */
{ HRDATAD (M68K_A1, m68k_registers[M68K_REG_A1], 32, "M68K A1 register"),
}, /* 47 M68K, A1 */
{ HRDATAD (M68K_A2, m68k_registers[M68K_REG_A2], 32, "M68K A2 register"),
}, /* 48 M68K, A2 */
{ HRDATAD (M68K_A3, m68k_registers[M68K_REG_A3], 32, "M68K A3 register"),
}, /* 49 M68K, A3 */
{ HRDATAD (M68K_A4, m68k_registers[M68K_REG_A4], 32, "M68K A4 register"),
}, /* 50 M68K, A4 */
{ HRDATAD (M68K_A5, m68k_registers[M68K_REG_A5], 32, "M68K A5 register"),
}, /* 51 M68K, A5 */
{ HRDATAD (M68K_A6, m68k_registers[M68K_REG_A6], 32, "M68K A6 register"),
}, /* 52 M68K, A6 */
{ HRDATAD (M68K_A7, m68k_registers[M68K_REG_A7], 32, "M68K A7 register"),
}, /* 53 M68K, A7 */
{ HRDATAD (M68K_PC, m68k_registers[M68K_REG_PC], 32, "M68K Program Counter register"),
}, /* 54 M68K, PC */
{ HRDATAD (M68K_SR, m68k_registers[M68K_REG_SR], 32, "M68K Status Register"),
}, /* 55 M68K, SR */
{ HRDATAD (M68K_SP, m68k_registers[M68K_REG_SP], 32, "M68K Stack Pointer register"),
}, /* 56 M68K, SP */
{ HRDATAD (M68K_USP, m68k_registers[M68K_REG_USP], 32, "M68K User Stack Pointer register"),
}, /* 57 M68K, USP */
{ HRDATAD (M68K_ISP, m68k_registers[M68K_REG_ISP], 32, "M68K Interrupt Stack Pointer register"),
}, /* 58 M68K, ISP */
{ HRDATAD (M68K_MSP, m68k_registers[M68K_REG_MSP], 32, "M68K Master Stack Pointer register"),
}, /* 59 M68K, MSP */
{ HRDATAD (M68K_SFC, m68k_registers[M68K_REG_SFC], 32, "M68K Source Function Code register"),
}, /* 60 M68K, SFC */
{ HRDATAD (M68K_DFC, m68k_registers[M68K_REG_DFC], 32, "M68K Destination Function Code register"),
}, /* 61 M68K, DFC */
{ HRDATAD (M68K_VBR, m68k_registers[M68K_REG_VBR], 32, "M68K Vector Base Register"),
}, /* 62 M68K, VBR */
{ HRDATAD (M68K_CACR, m68k_registers[M68K_REG_CACR], 32, "M68K Cache Control Register"),
}, /* 63 M68K, CACR */
{ HRDATAD (M68K_CAAR, m68k_registers[M68K_REG_CAAR], 32, "M68K Cache Address Register"),
}, /* 64 M68K, CAAR */
{ HRDATAD (M68K_PREF_ADDR, m68k_registers[M68K_REG_PREF_ADDR], 32, "M68K Last Prefetch Address register"),
}, /* 65 M68K, PREF_ADDR */
{ HRDATAD (M68K_PREF_DATA, m68k_registers[M68K_REG_PREF_DATA], 32, "M68K Last Prefetch Data register"),
}, /* 66 M68K, PREF_DATA */
{ HRDATAD (M68K_PPC, m68k_registers[M68K_REG_PPC], 32, "M68K Previous Program Counter register"),
}, /* 67 M68K, PPC */
{ HRDATAD (M68K_IR, m68k_registers[M68K_REG_IR], 32, "M68K Instruction Register"),
}, /* 68 M68K, IR */
{ HRDATAD (M68K_CPU_TYPE, m68k_registers[M68K_REG_CPU_TYPE], 32, "M68K CPU Type register"),
REG_RO }, /* 69 M68K, CPU_TYPE */
// Pseudo registers
{ FLDATAD (OPSTOP, cpu_unit.flags, UNIT_CPU_V_OPSTOP, "Stop on invalid operation pseudo register"),
REG_HRO }, /* 70 */
{ HRDATAD (SR, SR, 8, "Front panel switches pseudo register"),
}, /* 71 */
{ HRDATAD (BANK, bankSelect, MAXBANKSLOG2, "Active bank pseudo register"),
}, /* 72 */
{ HRDATAD (COMMON, common, 32, "Starting address of common memory pseudo register"),
}, /* 73 */
{ HRDATAD (SWITCHERPORT, switcherPort, 8, "I/O port for CPU switcher pseudo register"),
}, /* 74 */
{ DRDATAD (CLOCK, clockFrequency, 32, "Clock frequency in kHz for 8080 / Z80 pseudo register"),
}, /* 75 */
{ DRDATAD (SLICE, sliceLength, 16, "Length of time slice for 8080 / Z80 pseudo register"),
}, /* 76 */
{ DRDATAD (TSTATES, executedTStates, 32, "Executed t-states for 8080 / Z80 pseudo register"),
REG_RO }, /* 77 */
{ HRDATAD (CAPACITY,cpu_unit.capac, 32, "Size of RAM pseudo register"),
REG_RO }, /* 78 */
{ HRDATAD (PREVCAP, previousCapacity, 32, "Previous size of RAM pseudo register"),
REG_RO }, /* 79 */
{ BRDATAD (PCQ, pcq, 16, 16, PCQ_SIZE, "Program counter circular buffer for 8080 /Z80 pseudo register"),
REG_RO + REG_CIRC }, /* 80 */
{ DRDATAD (PCQP, pcq_p, PCQ_SIZE_LOG2, "Circular buffer head for 8080 / Z80 pseudo register"),
REG_HRO }, /* 81 */
{ HRDATAD (WRU, sim_int_char, 8, "Interrupt character pseudo register"),
}, /* 82 */
{ HRDATAD(COMMONLOW,common_low, 1, "If set, use low memory for common area"),
}, /* 83 */
{ HRDATAD(VECINT,vectorInterrupt, 8, "Vector Interrupt pseudo register"),
}, /* 84 */
{ BRDATAD (DATABUS, dataBus, 16, 8, MAX_INT_VECTORS, "Data bus pseudo register"),
REG_RO + REG_CIRC }, /* 85 */
{ HRDATAD(MMIOBASE, mmiobase, 24, "Base address for 68K Memory-mapped I/O"),
}, /* 86 */
{ HRDATAD(MMIOSIZE, mmiosize, 17, "Size of 68K Memory-mapped I/O window"),
}, /* 87 */
{ DRDATAD(M68KVAR, m68kvariant, 17, "M68K Type (68000, 68010, etc.)"),
}, /* 88 */
{ HRDATAD(NMI, nmiInterrupt, 1, "NMI Interrupt pseudo register"),
}, /* 89 */
{ NULL }
};
static const char* cpu_description(DEVICE *dptr) {
return "Central Processing Unit";
}
static MTAB cpu_mod[] = {
{ MTAB_XTD | MTAB_VDV, CHIP_TYPE_8080, NULL, "8080", &cpu_set_chiptype,
NULL, NULL, "Chooses 8080 CPU"},
{ MTAB_XTD | MTAB_VDV, CHIP_TYPE_Z80, NULL, "Z80", &cpu_set_chiptype,
NULL, NULL, "Chooses Z80 CPU" },
{ MTAB_XTD | MTAB_VDV, CHIP_TYPE_8086, NULL, "8086", &cpu_set_chiptype,
NULL, NULL, "Chooses 8086 CPU" },
{ MTAB_XTD | MTAB_VDV, CHIP_TYPE_M68K, NULL, "M68K", &cpu_set_chiptype,
NULL, NULL, "Chooses M68K CPU" },
{ UNIT_CPU_OPSTOP, UNIT_CPU_OPSTOP, "ITRAP", "ITRAP", NULL, &chip_show,
NULL, "Stop on illegal instruction" },
{ UNIT_CPU_OPSTOP, 0, "NOITRAP", "NOITRAP", NULL, &chip_show,
NULL, "Do not stop on illegal instruction" },
{ UNIT_CPU_STOPONHALT, UNIT_CPU_STOPONHALT,"STOPONHALT", "STOPONHALT", NULL,
NULL, NULL, "Stop on halt instruction" },
{ UNIT_CPU_STOPONHALT, 0, "LOOPONHALT", "LOOPONHALT", NULL,
NULL, NULL, "Enter loop on halt instruction" },
{ UNIT_CPU_BANKED, UNIT_CPU_BANKED, "BANKED", "BANKED", &cpu_set_banked,
NULL, NULL, "Enable banked memory for 8080 / Z80" },
{ UNIT_CPU_BANKED, 0, "NONBANKED", "NONBANKED", &cpu_set_nonbanked,
NULL, NULL, "Disable banked memory for 8080 / Z80" },
{ UNIT_CPU_ALTAIRROM, UNIT_CPU_ALTAIRROM, "ALTAIRROM", "ALTAIRROM", &cpu_set_altairrom,
NULL, NULL, "Enable Altair ROM for 8080 / Z80" },
{ UNIT_CPU_ALTAIRROM, 0, "NOALTAIRROM", "NOALTAIRROM", &cpu_set_noaltairrom,
NULL, NULL, "Disable Altair ROM for 8080 / Z80"},
{ UNIT_CPU_VERBOSE, UNIT_CPU_VERBOSE, "VERBOSE", "VERBOSE", NULL, &cpu_show,
NULL, "Enable verbose messages" },
{ UNIT_CPU_VERBOSE, 0, "QUIET", "QUIET", NULL, NULL,
NULL, "Disable verbose messages" },
{ MTAB_VDV, 0, NULL, "CLEARMEMORY", &cpu_clear_command,
NULL, NULL, "Clears the RAM" },
{ UNIT_CPU_MMU, UNIT_CPU_MMU, "MMU", "MMU", NULL, NULL,
NULL, "Enable the Memory Management Unit for 8080 / Z80" },
{ UNIT_CPU_MMU, 0, "NOMMU", "NOMMU", &cpu_set_nommu,
NULL, NULL, "Disable the Memory Management Unit for 8080 / Z80" },
{ MTAB_XTD | MTAB_VDV, 0, NULL, "MEMORY", &cpu_set_memory,
NULL, NULL, "Sets the RAM size for 8080 / Z80 / 8086" },
{ UNIT_CPU_SWITCHER, UNIT_CPU_SWITCHER, "SWITCHER", "SWITCHER", &cpu_set_switcher, &cpu_show_switcher,
NULL, "Sets CPU switcher port for 8080 / Z80 / 8086" },
{ UNIT_CPU_SWITCHER, 0, "NOSWITCHER", "NOSWITCHER", &cpu_reset_switcher, &cpu_show_switcher,
NULL, "Resets CPU switcher port for 8080 / Z80 / 8086" },
{ UNIT_CPU_PO, UNIT_CPU_PO, "PO", "PO", NULL, NULL,
NULL, "Enable programmed output messages" },
{ UNIT_CPU_PO, 0, "NOPO", "NOPO", NULL, NULL,
NULL, "Disable programmed output messages" },
{ MTAB_XTD | MTAB_VDV, 0, NULL, "AZ80", &cpu_set_ramtype,
NULL, NULL, "Sets the RAM type to AltairZ80 RAM for 8080 / Z80 / 8086" },
{ MTAB_XTD | MTAB_VDV, 1, NULL, "HRAM", &cpu_set_ramtype,
NULL, NULL, "Sets the RAM type to NorthStar HRAM for 8080 / Z80 / 8086" },
{ MTAB_XTD | MTAB_VDV, 2, NULL, "VRAM", &cpu_set_ramtype,
NULL, NULL, "Sets the RAM type to Vector RAM for 8080 / Z80 / 8086" },
{ MTAB_XTD | MTAB_VDV, 3, NULL, "CRAM", &cpu_set_ramtype,
NULL, NULL, "Sets the RAM type to Cromemco RAM for 8080 / Z80 / 8086" },
{ MTAB_XTD | MTAB_VDV, 4, NULL, "B810", &cpu_set_ramtype,
NULL, NULL, "Sets the RAM type AB Digital Design B810 8080 / Z80 / 8086"},
{ MTAB_VDV, 4, NULL, "4KB", &cpu_set_size,
NULL, NULL, "Sets the RAM size to 4KB for 8080 / Z80 / 8086" },
{ MTAB_VDV, 8, NULL, "8KB", &cpu_set_size,
NULL, NULL, "Sets the RAM size to 8KB for 8080 / Z80 / 8086" },
{ MTAB_VDV, 12, NULL, "12KB", &cpu_set_size,
NULL, NULL, "Sets the RAM size to 12KB for 8080 / Z80 / 8086" },
{ MTAB_VDV, 16, NULL, "16KB", &cpu_set_size,
NULL, NULL, "Sets the RAM size to 16KB for 8080 / Z80 / 8086" },
{ MTAB_VDV, 20, NULL, "20KB", &cpu_set_size,
NULL, NULL, "Sets the RAM size to 20KB for 8080 / Z80 / 8086" },
{ MTAB_VDV, 24, NULL, "24KB", &cpu_set_size,
NULL, NULL, "Sets the RAM size to 24KB for 8080 / Z80 / 8086" },
{ MTAB_VDV, 28, NULL, "28KB", &cpu_set_size,
NULL, NULL, "Sets the RAM size to 28KB for 8080 / Z80 / 8086" },
{ MTAB_VDV, 32, NULL, "32KB", &cpu_set_size,
NULL, NULL, "Sets the RAM size to 32KB for 8080 / Z80 / 8086" },
{ MTAB_VDV, 36, NULL, "36KB", &cpu_set_size,
NULL, NULL, "Sets the RAM size to 36KB for 8080 / Z80 / 8086" },
{ MTAB_VDV, 40, NULL, "40KB", &cpu_set_size,
NULL, NULL, "Sets the RAM size to 40KB for 8080 / Z80 / 8086" },
{ MTAB_VDV, 44, NULL, "44KB", &cpu_set_size,
NULL, NULL, "Sets the RAM size to 44KB for 8080 / Z80 / 8086" },
{ MTAB_VDV, 48, NULL, "48KB", &cpu_set_size,
NULL, NULL, "Sets the RAM size to 48KB for 8080 / Z80 / 8086" },
{ MTAB_VDV, 52, NULL, "52KB", &cpu_set_size,
NULL, NULL, "Sets the RAM size to 52KB for 8080 / Z80 / 8086" },
{ MTAB_VDV, 56, NULL, "56KB", &cpu_set_size,
NULL, NULL, "Sets the RAM size to 56KB for 8080 / Z80 / 8086" },
{ MTAB_VDV, 60, NULL, "60KB", &cpu_set_size,
NULL, NULL, "Sets the RAM size to 60KB for 8080 / Z80 / 8086" },
{ MTAB_VDV, 64, NULL, "64KB", &cpu_set_size,
NULL, NULL, "Sets the RAM size to 64KB for 8080 / Z80 / 8086" },
{ MTAB_VDV, M68K_CPU_TYPE_68000,NULL, "68000", &m68k_set_chiptype,
NULL, NULL, "Sets the M68K variant to 68000" },
{ MTAB_VDV, M68K_CPU_TYPE_68010,NULL, "68010", &m68k_set_chiptype,
NULL, NULL, "Sets the M68K variant to 68010" },
{ MTAB_VDV, M68K_CPU_TYPE_68020,NULL, "68020", &m68k_set_chiptype,
NULL, NULL, "Sets the M68K variant to 68020" },
{ MTAB_XTD | MTAB_VDV, M68K_CPU_TYPE_68EC020,NULL, "68EC020", &m68k_set_chiptype,
NULL, NULL, "Sets the M68K variant to 68EC020" },
{ MTAB_XTD | MTAB_VDV, M68K_CPU_TYPE_68030,NULL, "68030", &m68k_set_chiptype,
NULL, NULL, "Sets the M68K variant to 68030" },
{ MTAB_XTD | MTAB_VDV, M68K_CPU_TYPE_68EC030,NULL, "68EC030", &m68k_set_chiptype,
NULL, NULL, "Sets the M68K variant to 68EC030" },
{ MTAB_XTD | MTAB_VDV, M68K_CPU_TYPE_68040,NULL, "68040", &m68k_set_chiptype,
NULL, NULL, "Sets the M68K variant to 68040" },
{ MTAB_XTD | MTAB_VDV, M68K_CPU_TYPE_68EC040,NULL, "68EC040", &m68k_set_chiptype,
NULL, NULL, "Sets the M68K variant to 68EC040" },
{ MTAB_XTD | MTAB_VDV, M68K_CPU_TYPE_68LC040,NULL, "68LC040", &m68k_set_chiptype,
NULL, NULL, "Sets the M68K variant to 68LC040" },
{ MTAB_XTD | MTAB_VDV, M68K_CPU_TYPE_SCC68070,NULL, "SCC68070", &m68k_set_chiptype,
NULL, NULL, "Sets the M68K variant to SCC68070" },
{ MTAB_XTD|MTAB_VDV|MTAB_NMO|MTAB_VALO|MTAB_SHP, 0, "HISTORY", "HISTORY", &cpu_set_hist, &cpu_show_hist,
NULL, "CPU instruction history buffer"},
{ 0 }
};
/* Simulator-specific commands */
static CTAB cpu_cmd_tbl[] = {
{ "MEM", &cpu_cmd_memory, 0, "MEM <address> Dump a block of memory\n" },
{ "REG", &cpu_cmd_reg, 0, "REG Display registers\n" },
{ NULL, NULL, 0, NULL }
};
/* Debug Flags */
static DEBTAB cpu_dt[] = {
{ "LOG_IN", IN_MSG, "Log IN operations" },
{ "LOG_OUT", OUT_MSG, "Log OUT operations" },
{ "LOG_INT", INT_MSG, "Log interrupts" },
{ NULL, 0 }
};
DEVICE cpu_dev = {
"CPU", &cpu_unit, cpu_reg, cpu_mod,
1, 16, 16, 1, 16, 8,
&cpu_ex, &cpu_dep, &cpu_reset,
NULL, NULL, NULL,
NULL, DEV_DEBUG, 0,
cpu_dt, NULL, NULL, NULL, NULL, NULL, &cpu_description
};
/* This is the I/O configuration table. There are 255 possible
device addresses, if a device is plugged to a port it's routine
address is here, 'nulldev' means no device is available
*/
static struct idev dev_table[256] = {
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&sio0d, "sio0d"}, {&sio0s, "sio0s"}, /* 00 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* 04 */
{&dsk10, "dsk10"}, {&dsk11, "dsk11"}, {&dsk12, "dsk12"}, {&nulldev, "nulldev"}, /* 08 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* 0C */
{&sio0s, "sio0s"}, {&sio0d, "sio0d"}, {&sio1s, "sio1s"}, {&sio1d, "sio1d"}, /* 10 */
{&sio0s, "sio0s"}, {&sio0d, "sio0d"}, {&sio0s, "sio0s"}, {&sio0d, "sio0d"}, /* 14 */
{&sio0s, "sio0s"}, {&sio0d, "sio0d"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* 18 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* 1C */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* 20 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* 24 */
{&netStatus, "netStatus"}, {&netData, "netData"}, {&netStatus, "netStatus"}, {&netData, "netData"}, /* 28 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* 2C */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&netStatus, "netStatus"},{&netData, "netData"}, /* 30 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* 34 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* 38 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* 3C */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* 40 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* 44 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* 48 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* 4C */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* 50 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* 54 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* 58 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* 5C */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* 60 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* 64 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* 68 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* 6C */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* 70 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* 74 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* 78 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* 7C */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* 80 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* 84 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* 88 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* 8C */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* 90 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* 94 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* 98 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* 9C */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* A0 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* A4 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* A8 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* AC */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* B0 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* B4 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* B8 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* BC */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* C0 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* C4 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* C8 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* CC */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* D0 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* D4 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* D8 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* DC */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* E0 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* E4 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* E8 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* EC */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* F0 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* F4 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* F8 */
{&nulldev, "nulldev"}, {&hdsk_io, "hdsk_io"}, {&simh_dev,"simh_dev"},{&sr_dev, "sr_dev"} /* FC */
};
const char* handlerNameForPort(const int32 port) {
return dev_table[port & 0xff].name;
}
#define RAM_TYPE_AZ80 0 /* Altair-Z80 RAM card */
#define RAM_TYPE_HRAM 1 /* North Start Horizon RAM card */
#define RAM_TYPE_VRAM 2 /* Vector Graphic RAM card */
#define RAM_TYPE_CRAM 3 /* Cromemco RAM card */
#define RAM_TYPE_B810 4 /* AB Digital Design B810 RAM card */
#define MAX_RAM_TYPE RAM_TYPE_B810
static int32 ramtype = RAM_TYPE_AZ80;
ChipType chiptype = CHIP_TYPE_8080;
void out(const uint32 Port, const uint32 Value) {
if ((cpu_dev.dctrl & OUT_MSG) && sim_deb) {
fprintf(sim_deb, "CPU: " ADDRESS_FORMAT
" OUT(port=0x%04x [%5d] %s, value=0x%04x [%5d])\n", PCX, Port, Port, dev_table[Port & 0xff].name, Value, Value);
fflush(sim_deb);
}
dev_table[Port & 0xff].routine(Port, 1, Value);
if ((cpu_dev.dctrl & OUT_MSG) && sim_deb) {
fprintf(sim_deb, "CPU: " ADDRESS_FORMAT
" OUT(port=0x%04x [%5d] %s, value=0x%04x [%5d]) done\n", PCX, Port, Port, dev_table[Port & 0xff].name, Value, Value);
fflush(sim_deb);
}
}
uint32 in(const uint32 Port) {
uint32 result;
if ((cpu_dev.dctrl & IN_MSG) && sim_deb) {
fprintf(sim_deb, "CPU: " ADDRESS_FORMAT
" IN(port=0x%04x [%5d] %s)\n", PCX, Port, Port, dev_table[Port & 0xff].name);
fflush(sim_deb);
}
result = dev_table[Port & 0xff].routine(Port, 0, 0);
if ((cpu_dev.dctrl & IN_MSG) && sim_deb) {
fprintf(sim_deb, "CPU: " ADDRESS_FORMAT
" IN(port=0x%04x [%5d] %s) = 0x%04x [%5d]\n", PCX, Port, Port, dev_table[Port & 0xff].name, result, result);
fflush(sim_deb);
}
return result;
}
/* the following tables precompute some common subexpressions
parityTable[i] 0..255 (number of 1's in i is odd) ? 0 : 4
incTable[i] 0..256! (i & 0xa8) | (((i & 0xff) == 0) << 6) | (((i & 0xf) == 0) << 4)
decTable[i] 0..255 (i & 0xa8) | (((i & 0xff) == 0) << 6) | (((i & 0xf) == 0xf) << 4) | 2
cbitsTable[i] 0..511 (i & 0x10) | ((i >> 8) & 1)
cbitsDup8Table[i] 0..511 (i & 0x10) | ((i >> 8) & 1) | ((i & 0xff) << 8) | (i & 0xa8) |
(((i & 0xff) == 0) << 6)
cbitsDup16Table[i] 0..511 (i & 0x10) | ((i >> 8) & 1) | (i & 0x28)
cbits2Table[i] 0..511 (i & 0x10) | ((i >> 8) & 1) | 2
rrcaTable[i] 0..255 ((i & 1) << 15) | ((i >> 1) << 8) | ((i >> 1) & 0x28) | (i & 1)
rraTable[i] 0..255 ((i >> 1) << 8) | ((i >> 1) & 0x28) | (i & 1)
addTable[i] 0..511 ((i & 0xff) << 8) | (i & 0xa8) | (((i & 0xff) == 0) << 6)
subTable[i] 0..255 ((i & 0xff) << 8) | (i & 0xa8) | (((i & 0xff) == 0) << 6) | 2
andTable[i] 0..255 (i << 8) | (i & 0xa8) | ((i == 0) << 6) | 0x10 | parityTable[i]
xororTable[i] 0..255 (i << 8) | (i & 0xa8) | ((i == 0) << 6) | parityTable[i]
rotateShiftTable[i] 0..255 (i & 0xa8) | (((i & 0xff) == 0) << 6) | parityTable[i & 0xff]
incZ80Table[i] 0..256! (i & 0xa8) | (((i & 0xff) == 0) << 6) |
(((i & 0xf) == 0) << 4) | ((i == 0x80) << 2)
decZ80Table[i] 0..255 (i & 0xa8) | (((i & 0xff) == 0) << 6) |
(((i & 0xf) == 0xf) << 4) | ((i == 0x7f) << 2) | 2
cbitsZ80Table[i] 0..511 (i & 0x10) | (((i >> 6) ^ (i >> 5)) & 4) | ((i >> 8) & 1)
cbitsZ80DupTable[i] 0..511 (i & 0x10) | (((i >> 6) ^ (i >> 5)) & 4) |
((i >> 8) & 1) | (i & 0xa8)
cbits2Z80Table[i] 0..511 (i & 0x10) | (((i >> 6) ^ (i >> 5)) & 4) | ((i >> 8) & 1) | 2
cbits2Z80DupTable[i] 0..511 (i & 0x10) | (((i >> 6) ^ (i >> 5)) & 4) | ((i >> 8) & 1) | 2 |
(i & 0xa8)
negTable[i] 0..255 (((i & 0x0f) != 0) << 4) | ((i == 0x80) << 2) | 2 | (i != 0)
rrdrldTable[i] 0..255 (i << 8) | (i & 0xa8) | (((i & 0xff) == 0) << 6) | parityTable[i]
cpTable[i] 0..255 (i & 0x80) | (((i & 0xff) == 0) << 6)
*/
/* parityTable[i] = (number of 1's in i is odd) ? 0 : 4, i = 0..255 */
static const uint8 parityTable[256] = {
4,0,0,4,0,4,4,0,0,4,4,0,4,0,0,4,
0,4,4,0,4,0,0,4,4,0,0,4,0,4,4,0,
0,4,4,0,4,0,0,4,4,0,0,4,0,4,4,0,
4,0,0,4,0,4,4,0,0,4,4,0,4,0,0,4,
0,4,4,0,4,0,0,4,4,0,0,4,0,4,4,0,
4,0,0,4,0,4,4,0,0,4,4,0,4,0,0,4,
4,0,0,4,0,4,4,0,0,4,4,0,4,0,0,4,
0,4,4,0,4,0,0,4,4,0,0,4,0,4,4,0,
0,4,4,0,4,0,0,4,4,0,0,4,0,4,4,0,
4,0,0,4,0,4,4,0,0,4,4,0,4,0,0,4,
4,0,0,4,0,4,4,0,0,4,4,0,4,0,0,4,
0,4,4,0,4,0,0,4,4,0,0,4,0,4,4,0,
4,0,0,4,0,4,4,0,0,4,4,0,4,0,0,4,
0,4,4,0,4,0,0,4,4,0,0,4,0,4,4,0,
0,4,4,0,4,0,0,4,4,0,0,4,0,4,4,0,
4,0,0,4,0,4,4,0,0,4,4,0,4,0,0,4,
};
/* incTable[i] = (i & 0xa8) | (((i & 0xff) == 0) << 6) | (((i & 0xf) == 0) << 4), i = 0..256 */
static const uint8 incTable[257] = {
80, 0, 0, 0, 0, 0, 0, 0, 8, 8, 8, 8, 8, 8, 8, 8,
16, 0, 0, 0, 0, 0, 0, 0, 8, 8, 8, 8, 8, 8, 8, 8,
48, 32, 32, 32, 32, 32, 32, 32, 40, 40, 40, 40, 40, 40, 40, 40,
48, 32, 32, 32, 32, 32, 32, 32, 40, 40, 40, 40, 40, 40, 40, 40,
16, 0, 0, 0, 0, 0, 0, 0, 8, 8, 8, 8, 8, 8, 8, 8,
16, 0, 0, 0, 0, 0, 0, 0, 8, 8, 8, 8, 8, 8, 8, 8,
48, 32, 32, 32, 32, 32, 32, 32, 40, 40, 40, 40, 40, 40, 40, 40,
48, 32, 32, 32, 32, 32, 32, 32, 40, 40, 40, 40, 40, 40, 40, 40,
144,128,128,128,128,128,128,128,136,136,136,136,136,136,136,136,
144,128,128,128,128,128,128,128,136,136,136,136,136,136,136,136,
176,160,160,160,160,160,160,160,168,168,168,168,168,168,168,168,
176,160,160,160,160,160,160,160,168,168,168,168,168,168,168,168,
144,128,128,128,128,128,128,128,136,136,136,136,136,136,136,136,
144,128,128,128,128,128,128,128,136,136,136,136,136,136,136,136,
176,160,160,160,160,160,160,160,168,168,168,168,168,168,168,168,
176,160,160,160,160,160,160,160,168,168,168,168,168,168,168,168, 80
};
/* decTable[i] = (i & 0xa8) | (((i & 0xff) == 0) << 6) | (((i & 0xf) == 0xf) << 4) | 2, i = 0..255 */
static const uint8 decTable[256] = {
66, 2, 2, 2, 2, 2, 2, 2, 10, 10, 10, 10, 10, 10, 10, 26,
2, 2, 2, 2, 2, 2, 2, 2, 10, 10, 10, 10, 10, 10, 10, 26,
34, 34, 34, 34, 34, 34, 34, 34, 42, 42, 42, 42, 42, 42, 42, 58,
34, 34, 34, 34, 34, 34, 34, 34, 42, 42, 42, 42, 42, 42, 42, 58,
2, 2, 2, 2, 2, 2, 2, 2, 10, 10, 10, 10, 10, 10, 10, 26,
2, 2, 2, 2, 2, 2, 2, 2, 10, 10, 10, 10, 10, 10, 10, 26,
34, 34, 34, 34, 34, 34, 34, 34, 42, 42, 42, 42, 42, 42, 42, 58,
34, 34, 34, 34, 34, 34, 34, 34, 42, 42, 42, 42, 42, 42, 42, 58,
130,130,130,130,130,130,130,130,138,138,138,138,138,138,138,154,
130,130,130,130,130,130,130,130,138,138,138,138,138,138,138,154,
162,162,162,162,162,162,162,162,170,170,170,170,170,170,170,186,
162,162,162,162,162,162,162,162,170,170,170,170,170,170,170,186,
130,130,130,130,130,130,130,130,138,138,138,138,138,138,138,154,
130,130,130,130,130,130,130,130,138,138,138,138,138,138,138,154,
162,162,162,162,162,162,162,162,170,170,170,170,170,170,170,186,
162,162,162,162,162,162,162,162,170,170,170,170,170,170,170,186,
};
/* cbitsTable[i] = (i & 0x10) | ((i >> 8) & 1), i = 0..511 */
static const uint8 cbitsTable[512] = {
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,
};
/* cbitsDup8Table[i] = (i & 0x10) | ((i >> 8) & 1) | ((i & 0xff) << 8) | (i & 0xa8) |
(((i & 0xff) == 0) << 6), i = 0..511 */
static const uint16 cbitsDup8Table[512] = {
0x0040,0x0100,0x0200,0x0300,0x0400,0x0500,0x0600,0x0700,
0x0808,0x0908,0x0a08,0x0b08,0x0c08,0x0d08,0x0e08,0x0f08,
0x1010,0x1110,0x1210,0x1310,0x1410,0x1510,0x1610,0x1710,
0x1818,0x1918,0x1a18,0x1b18,0x1c18,0x1d18,0x1e18,0x1f18,
0x2020,0x2120,0x2220,0x2320,0x2420,0x2520,0x2620,0x2720,
0x2828,0x2928,0x2a28,0x2b28,0x2c28,0x2d28,0x2e28,0x2f28,
0x3030,0x3130,0x3230,0x3330,0x3430,0x3530,0x3630,0x3730,
0x3838,0x3938,0x3a38,0x3b38,0x3c38,0x3d38,0x3e38,0x3f38,
0x4000,0x4100,0x4200,0x4300,0x4400,0x4500,0x4600,0x4700,
0x4808,0x4908,0x4a08,0x4b08,0x4c08,0x4d08,0x4e08,0x4f08,
0x5010,0x5110,0x5210,0x5310,0x5410,0x5510,0x5610,0x5710,
0x5818,0x5918,0x5a18,0x5b18,0x5c18,0x5d18,0x5e18,0x5f18,
0x6020,0x6120,0x6220,0x6320,0x6420,0x6520,0x6620,0x6720,
0x6828,0x6928,0x6a28,0x6b28,0x6c28,0x6d28,0x6e28,0x6f28,
0x7030,0x7130,0x7230,0x7330,0x7430,0x7530,0x7630,0x7730,
0x7838,0x7938,0x7a38,0x7b38,0x7c38,0x7d38,0x7e38,0x7f38,
0x8080,0x8180,0x8280,0x8380,0x8480,0x8580,0x8680,0x8780,
0x8888,0x8988,0x8a88,0x8b88,0x8c88,0x8d88,0x8e88,0x8f88,
0x9090,0x9190,0x9290,0x9390,0x9490,0x9590,0x9690,0x9790,
0x9898,0x9998,0x9a98,0x9b98,0x9c98,0x9d98,0x9e98,0x9f98,
0xa0a0,0xa1a0,0xa2a0,0xa3a0,0xa4a0,0xa5a0,0xa6a0,0xa7a0,
0xa8a8,0xa9a8,0xaaa8,0xaba8,0xaca8,0xada8,0xaea8,0xafa8,
0xb0b0,0xb1b0,0xb2b0,0xb3b0,0xb4b0,0xb5b0,0xb6b0,0xb7b0,
0xb8b8,0xb9b8,0xbab8,0xbbb8,0xbcb8,0xbdb8,0xbeb8,0xbfb8,
0xc080,0xc180,0xc280,0xc380,0xc480,0xc580,0xc680,0xc780,
0xc888,0xc988,0xca88,0xcb88,0xcc88,0xcd88,0xce88,0xcf88,
0xd090,0xd190,0xd290,0xd390,0xd490,0xd590,0xd690,0xd790,
0xd898,0xd998,0xda98,0xdb98,0xdc98,0xdd98,0xde98,0xdf98,
0xe0a0,0xe1a0,0xe2a0,0xe3a0,0xe4a0,0xe5a0,0xe6a0,0xe7a0,
0xe8a8,0xe9a8,0xeaa8,0xeba8,0xeca8,0xeda8,0xeea8,0xefa8,
0xf0b0,0xf1b0,0xf2b0,0xf3b0,0xf4b0,0xf5b0,0xf6b0,0xf7b0,
0xf8b8,0xf9b8,0xfab8,0xfbb8,0xfcb8,0xfdb8,0xfeb8,0xffb8,
0x0041,0x0101,0x0201,0x0301,0x0401,0x0501,0x0601,0x0701,
0x0809,0x0909,0x0a09,0x0b09,0x0c09,0x0d09,0x0e09,0x0f09,
0x1011,0x1111,0x1211,0x1311,0x1411,0x1511,0x1611,0x1711,
0x1819,0x1919,0x1a19,0x1b19,0x1c19,0x1d19,0x1e19,0x1f19,
0x2021,0x2121,0x2221,0x2321,0x2421,0x2521,0x2621,0x2721,
0x2829,0x2929,0x2a29,0x2b29,0x2c29,0x2d29,0x2e29,0x2f29,
0x3031,0x3131,0x3231,0x3331,0x3431,0x3531,0x3631,0x3731,
0x3839,0x3939,0x3a39,0x3b39,0x3c39,0x3d39,0x3e39,0x3f39,
0x4001,0x4101,0x4201,0x4301,0x4401,0x4501,0x4601,0x4701,
0x4809,0x4909,0x4a09,0x4b09,0x4c09,0x4d09,0x4e09,0x4f09,
0x5011,0x5111,0x5211,0x5311,0x5411,0x5511,0x5611,0x5711,
0x5819,0x5919,0x5a19,0x5b19,0x5c19,0x5d19,0x5e19,0x5f19,
0x6021,0x6121,0x6221,0x6321,0x6421,0x6521,0x6621,0x6721,
0x6829,0x6929,0x6a29,0x6b29,0x6c29,0x6d29,0x6e29,0x6f29,
0x7031,0x7131,0x7231,0x7331,0x7431,0x7531,0x7631,0x7731,
0x7839,0x7939,0x7a39,0x7b39,0x7c39,0x7d39,0x7e39,0x7f39,
0x8081,0x8181,0x8281,0x8381,0x8481,0x8581,0x8681,0x8781,
0x8889,0x8989,0x8a89,0x8b89,0x8c89,0x8d89,0x8e89,0x8f89,
0x9091,0x9191,0x9291,0x9391,0x9491,0x9591,0x9691,0x9791,
0x9899,0x9999,0x9a99,0x9b99,0x9c99,0x9d99,0x9e99,0x9f99,
0xa0a1,0xa1a1,0xa2a1,0xa3a1,0xa4a1,0xa5a1,0xa6a1,0xa7a1,
0xa8a9,0xa9a9,0xaaa9,0xaba9,0xaca9,0xada9,0xaea9,0xafa9,
0xb0b1,0xb1b1,0xb2b1,0xb3b1,0xb4b1,0xb5b1,0xb6b1,0xb7b1,
0xb8b9,0xb9b9,0xbab9,0xbbb9,0xbcb9,0xbdb9,0xbeb9,0xbfb9,
0xc081,0xc181,0xc281,0xc381,0xc481,0xc581,0xc681,0xc781,
0xc889,0xc989,0xca89,0xcb89,0xcc89,0xcd89,0xce89,0xcf89,
0xd091,0xd191,0xd291,0xd391,0xd491,0xd591,0xd691,0xd791,
0xd899,0xd999,0xda99,0xdb99,0xdc99,0xdd99,0xde99,0xdf99,
0xe0a1,0xe1a1,0xe2a1,0xe3a1,0xe4a1,0xe5a1,0xe6a1,0xe7a1,
0xe8a9,0xe9a9,0xeaa9,0xeba9,0xeca9,0xeda9,0xeea9,0xefa9,
0xf0b1,0xf1b1,0xf2b1,0xf3b1,0xf4b1,0xf5b1,0xf6b1,0xf7b1,
0xf8b9,0xf9b9,0xfab9,0xfbb9,0xfcb9,0xfdb9,0xfeb9,0xffb9,
};
/* cbitsDup16Table[i] = (i & 0x10) | ((i >> 8) & 1) | (i & 0x28), i = 0..511 */
static const uint8 cbitsDup16Table[512] = {
0, 0, 0, 0, 0, 0, 0, 0, 8, 8, 8, 8, 8, 8, 8, 8,
16,16,16,16,16,16,16,16,24,24,24,24,24,24,24,24,
32,32,32,32,32,32,32,32,40,40,40,40,40,40,40,40,
48,48,48,48,48,48,48,48,56,56,56,56,56,56,56,56,
0, 0, 0, 0, 0, 0, 0, 0, 8, 8, 8, 8, 8, 8, 8, 8,
16,16,16,16,16,16,16,16,24,24,24,24,24,24,24,24,
32,32,32,32,32,32,32,32,40,40,40,40,40,40,40,40,
48,48,48,48,48,48,48,48,56,56,56,56,56,56,56,56,
0, 0, 0, 0, 0, 0, 0, 0, 8, 8, 8, 8, 8, 8, 8, 8,
16,16,16,16,16,16,16,16,24,24,24,24,24,24,24,24,
32,32,32,32,32,32,32,32,40,40,40,40,40,40,40,40,
48,48,48,48,48,48,48,48,56,56,56,56,56,56,56,56,
0, 0, 0, 0, 0, 0, 0, 0, 8, 8, 8, 8, 8, 8, 8, 8,
16,16,16,16,16,16,16,16,24,24,24,24,24,24,24,24,
32,32,32,32,32,32,32,32,40,40,40,40,40,40,40,40,
48,48,48,48,48,48,48,48,56,56,56,56,56,56,56,56,
1, 1, 1, 1, 1, 1, 1, 1, 9, 9, 9, 9, 9, 9, 9, 9,
17,17,17,17,17,17,17,17,25,25,25,25,25,25,25,25,
33,33,33,33,33,33,33,33,41,41,41,41,41,41,41,41,
49,49,49,49,49,49,49,49,57,57,57,57,57,57,57,57,
1, 1, 1, 1, 1, 1, 1, 1, 9, 9, 9, 9, 9, 9, 9, 9,
17,17,17,17,17,17,17,17,25,25,25,25,25,25,25,25,
33,33,33,33,33,33,33,33,41,41,41,41,41,41,41,41,
49,49,49,49,49,49,49,49,57,57,57,57,57,57,57,57,
1, 1, 1, 1, 1, 1, 1, 1, 9, 9, 9, 9, 9, 9, 9, 9,
17,17,17,17,17,17,17,17,25,25,25,25,25,25,25,25,
33,33,33,33,33,33,33,33,41,41,41,41,41,41,41,41,
49,49,49,49,49,49,49,49,57,57,57,57,57,57,57,57,
1, 1, 1, 1, 1, 1, 1, 1, 9, 9, 9, 9, 9, 9, 9, 9,
17,17,17,17,17,17,17,17,25,25,25,25,25,25,25,25,
33,33,33,33,33,33,33,33,41,41,41,41,41,41,41,41,
49,49,49,49,49,49,49,49,57,57,57,57,57,57,57,57,
};
/* cbits2Table[i] = (i & 0x10) | ((i >> 8) & 1) | 2, i = 0..511 */
static const uint8 cbits2Table[512] = {
2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
18,18,18,18,18,18,18,18,18,18,18,18,18,18,18,18,
2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
18,18,18,18,18,18,18,18,18,18,18,18,18,18,18,18,
2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,