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rtl/verilog/apb_gpio.sv

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/////////////////////////////////////////////////////////////////
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// //
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// ██████╗ ██████╗ █████╗ //
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// ██╔══██╗██╔═══██╗██╔══██╗ //
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// ██████╔╝██║ ██║███████║ //
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// ██╔══██╗██║ ██║██╔══██║ //
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// ██║ ██║╚██████╔╝██║ ██║ //
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// ╚═╝ ╚═╝ ╚═════╝ ╚═╝ ╚═╝ //
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// ██╗ ██████╗ ██████╗ ██╗ ██████╗ //
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// ██║ ██╔═══██╗██╔════╝ ██║██╔════╝ //
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// ██║ ██║ ██║██║ ███╗██║██║ //
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// ██║ ██║ ██║██║ ██║██║██║ //
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// ███████╗╚██████╔╝╚██████╔╝██║╚██████╗ //
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// ╚══════╝ ╚═════╝ ╚═════╝ ╚═╝ ╚═════╝ //
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// //
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// APB GPIO //
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// //
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/////////////////////////////////////////////////////////////////
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// //
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// Copyright (C) 2016-2017 ROA Logic BV //
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// www.roalogic.com //
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// //
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// Unless specifically agreed in writing, this software is //
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// licensed under the RoaLogic Non-Commercial License //
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// version-1.0 (the "License"), a copy of which is included //
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// with this file or may be found on the RoaLogic website //
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// http://www.roalogic.com. You may not use the file except //
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// in compliance with the License. //
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// //
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// THIS SOFTWARE IS PROVIDED "AS IS" AND WITHOUT ANY //
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// EXPRESS OF IMPLIED WARRANTIES OF ANY KIND. //
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// See the License for permissions and limitations under the //
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// License. //
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// //
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/////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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// ,------. ,--. ,--. //
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// | .--. ' ,---. ,--,--. | | ,---. ,---. `--' ,---. //
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// | '--'.'| .-. |' ,-. | | | | .-. | .-. |,--.| .--' //
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// | |\ \ ' '-' '\ '-' | | '--.' '-' ' '-' || |\ `--. //
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// `--' '--' `---' `--`--' `-----' `---' `- /`--' `---' //
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// `---' //
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// APB4 GPIO //
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// //
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/////////////////////////////////////////////////////////////////////
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// //
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// Copyright (C) 2016-2018 ROA Logic BV //
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// www.roalogic.com //
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// //
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// Unless specifically agreed in writing, this software is //
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// licensed under the RoaLogic Non-Commercial License //
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// version-1.0 (the "License"), a copy of which is included //
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// with this file or may be found on the RoaLogic website //
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// http://www.roalogic.com. You may not use the file except //
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// in compliance with the License. //
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// //
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// THIS SOFTWARE IS PROVIDED "AS IS" AND WITHOUT ANY //
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// EXPRESS OF IMPLIED WARRANTIES OF ANY KIND. //
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// See the License for permissions and limitations under the //
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// License. //
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// //
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/////////////////////////////////////////////////////////////////////
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// +FHDR - Semiconductor Reuse Standard File Header Section -------
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// FILE NAME : apb_gpio.sv
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// DEPARTMENT :
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// AUTHOR : rherveille
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// AUTHOR'S EMAIL :
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// ------------------------------------------------------------------
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// RELEASE HISTORY
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// VERSION DATE AUTHOR DESCRIPTION
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// 1.0 2017-03-29 rherveille initial release
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// ------------------------------------------------------------------
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// KEYWORDS : AMBA APB4 General Purpose IO GPIO
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// ------------------------------------------------------------------
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// PURPOSE : General purpose IO
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// ------------------------------------------------------------------
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// PARAMETERS
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// PARAM NAME RANGE DESCRIPTION DEFAULT UNITS
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// PDATA_SIZE 1+ Databus (and GPIO) size 8 bits
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// ------------------------------------------------------------------
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// REUSE ISSUES
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// Reset Strategy : external asynchronous active low; PRESETn
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// Clock Domains : PCLK, rising edge
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// Critical Timing :
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// Test Features : na
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// Asynchronous I/F : no
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// Scan Methodology : na
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// Instantiations : na
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// Synthesizable (y/n) : Yes
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// Other :
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// -FHDR-------------------------------------------------------------
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/*

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