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Fixed tr_status[n]
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rtl/verilog/apb_gpio.sv

Lines changed: 10 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,7 @@
99
// //
1010
/////////////////////////////////////////////////////////////////////
1111
// //
12-
// Copyright (C) 2016-2018 ROA Logic BV //
12+
// Copyright (C) 2017-2020 ROA Logic BV //
1313
// www.roalogic.com //
1414
// //
1515
// Unless specifically agreed in writing, this software is //
@@ -126,7 +126,7 @@ module apb_gpio #(
126126
IRQ_ENA = 8;
127127

128128
//number of synchronisation flipflop stages on GPIO inputs
129-
localparam INPUT_STAGES = 3;
129+
localparam INPUT_STAGES = 2;
130130

131131

132132
//////////////////////////////////////////////////////////////////
@@ -155,8 +155,6 @@ module apb_gpio #(
155155
//Input register, to prevent metastability
156156
logic [PDATA_SIZE-1:0] input_regs [INPUT_STAGES];
157157

158-
integer n;
159-
160158

161159
//////////////////////////////////////////////////////////////////
162160
//
@@ -285,7 +283,7 @@ module apb_gpio #(
285283
* Internals
286284
*/
287285
always @(posedge PCLK)
288-
for (n=0; n<INPUT_STAGES; n++)
286+
for (int n=0; n<INPUT_STAGES; n++)
289287
if (n==0) input_regs[n] <= gpio_i;
290288
else input_regs[n] <= input_regs[n-1];
291289

@@ -297,7 +295,7 @@ module apb_gpio #(
297295
// 0=push-pull drive out_reg value onto transmitter input
298296
// 1=open-drain always drive '0' onto transmitter
299297
always @(posedge PCLK)
300-
for (n=0; n<PDATA_SIZE; n++)
298+
for (int n=0; n<PDATA_SIZE; n++)
301299
gpio_o[n] <= mode_reg[n] ? 1'b0 : out_reg[n];
302300

303301

@@ -307,7 +305,7 @@ module apb_gpio #(
307305
// 1=open-drain 1=Hi-Z disable transmitter
308306
// 0=low enable transmitter
309307
always @(posedge PCLK)
310-
for (n=0; n<PDATA_SIZE; n++)
308+
for (int n=0; n<PDATA_SIZE; n++)
311309
gpio_oe[n] <= dir_reg[n] & ~(mode_reg[n] ? out_reg[n] : 1'b0);
312310

313311

@@ -334,12 +332,12 @@ module apb_gpio #(
334332

335333
//trigger status
336334
always_comb
337-
for (n=0; n<PDATA_SIZE; n++)
335+
for (int n=0; n<PDATA_SIZE; n++)
338336
case (tr_type_reg[n])
339-
0: tr_status = (tr_lvl0_reg[n] & ~in_reg[n]) |
340-
(tr_lvl1_reg[n] & in_reg[n]);
341-
1: tr_status = (tr_lvl0_reg[n] & tr_falling_edge_reg[n]) |
342-
(tr_lvl1_reg[n] & tr_rising_edge_reg [n]);
337+
0: tr_status[n] = (tr_lvl0_reg[n] & ~in_reg[n]) |
338+
(tr_lvl1_reg[n] & in_reg[n]);
339+
1: tr_status[n] = (tr_lvl0_reg[n] & tr_falling_edge_reg[n]) |
340+
(tr_lvl1_reg[n] & tr_rising_edge_reg [n]);
343341
endcase
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345343

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