Resolve merge conflict (10/15/16)

Author: kzhuravl

include/llvm/CodeGen/MachineMemOperand.h

@@ -127,8 +127,6 @@ class MachineMemOperand {
     /// For cmpxchg atomic operations, atomic ordering requirements when store
     /// does not occur.
     unsigned FailureOrdering : 4; // enum AtomicOrdering
-    /// Reserved/unused.
-    unsigned Reserved : 16;
   };
 
   MachinePointerInfo PtrInfo;
@@ -139,17 +137,6 @@ class MachineMemOperand {
   AAMDNodes AAInfo;
   const MDNode *Ranges;
 
-  /// Initialize atomic information for this memory operation.
-  void InitAtomicInfo(SynchronizationScope SynchScope, AtomicOrdering Ordering,
-                      AtomicOrdering FailureOrdering) {
-    AtomicInfo.SynchScope = static_cast<unsigned>(SynchScope);
-    assert(getSynchScope() == SynchScope && "Value truncated");
-    AtomicInfo.Ordering = static_cast<unsigned>(Ordering);
-    assert(getOrdering() == Ordering && "Value truncated");
-    AtomicInfo.FailureOrdering = static_cast<unsigned>(FailureOrdering);
-    assert(getFailureOrdering() == FailureOrdering && "Value truncated");
-  }
-
 public:
   /// Construct a MachineMemOperand object with the specified PtrInfo, flags,
   /// size, and base alignment. For atomic operations the synchronization scope

include/llvm/CodeGen/SelectionDAGNodes.h

@@ -1196,23 +1196,28 @@ class AtomicSDNode : public MemSDNode {
   const SDValue &getBasePtr() const { return getOperand(1); }
   const SDValue &getVal() const { return getOperand(2); }
 
+  /// Returns true if this SDNode represents cmpxchg atomic operation, false
+  /// otherwise.
+  bool isCompareAndSwap() const {
+    unsigned Op = getOpcode();
+    return Op == ISD::ATOMIC_CMP_SWAP ||
+           Op == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS;
+  }
+
   /// For cmpxchg atomic operations, return the atomic ordering requirements
   /// when store occurs.
   AtomicOrdering getSuccessOrdering() const {
+    assert(isCompareAndSwap() && "Must be cmpxchg operation");
     return MMO->getSuccessOrdering();
   }
 
   /// For cmpxchg atomic operations, return the atomic ordering requirements
   /// when store does not occur.
   AtomicOrdering getFailureOrdering() const {
+    assert(isCompareAndSwap() && "Must be cmpxchg operation");
     return MMO->getFailureOrdering();
   }
 
-  bool isCompareAndSwap() const {
-    unsigned Op = getOpcode();
-    return Op == ISD::ATOMIC_CMP_SWAP || Op == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS;
-  }
-
   // Methods to support isa and dyn_cast
   static bool classof(const SDNode *N) {
     return N->getOpcode() == ISD::ATOMIC_CMP_SWAP     ||

lib/CodeGen/MachineInstr.cpp

@@ -548,7 +548,13 @@ MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, Flags f,
          "invalid pointer value");
   assert(getBaseAlignment() == a && "Alignment is not a power of 2!");
   assert((isLoad() || isStore()) && "Not a load/store!");
-  InitAtomicInfo(SynchScope, Ordering, FailureOrdering);
+
+  AtomicInfo.SynchScope = static_cast<unsigned>(SynchScope);
+  assert(getSynchScope() == SynchScope && "Value truncated");
+  AtomicInfo.Ordering = static_cast<unsigned>(Ordering);
+  assert(getOrdering() == Ordering && "Value truncated");
+  AtomicInfo.FailureOrdering = static_cast<unsigned>(FailureOrdering);
+  assert(getFailureOrdering() == FailureOrdering && "Value truncated");
 }
 
 /// Profile - Gather unique data for the object.

lib/Target/ARM/ARMFastISel.cpp

@@ -112,11 +112,6 @@ class ARMFastISel final : public FastISel {
                              const TargetRegisterClass *RC,
                              unsigned Op0, bool Op0IsKill,
                              uint64_t Imm);
-    unsigned fastEmitInst_rri(unsigned MachineInstOpcode,
-                              const TargetRegisterClass *RC,
-                              unsigned Op0, bool Op0IsKill,
-                              unsigned Op1, bool Op1IsKill,
-                              uint64_t Imm);
     unsigned fastEmitInst_i(unsigned MachineInstOpcode,
                             const TargetRegisterClass *RC,
                             uint64_t Imm);
@@ -351,36 +346,6 @@ unsigned ARMFastISel::fastEmitInst_ri(unsigned MachineInstOpcode,
   return ResultReg;
 }
 
-unsigned ARMFastISel::fastEmitInst_rri(unsigned MachineInstOpcode,
-                                       const TargetRegisterClass *RC,
-                                       unsigned Op0, bool Op0IsKill,
-                                       unsigned Op1, bool Op1IsKill,
-                                       uint64_t Imm) {
-  unsigned ResultReg = createResultReg(RC);
-  const MCInstrDesc &II = TII.get(MachineInstOpcode);
-
-  // Make sure the input operands are sufficiently constrained to be legal
-  // for this instruction.
-  Op0 = constrainOperandRegClass(II, Op0, 1);
-  Op1 = constrainOperandRegClass(II, Op1, 2);
-  if (II.getNumDefs() >= 1) {
-    AddOptionalDefs(
-        BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
-            .addReg(Op0, Op0IsKill * RegState::Kill)
-            .addReg(Op1, Op1IsKill * RegState::Kill)
-            .addImm(Imm));
-  } else {
-    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
-                   .addReg(Op0, Op0IsKill * RegState::Kill)
-                   .addReg(Op1, Op1IsKill * RegState::Kill)
-                   .addImm(Imm));
-    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
-                           TII.get(TargetOpcode::COPY), ResultReg)
-                   .addReg(II.ImplicitDefs[0]));
-  }
-  return ResultReg;
-}
-
 unsigned ARMFastISel::fastEmitInst_i(unsigned MachineInstOpcode,
                                      const TargetRegisterClass *RC,
                                      uint64_t Imm) {