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[AArch64][SVE] Asm: Support for saturating INC/DEC (64bit scalar) instructions.
Summary: The variants added by this patch are: - SQINC (signed increment) - UQINC (unsigned increment) - SQDEC (signed decrement) - UQDEC (unsigned decrement) For example: uqincw x0, all, mul #4 Reviewers: rengolin, fhahn, SjoerdMeijer, samparker, javed.absar Differential Revision: https://reviews.llvm.org/D47715 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334948 91177308-0d34-0410-b5e6-96231b3b80d8
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‎lib/Target/AArch64/AArch64SVEInstrInfo.td

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@@ -527,6 +527,26 @@ let Predicates = [HasSVE] in {
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defm CMPLO_WIDE_PPzZZ : sve_int_cmp_1_wide<0b110, "cmplo">;
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defm CMPLS_WIDE_PPzZZ : sve_int_cmp_1_wide<0b111, "cmpls">;
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defm SQINCB_XPiI : sve_int_pred_pattern_b_x64<0b00100, "sqincb">;
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defm UQINCB_XPiI : sve_int_pred_pattern_b_x64<0b00101, "uqincb">;
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defm SQDECB_XPiI : sve_int_pred_pattern_b_x64<0b00110, "sqdecb">;
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defm UQDECB_XPiI : sve_int_pred_pattern_b_x64<0b00111, "uqdecb">;
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defm SQINCH_XPiI : sve_int_pred_pattern_b_x64<0b01100, "sqinch">;
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defm UQINCH_XPiI : sve_int_pred_pattern_b_x64<0b01101, "uqinch">;
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defm SQDECH_XPiI : sve_int_pred_pattern_b_x64<0b01110, "sqdech">;
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defm UQDECH_XPiI : sve_int_pred_pattern_b_x64<0b01111, "uqdech">;
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defm SQINCW_XPiI : sve_int_pred_pattern_b_x64<0b10100, "sqincw">;
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defm UQINCW_XPiI : sve_int_pred_pattern_b_x64<0b10101, "uqincw">;
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defm SQDECW_XPiI : sve_int_pred_pattern_b_x64<0b10110, "sqdecw">;
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defm UQDECW_XPiI : sve_int_pred_pattern_b_x64<0b10111, "uqdecw">;
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defm SQINCD_XPiI : sve_int_pred_pattern_b_x64<0b11100, "sqincd">;
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defm UQINCD_XPiI : sve_int_pred_pattern_b_x64<0b11101, "uqincd">;
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defm SQDECD_XPiI : sve_int_pred_pattern_b_x64<0b11110, "sqdecd">;
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defm UQDECD_XPiI : sve_int_pred_pattern_b_x64<0b11111, "uqdecd">;
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defm INDEX_RR : sve_int_index_rr<"index">;
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defm INDEX_IR : sve_int_index_ir<"index">;
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defm INDEX_RI : sve_int_index_ri<"index">;

‎lib/Target/AArch64/SVEInstrFormats.td

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@@ -314,6 +314,37 @@ multiclass sve_int_pred_pattern_a<bits<3> opc, string asm> {
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(!cast<Instruction>(NAME) GPR64:$Rdn, 0b11111, 1), 2>;
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}
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class sve_int_pred_pattern_b<bits<5> opc, string asm, RegisterOperand dt,
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RegisterOperand st>
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: I<(outs dt:$Rdn), (ins st:$_Rdn, sve_pred_enum:$pattern, sve_incdec_imm:$imm4),
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asm, "\t$Rdn, $pattern, mul $imm4",
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"",
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[]>, Sched<[]> {
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bits<5> Rdn;
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bits<5> pattern;
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bits<4> imm4;
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let Inst{31-24} = 0b00000100;
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let Inst{23-22} = opc{4-3};
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let Inst{21} = 0b1;
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let Inst{20} = opc{2};
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let Inst{19-16} = imm4;
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let Inst{15-12} = 0b1111;
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let Inst{11-10} = opc{1-0};
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let Inst{9-5} = pattern;
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let Inst{4-0} = Rdn;
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let Constraints = "$Rdn = $_Rdn";
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}
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multiclass sve_int_pred_pattern_b_x64<bits<5> opc, string asm> {
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def NAME : sve_int_pred_pattern_b<opc, asm, GPR64z, GPR64z>;
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def : InstAlias<asm # "\t$Rdn, $pattern",
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(!cast<Instruction>(NAME) GPR64z:$Rdn, sve_pred_enum:$pattern, 1), 1>;
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def : InstAlias<asm # "\t$Rdn",
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(!cast<Instruction>(NAME) GPR64z:$Rdn, 0b11111, 1), 2>;
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}
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//===----------------------------------------------------------------------===//
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// SVE Permute - Cross Lane Group

‎test/MC/AArch64/SVE/sqdecb-diagnostics.s

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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
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// ------------------------------------------------------------------------- //
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// Invalid result register
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sqdecb w0
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
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// CHECK-NEXT: sqdecb w0
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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sqdecb wsp
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
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// CHECK-NEXT: sqdecb wsp
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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sqdecb sp
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
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// CHECK-NEXT: sqdecb sp
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// ------------------------------------------------------------------------- //
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// Immediate not compatible with encode/decode function.
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sqdecb x0, all, mul #-1
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
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// CHECK-NEXT: sqdecb x0, all, mul #-1
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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sqdecb x0, all, mul #0
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
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// CHECK-NEXT: sqdecb x0, all, mul #0
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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sqdecb x0, all, mul #17
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
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// CHECK-NEXT: sqdecb x0, all, mul #17
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// ------------------------------------------------------------------------- //
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// Invalid predicate patterns
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sqdecb x0, vl512
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
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// CHECK-NEXT: sqdecb x0, vl512
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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sqdecb x0, vl9
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
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// CHECK-NEXT: sqdecb x0, vl9
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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sqdecb x0, #-1
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
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// CHECK-NEXT: sqdecb x0, #-1
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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sqdecb x0, #32
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
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// CHECK-NEXT: sqdecb x0, #32
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

‎test/MC/AArch64/SVE/sqdecb.s

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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
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// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
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// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
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// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
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// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
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// ---------------------------------------------------------------------------//
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// Test 64-bit form (x0) and its aliases
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// ---------------------------------------------------------------------------//
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sqdecb x0
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// CHECK-INST: sqdecb x0
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// CHECK-ENCODING: [0xe0,0xfb,0x30,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: e0 fb 30 04 <unknown>
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sqdecb x0, all
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// CHECK-INST: sqdecb x0
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// CHECK-ENCODING: [0xe0,0xfb,0x30,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: e0 fb 30 04 <unknown>
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sqdecb x0, all, mul #1
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// CHECK-INST: sqdecb x0
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// CHECK-ENCODING: [0xe0,0xfb,0x30,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: e0 fb 30 04 <unknown>
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sqdecb x0, all, mul #16
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// CHECK-INST: sqdecb x0, all, mul #16
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// CHECK-ENCODING: [0xe0,0xfb,0x3f,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: e0 fb 3f 04 <unknown>
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// ---------------------------------------------------------------------------//
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// Test all patterns for 64-bit form
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// ---------------------------------------------------------------------------//
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sqdecb x0, pow2
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// CHECK-INST: sqdecb x0, pow2
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// CHECK-ENCODING: [0x00,0xf8,0x30,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 f8 30 04 <unknown>
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sqdecb x0, vl1
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// CHECK-INST: sqdecb x0, vl1
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// CHECK-ENCODING: [0x20,0xf8,0x30,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 20 f8 30 04 <unknown>
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sqdecb x0, vl2
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// CHECK-INST: sqdecb x0, vl2
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// CHECK-ENCODING: [0x40,0xf8,0x30,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 40 f8 30 04 <unknown>
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sqdecb x0, vl3
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// CHECK-INST: sqdecb x0, vl3
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// CHECK-ENCODING: [0x60,0xf8,0x30,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 60 f8 30 04 <unknown>
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sqdecb x0, vl4
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// CHECK-INST: sqdecb x0, vl4
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// CHECK-ENCODING: [0x80,0xf8,0x30,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 80 f8 30 04 <unknown>
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sqdecb x0, vl5
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// CHECK-INST: sqdecb x0, vl5
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// CHECK-ENCODING: [0xa0,0xf8,0x30,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: a0 f8 30 04 <unknown>
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sqdecb x0, vl6
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// CHECK-INST: sqdecb x0, vl6
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// CHECK-ENCODING: [0xc0,0xf8,0x30,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: c0 f8 30 04 <unknown>
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sqdecb x0, vl7
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// CHECK-INST: sqdecb x0, vl7
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// CHECK-ENCODING: [0xe0,0xf8,0x30,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: e0 f8 30 04 <unknown>
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sqdecb x0, vl8
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// CHECK-INST: sqdecb x0, vl8
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// CHECK-ENCODING: [0x00,0xf9,0x30,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 f9 30 04 <unknown>
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sqdecb x0, vl16
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// CHECK-INST: sqdecb x0, vl16
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// CHECK-ENCODING: [0x20,0xf9,0x30,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 20 f9 30 04 <unknown>
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sqdecb x0, vl32
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// CHECK-INST: sqdecb x0, vl32
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// CHECK-ENCODING: [0x40,0xf9,0x30,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 40 f9 30 04 <unknown>
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sqdecb x0, vl64
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// CHECK-INST: sqdecb x0, vl64
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// CHECK-ENCODING: [0x60,0xf9,0x30,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 60 f9 30 04 <unknown>
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sqdecb x0, vl128
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// CHECK-INST: sqdecb x0, vl128
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// CHECK-ENCODING: [0x80,0xf9,0x30,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 80 f9 30 04 <unknown>
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sqdecb x0, vl256
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// CHECK-INST: sqdecb x0, vl256
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// CHECK-ENCODING: [0xa0,0xf9,0x30,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: a0 f9 30 04 <unknown>
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sqdecb x0, #14
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// CHECK-INST: sqdecb x0, #14
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// CHECK-ENCODING: [0xc0,0xf9,0x30,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: c0 f9 30 04 <unknown>
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sqdecb x0, #15
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// CHECK-INST: sqdecb x0, #15
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// CHECK-ENCODING: [0xe0,0xf9,0x30,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: e0 f9 30 04 <unknown>
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sqdecb x0, #16
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// CHECK-INST: sqdecb x0, #16
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// CHECK-ENCODING: [0x00,0xfa,0x30,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 fa 30 04 <unknown>
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sqdecb x0, #17
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// CHECK-INST: sqdecb x0, #17
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// CHECK-ENCODING: [0x20,0xfa,0x30,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 20 fa 30 04 <unknown>
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sqdecb x0, #18
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// CHECK-INST: sqdecb x0, #18
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// CHECK-ENCODING: [0x40,0xfa,0x30,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 40 fa 30 04 <unknown>
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sqdecb x0, #19
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// CHECK-INST: sqdecb x0, #19
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// CHECK-ENCODING: [0x60,0xfa,0x30,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 60 fa 30 04 <unknown>
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sqdecb x0, #20
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// CHECK-INST: sqdecb x0, #20
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// CHECK-ENCODING: [0x80,0xfa,0x30,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 80 fa 30 04 <unknown>
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sqdecb x0, #21
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// CHECK-INST: sqdecb x0, #21
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// CHECK-ENCODING: [0xa0,0xfa,0x30,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: a0 fa 30 04 <unknown>
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sqdecb x0, #22
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// CHECK-INST: sqdecb x0, #22
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// CHECK-ENCODING: [0xc0,0xfa,0x30,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: c0 fa 30 04 <unknown>
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sqdecb x0, #23
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// CHECK-INST: sqdecb x0, #23
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// CHECK-ENCODING: [0xe0,0xfa,0x30,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: e0 fa 30 04 <unknown>
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sqdecb x0, #24
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// CHECK-INST: sqdecb x0, #24
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// CHECK-ENCODING: [0x00,0xfb,0x30,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 fb 30 04 <unknown>
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sqdecb x0, #25
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// CHECK-INST: sqdecb x0, #25
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// CHECK-ENCODING: [0x20,0xfb,0x30,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 20 fb 30 04 <unknown>
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sqdecb x0, #26
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// CHECK-INST: sqdecb x0, #26
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// CHECK-ENCODING: [0x40,0xfb,0x30,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 40 fb 30 04 <unknown>
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sqdecb x0, #27
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// CHECK-INST: sqdecb x0, #27
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// CHECK-ENCODING: [0x60,0xfb,0x30,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 60 fb 30 04 <unknown>
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sqdecb x0, #28
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// CHECK-INST: sqdecb x0, #28
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// CHECK-ENCODING: [0x80,0xfb,0x30,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 80 fb 30 04 <unknown>

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