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arsenmarsenm
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Reapply "RegAllocFast: Rewrite and improve"
This reverts commit 73a6a16.
1 parent 944691f commit 89baeae

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‎lldb/test/Shell/SymbolFile/NativePDB/disassembly.cpp

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -28,11 +28,9 @@ int main(int argc, char **argv) {
2828
// CHECK-NEXT: disassembly.cpp.tmp.exe[{{.*}}] <+17>: mov dword ptr [rsp + 0x24], ecx
2929
// CHECK: ** 15 foo();
3030
// CHECK: disassembly.cpp.tmp.exe[{{.*}}] <+21>: call {{.*}} ; foo at disassembly.cpp:12
31-
// CHECK-NEXT: disassembly.cpp.tmp.exe[{{.*}}] <+26>: xor ecx, ecx
32-
// CHECK-NEXT: disassembly.cpp.tmp.exe[{{.*}}] <+28>: mov dword ptr [rsp + 0x20], eax
31+
// CHECK-NEXT: disassembly.cpp.tmp.exe[{{.*}}] <+26>: xor eax, eax
3332
// CHECK: ** 16 return 0;
3433
// CHECK-NEXT: 17 }
3534
// CHECK-NEXT: 18
36-
// CHECK: disassembly.cpp.tmp.exe[{{.*}}] <+32>: mov eax, ecx
37-
// CHECK-NEXT: disassembly.cpp.tmp.exe[{{.*}}] <+34>: add rsp, 0x38
38-
// CHECK-NEXT: disassembly.cpp.tmp.exe[{{.*}}] <+38>: ret
35+
// CHECK: disassembly.cpp.tmp.exe[{{.*}}] <+28>: add rsp, 0x38
36+
// CHECK-NEXT: disassembly.cpp.tmp.exe[{{.*}}] <+32>: ret

‎llvm/lib/CodeGen/RegAllocFast.cpp

Lines changed: 725 additions & 547 deletions
Large diffs are not rendered by default.

‎llvm/test/CodeGen/AArch64/GlobalISel/builtin-return-address-pacret.ll

Lines changed: 31 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
1-
;; RUN: llc -mtriple aarch64 -global-isel -O0 %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-NOP
2-
;; RUN: llc -mtriple aarch64 -mattr=+v8.3a -global-isel -O0 %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-V83
1+
;; RUN: llc -mtriple aarch64 -global-isel -O0 %s -o - | FileCheck -enable-var-scope %s --check-prefixes=CHECK,CHECK-NOP
2+
;; RUN: llc -mtriple aarch64 -mattr=+v8.3a -global-isel -O0 %s -o - | FileCheck -enable-var-scope %s --check-prefixes=CHECK,CHECK-V83
33
declare void @g0() #1
44
declare void @g1(i8*) #1
55
declare void @g2(i32, i8*) #1
@@ -18,22 +18,22 @@ entry:
1818
;; CHECK-LABEL: f0:
1919
;; CHECK-NOT: {{(mov|ldr)}} x30
2020
;; CHECK-NOP: hint #7
21-
;; CHECK-V83: xpaci x30
21+
;; CHECK-V83: mov [[COPY_X30:x[0-9]+]], x30
22+
;; CHECK-V83: xpaci [[COPY_X30]]
2223
;; CHECK: bl g1
2324
;; CHECK: ldr x[[T0:[0-9]+]], [x29]
2425
;; CHECK-NOP-NEXT: ldr x30, [x[[T0]], #8]
2526
;; CHECK-NOP-NEXT: hint #7
26-
;; CHECK-V83-NEXT: ldr x[[T0]], [x[[T0]], #8]
27-
;; CHECK-V83-NEXT: xpaci x[[T0]]
27+
;; CHECK-V83-NEXT: ldr x[[LD0:[0-9]+]], [x[[T0]], #8]
28+
;; CHECK-V83-NEXT: xpaci x[[LD0]]
2829
;; CHECK: bl g2
2930
;; CHECK: ldr x[[T1:[0-9]+]], [x29]
3031
;; CHECK-NEXT: ldr x[[T1]], [x[[T1]]]
3132
;; CHECK-NOP-NEXT: ldr x30, [x[[T1]], #8]
3233
;; CHECK-NOP-NEXT: hint #7
3334
;; CHECK-NOP-NEXT: mov x0, x30
34-
;; CHECK-V83-NEXT: ldr x[[T1]], [x[[T1]], #8]
35-
;; CHECK-V83-NEXT: xpaci x[[T1]]
36-
;; CHECK-V83-NEXT: mov x0, x[[T1]]
35+
;; CHECK-V83-NEXT: ldr x0, [x[[T1]], #8]
36+
;; CHECK-V83-NEXT: xpaci x0
3737

3838
define i8* @f1() #0 {
3939
entry:
@@ -49,23 +49,25 @@ entry:
4949
;; CHECK-NOP-DAG: str x30, [sp, #[[OFF:[0-9]+]]
5050
;; CHECK-NOP: ldr x30, [x[[T0]], #8]
5151
;; CHECK-NOP-NEXT: hint #7
52-
;; CHECK-V83: ldr x[[T0]], [x[[T0]], #8]
53-
;; CHECK-V83-NEXT: xpaci x[[T0]]
54-
;; CHECK-V83: str x30, [sp, #[[OFF:[0-9]+]]
52+
;; CHECK-V83-DAG: str x30, [sp, #[[OFF:[0-9]+]]
53+
;; CHECK-V83: ldr x[[T1:[0-9]+]], [x[[T0]], #8]
54+
;; CHECK-V83-NEXT: xpaci x[[T1]]
55+
5556
;; CHECK: bl g1
56-
;; CHECK: ldr x[[T1:[0-9]+]], [x29]
57-
;; CHECK-NEXT: ldr x[[T1]], [x[[T1]]]
58-
;; CHECK-NOP-NEXT: ldr x30, [x[[T1]], #8]
57+
;; CHECK: ldr x[[T2:[0-9]+]], [x29]
58+
;; CHECK-NEXT: ldr x[[T2]], [x[[T2]]]
59+
;; CHECK-NOP-NEXT: ldr x30, [x[[T2]], #8]
5960
;; CHECK-NOP-NEXT: hint #7
60-
;; CHECK-V83-NEXT: ldr x[[T1]], [x[[T1]], #8]
61-
;; CHECK-V83-NEXT: xpaci x[[T1]]
61+
;; CHECK-V83-NEXT: ldr x[[T3:[0-9]+]], [x[[T2]], #8]
62+
;; CHECK-V83-NEXT: xpaci x[[T3]]
6263
;; CHECK: bl g2
63-
;; CHECK: ldr x[[T2:[0-9]+]], [sp, #[[OFF]]]
64-
;; CHECK-NOP-NEXT: mov x30, x[[T2]]
64+
65+
;; CHECK-NOP: ldr x30, [sp, #[[OFF]]]
6566
;; CHECK-NOP-NEXT: hint #7
6667
;; CHECK-NOP-NEXT: mov x0, x30
67-
;; CHECK-V83-NEXT: xpaci x[[T2]]
68-
;; CHECK-V83-NEXT: mov x0, x[[T2]]
68+
69+
;; CHECK-V83: ldr x0, [sp, #[[OFF]]]
70+
;; CHECK-V83-NEXT: xpaci x0
6971
;; CHECK-NOT: x0
7072
;; CHECK: ret
7173

@@ -77,12 +79,12 @@ entry:
7779
}
7880
;; CHECK-LABEL: f2
7981
;; CHECK: bl g0
80-
;; CHECK: ldr x[[T0:[0-9]+]], [sp,
81-
;; CHECK-NOP-NEXT: mov x30, x[[T2]]
82+
;; CHECK-NOP: ldr x30, [sp,
8283
;; CHECK-NOP-NEXT: hint #7
8384
;; CHECK-NOP-NEXT: mov x0, x30
84-
;; CHECK-V83-NEXT: xpaci x[[T2]]
85-
;; CHECK-V83-NEXT: mov x0, x[[T2]]
85+
86+
;; CHECK-V83: ldr x0, [sp,
87+
;; CHECK-V83-NEXT: xpaci x0
8688
;; CHECK-NOT: x0
8789
;; CHECK: ret
8890

@@ -92,10 +94,12 @@ entry:
9294
ret i8* %0
9395
}
9496
;; CHECK-LABEL: f3:
95-
;; CHECK: str x30, [sp,
97+
;; CHECK-NOP: str x30, [sp,
9698
;; CHECK-NOP-NEXT: hint #7
97-
;; CHECK-V83-NEXT: xpaci x30
98-
;; CHECK-NEXT: mov x0, x30
99+
;; CHECK-NOP-NEXT: mov x0, x30
100+
101+
;; CHECK-V83: mov x0, x30
102+
;; CHECK-V83-NEXT: xpaci x0
99103
;; CHECK-NOT: x0
100104
;; CHECK: ret
101105
attributes #0 = { nounwind }

‎llvm/test/CodeGen/AArch64/GlobalISel/darwin-tls-call-clobber.ll

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -31,9 +31,8 @@ target triple = "arm64-apple-ios13.0.0"
3131
; This test checks that we don't re-use the register for the variable descriptor
3232
; for the second ldr.
3333
; CHECK: adrp x[[PTR1:[0-9]+]], _t_val@TLVPPAGE
34-
; CHECK: ldr x[[PTR1]], [x[[PTR1]], _t_val@TLVPPAGEOFF]
35-
; CHECK: ldr x[[FPTR:[0-9]+]], [x[[PTR1]]]
36-
; CHECK: mov x0, x[[PTR1]]
34+
; CHECK: ldr x0, [x[[PTR1]], _t_val@TLVPPAGEOFF]
35+
; CHECK: ldr x[[FPTR:[0-9]+]], [x0]
3736
; CHECK: blr x[[FPTR]]
3837

3938
define void @_Z4funcPKc(i8* %id) {

‎llvm/test/CodeGen/AArch64/arm64-fast-isel-br.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -94,7 +94,7 @@ entry:
9494
store i32 %c, i32* %c.addr, align 4
9595
store i64 %d, i64* %d.addr, align 8
9696
%0 = load i16, i16* %b.addr, align 2
97-
; CHECK: tbz w8, #0, LBB4_2
97+
; CHECK: tbz {{w[0-9]+}}, #0, LBB4_2
9898
%conv = trunc i16 %0 to i1
9999
br i1 %conv, label %if.then, label %if.end
100100

‎llvm/test/CodeGen/AArch64/arm64-fast-isel-call.ll

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -79,8 +79,7 @@ declare i32 @bar(i8 zeroext, i8 zeroext, i8 zeroext, i8 zeroext, i8 zeroext, i8
7979
define i32 @t2() {
8080
entry:
8181
; CHECK-LABEL: t2
82-
; CHECK: mov [[REG1:x[0-9]+]], xzr
83-
; CHECK: mov x0, [[REG1]]
82+
; CHECK: mov x0, xzr
8483
; CHECK: mov w1, #-8
8584
; CHECK: mov [[REG2:w[0-9]+]], #1023
8685
; CHECK: uxth w2, [[REG2]]

‎llvm/test/CodeGen/AArch64/arm64-fast-isel-conversion-fallback.ll

Lines changed: 16 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -4,9 +4,8 @@
44
define i32 @fptosi_wh(half %a) nounwind ssp {
55
entry:
66
; CHECK-LABEL: fptosi_wh
7-
; CHECK: fcvt s0, h0
8-
; CHECK: fcvtzs [[REG:w[0-9]+]], s0
9-
; CHECK: mov w0, [[REG]]
7+
; CHECK: fcvt [[REG:s[0-9]+]], h0
8+
; CHECK: fcvtzs w0, [[REG]]
109
%conv = fptosi half %a to i32
1110
ret i32 %conv
1211
}
@@ -15,9 +14,8 @@ entry:
1514
define i32 @fptoui_swh(half %a) nounwind ssp {
1615
entry:
1716
; CHECK-LABEL: fptoui_swh
18-
; CHECK: fcvt s0, h0
19-
; CHECK: fcvtzu [[REG:w[0-9]+]], s0
20-
; CHECK: mov w0, [[REG]]
17+
; CHECK: fcvt [[REG:s[0-9]+]], h0
18+
; CHECK: fcvtzu w0, [[REG]]
2119
%conv = fptoui half %a to i32
2220
ret i32 %conv
2321
}
@@ -26,8 +24,8 @@ entry:
2624
define half @sitofp_hw_i1(i1 %a) nounwind ssp {
2725
entry:
2826
; CHECK-LABEL: sitofp_hw_i1
29-
; CHECK: sbfx w8, w0, #0, #1
30-
; CHECK: scvtf s0, w8
27+
; CHECK: sbfx [[REG:w[0-9]+]], w0, #0, #1
28+
; CHECK: scvtf s0, [[REG]]
3129
; CHECK: fcvt h0, s0
3230
%conv = sitofp i1 %a to half
3331
ret half %conv
@@ -37,8 +35,8 @@ entry:
3735
define half @sitofp_hw_i8(i8 %a) nounwind ssp {
3836
entry:
3937
; CHECK-LABEL: sitofp_hw_i8
40-
; CHECK: sxtb w8, w0
41-
; CHECK: scvtf s0, w8
38+
; CHECK: sxtb [[REG:w[0-9]+]], w0
39+
; CHECK: scvtf s0, [[REG]]
4240
; CHECK: fcvt h0, s0
4341
%conv = sitofp i8 %a to half
4442
ret half %conv
@@ -48,8 +46,8 @@ entry:
4846
define half @sitofp_hw_i16(i16 %a) nounwind ssp {
4947
entry:
5048
; CHECK-LABEL: sitofp_hw_i16
51-
; CHECK: sxth w8, w0
52-
; CHECK: scvtf s0, w8
49+
; CHECK: sxth [[REG:w[0-9]+]], w0
50+
; CHECK: scvtf s0, [[REG]]
5351
; CHECK: fcvt h0, s0
5452
%conv = sitofp i16 %a to half
5553
ret half %conv
@@ -79,8 +77,8 @@ entry:
7977
define half @uitofp_hw_i1(i1 %a) nounwind ssp {
8078
entry:
8179
; CHECK-LABEL: uitofp_hw_i1
82-
; CHECK: and w8, w0, #0x1
83-
; CHECK: ucvtf s0, w8
80+
; CHECK: and [[REG:w[0-9]+]], w0, #0x1
81+
; CHECK: ucvtf s0, [[REG]]
8482
; CHECK: fcvt h0, s0
8583
%conv = uitofp i1 %a to half
8684
ret half %conv
@@ -90,8 +88,8 @@ entry:
9088
define half @uitofp_hw_i8(i8 %a) nounwind ssp {
9189
entry:
9290
; CHECK-LABEL: uitofp_hw_i8
93-
; CHECK: and w8, w0, #0xff
94-
; CHECK: ucvtf s0, w8
91+
; CHECK: and [[REG:w[0-9]+]], w0, #0xff
92+
; CHECK: ucvtf s0, [[REG]]
9593
; CHECK: fcvt h0, s0
9694
%conv = uitofp i8 %a to half
9795
ret half %conv
@@ -101,8 +99,8 @@ entry:
10199
define half @uitofp_hw_i16(i16 %a) nounwind ssp {
102100
entry:
103101
; CHECK-LABEL: uitofp_hw_i16
104-
; CHECK: and w8, w0, #0xffff
105-
; CHECK: ucvtf s0, w8
102+
; CHECK: and [[REG:w[0-9]+]], w0, #0xffff
103+
; CHECK: ucvtf s0, [[REG]]
106104
; CHECK: fcvt h0, s0
107105
%conv = uitofp i16 %a to half
108106
ret half %conv

‎llvm/test/CodeGen/AArch64/arm64-fast-isel-conversion.ll

Lines changed: 29 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
; RUN: llc -O0 -fast-isel -fast-isel-abort=1 -verify-machineinstrs -mtriple=arm64-apple-darwin -mcpu=cyclone < %s | FileCheck %s
1+
; RUN: llc -O0 -fast-isel -fast-isel-abort=1 -verify-machineinstrs -mtriple=arm64-apple-darwin -mcpu=cyclone < %s | FileCheck -enable-var-scope %s
22

33
;; Test various conversions.
44
define zeroext i32 @trunc_(i8 zeroext %a, i16 zeroext %b, i32 %c, i64 %d) nounwind ssp {
@@ -49,13 +49,12 @@ entry:
4949
; CHECK: strh w1, [sp, #12]
5050
; CHECK: str w2, [sp, #8]
5151
; CHECK: str x3, [sp]
52-
; CHECK: ldrb w8, [sp, #15]
53-
; CHECK: strh w8, [sp, #12]
54-
; CHECK: ldrh w8, [sp, #12]
55-
; CHECK: str w8, [sp, #8]
56-
; CHECK: ldr w8, [sp, #8]
57-
; CHECK: ; kill: def $x8 killed $w8
58-
; CHECK: str x8, [sp]
52+
; CHECK: ldrb [[REG0:w[0-9]+]], [sp, #15]
53+
; CHECK: strh [[REG0]], [sp, #12]
54+
; CHECK: ldrh [[REG1:w[0-9]+]], [sp, #12]
55+
; CHECK: str [[REG1]], [sp, #8]
56+
; CHECK: ldr w[[REG2:[0-9]+]], [sp, #8]
57+
; CHECK: str x[[REG2]], [sp]
5958
; CHECK: ldr x0, [sp]
6059
; CHECK: ret
6160
%a.addr = alloca i8, align 1
@@ -105,12 +104,12 @@ entry:
105104
; CHECK: strh w1, [sp, #12]
106105
; CHECK: str w2, [sp, #8]
107106
; CHECK: str x3, [sp]
108-
; CHECK: ldrsb w8, [sp, #15]
109-
; CHECK: strh w8, [sp, #12]
110-
; CHECK: ldrsh w8, [sp, #12]
111-
; CHECK: str w8, [sp, #8]
112-
; CHECK: ldrsw x8, [sp, #8]
113-
; CHECK: str x8, [sp]
107+
; CHECK: ldrsb [[REG0:w[0-9]+]], [sp, #15]
108+
; CHECK: strh [[REG0]], [sp, #12]
109+
; CHECK: ldrsh [[REG1:w[0-9]+]], [sp, #12]
110+
; CHECK: str [[REG1]], [sp, #8]
111+
; CHECK: ldrsw [[REG2:x[0-9]+]], [sp, #8]
112+
; CHECK: str [[REG2]], [sp]
114113
; CHECK: ldr x0, [sp]
115114
; CHECK: ret
116115
%a.addr = alloca i8, align 1
@@ -166,8 +165,8 @@ entry:
166165
define signext i16 @sext_i1_i16(i1 %a) nounwind ssp {
167166
entry:
168167
; CHECK-LABEL: sext_i1_i16
169-
; CHECK: sbfx w8, w0, #0, #1
170-
; CHECK-NEXT: sxth w0, w8
168+
; CHECK: sbfx [[REG:w[0-9]+]], w0, #0, #1
169+
; CHECK: sxth w0, [[REG]]
171170
%conv = sext i1 %a to i16
172171
ret i16 %conv
173172
}
@@ -176,8 +175,8 @@ entry:
176175
define signext i8 @sext_i1_i8(i1 %a) nounwind ssp {
177176
entry:
178177
; CHECK-LABEL: sext_i1_i8
179-
; CHECK: sbfx w8, w0, #0, #1
180-
; CHECK-NEXT: sxtb w0, w8
178+
; CHECK: sbfx [[REG:w[0-9]+]], w0, #0, #1
179+
; CHECK: sxtb w0, [[REG]]
181180
%conv = sext i1 %a to i8
182181
ret i8 %conv
183182
}
@@ -240,8 +239,8 @@ entry:
240239
define float @sitofp_sw_i1(i1 %a) nounwind ssp {
241240
entry:
242241
; CHECK-LABEL: sitofp_sw_i1
243-
; CHECK: sbfx w8, w0, #0, #1
244-
; CHECK: scvtf s0, w8
242+
; CHECK: sbfx [[REG:w[0-9]+]], w0, #0, #1
243+
; CHECK: scvtf s0, [[REG]]
245244
%conv = sitofp i1 %a to float
246245
ret float %conv
247246
}
@@ -250,8 +249,8 @@ entry:
250249
define float @sitofp_sw_i8(i8 %a) nounwind ssp {
251250
entry:
252251
; CHECK-LABEL: sitofp_sw_i8
253-
; CHECK: sxtb w8, w0
254-
; CHECK: scvtf s0, w8
252+
; CHECK: sxtb [[REG:w[0-9]+]], w0
253+
; CHECK: scvtf s0, [[REG]]
255254
%conv = sitofp i8 %a to float
256255
ret float %conv
257256
}
@@ -304,8 +303,8 @@ entry:
304303
define float @uitofp_sw_i1(i1 %a) nounwind ssp {
305304
entry:
306305
; CHECK-LABEL: uitofp_sw_i1
307-
; CHECK: and w8, w0, #0x1
308-
; CHECK: ucvtf s0, w8
306+
; CHECK: and [[REG:w[0-9]+]], w0, #0x1
307+
; CHECK: ucvtf s0, [[REG]]
309308
%conv = uitofp i1 %a to float
310309
ret float %conv
311310
}
@@ -374,7 +373,8 @@ entry:
374373
define zeroext i16 @i64_trunc_i16(i64 %a) nounwind ssp {
375374
entry:
376375
; CHECK-LABEL: i64_trunc_i16
377-
; CHECK: and [[REG2:w[0-9]+]], w0, #0xffff
376+
; CHECK: mov x[[TMP:[0-9]+]], x0
377+
; CHECK: and [[REG2:w[0-9]+]], w[[TMP]], #0xffff{{$}}
378378
; CHECK: uxth w0, [[REG2]]
379379
%conv = trunc i64 %a to i16
380380
ret i16 %conv
@@ -383,7 +383,8 @@ entry:
383383
define zeroext i8 @i64_trunc_i8(i64 %a) nounwind ssp {
384384
entry:
385385
; CHECK-LABEL: i64_trunc_i8
386-
; CHECK: and [[REG2:w[0-9]+]], w0, #0xff
386+
; CHECK: mov x[[TMP:[0-9]+]], x0
387+
; CHECK: and [[REG2:w[0-9]+]], w[[TMP]], #0xff{{$}}
387388
; CHECK: uxtb w0, [[REG2]]
388389
%conv = trunc i64 %a to i8
389390
ret i8 %conv
@@ -392,7 +393,8 @@ entry:
392393
define zeroext i1 @i64_trunc_i1(i64 %a) nounwind ssp {
393394
entry:
394395
; CHECK-LABEL: i64_trunc_i1
395-
; CHECK: and [[REG2:w[0-9]+]], w0, #0x1
396+
; CHECK: mov x[[TMP:[0-9]+]], x0
397+
; CHECK: and [[REG2:w[0-9]+]], w[[TMP]], #0x1{{$}}
396398
; CHECK: and w0, [[REG2]], #0x1
397399
%conv = trunc i64 %a to i1
398400
ret i1 %conv

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