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16 | 16 | namespace llvm {
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17 | 17 | namespace RISCV {
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18 | 18 | enum Fixups {
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19 |
| - // fixup_riscv_hi20 - 20-bit fixup corresponding to hi(foo) for |
20 |
| - // instructions like lui |
| 19 | + // 20-bit fixup corresponding to %hi(foo) for instructions like lui |
21 | 20 | fixup_riscv_hi20 = FirstTargetFixupKind,
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22 |
| - // fixup_riscv_lo12_i - 12-bit fixup corresponding to lo(foo) for |
23 |
| - // instructions like addi |
| 21 | + // 12-bit fixup corresponding to %lo(foo) for instructions like addi |
24 | 22 | fixup_riscv_lo12_i,
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25 |
| - // fixup_riscv_lo12_s - 12-bit fixup corresponding to lo(foo) for |
26 |
| - // the S-type store instructions |
| 23 | + // 12-bit fixup corresponding to %lo(foo) for the S-type store instructions |
27 | 24 | fixup_riscv_lo12_s,
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28 |
| - // fixup_riscv_pcrel_hi20 - 20-bit fixup corresponding to pcrel_hi(foo) for |
29 |
| - // instructions like auipc |
| 25 | + // 20-bit fixup corresponding to %pcrel_hi(foo) for instructions like auipc |
30 | 26 | fixup_riscv_pcrel_hi20,
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31 |
| - // fixup_riscv_pcrel_lo12_i - 12-bit fixup corresponding to pcrel_lo(foo) for |
32 |
| - // instructions like addi |
| 27 | + // 12-bit fixup corresponding to %pcrel_lo(foo) for instructions like addi |
33 | 28 | fixup_riscv_pcrel_lo12_i,
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34 |
| - // fixup_riscv_pcrel_lo12_s - 12-bit fixup corresponding to pcrel_lo(foo) for |
35 |
| - // the S-type store instructions |
| 29 | + // 12-bit fixup corresponding to %pcrel_lo(foo) for the S-type store |
| 30 | + // instructions |
36 | 31 | fixup_riscv_pcrel_lo12_s,
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37 |
| - // fixup_riscv_got_hi20 - 20-bit fixup corresponding to got_pcrel_hi(foo) for |
38 |
| - // instructions like auipc |
| 32 | + // 20-bit fixup corresponding to %got_pcrel_hi(foo) for instructions like |
| 33 | + // auipc |
39 | 34 | fixup_riscv_got_hi20,
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40 |
| - // fixup_riscv_tprel_hi20 - 20-bit fixup corresponding to tprel_hi(foo) for |
41 |
| - // instructions like lui |
| 35 | + // 20-bit fixup corresponding to %tprel_hi(foo) for instructions like lui |
42 | 36 | fixup_riscv_tprel_hi20,
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43 |
| - // fixup_riscv_tprel_lo12_i - 12-bit fixup corresponding to tprel_lo(foo) for |
44 |
| - // instructions like addi |
| 37 | + // 12-bit fixup corresponding to %tprel_lo(foo) for instructions like addi |
45 | 38 | fixup_riscv_tprel_lo12_i,
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46 |
| - // fixup_riscv_tprel_lo12_s - 12-bit fixup corresponding to tprel_lo(foo) for |
47 |
| - // the S-type store instructions |
| 39 | + // 12-bit fixup corresponding to %tprel_lo(foo) for the S-type store |
| 40 | + // instructions |
48 | 41 | fixup_riscv_tprel_lo12_s,
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49 |
| - // fixup_riscv_tprel_add - A fixup corresponding to %tprel_add(foo) for the |
50 |
| - // add_tls instruction. Used to provide a hint to the linker. |
| 42 | + // Fixup corresponding to %tprel_add(foo) for PseudoAddTPRel, used as a linker |
| 43 | + // hint |
51 | 44 | fixup_riscv_tprel_add,
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52 |
| - // fixup_riscv_tls_got_hi20 - 20-bit fixup corresponding to |
53 |
| - // tls_ie_pcrel_hi(foo) for instructions like auipc |
| 45 | + // 20-bit fixup corresponding to %tls_ie_pcrel_hi(foo) for instructions like |
| 46 | + // auipc |
54 | 47 | fixup_riscv_tls_got_hi20,
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55 |
| - // fixup_riscv_tls_gd_hi20 - 20-bit fixup corresponding to |
56 |
| - // tls_gd_pcrel_hi(foo) for instructions like auipc |
| 48 | + // 20-bit fixup corresponding to %tls_gd_pcrel_hi(foo) for instructions like |
| 49 | + // auipc |
57 | 50 | fixup_riscv_tls_gd_hi20,
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58 |
| - // fixup_riscv_jal - 20-bit fixup for symbol references in the jal |
59 |
| - // instruction |
| 51 | + // 20-bit fixup for symbol references in the jal instruction |
60 | 52 | fixup_riscv_jal,
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61 |
| - // fixup_riscv_branch - 12-bit fixup for symbol references in the branch |
62 |
| - // instructions |
| 53 | + // 12-bit fixup for symbol references in the branch instructions |
63 | 54 | fixup_riscv_branch,
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64 |
| - // fixup_riscv_rvc_jump - 11-bit fixup for symbol references in the |
65 |
| - // compressed jump instruction |
| 55 | + // 11-bit fixup for symbol references in the compressed jump instruction |
66 | 56 | fixup_riscv_rvc_jump,
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67 |
| - // fixup_riscv_rvc_branch - 8-bit fixup for symbol references in the |
68 |
| - // compressed branch instruction |
| 57 | + // 8-bit fixup for symbol references in the compressed branch instruction |
69 | 58 | fixup_riscv_rvc_branch,
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70 |
| - // fixup_riscv_call - A fixup representing a call attached to the auipc |
| 59 | + // Fixup representing a legacy no-pic function call attached to the auipc |
71 | 60 | // instruction in a pair composed of adjacent auipc+jalr instructions.
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72 | 61 | fixup_riscv_call,
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73 |
| - // fixup_riscv_call_plt - A fixup representing a procedure linkage table call |
74 |
| - // attached to the auipc instruction in a pair composed of adjacent auipc+jalr |
75 |
| - // instructions. |
| 62 | + // Fixup representing a function call attached to the auipc instruction in a |
| 63 | + // pair composed of adjacent auipc+jalr instructions. |
76 | 64 | fixup_riscv_call_plt,
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77 |
| - // fixup_riscv_relax - Used to generate an R_RISCV_RELAX relocation type, |
78 |
| - // which indicates the linker may relax the instruction pair. |
| 65 | + // Used to generate an R_RISCV_RELAX relocation, which indicates the linker |
| 66 | + // may relax the instruction pair. |
79 | 67 | fixup_riscv_relax,
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80 |
| - // fixup_riscv_align - Used to generate an R_RISCV_ALIGN relocation type, |
81 |
| - // which indicates the linker should fixup the alignment after linker |
82 |
| - // relaxation. |
| 68 | + // Used to generate an R_RISCV_ALIGN relocation, which indicates the linker |
| 69 | + // should fixup the alignment after linker relaxation. |
83 | 70 | fixup_riscv_align,
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84 | 71 |
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85 |
| - // fixup_riscv_invalid - used as a sentinel and a marker, must be last fixup |
| 72 | + // Used as a sentinel, must be the last |
86 | 73 | fixup_riscv_invalid,
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87 | 74 | NumTargetFixupKinds = fixup_riscv_invalid - FirstTargetFixupKind
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88 | 75 | };
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