From bd0b266619629f216b4fea920e23cc4b9557639d Mon Sep 17 00:00:00 2001 From: Gunar Schorcht Date: Thu, 16 Jul 2020 13:30:32 +0200 Subject: [PATCH] cpu/stm32*: changes for new GPIO API --- cpu/stm32/Kconfig | 1 + cpu/stm32/Makefile.dep | 3 + cpu/stm32/Makefile.features | 2 +- cpu/stm32/include/gpio_arch.h | 209 +++++++++++++++++++++++++++++++++ cpu/stm32/include/periph_cpu.h | 186 ++++++----------------------- cpu/stm32/periph/adc_f1.c | 2 +- cpu/stm32/periph/adc_l1.c | 2 +- cpu/stm32/periph/adc_l4.c | 8 +- cpu/stm32/periph/can.c | 4 +- cpu/stm32/periph/eth.c | 1 + cpu/stm32/periph/gpio_all.c | 163 ++++++++++++------------- cpu/stm32/periph/gpio_f1.c | 141 +++++++++------------- cpu/stm32/periph/i2c_2.c | 4 +- cpu/stm32/periph/pwm.c | 6 +- cpu/stm32/periph/qdec.c | 2 +- cpu/stm32/periph/spi.c | 24 ++-- cpu/stm32/periph/uart.c | 10 +- cpu/stm32/periph/usbdev.c | 1 + 18 files changed, 409 insertions(+), 360 deletions(-) create mode 100644 cpu/stm32/include/gpio_arch.h diff --git a/cpu/stm32/Kconfig b/cpu/stm32/Kconfig index 101d237c960b..132c6573028e 100644 --- a/cpu/stm32/Kconfig +++ b/cpu/stm32/Kconfig @@ -11,6 +11,7 @@ config CPU_STM32 select HAS_BOOTLOADER_STM32 select HAS_PERIPH_CPUID select HAS_PERIPH_GPIO + select HAS_PERIPH_GPIO_EXP select HAS_PERIPH_GPIO_IRQ select HAS_PUF_SRAM select HAS_PERIPH_TIMER_PERIODIC diff --git a/cpu/stm32/Makefile.dep b/cpu/stm32/Makefile.dep index aeba105e33d0..863fac102e79 100644 --- a/cpu/stm32/Makefile.dep +++ b/cpu/stm32/Makefile.dep @@ -16,6 +16,9 @@ ifneq (,$(filter periph_uart_nonblocking,$(USEMODULE))) USEMODULE += tsrb endif +# 16 bit GPIO pin mask required +USEMODULE += gpio_mask_16bit + ifneq (,$(filter stm32_eth,$(USEMODULE))) FEATURES_REQUIRED += periph_eth USEMODULE += netdev_eth diff --git a/cpu/stm32/Makefile.features b/cpu/stm32/Makefile.features index 106c07a154bc..a6755e2ed127 100644 --- a/cpu/stm32/Makefile.features +++ b/cpu/stm32/Makefile.features @@ -3,7 +3,7 @@ include $(RIOTCPU)/stm32/stm32_info.mk FEATURES_PROVIDED += bootloader_stm32 FEATURES_PROVIDED += cpu_stm32$(CPU_FAM) FEATURES_PROVIDED += periph_cpuid -FEATURES_PROVIDED += periph_gpio periph_gpio_irq +FEATURES_PROVIDED += periph_gpio periph_gpio_irq periph_gpio_exp FEATURES_PROVIDED += puf_sram FEATURES_PROVIDED += periph_timer_periodic FEATURES_PROVIDED += periph_uart_modecfg diff --git a/cpu/stm32/include/gpio_arch.h b/cpu/stm32/include/gpio_arch.h new file mode 100644 index 000000000000..c60ecff3d4d4 --- /dev/null +++ b/cpu/stm32/include/gpio_arch.h @@ -0,0 +1,209 @@ +/* + * Copyright (C) 2016 Freie Universität Berlin + * 2017 OTA keys S.A. + * 2020 Gunar Schorcht + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup cpu_stm32 + * @{ + * + * @file + * @brief Shared CPU specific GPIO definitions for the STM32 family + * + * @author Hauke Petersen + * @author Vincent Dupont + * @author Gunar Schorcht + */ + +#ifndef GPIO_ARCH_H +#define GPIO_ARCH_H + +#include "cpu.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Define a magic number that tells us to use hardware chip select + * + * We use a random value here, that does clearly differentiate from any possible + * GPIO pin number. + */ +#define SPI_HWCS_MASK (0x80) + +/** + * @brief Override the default SPI hardware chip select access macro + * + * Since the CPU does only support one single hardware chip select line, we can + * detect the usage of non-valid lines by comparing to SPI_HWCS_MASK. + */ +#define SPI_HWCS(x) ((gpio_t){ .port.dev = NULL, .pin = SPI_HWCS_MASK | x }) + +/** + * @brief Test whether a GPIO pin is defined as SPI hardware chip select + */ +#define SPI_HWCS_IS(x) (x.port.dev == NULL && ((x.pin & SPI_HWCS_MASK) == SPI_HWCS_MASK)) + +/** + * @brief Base register address for MCU GPIO ports + * + * For all STM32 MCUs except the STM32F1 family, masking the last 14 bits + * corresponds to the base address of GPIO port A `GPIOA_BASE`, where these + * 14 bits are zero. For the STM32F1 family, however, these 14 bits are not + * zero because the base address of GPIO port A starts at + * `APB2PERIPH_BASE + 0x800`. Therefore, for the STM32F1 family, `GPIOA_BASE` + * cannot be used as the base address when testing for an MCU GPIO port. + * Instead `APB2PERIPH_BASE` must be used for STM32F1 family. + */ +#ifdef STM32F1 +#define GPIO_CPU_PORT_BASE (APB2PERIPH_BASE) +#else +#define GPIO_CPU_PORT_BASE (GPIOA_BASE) +#endif + +/** + * @brief Mask for MCU port register addresses + */ +#define GPIO_CPU_PORT_MASK (0xffffc000UL) + +/** + * @brief Convert MCU port number into its register address + */ +#define GPIO_CPU_PORT(port) (GPIOA_BASE + (port << 10)) + +/** + * @brief Convert a MCU port register address into its port number + * + */ +#ifdef STM32F1 +#define GPIO_CPU_PORT_NUM(port) (((port >> 10) & 0x0f) - 2) +#else +#define GPIO_CPU_PORT_NUM(port) ((port >> 10) & 0x0f) +#endif + +/** + * @brief Available MUX values for configuring a pin's alternate function + */ +typedef enum { +#ifdef CPU_FAM_STM32F1 + GPIO_AF_OUT_PP = 0xb, /**< alternate function output - push-pull */ + GPIO_AF_OUT_OD = 0xf, /**< alternate function output - open-drain */ +#else + GPIO_AF0 = 0, /**< use alternate function 0 */ + GPIO_AF1, /**< use alternate function 1 */ + GPIO_AF2, /**< use alternate function 2 */ + GPIO_AF3, /**< use alternate function 3 */ + GPIO_AF4, /**< use alternate function 4 */ + GPIO_AF5, /**< use alternate function 5 */ + GPIO_AF6, /**< use alternate function 6 */ + GPIO_AF7, /**< use alternate function 7 */ +#ifndef CPU_FAM_STM32F0 + GPIO_AF8, /**< use alternate function 8 */ + GPIO_AF9, /**< use alternate function 9 */ + GPIO_AF10, /**< use alternate function 10 */ + GPIO_AF11, /**< use alternate function 11 */ + GPIO_AF12, /**< use alternate function 12 */ + GPIO_AF13, /**< use alternate function 13 */ + GPIO_AF14, /**< use alternate function 14 */ + GPIO_AF15 /**< use alternate function 15 */ +#endif +#endif +} gpio_af_t; + +#ifdef CPU_FAM_STM32F1 +#ifndef DOXYGEN +/** + * @brief Generate GPIO mode bitfields + * + * We use 4 bit to determine the pin functions: + * - bit 4: ODR value + * - bit 2+3: in/out + * - bit 1: PU enable + * - bit 2: OD enable + */ +#define GPIO_MODE(mode, cnf, odr) (mode | (cnf << 2) | (odr << 4)) + +/** + * @brief Override GPIO mode options + * + * We use 4 bit to encode CNF and MODE. + * @{ + */ +#define HAVE_GPIO_MODE_T +typedef enum { + GPIO_IN = GPIO_MODE(0, 1, 0), /**< input w/o pull R */ + GPIO_IN_PD = GPIO_MODE(0, 2, 0), /**< input with pull-down */ + GPIO_IN_PU = GPIO_MODE(0, 2, 1), /**< input with pull-up */ + GPIO_OUT = GPIO_MODE(3, 0, 0), /**< push-pull output */ + GPIO_OD = GPIO_MODE(3, 1, 0), /**< open-drain w/o pull R */ + GPIO_OD_PU = (0xff) /**< not supported by HW */ +} gpio_mode_t; +/** @} */ +#endif /* ndef DOXYGEN */ + +/** + * @brief Override values for pull register configuration + * @{ + */ +#define HAVE_GPIO_PP_T +typedef enum { + GPIO_NOPULL = 4, /**< do not use internal pull resistors */ + GPIO_PULLUP = 9, /**< enable internal pull-up resistor */ + GPIO_PULLDOWN = 8 /**< enable internal pull-down resistor */ +} gpio_pp_t; +/** @} */ +#else /* CPU_FAM_STM32F1 */ +/** + * @brief Generate GPIO mode bitfields + * + * We use 5 bit to encode the mode: + * - bit 0+1: pin mode (input / output) + * - bit 2+3: pull resistor configuration + * - bit 4: output type (0: push-pull, 1: open-drain) + */ +#define GPIO_MODE(io, pr, ot) ((io << 0) | (pr << 2) | (ot << 4)) + +#ifndef DOXYGEN +/** + * @brief Override GPIO mode options + * @{ + */ +#define HAVE_GPIO_MODE_T +typedef enum { + GPIO_IN = GPIO_MODE(0, 0, 0), /**< input w/o pull R */ + GPIO_IN_PD = GPIO_MODE(0, 2, 0), /**< input with pull-down */ + GPIO_IN_PU = GPIO_MODE(0, 1, 0), /**< input with pull-up */ + GPIO_OUT = GPIO_MODE(1, 0, 0), /**< push-pull output */ + GPIO_OD = GPIO_MODE(1, 0, 1), /**< open-drain w/o pull R */ + GPIO_OD_PU = GPIO_MODE(1, 1, 1) /**< open-drain with pull-up */ +} gpio_mode_t; +/** @} */ +#endif /* ndef DOXYGEN */ +#endif /* ndef CPU_FAM_STM32F1 */ + +#ifndef DOXYGEN +/** + * @brief Override flank configuration values + * @{ + */ +#define HAVE_GPIO_FLANK_T +typedef enum { + GPIO_RISING = 1, /**< emit interrupt on rising flank */ + GPIO_FALLING = 2, /**< emit interrupt on falling flank */ + GPIO_BOTH = 3 /**< emit interrupt on both flanks */ +} gpio_flank_t; +/** @} */ +#endif /* ndef DOXYGEN */ + +#ifdef __cplusplus +} +#endif + +#endif /* GPIO_ARCH_H */ +/** @} */ diff --git a/cpu/stm32/include/periph_cpu.h b/cpu/stm32/include/periph_cpu.h index 37fd12278fda..77bdb462fbdc 100644 --- a/cpu/stm32/include/periph_cpu.h +++ b/cpu/stm32/include/periph_cpu.h @@ -23,6 +23,7 @@ #include "cpu.h" #include "macros/units.h" +#include "periph/gpio.h" #if defined(CPU_FAM_STM32F0) #include "periph/f0/periph_cpu.h" @@ -194,26 +195,6 @@ typedef enum { #endif } bus_t; -#ifndef DOXYGEN -/** - * @brief Overwrite the default gpio_t type definition - * @{ - */ -#define HAVE_GPIO_T -typedef uint32_t gpio_t; -/** @} */ -#endif - -/** - * @brief Definition of a fitting UNDEF value - */ -#define GPIO_UNDEF (0xffffffff) - -/** - * @brief Define a CPU specific GPIO pin generator macro - */ -#define GPIO_PIN(x, y) ((GPIOA_BASE + (x << 10)) | y) - /** * @brief Available GPIO ports */ @@ -254,20 +235,37 @@ enum { }; /** - * @brief Define a magic number that tells us to use hardware chip select - * - * We use a random value here, that does clearly differentiate from any possible - * GPIO_PIN(x) value. - */ -#define SPI_HWCS_MASK (0xffffff00) - -/** - * @brief Override the default SPI hardware chip select access macro + *@brief The port number of the first GPIO expander port * - * Since the CPU does only support one single hardware chip select line, we can - * detect the usage of non-valid lines by comparing to SPI_HWCS_VALID. - */ -#define SPI_HWCS(x) (SPI_HWCS_MASK | x) + * GPIO_EXP_PORT defines the number of the first GPIO expander port. The + * port number is a sequential number that goes from 0 to `GPIO_EXP_PORT-1` + * for MCU ports. For GPIO expanders, the port number is derived from + * `GPIO_EXP_PORT` and their index in the GPIO device table #gpio_devs as + * offset. + */ +#if defined(GPIOK) +#define GPIO_EXP_PORT 11 +#elif defined(GPIOJ) +#define GPIO_EXP_PORT 10 +#elif defined(GPIOI) +#define GPIO_EXP_PORT 9 +#elif defined(GPIOH) +#define GPIO_EXP_PORT 8 +#elif defined(GPIOG) +#define GPIO_EXP_PORT 7 +#elif defined(GPIOF) +#define GPIO_EXP_PORT 6 +#elif defined(GPIOE) +#define GPIO_EXP_PORT 5 +#elif defined(GPIOD) +#define GPIO_EXP_PORT 4 +#elif defined(GPIOC) +#define GPIO_EXP_PORT 3 +#elif defined(GPIOB) +#define GPIO_EXP_PORT 2 +#else +#define GPIO_EXP_PORT 1 +#endif /** * @name Use the shared I2C functions @@ -284,120 +282,6 @@ enum { #endif /** @} */ -/** - * @brief Available MUX values for configuring a pin's alternate function - */ -typedef enum { -#ifdef CPU_FAM_STM32F1 - GPIO_AF_OUT_PP = 0xb, /**< alternate function output - push-pull */ - GPIO_AF_OUT_OD = 0xf, /**< alternate function output - open-drain */ -#else - GPIO_AF0 = 0, /**< use alternate function 0 */ - GPIO_AF1, /**< use alternate function 1 */ - GPIO_AF2, /**< use alternate function 2 */ - GPIO_AF3, /**< use alternate function 3 */ - GPIO_AF4, /**< use alternate function 4 */ - GPIO_AF5, /**< use alternate function 5 */ - GPIO_AF6, /**< use alternate function 6 */ - GPIO_AF7, /**< use alternate function 7 */ -#ifndef CPU_FAM_STM32F0 - GPIO_AF8, /**< use alternate function 8 */ - GPIO_AF9, /**< use alternate function 9 */ - GPIO_AF10, /**< use alternate function 10 */ - GPIO_AF11, /**< use alternate function 11 */ - GPIO_AF12, /**< use alternate function 12 */ - GPIO_AF13, /**< use alternate function 13 */ - GPIO_AF14, /**< use alternate function 14 */ - GPIO_AF15 /**< use alternate function 15 */ -#endif -#endif -} gpio_af_t; - -#ifdef CPU_FAM_STM32F1 -#ifndef DOXYGEN -/** - * @brief Generate GPIO mode bitfields - * - * We use 4 bit to determine the pin functions: - * - bit 4: ODR value - * - bit 2+3: in/out - * - bit 1: PU enable - * - bit 2: OD enable - */ -#define GPIO_MODE(mode, cnf, odr) (mode | (cnf << 2) | (odr << 4)) - -/** - * @brief Override GPIO mode options - * - * We use 4 bit to encode CNF and MODE. - * @{ - */ -#define HAVE_GPIO_MODE_T -typedef enum { - GPIO_IN = GPIO_MODE(0, 1, 0), /**< input w/o pull R */ - GPIO_IN_PD = GPIO_MODE(0, 2, 0), /**< input with pull-down */ - GPIO_IN_PU = GPIO_MODE(0, 2, 1), /**< input with pull-up */ - GPIO_OUT = GPIO_MODE(3, 0, 0), /**< push-pull output */ - GPIO_OD = GPIO_MODE(3, 1, 0), /**< open-drain w/o pull R */ - GPIO_OD_PU = (0xff) /**< not supported by HW */ -} gpio_mode_t; -/** @} */ -#endif /* ndef DOXYGEN */ - -/** - * @brief Override values for pull register configuration - * @{ - */ -#define HAVE_GPIO_PP_T -typedef enum { - GPIO_NOPULL = 4, /**< do not use internal pull resistors */ - GPIO_PULLUP = 9, /**< enable internal pull-up resistor */ - GPIO_PULLDOWN = 8 /**< enable internal pull-down resistor */ -} gpio_pp_t; -/** @} */ -#else /* CPU_FAM_STM32F1 */ -/** - * @brief Generate GPIO mode bitfields - * - * We use 5 bit to encode the mode: - * - bit 0+1: pin mode (input / output) - * - bit 2+3: pull resistor configuration - * - bit 4: output type (0: push-pull, 1: open-drain) - */ -#define GPIO_MODE(io, pr, ot) ((io << 0) | (pr << 2) | (ot << 4)) - -#ifndef DOXYGEN -/** - * @brief Override GPIO mode options - * @{ - */ -#define HAVE_GPIO_MODE_T -typedef enum { - GPIO_IN = GPIO_MODE(0, 0, 0), /**< input w/o pull R */ - GPIO_IN_PD = GPIO_MODE(0, 2, 0), /**< input with pull-down */ - GPIO_IN_PU = GPIO_MODE(0, 1, 0), /**< input with pull-up */ - GPIO_OUT = GPIO_MODE(1, 0, 0), /**< push-pull output */ - GPIO_OD = GPIO_MODE(1, 0, 1), /**< open-drain w/o pull R */ - GPIO_OD_PU = GPIO_MODE(1, 1, 1) /**< open-drain with pull-up */ -} gpio_mode_t; -/** @} */ -#endif /* ndef DOXYGEN */ -#endif /* ndef CPU_FAM_STM32F1 */ - -#ifndef DOXYGEN -/** - * @brief Override flank configuration values - * @{ - */ -#define HAVE_GPIO_FLANK_T -typedef enum { - GPIO_RISING = 1, /**< emit interrupt on rising flank */ - GPIO_FALLING = 2, /**< emit interrupt on falling flank */ - GPIO_BOTH = 3 /**< emit interrupt on both flanks */ -} gpio_flank_t; -/** @} */ -#endif /* ndef DOXYGEN */ - /** * @brief DMA configuration */ @@ -868,17 +752,17 @@ void periph_clk_dis(bus_t bus, uint32_t mask); /** * @brief Configure the alternate function for the given pin * - * @param[in] pin pin to configure + * @param[in] gpio gpio to configure * @param[in] af alternate function to use */ -void gpio_init_af(gpio_t pin, gpio_af_t af); +void gpio_init_af(gpio_t gpio, gpio_af_t af); /** * @brief Configure the given pin to be used as ADC input * - * @param[in] pin pin to configure + * @param[in] gpio gpio to configure */ -void gpio_init_analog(gpio_t pin); +void gpio_init_analog(gpio_t gpio); #ifdef MODULE_PERIPH_DMA /** diff --git a/cpu/stm32/periph/adc_f1.c b/cpu/stm32/periph/adc_f1.c index 2323598137a6..b82ed98c5777 100644 --- a/cpu/stm32/periph/adc_f1.c +++ b/cpu/stm32/periph/adc_f1.c @@ -88,7 +88,7 @@ int adc_init(adc_t line) prep(line); /* configure the pin */ - if (adc_config[line].pin != GPIO_UNDEF) { + if (gpio_is_valid(adc_config[line].pin)) { gpio_init_analog(adc_config[line].pin); } /* set clock prescaler to get the maximal possible ADC clock value */ diff --git a/cpu/stm32/periph/adc_l1.c b/cpu/stm32/periph/adc_l1.c index d7c97003c4d8..46b79c474ab4 100644 --- a/cpu/stm32/periph/adc_l1.c +++ b/cpu/stm32/periph/adc_l1.c @@ -102,7 +102,7 @@ int adc_init(adc_t line) prep(); /* configure the pin */ - if ((adc_config[line].pin != GPIO_UNDEF)) + if (gpio_is_valid(adc_config[line].pin)) gpio_init_analog(adc_config[line].pin); /* set ADC clock prescaler */ diff --git a/cpu/stm32/periph/adc_l4.c b/cpu/stm32/periph/adc_l4.c index 5b637d640f52..168e9e8950e2 100644 --- a/cpu/stm32/periph/adc_l4.c +++ b/cpu/stm32/periph/adc_l4.c @@ -85,17 +85,17 @@ static inline void done(adc_t line) /** * @brief Extract the port base address from the given pin identifier */ -static inline GPIO_TypeDef *_port(gpio_t pin) +static inline GPIO_TypeDef *_port(gpio_t gpio) { - return (GPIO_TypeDef *)(pin & ~(0x0f)); + return (GPIO_TypeDef *)(gpio.port.reg); } /** * @brief Extract the pin number from the last 4 bit of the pin identifier */ -static inline int _pin_num(gpio_t pin) +static inline int _pin_num(gpio_t gpio) { - return (pin & 0x0f); + return (gpio.pin); } int adc_init(adc_t line) diff --git a/cpu/stm32/periph/can.c b/cpu/stm32/periph/can.c index 41ca14a2ea41..2c125a3137c2 100644 --- a/cpu/stm32/periph/can.c +++ b/cpu/stm32/periph/can.c @@ -243,11 +243,11 @@ void candev_stm32_set_pins(can_t *dev, gpio_t tx_pin, gpio_t rx_pin, void candev_stm32_set_pins(can_t *dev, gpio_t tx_pin, gpio_t rx_pin) #endif { - if (dev->tx_pin != GPIO_UNDEF) { + if (gpio_is_valid(dev->tx_pin)) { gpio_init(dev->tx_pin, GPIO_IN); gpio_init_analog(dev->tx_pin); } - if (dev->rx_pin != GPIO_UNDEF) { + if (gpio_is_valid(dev->rx_pin)) { gpio_init(dev->rx_pin, GPIO_IN); gpio_init_analog(dev->rx_pin); } diff --git a/cpu/stm32/periph/eth.c b/cpu/stm32/periph/eth.c index 27b394b91a76..75c1661bffda 100644 --- a/cpu/stm32/periph/eth.c +++ b/cpu/stm32/periph/eth.c @@ -29,6 +29,7 @@ #include "net/ethernet.h" #include "net/netdev/eth.h" #include "periph/gpio.h" +#include "periph_conf.h" #define ENABLE_DEBUG (0) #include "debug.h" diff --git a/cpu/stm32/periph/gpio_all.c b/cpu/stm32/periph/gpio_all.c index ebb58285f547..aa817c5deafa 100644 --- a/cpu/stm32/periph/gpio_all.c +++ b/cpu/stm32/periph/gpio_all.c @@ -58,51 +58,42 @@ static gpio_isr_ctx_t isr_ctx[EXTI_NUMOF]; #endif /** - * @brief Extract the port base address from the given pin identifier + * @brief Converts a port into a pointer to its register structure */ -static inline GPIO_TypeDef *_port(gpio_t pin) +static inline GPIO_TypeDef *_port(gpio_port_t port) { - return (GPIO_TypeDef *)(pin & ~(0x0f)); + return (GPIO_TypeDef *)port.reg; } /** - * @brief Extract the port number form the given identifier + * @brief Convert a port to its port number * * The port number is extracted by looking at bits 10, 11, 12, 13 of the base * register addresses. */ -static inline int _port_num(gpio_t pin) +static inline int _port_num(gpio_port_t port) { - return ((pin >> 10) & 0x0f); + return GPIO_CPU_PORT_NUM(port.reg); } -/** - * @brief Extract the pin number from the last 4 bit of the pin identifier - */ -static inline int _pin_num(gpio_t pin) -{ - return (pin & 0x0f); -} - -static inline void port_init_clock(GPIO_TypeDef *port, gpio_t pin) +static inline void port_init_clock(gpio_port_t port) { - (void)port; /* <-- Only used for when port G requires special handling */ #if defined(CPU_FAM_STM32F0) || defined (CPU_FAM_STM32F3) || defined(CPU_FAM_STM32L1) - periph_clk_en(AHB, (RCC_AHBENR_GPIOAEN << _port_num(pin))); + periph_clk_en(AHB, (RCC_AHBENR_GPIOAEN << _port_num(port))); #elif defined (CPU_FAM_STM32L0) || defined(CPU_FAM_STM32G0) - periph_clk_en(IOP, (RCC_IOPENR_GPIOAEN << _port_num(pin))); + periph_clk_en(IOP, (RCC_IOPENR_GPIOAEN << _port_num(port))); #elif defined (CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \ defined (CPU_FAM_STM32G4) - periph_clk_en(AHB2, (RCC_AHB2ENR_GPIOAEN << _port_num(pin))); + periph_clk_en(AHB2, (RCC_AHB2ENR_GPIOAEN << _port_num(port))); #ifdef PWR_CR2_IOSV - if (port == GPIOG) { + if (port.reg == GPIOG_BASE) { /* Port G requires external power supply */ periph_clk_en(APB1, RCC_APB1ENR1_PWREN); PWR->CR2 |= PWR_CR2_IOSV; } #endif /* PWR_CR2_IOSV */ #else - periph_clk_en(AHB1, (RCC_AHB1ENR_GPIOAEN << _port_num(pin))); + periph_clk_en(AHB1, (RCC_AHB1ENR_GPIOAEN << _port_num(port))); #endif } @@ -114,112 +105,102 @@ static inline void set_mode(GPIO_TypeDef *port, int pin_num, unsigned mode) port->MODER = tmp; } -int gpio_init(gpio_t pin, gpio_mode_t mode) +int gpio_cpu_init(gpio_port_t port, gpio_pin_t pin, gpio_mode_t mode) { - GPIO_TypeDef *port = _port(pin); - int pin_num = _pin_num(pin); - /* enable clock */ - port_init_clock(port, pin); + port_init_clock(port); /* set mode */ - set_mode(port, pin_num, mode); + set_mode(_port(port), pin, mode); /* set pull resistor configuration */ - port->PUPDR &= ~(0x3 << (2 * pin_num)); - port->PUPDR |= (((mode >> 2) & 0x3) << (2 * pin_num)); + _port(port)->PUPDR &= ~(0x3 << (2 * pin)); + _port(port)->PUPDR |= (((mode >> 2) & 0x3) << (2 * pin)); /* set output mode */ - port->OTYPER &= ~(1 << pin_num); - port->OTYPER |= (((mode >> 4) & 0x1) << pin_num); + _port(port)->OTYPER &= ~(1 << pin); + _port(port)->OTYPER |= (((mode >> 4) & 0x1) << pin); /* set pin speed to maximum */ - port->OSPEEDR |= (3 << (2 * pin_num)); + _port(port)->OSPEEDR |= (3 << (2 * pin)); return 0; } -void gpio_init_af(gpio_t pin, gpio_af_t af) +void gpio_init_af(gpio_t gpio, gpio_af_t af) { - GPIO_TypeDef *port = _port(pin); - uint32_t pin_num = _pin_num(pin); + GPIO_TypeDef *port = _port(gpio.port); + gpio_pin_t pin =gpio.pin; /* enable clock */ - port_init_clock(port, pin); + port_init_clock(gpio.port); /* set selected function */ - port->AFR[(pin_num > 7) ? 1 : 0] &= ~(0xf << ((pin_num & 0x07) * 4)); - port->AFR[(pin_num > 7) ? 1 : 0] |= (af << ((pin_num & 0x07) * 4)); + port->AFR[(pin > 7) ? 1 : 0] &= ~(0xf << ((pin & 0x07) * 4)); + port->AFR[(pin > 7) ? 1 : 0] |= (af << ((pin & 0x07) * 4)); /* set pin to AF mode */ - set_mode(port, pin_num, 2); + set_mode(port, pin, 2); } -void gpio_init_analog(gpio_t pin) +void gpio_init_analog(gpio_t gpio) { /* enable clock, needed as this function can be used without calling * gpio_init first */ #if defined(CPU_FAM_STM32F0) || defined (CPU_FAM_STM32F3) || defined(CPU_FAM_STM32L1) - periph_clk_en(AHB, (RCC_AHBENR_GPIOAEN << _port_num(pin))); + periph_clk_en(AHB, (RCC_AHBENR_GPIOAEN << _port_num(gpio.port))); #elif defined (CPU_FAM_STM32L0) || defined(CPU_FAM_STM32G0) - periph_clk_en(IOP, (RCC_IOPENR_GPIOAEN << _port_num(pin))); + periph_clk_en(IOP, (RCC_IOPENR_GPIOAEN << _port_num(gpio.port))); #elif defined (CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \ defined (CPU_FAM_STM32G4) - periph_clk_en(AHB2, (RCC_AHB2ENR_GPIOAEN << _port_num(pin))); + periph_clk_en(AHB2, (RCC_AHB2ENR_GPIOAEN << _port_num(gpio.port))); #else - periph_clk_en(AHB1, (RCC_AHB1ENR_GPIOAEN << _port_num(pin))); + periph_clk_en(AHB1, (RCC_AHB1ENR_GPIOAEN << _port_num(gpio.port))); #endif /* set to analog mode */ - _port(pin)->MODER |= (0x3 << (2 * _pin_num(pin))); + _port(gpio.port)->MODER |= (0x3 << ((uint32_t)gpio.pin << 1)); } -void gpio_irq_enable(gpio_t pin) +void gpio_cpu_irq_enable(gpio_port_t port, gpio_pin_t pin) { - EXTI_REG_IMR |= (1 << _pin_num(pin)); + (void)port; + EXTI_REG_IMR |= (1 << pin); } -void gpio_irq_disable(gpio_t pin) +void gpio_cpu_irq_disable(gpio_port_t port, gpio_pin_t pin) { - EXTI_REG_IMR &= ~(1 << _pin_num(pin)); + (void)port; + EXTI_REG_IMR &= ~(1 << pin); } -int gpio_read(gpio_t pin) +gpio_mask_t gpio_cpu_read(gpio_port_t port) { - return (_port(pin)->IDR & (1 << _pin_num(pin))); + return _port(port)->IDR; } -void gpio_set(gpio_t pin) +void gpio_cpu_set(gpio_port_t port, gpio_mask_t pins) { - _port(pin)->BSRR = (1 << _pin_num(pin)); + _port(port)->BSRR = pins; } -void gpio_clear(gpio_t pin) +void gpio_cpu_clear(gpio_port_t port, gpio_mask_t pins) { - _port(pin)->BSRR = (1 << (_pin_num(pin) + 16)); + _port(port)->BSRR = ((uint32_t)pins << 16); } -void gpio_toggle(gpio_t pin) +void gpio_cpu_toggle(gpio_port_t port, gpio_mask_t pins) { - if (gpio_read(pin)) { - gpio_clear(pin); - } else { - gpio_set(pin); - } + _port(port)->ODR = _port(port)->ODR ^ pins; } -void gpio_write(gpio_t pin, int value) +void gpio_cpu_write(gpio_port_t port, gpio_mask_t values) { - if (value) { - gpio_set(pin); - } else { - gpio_clear(pin); - } + _port(port)->ODR = values; } #ifdef MODULE_PERIPH_GPIO_IRQ -int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, - gpio_cb_t cb, void *arg) +int gpio_cpu_init_int(gpio_port_t port, gpio_pin_t pin, gpio_mode_t mode, + gpio_flank_t flank, gpio_cb_t cb, void *arg) { - int pin_num = _pin_num(pin); - int port_num = _port_num(pin); + int port_num = _port_num(port); /* set callback */ - isr_ctx[pin_num].cb = cb; - isr_ctx[pin_num].arg = arg; + isr_ctx[pin].cb = cb; + isr_ctx[pin].arg = arg; /* enable clock of the SYSCFG module for EXTI configuration */ #ifndef CPU_FAM_STM32WB @@ -233,25 +214,25 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, #endif /* initialize pin as input */ - gpio_init(pin, mode); + gpio_cpu_init(port, pin, mode); /* enable global pin interrupt */ #if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32L0) || \ defined(CPU_FAM_STM32G0) - if (pin_num < 2) { + if (pin < 2) { NVIC_EnableIRQ(EXTI0_1_IRQn); } - else if (pin_num < 4) { + else if (pin < 4) { NVIC_EnableIRQ(EXTI2_3_IRQn); } else { NVIC_EnableIRQ(EXTI4_15_IRQn); } #else - if (pin_num < 5) { - NVIC_EnableIRQ(EXTI0_IRQn + pin_num); + if (pin < 5) { + NVIC_EnableIRQ(EXTI0_IRQn + pin); } - else if (pin_num < 10) { + else if (pin < 10) { NVIC_EnableIRQ(EXTI9_5_IRQn); } else { @@ -259,27 +240,27 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, } #endif /* configure the active flank */ - EXTI_REG_RTSR &= ~(1 << pin_num); - EXTI_REG_RTSR |= ((flank & 0x1) << pin_num); - EXTI_REG_FTSR &= ~(1 << pin_num); - EXTI_REG_FTSR |= ((flank >> 1) << pin_num); + EXTI_REG_RTSR &= ~(1 << pin); + EXTI_REG_RTSR |= ((flank & 0x1) << pin); + EXTI_REG_FTSR &= ~(1 << pin); + EXTI_REG_FTSR |= ((flank >> 1) << pin); #if defined(CPU_FAM_STM32G0) /* enable specific pin as exti sources */ - EXTI->EXTICR[pin_num >> 2] &= ~(0xf << ((pin_num & 0x03) * 8)); - EXTI->EXTICR[pin_num >> 2] |= (port_num << ((pin_num & 0x03) * 8)); + EXTI->EXTICR[pin >> 2] &= ~(0xf << ((pin & 0x03) * 8)); + EXTI->EXTICR[pin >> 2] |= (port_num << ((pin & 0x03) * 8)); /* clear any pending requests */ - EXTI->RPR1 = (1 << pin_num); - EXTI->FPR1 = (1 << pin_num); + EXTI->RPR1 = (1 << pin); + EXTI->FPR1 = (1 << pin); #else /* enable specific pin as exti sources */ - SYSCFG->EXTICR[pin_num >> 2] &= ~(0xf << ((pin_num & 0x03) * 4)); - SYSCFG->EXTICR[pin_num >> 2] |= (port_num << ((pin_num & 0x03) * 4)); + SYSCFG->EXTICR[pin >> 2] &= ~(0xf << ((pin & 0x03) * 4)); + SYSCFG->EXTICR[pin >> 2] |= (port_num << ((pin & 0x03) * 4)); /* clear any pending requests */ - EXTI_REG_PR = (1 << pin_num); + EXTI_REG_PR = (1 << pin); #endif /* unmask the pins interrupt channel */ - EXTI_REG_IMR |= (1 << pin_num); + EXTI_REG_IMR |= (1 << pin); return 0; } diff --git a/cpu/stm32/periph/gpio_f1.c b/cpu/stm32/periph/gpio_f1.c index 523cdef47ecc..7cd7b1e423b5 100644 --- a/cpu/stm32/periph/gpio_f1.c +++ b/cpu/stm32/periph/gpio_f1.c @@ -48,30 +48,22 @@ static gpio_isr_ctx_t exti_ctx[GPIO_ISR_CHAN_NUMOF]; #endif /* MODULE_PERIPH_GPIO_IRQ */ /** - * @brief Extract the pin's port base address from the given pin identifier + * @brief Converts a port into a pointer to its register structure */ -static inline GPIO_TypeDef *_port(gpio_t pin) +static inline GPIO_TypeDef *_port(gpio_port_t port) { - return (GPIO_TypeDef *)(pin & ~(0x0f)); + return (GPIO_TypeDef *)port.reg; } /** - * @brief Extract the port number from the given pin identifier + * @brief Convert a port into its port number * - * Isolating bits 10 to 13 of the port base addresses leads to unique port - * numbers. + * The port number is extracted by looking at bits 10, 11, 12, 13 of the base + * register addresses. */ -static inline int _port_num(gpio_t pin) +static inline int _port_num(gpio_port_t port) { - return (((pin >> 10) & 0x0f) - 2); -} - -/** - * @brief Get the pin number from the pin identifier, encoded in the LSB 4 bit - */ -static inline int _pin_num(gpio_t pin) -{ - return (pin & 0x0f); + return GPIO_CPU_PORT_NUM(port.reg); } /** @@ -95,147 +87,124 @@ static inline void set_mode_or_af(GPIO_TypeDef *port, int pin_num, *crl = tmp; } -int gpio_init(gpio_t pin, gpio_mode_t mode) +int gpio_cpu_init(gpio_port_t port, gpio_pin_t pin, gpio_mode_t mode) { - GPIO_TypeDef *port = _port(pin); - int pin_num = _pin_num(pin); - /* open-drain output with pull-up is not supported */ if (mode == GPIO_OD_PU) { return -1; } /* enable the clock for the selected port */ - periph_clk_en(APB2, (RCC_APB2ENR_IOPAEN << _port_num(pin))); + periph_clk_en(APB2, (RCC_APB2ENR_IOPAEN << _port_num(port))); /* set pin mode */ - set_mode_or_af(port, pin_num, mode); + set_mode_or_af(_port(port), pin, mode); /* For input modes, ODR controls pull up settings */ if (gpio_mode_is_input(mode)) { if (mode == GPIO_IN_PU) - port->ODR |= 1 << pin_num; + _port(port)->ODR |= 1 << pin; else - port->ODR &= ~(1 << pin_num); + _port(port)->ODR &= ~(1 << pin); } return 0; /* all OK */ } -void gpio_init_af(gpio_t pin, gpio_af_t af) +void gpio_init_af(gpio_t gpio, gpio_af_t af) { - int pin_num = _pin_num(pin); - GPIO_TypeDef *port = _port(pin); + gpio_pin_t pin = gpio.pin; + GPIO_TypeDef *port = _port(gpio.port); /* enable the clock for the selected port */ - periph_clk_en(APB2, (RCC_APB2ENR_IOPAEN << _port_num(pin))); + periph_clk_en(APB2, (RCC_APB2ENR_IOPAEN << _port_num(gpio.port))); /* configure the pin */ - set_mode_or_af(port, pin_num, af); + set_mode_or_af(port, pin, af); } -void gpio_init_analog(gpio_t pin) +void gpio_init_analog(gpio_t gpio) { /* enable the GPIO port RCC */ - periph_clk_en(APB2, (RCC_APB2ENR_IOPAEN << _port_num(pin))); + periph_clk_en(APB2, (RCC_APB2ENR_IOPAEN << _port_num(gpio.port))); /* map the pin as analog input */ - int pin_num = _pin_num(pin); - *(uint32_t *)(&_port(pin)->CRL + (pin_num >= 8)) &= ~(0xfl << (4 * (pin_num - ((pin_num >= 8) * 8)))); + gpio_pin_t pin = gpio.pin; + *(uint32_t *)(&_port(gpio.port)->CRL + (pin >= 8)) &= ~(0xfl << (4 * (pin - ((pin >= 8) * 8)))); } -int gpio_read(gpio_t pin) +gpio_mask_t gpio_cpu_read(gpio_port_t port) { - GPIO_TypeDef *port = _port(pin); - int pin_num = _pin_num(pin); - - if (*(uint32_t *)(&port->CRL + (pin_num >> 3)) & (0x3 << ((pin_num & 0x7) << 2))) { - /* pin is output */ - return (port->ODR & (1 << pin_num)); - } - else { - /* or input */ - return (port->IDR & (1 << pin_num)); - } + return _port(port)->IDR; } -void gpio_set(gpio_t pin) +void gpio_cpu_set(gpio_port_t port, gpio_mask_t pins) { - _port(pin)->BSRR = (1 << _pin_num(pin)); + _port(port)->BSRR = pins; } -void gpio_clear(gpio_t pin) +void gpio_cpu_clear(gpio_port_t port, gpio_mask_t pins) { - _port(pin)->BRR = (1 << _pin_num(pin)); + _port(port)->BRR = pins; } -void gpio_toggle(gpio_t pin) +void gpio_cpu_toggle(gpio_port_t port, gpio_mask_t pins) { - if (gpio_read(pin)) { - gpio_clear(pin); - } - else { - gpio_set(pin); - } + _port(port)->ODR = _port(port)->ODR ^ pins; } -void gpio_write(gpio_t pin, int value) +void gpio_cpu_write(gpio_port_t port, gpio_mask_t values) { - if (value) { - _port(pin)->BSRR = (1 << _pin_num(pin)); - } - else { - _port(pin)->BRR = (1 << _pin_num(pin)); - } + _port(port)->ODR = values; } #ifdef MODULE_PERIPH_GPIO_IRQ -int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, - gpio_cb_t cb, void *arg) +int gpio_cpu_init_int(gpio_port_t port, gpio_pin_t pin, gpio_mode_t mode, gpio_flank_t flank, + gpio_cb_t cb, void *arg) { - int pin_num = _pin_num(pin); - /* disable interrupts on the channel we want to edit (just in case) */ - EXTI->IMR &= ~(1 << pin_num); + EXTI->IMR &= ~(1 << pin); /* configure pin as input */ - gpio_init(pin, mode); + gpio_cpu_init(port, pin, mode); /* set callback */ - exti_ctx[pin_num].cb = cb; - exti_ctx[pin_num].arg = arg; + exti_ctx[pin].cb = cb; + exti_ctx[pin].arg = arg; /* enable alternate function clock for the GPIO module */ periph_clk_en(APB2, RCC_APB2ENR_AFIOEN); /* configure the EXTI channel */ - AFIO->EXTICR[pin_num >> 2] &= ~(0xf << ((pin_num & 0x3) * 4)); - AFIO->EXTICR[pin_num >> 2] |= (_port_num(pin) << ((pin_num & 0x3) * 4)); + AFIO->EXTICR[pin >> 2] &= ~(0xf << ((pin & 0x3) * 4)); + AFIO->EXTICR[pin >> 2] |= (_port_num(port) << ((pin & 0x3) * 4)); /* configure the active flank */ - EXTI->RTSR &= ~(1 << pin_num); - EXTI->RTSR |= ((flank & 0x1) << pin_num); - EXTI->FTSR &= ~(1 << pin_num); - EXTI->FTSR |= ((flank >> 1) << pin_num); + EXTI->RTSR &= ~(1 << pin); + EXTI->RTSR |= ((flank & 0x1) << pin); + EXTI->FTSR &= ~(1 << pin); + EXTI->FTSR |= ((flank >> 1) << pin); /* active global interrupt for the selected port */ - if (pin_num < 5) { - NVIC_EnableIRQ(EXTI0_IRQn + pin_num); + if (pin < 5) { + NVIC_EnableIRQ(EXTI0_IRQn + pin); } - else if (pin_num < 10) { + else if (pin < 10) { NVIC_EnableIRQ(EXTI9_5_IRQn); } else { NVIC_EnableIRQ(EXTI15_10_IRQn); } /* clear event mask */ - EXTI->EMR &= ~(1 << pin_num); + EXTI->EMR &= ~(1 << pin); /* unmask the pins interrupt channel */ - EXTI->IMR |= (1 << pin_num); + EXTI->IMR |= (1 << pin); return 0; } -void gpio_irq_enable(gpio_t pin) +void gpio_cpu_irq_enable(gpio_port_t port, gpio_pin_t pin) { - EXTI->IMR |= (1 << _pin_num(pin)); + (void)port; + EXTI->IMR |= (1 << pin); } -void gpio_irq_disable(gpio_t pin) +void gpio_cpu_irq_disable(gpio_port_t port, gpio_pin_t pin) { - EXTI->IMR &= ~(1 << _pin_num(pin)); + (void)port; + EXTI->IMR &= ~(1 << pin); } void isr_exti(void) diff --git a/cpu/stm32/periph/i2c_2.c b/cpu/stm32/periph/i2c_2.c index d31f28989b5d..5857a776e9bd 100644 --- a/cpu/stm32/periph/i2c_2.c +++ b/cpu/stm32/periph/i2c_2.c @@ -114,8 +114,8 @@ static void _init_pins(i2c_t dev) gpio_init(i2c_config[dev].sda_pin, GPIO_OD_PU); #ifdef CPU_FAM_STM32F1 /* This is needed in case the remapped pins are used */ - if (i2c_config[dev].scl_pin == GPIO_PIN(PORT_B, 8) || - i2c_config[dev].sda_pin == GPIO_PIN(PORT_B, 9)) { + if (gpio_is_equal(i2c_config[dev].scl_pin, GPIO_PIN(PORT_B, 8)) || + gpio_is_equal(i2c_config[dev].sda_pin, GPIO_PIN(PORT_B, 9))) { /* The remapping periph clock must first be enabled */ RCC->APB2ENR |= RCC_APB2ENR_AFIOEN; /* Then the remap can occur */ diff --git a/cpu/stm32/periph/pwm.c b/cpu/stm32/periph/pwm.c index c96ff970501b..df3e34f4c718 100644 --- a/cpu/stm32/periph/pwm.c +++ b/cpu/stm32/periph/pwm.c @@ -62,7 +62,7 @@ uint32_t pwm_init(pwm_t pwm, pwm_mode_t mode, uint32_t freq, uint16_t res) /* configure the used pins */ unsigned i = 0; - while ((i < TIMER_CHANNEL_NUMOF) && (pwm_config[pwm].chan[i].pin != GPIO_UNDEF)) { + while ((i < TIMER_CHANNEL_NUMOF) && gpio_is_valid(pwm_config[pwm].chan[i].pin)) { gpio_init(pwm_config[pwm].chan[i].pin, GPIO_OUT); gpio_init_af(pwm_config[pwm].chan[i].pin, pwm_config[pwm].af); i++; @@ -109,7 +109,7 @@ uint8_t pwm_channels(pwm_t pwm) assert(pwm < PWM_NUMOF); unsigned i = 0; - while ((i < TIMER_CHANNEL_NUMOF) && (pwm_config[pwm].chan[i].pin != GPIO_UNDEF)) { + while ((i < TIMER_CHANNEL_NUMOF) && gpio_is_valid(pwm_config[pwm].chan[i].pin)) { i++; } return (uint8_t)i; @@ -119,7 +119,7 @@ void pwm_set(pwm_t pwm, uint8_t channel, uint16_t value) { assert((pwm < PWM_NUMOF) && (channel < TIMER_CHANNEL_NUMOF) && - (pwm_config[pwm].chan[channel].pin != GPIO_UNDEF)); + gpio_is_valid(pwm_config[pwm].chan[channel].pin)); /* norm value to maximum possible value */ if (value > dev(pwm)->ARR + 1) { diff --git a/cpu/stm32/periph/qdec.c b/cpu/stm32/periph/qdec.c index 1eaef3657526..ac6182ecf52b 100644 --- a/cpu/stm32/periph/qdec.c +++ b/cpu/stm32/periph/qdec.c @@ -96,7 +96,7 @@ int32_t qdec_init(qdec_t qdec, qdec_mode_t mode, qdec_cb_t cb, void *arg) /* Configure the used pins */ i = 0; - while ((i < QDEC_CHAN) && (qdec_config[qdec].chan[i].pin != GPIO_UNDEF)) { + while ((i < QDEC_CHAN) && gpio_is_valid(qdec_config[qdec].chan[i].pin)) { gpio_init(qdec_config[qdec].chan[i].pin, GPIO_IN); #ifndef CPU_FAM_STM32F1 gpio_init_af(qdec_config[qdec].chan[i].pin, qdec_config[qdec].af); diff --git a/cpu/stm32/periph/spi.c b/cpu/stm32/periph/spi.c index 176b3d35b0b3..f248bd0d97e0 100644 --- a/cpu/stm32/periph/spi.c +++ b/cpu/stm32/periph/spi.c @@ -148,13 +148,13 @@ int spi_init_cs(spi_t bus, spi_cs_t cs) if (bus >= SPI_NUMOF) { return SPI_NODEV; } - if (cs == SPI_CS_UNDEF || - (((cs & SPI_HWCS_MASK) == SPI_HWCS_MASK) && (cs & ~(SPI_HWCS_MASK)))) { + if (gpio_is_equal(cs, SPI_CS_UNDEF) || + (SPI_HWCS_IS(cs) && !gpio_is_equal(cs, SPI_HWCS(0)))) { return SPI_NOCS; } - if (cs == SPI_HWCS_MASK) { - if (spi_config[bus].cs_pin == GPIO_UNDEF) { + if (!gpio_is_equal(cs, SPI_HWCS(0))) { + if (!gpio_is_valid(spi_config[bus].cs_pin)) { return SPI_NOCS; } #ifdef CPU_FAM_STM32F1 @@ -165,8 +165,8 @@ int spi_init_cs(spi_t bus, spi_cs_t cs) #endif } else { - gpio_init((gpio_t)cs, GPIO_OUT); - gpio_set((gpio_t)cs); + gpio_init(cs, GPIO_OUT); + gpio_set(cs); } return SPI_OK; @@ -221,7 +221,7 @@ int spi_acquire(spi_t bus, spi_cs_t cs, spi_mode_t mode, spi_clk_t clk) uint16_t cr1_settings = ((br << BR_SHIFT) | mode | SPI_CR1_MSTR); /* Settings to add to CR2 in addition to SPI_CR2_SETTINGS */ uint16_t cr2_extra_settings = 0; - if (cs != SPI_HWCS_MASK) { + if (!SPI_HWCS_IS(cs)) { cr1_settings |= (SPI_CR1_SSM | SPI_CR1_SSI); } else { @@ -368,8 +368,8 @@ void spi_transfer_bytes(spi_t bus, spi_cs_t cs, bool cont, /* active the given chip select line */ dev(bus)->CR1 |= (SPI_CR1_SPE); /* this pulls the HW CS line low */ - if ((cs != SPI_HWCS_MASK) && (cs != SPI_CS_UNDEF)) { - gpio_clear((gpio_t)cs); + if (!SPI_HWCS_IS(cs) && !gpio_is_equal(cs, SPI_CS_UNDEF)) { + gpio_clear(cs); } #ifdef MODULE_PERIPH_DMA @@ -384,10 +384,10 @@ void spi_transfer_bytes(spi_t bus, spi_cs_t cs, bool cont, #endif /* release the chip select if not specified differently */ - if ((!cont) && (cs != SPI_CS_UNDEF)) { + if ((!cont) && (!gpio_is_equal(cs, SPI_CS_UNDEF))) { dev(bus)->CR1 &= ~(SPI_CR1_SPE); /* pull HW CS line high */ - if (cs != SPI_HWCS_MASK) { - gpio_set((gpio_t)cs); + if (!SPI_HWCS_IS(cs)) { + gpio_set(cs); } } } diff --git a/cpu/stm32/periph/uart.c b/cpu/stm32/periph/uart.c index 170dd7c342ff..57cf3cea2edb 100644 --- a/cpu/stm32/periph/uart.c +++ b/cpu/stm32/periph/uart.c @@ -105,7 +105,7 @@ static inline void uart_init_lpuart(uart_t uart, uint32_t baudrate); #ifdef MODULE_PERIPH_UART_HW_FC static inline void uart_init_rts_pin(uart_t uart) { - if (uart_config[uart].rts_pin != GPIO_UNDEF) { + if (gpio_is_valid(uart_config[uart].rts_pin)) { gpio_init(uart_config[uart].rts_pin, GPIO_OUT); #ifdef CPU_FAM_STM32F1 gpio_init_af(uart_config[uart].rts_pin, GPIO_AF_OUT_PP); @@ -117,7 +117,7 @@ static inline void uart_init_rts_pin(uart_t uart) static inline void uart_init_cts_pin(uart_t uart) { - if (uart_config[uart].cts_pin != GPIO_UNDEF) { + if (gpio_is_valid(uart_config[uart].cts_pin)) { gpio_init(uart_config[uart].cts_pin, GPIO_IN); #ifndef CPU_FAM_STM32F1 gpio_init_af(uart_config[uart].cts_pin, uart_config[uart].cts_af); @@ -226,10 +226,10 @@ int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, void *arg) #endif #ifdef MODULE_PERIPH_UART_HW_FC - if (uart_config[uart].cts_pin != GPIO_UNDEF) { + if (gpio_is_valid(uart_config[uart].cts_pin)) { dev(uart)->CR3 |= USART_CR3_CTSE; } - if (uart_config[uart].rts_pin != GPIO_UNDEF) { + if (gpio_is_valid(uart_config[uart].rts_pin)) { dev(uart)->CR3 |= USART_CR3_RTSE; } #endif @@ -443,7 +443,7 @@ void uart_poweroff(uart_t uart) #ifdef MODULE_PERIPH_UART_HW_FC /* the uart peripheral does not put RTS high from hardware when * UE flag is cleared, so we need to do this manually */ - if (uart_config[uart].rts_pin != GPIO_UNDEF) { + if (gpio_is_valid(uart_config[uart].rts_pin)) { gpio_init(uart_config[uart].rts_pin, GPIO_OUT); gpio_set(uart_config[uart].rts_pin); } diff --git a/cpu/stm32/periph/usbdev.c b/cpu/stm32/periph/usbdev.c index b3f5ecfb008b..d8a527d51740 100644 --- a/cpu/stm32/periph/usbdev.c +++ b/cpu/stm32/periph/usbdev.c @@ -26,6 +26,7 @@ #include "xtimer.h" #include "cpu.h" #include "cpu_conf.h" +#include "periph_conf.h" #include "periph/pm.h" #include "periph/gpio.h" #include "periph/usbdev.h"