From 45b353c6ef5901231893b0df770170cea7f27a33 Mon Sep 17 00:00:00 2001 From: Marian Buschsieweke Date: Wed, 14 Jun 2023 16:18:15 +0200 Subject: [PATCH] cpu/msp430: make use of vendor header files The MSP430 vendor files already provide macros containing register constants and symbols (provided via linker scripts) containing addresses of peripheral registers. So lets make use of that rather than maintaining a long list of constants. --- boards/msb-430/include/periph_conf.h | 16 +- boards/msb-430h/include/periph_conf.h | 16 +- .../olimex-msp430-h1611/include/periph_conf.h | 16 +- .../olimex-msp430-h2618/include/periph_conf.h | 18 +- boards/telosb/include/periph_conf.h | 17 +- boards/z1/include/periph_conf.h | 18 +- cpu/msp430/include/f2xx_g2xx/msp430_regs.h | 198 +++++++---------- cpu/msp430/include/f2xx_g2xx/periph_cpu.h | 13 +- cpu/msp430/include/msp430_regs_common.h | 200 +++++++----------- cpu/msp430/include/periph_cpu_common.h | 7 +- cpu/msp430/include/x1xx/msp430_regs.h | 89 ++++---- cpu/msp430/include/x1xx/periph_cpu.h | 15 +- cpu/msp430/ldscripts/msp430_common.ld | 17 ++ cpu/msp430/ldscripts/msp430_f2xx_g2xx.ld | 6 + cpu/msp430/ldscripts/msp430_x1xx.ld | 7 + cpu/msp430/ldscripts/riot-msp430f1611.ld | 1 + cpu/msp430/ldscripts/riot-msp430f1612.ld | 1 + cpu/msp430/ldscripts/riot-msp430f1617.ld | 1 + cpu/msp430/ldscripts/riot-msp430f2617.ld | 1 + cpu/msp430/ldscripts/riot-msp430f2618.ld | 1 + cpu/msp430/periph/gpio.c | 60 +++--- cpu/msp430/periph/spi_usart.c | 22 +- cpu/msp430/periph/spi_usci.c | 13 +- cpu/msp430/periph/timer.c | 22 +- cpu/msp430/periph/uart_usart.c | 31 +-- cpu/msp430/periph/uart_usci.c | 30 +-- dist/tools/doccheck/exclude_simple | 159 +------------- dist/tools/doccheck/generic_exclude_patterns | 3 - makefiles/arch/msp430.inc.mk | 1 + 29 files changed, 391 insertions(+), 608 deletions(-) create mode 100644 cpu/msp430/ldscripts/msp430_f2xx_g2xx.ld create mode 100644 cpu/msp430/ldscripts/msp430_x1xx.ld diff --git a/boards/msb-430/include/periph_conf.h b/boards/msb-430/include/periph_conf.h index 0dfd94cacbfc..12c361a82e9b 100644 --- a/boards/msb-430/include/periph_conf.h +++ b/boards/msb-430/include/periph_conf.h @@ -49,7 +49,7 @@ static const msp430_clock_params_t clock_params = { * @{ */ #define TIMER_NUMOF (1U) -#define TIMER_BASE (TIMER_A) +#define TIMER_BASE (&TIMER_A) #define TIMER_CHAN (3) #define TIMER_ISR_CC0 (TIMERA0_VECTOR) #define TIMER_ISR_CCX (TIMERA1_VECTOR) @@ -61,14 +61,12 @@ static const msp430_clock_params_t clock_params = { */ #define UART_NUMOF (1U) -#define UART_BASE (USART_1) -#define UART_IE (SFR->IE2) -#define UART_IF (SFR->IFG2) +#define UART_BASE (&USART_1) +#define UART_SFR (&USART_1_SFR) #define UART_IE_RX_BIT (1 << 4) #define UART_IE_TX_BIT (1 << 5) -#define UART_ME (SFR->ME2) #define UART_ME_BITS (0x30) -#define UART_PORT (PORT_3) +#define UART_PORT (&PORT_3) #define UART_RX_PIN (1 << 6) #define UART_TX_PIN (1 << 7) #define UART_RX_ISR (USART1RX_VECTOR) @@ -82,12 +80,10 @@ static const msp430_clock_params_t clock_params = { #define SPI_NUMOF (1U) /* SPI configuration */ -#define SPI_BASE (USART_0) -#define SPI_IE (SFR->IE1) -#define SPI_IF (SFR->IFG1) +#define SPI_BASE (&USART_0) +#define SPI_SFR (&USART_0_SFR) #define SPI_IE_RX_BIT (1 << 6) #define SPI_IE_TX_BIT (1 << 7) -#define SPI_ME (SFR->ME1) #define SPI_ME_BIT (1 << 6) #define SPI_PIN_MISO GPIO_PIN(P5, 2) #define SPI_PIN_MOSI GPIO_PIN(P5, 1) diff --git a/boards/msb-430h/include/periph_conf.h b/boards/msb-430h/include/periph_conf.h index 47b60ab4dd98..7f0dc217e816 100644 --- a/boards/msb-430h/include/periph_conf.h +++ b/boards/msb-430h/include/periph_conf.h @@ -48,7 +48,7 @@ static const msp430_clock_params_t clock_params = { * @{ */ #define TIMER_NUMOF (1U) -#define TIMER_BASE (TIMER_A) +#define TIMER_BASE (&TIMER_A) #define TIMER_CHAN (3) #define TIMER_ISR_CC0 (TIMERA0_VECTOR) #define TIMER_ISR_CCX (TIMERA1_VECTOR) @@ -60,14 +60,12 @@ static const msp430_clock_params_t clock_params = { */ #define UART_NUMOF (1U) -#define UART_BASE (USART_1) -#define UART_IE (SFR->IE2) -#define UART_IF (SFR->IFG2) +#define UART_BASE (&USART_1) +#define UART_SFR (&USART_1_SFR) #define UART_IE_RX_BIT (1 << 4) #define UART_IE_TX_BIT (1 << 5) -#define UART_ME (SFR->ME2) #define UART_ME_BITS (0x30) -#define UART_PORT (PORT_3) +#define UART_PORT (&PORT_3) #define UART_RX_PIN (1 << 6) #define UART_TX_PIN (1 << 7) #define UART_RX_ISR (USART1RX_VECTOR) @@ -81,12 +79,10 @@ static const msp430_clock_params_t clock_params = { #define SPI_NUMOF (1U) /* SPI configuration */ -#define SPI_BASE (USART_0) -#define SPI_IE (SFR->IE1) -#define SPI_IF (SFR->IFG1) +#define SPI_BASE (&USART_0) +#define SPI_SFR (&USART_0_SFR) #define SPI_IE_RX_BIT (1 << 6) #define SPI_IE_TX_BIT (1 << 7) -#define SPI_ME (SFR->ME1) #define SPI_ME_BIT (1 << 6) #define SPI_PIN_MISO GPIO_PIN(P3, 2) #define SPI_PIN_MOSI GPIO_PIN(P3, 1) diff --git a/boards/olimex-msp430-h1611/include/periph_conf.h b/boards/olimex-msp430-h1611/include/periph_conf.h index fb5f92a9b993..de59e548f20a 100644 --- a/boards/olimex-msp430-h1611/include/periph_conf.h +++ b/boards/olimex-msp430-h1611/include/periph_conf.h @@ -48,7 +48,7 @@ static const msp430_clock_params_t clock_params = { * @{ */ #define TIMER_NUMOF (1U) -#define TIMER_BASE (TIMER_A) +#define TIMER_BASE (&TIMER_A) #define TIMER_CHAN (3) #define TIMER_ISR_CC0 (TIMERA0_VECTOR) #define TIMER_ISR_CCX (TIMERA1_VECTOR) @@ -60,14 +60,12 @@ static const msp430_clock_params_t clock_params = { */ #define UART_NUMOF (1U) -#define UART_BASE (USART_1) -#define UART_IE (SFR->IE2) -#define UART_IF (SFR->IFG2) +#define UART_BASE (&USART_1) +#define UART_SFR (&USART_1_SFR) #define UART_IE_RX_BIT (1 << 4) #define UART_IE_TX_BIT (1 << 5) -#define UART_ME (SFR->ME2) #define UART_ME_BITS (0x30) -#define UART_PORT (PORT_3) +#define UART_PORT (&PORT_3) #define UART_RX_PIN (1 << 6) #define UART_TX_PIN (1 << 7) #define UART_RX_ISR (USART1RX_VECTOR) @@ -81,12 +79,10 @@ static const msp430_clock_params_t clock_params = { #define SPI_NUMOF (1U) /* SPI configuration */ -#define SPI_BASE (USART_0) -#define SPI_IE (SFR->IE1) -#define SPI_IF (SFR->IFG1) +#define SPI_BASE (&USART_0) +#define SPI_SFR (&USART_0_SFR) #define SPI_IE_RX_BIT (1 << 6) #define SPI_IE_TX_BIT (1 << 7) -#define SPI_ME (SFR->ME1) #define SPI_ME_BIT (1 << 6) #define SPI_PIN_MISO GPIO_PIN(P3, 2) #define SPI_PIN_MOSI GPIO_PIN(P3, 1) diff --git a/boards/olimex-msp430-h2618/include/periph_conf.h b/boards/olimex-msp430-h2618/include/periph_conf.h index 3c089fe5211a..ebec03431a70 100644 --- a/boards/olimex-msp430-h2618/include/periph_conf.h +++ b/boards/olimex-msp430-h2618/include/periph_conf.h @@ -47,7 +47,7 @@ static const msp430_clock_params_t clock_params = { * @{ */ #define TIMER_NUMOF (1U) -#define TIMER_BASE (TIMER_A) +#define TIMER_BASE (&TIMER_A) #define TIMER_CHAN (3) #define TIMER_ISR_CC0 (TIMERA0_VECTOR) #define TIMER_ISR_CCX (TIMERA1_VECTOR) @@ -59,14 +59,14 @@ static const msp430_clock_params_t clock_params = { */ #define UART_NUMOF (1U) -#define UART_BASE (USCI_0) -#define UART_IE (SFR->IE2) -#define UART_IF (SFR->IFG2) +#define UART_BASE (&USCI_A0) +#define UART_IE (IE2) +#define UART_IF (IFG2) #define UART_IE_RX_BIT (1 << 0) #define UART_IE_TX_BIT (1 << 1) -#define UART_RX_PORT ((msp_port_t *)PORT_3) +#define UART_RX_PORT (&PORT_3) #define UART_RX_PIN (1 << 5) -#define UART_TX_PORT ((msp_port_t *)PORT_3) +#define UART_TX_PORT (&PORT_3) #define UART_TX_PIN (1 << 4) #define UART_RX_ISR (USCIAB0RX_VECTOR) #define UART_TX_ISR (USCIAB0TX_VECTOR) @@ -79,9 +79,9 @@ static const msp430_clock_params_t clock_params = { #define SPI_NUMOF (1U) /* SPI configuration */ -#define SPI_BASE (USCI_0_B_SPI) -#define SPI_IE (SFR->IE2) -#define SPI_IF (SFR->IFG2) +#define SPI_BASE (&USCI_B0) +#define SPI_IE (IE2) +#define SPI_IF (IFG2) #define SPI_IE_RX_BIT (1 << 2) #define SPI_IE_TX_BIT (1 << 3) #define SPI_PIN_MISO GPIO_PIN(P3, 2) diff --git a/boards/telosb/include/periph_conf.h b/boards/telosb/include/periph_conf.h index 214b73adbcd9..5ee5a858d982 100644 --- a/boards/telosb/include/periph_conf.h +++ b/boards/telosb/include/periph_conf.h @@ -48,7 +48,7 @@ static const msp430_clock_params_t clock_params = { * @{ */ #define TIMER_NUMOF (1U) -#define TIMER_BASE (TIMER_A) +#define TIMER_BASE (&TIMER_A) #define TIMER_CHAN (3) #define TIMER_ISR_CC0 (TIMERA0_VECTOR) #define TIMER_ISR_CCX (TIMERA1_VECTOR) @@ -60,14 +60,12 @@ static const msp430_clock_params_t clock_params = { */ #define UART_NUMOF (1U) -#define UART_BASE (USART_1) -#define UART_IE (SFR->IE2) -#define UART_IF (SFR->IFG2) +#define UART_BASE (&USART_1) +#define UART_SFR (&USART_1_SFR) #define UART_IE_RX_BIT (1 << 4) #define UART_IE_TX_BIT (1 << 5) -#define UART_ME (SFR->ME2) #define UART_ME_BITS (0x30) -#define UART_PORT (PORT_3) +#define UART_PORT (&PORT_3) #define UART_RX_PIN (1 << 6) #define UART_TX_PIN (1 << 7) #define UART_RX_ISR (USART1RX_VECTOR) @@ -80,13 +78,10 @@ static const msp430_clock_params_t clock_params = { */ #define SPI_NUMOF (1U) -/* SPI configuration */ -#define SPI_BASE (USART_0) -#define SPI_IE (SFR->IE1) -#define SPI_IF (SFR->IFG1) +#define SPI_BASE (&USART_0) +#define SPI_SFR (&USART_0_SFR) #define SPI_IE_RX_BIT (1 << 6) #define SPI_IE_TX_BIT (1 << 7) -#define SPI_ME (SFR->ME1) #define SPI_ME_BIT (1 << 6) #define SPI_PIN_MISO GPIO_PIN(P3, 2) #define SPI_PIN_MOSI GPIO_PIN(P3, 1) diff --git a/boards/z1/include/periph_conf.h b/boards/z1/include/periph_conf.h index 479cf12594ce..b3c32638f8f5 100644 --- a/boards/z1/include/periph_conf.h +++ b/boards/z1/include/periph_conf.h @@ -48,7 +48,7 @@ static const msp430_clock_params_t clock_params = { * @{ */ #define TIMER_NUMOF (1U) -#define TIMER_BASE (TIMER_A) +#define TIMER_BASE (&TIMER_A) #define TIMER_CHAN (3) #define TIMER_ISR_CC0 (TIMERA0_VECTOR) #define TIMER_ISR_CCX (TIMERA1_VECTOR) @@ -60,14 +60,14 @@ static const msp430_clock_params_t clock_params = { */ #define UART_NUMOF (1U) -#define UART_BASE (USCI_0) -#define UART_IE (SFR->IE2) -#define UART_IF (SFR->IFG2) +#define UART_BASE (&USCI_A0) +#define UART_IE (IE2) +#define UART_IF (IFG2) #define UART_IE_RX_BIT (1 << 0) #define UART_IE_TX_BIT (1 << 1) -#define UART_RX_PORT ((msp_port_t *)PORT_3) +#define UART_RX_PORT (&PORT_3) #define UART_RX_PIN (1 << 5) -#define UART_TX_PORT ((msp_port_t *)PORT_3) +#define UART_TX_PORT (&PORT_3) #define UART_TX_PIN (1 << 4) #define UART_RX_ISR (USCIAB0RX_VECTOR) #define UART_TX_ISR (USCIAB0TX_VECTOR) @@ -80,9 +80,9 @@ static const msp430_clock_params_t clock_params = { #define SPI_NUMOF (1U) /* SPI configuration */ -#define SPI_BASE (USCI_0_B_SPI) -#define SPI_IE (SFR->IE2) -#define SPI_IF (SFR->IFG2) +#define SPI_BASE (&USCI_B0) +#define SPI_IE (IE2) +#define SPI_IF (IFG2) #define SPI_IE_RX_BIT (1 << 2) #define SPI_IE_TX_BIT (1 << 3) #define SPI_PIN_MISO GPIO_PIN(P3, 2) diff --git a/cpu/msp430/include/f2xx_g2xx/msp430_regs.h b/cpu/msp430/include/f2xx_g2xx/msp430_regs.h index 5f820d4c807c..c91ff80368f9 100644 --- a/cpu/msp430/include/f2xx_g2xx/msp430_regs.h +++ b/cpu/msp430/include/f2xx_g2xx/msp430_regs.h @@ -24,6 +24,7 @@ #define F2XX_G2XX_MSP430_REGS_H #include +#include #include "msp430_regs_common.h" @@ -32,161 +33,118 @@ extern "C" { #endif /** - * @brief USCI universal serial control interface registers + * @brief Universal Serial Control Interface Type A (USCI_A) Registers */ typedef struct { REG8 ABCTL; /**< auto baud rate control */ REG8 IRTCTL; /**< IrDA transmit control */ REG8 IRRCTL; /**< IrDA receive control */ - REG8 ACTL0; /**< A control 0 */ - REG8 ACTL1; /**< A control 1 */ - REG8 ABR0; /**< A baud rate control 0 */ - REG8 ABR1; /**< A baud rate control 1 */ - REG8 AMCTL; /**< A modulation control */ - REG8 ASTAT; /**< A status */ - REG8 ARXBUF; /**< A receive buffer */ - REG8 ATXBUF; /**< A transmit buffer */ - REG8 BCTL0; /**< B control 0 */ - REG8 BCTL1; /**< B control 1 */ - REG8 BBR0; /**< B baud rate 0 */ - REG8 BBR1; /**< B baud rate 1 */ - REG8 BI2CIE; /**< I2C interrupt enable */ - REG8 BSTAT; /**< B status */ - REG8 BRXBUF; /**< B receive buffer */ - REG8 BTXBUF; /**< B transmit buffer */ -} msp_usci_t; + REG8 CTL0; /**< control 0 */ + REG8 CTL1; /**< control 1 */ + REG8 BR0; /**< baud rate control 0 */ + REG8 BR1; /**< baud rate control 1 */ + REG8 MCTL; /**< modulation control */ + REG8 STAT; /**< status register */ + REG8 RXBUF; /**< receive buffer */ + REG8 TXBUF; /**< transmit buffer */ +} msp_usci_a_t; /** - * @brief USCI SPI specific registers + * @brief Universal Serial Control Interface Type B (USCI_B) Registers */ typedef struct { - REG8 CTL0; /**< control 0 */ - REG8 CTL1; /**< control 1 */ - REG8 BR0; /**< baud rate 0 */ - REG8 BR1; /**< baud rate 1 */ - REG8 reserved; /**< reserved */ - REG8 STAT; /**< status */ - REG8 RXBUF; /**< receive buffer */ - REG8 TXBUF; /**< transmit buffer */ -} msp_usci_spi_t; + REG8 CTL0; /**< control 0 */ + REG8 CTL1; /**< control 1 */ + REG8 BR0; /**< baud rate control 0 */ + REG8 BR1; /**< baud rate control 1 */ + REG8 MCTL; /**< modulation control */ + REG8 STAT; /**< status register */ + REG8 RXBUF; /**< receive buffer */ + REG8 TXBUF; /**< transmit buffer */ +} msp_usci_b_t; /** - * @name USCI control A register 0 bitmap + * @name USCI clock selection + * + * The vendor header files expose clock configurations with hard to read + * names. So we provide alias with better names + * * @{ */ -#define USCI_ACTL0_UCSYNC (0x01) -#define USCI_ACTL0_MODE_MASK (0x06) -#define USCI_ACTL0_MODE_UART (0x00) -#define USCI_ACTL0_MODE_ILMM (0x02) -#define USCI_ACTL0_MODE_ABMM (0x04) -#define USCI_ACTL0_MODE_UART_ABR (0x06) -#define USCI_ACTL0_SPB (0x08) -#define USCI_ACTL0_7BIT (0x10) -#define USCI_ACTL0_MSB (0x20) -#define USCI_ACTL0_PAR (0x40) -#define USCI_ACTL0_PEN (0x80) +#define UCSSEL_UCLKI UCSSEL_0 /**< Clock USCI using CLKI (n/a in SPI mode) */ +#define UCSSEL_ACLK UCSSEL_1 /**< Clock USCI using auxiliary clock */ +#define UCSSEL_SMCLK UCSSEL_2 /**< Clock USCI using sub-system master clock */ /** @} */ /** - * @name USCI control register 0 bitmap SPI mode + * @name USCI Modulation Control fields + * + * The vendor header files provides bitmasks for each of the possible values + * from 0..7. But rather than creating a look up table, we can just shift the + * number in place, if there only would be a UCRBS_SHIFT macro. * @{ */ -#define USCI_SPI_CTL0_UCSYNC (0x01) -#define USCI_SPI_CTL0_MODE_3 (0x06) -#define USCI_SPI_CTL0_MODE_0 (0x00) -#define USCI_SPI_CTL0_MODE_1 (0x02) -#define USCI_SPI_CTL0_MODE_2 (0x04) -#define USCI_SPI_CTL0_MST (0x08) -#define USCI_SPI_CTL0_7BIT (0x10) -#define USCI_SPI_CTL0_MSB (0x20) -#define USCI_SPI_CTL0_CKPL (0x40) -#define USCI_SPI_CTL0_CKPH (0x80) -/** @} */ +#define UCBRS_MASK UCBRS_7 /**< Bitmask to retrieve the UCRBS field of the + USCI modulation control register */ +#if (UCBRS_7 == 0x0E) || defined(DOXYGEN) +#define UCBRS_POS 1 /**< Position of the UCRBS field in the + UCAxMCTL register */ +#else +/* The datasheet for the whole MCU family states the field is in bits 3-1, + * but let's better be safe than sorry here */ +#error "UCBRS field in the UCAxMCTL register at unexpected position." +#endif -/** - * @name USCI status register bitmap SPI mode - * @{ - */ -#define USCI_SPI_STAT_UCBUSY (0x01) -#define USCI_SPI_STAT_UCOE (0x20) -#define USCI_SPI_STAT_UCFE (0x40) -#define USCI_SPI_STAT_UCLISTEN (0x80) /** @} */ /** - * @name USCI control A register 1 bitmap - * @{ + * @brief "Convert" a USCI A into an USCI B interface + * + * The USCI peripheral come in two flavors: USCI A and USCI B with the following + * feature set. When comparing the memory map USCI B is a subset of USCI A + * registers, which conveniently have the same offsets. It is therefore possible + * to address USCI A registers as if it was a USCI B interface when operated + * in SPI mode. This makes implementation of SPI easier. + * + * | Name | UART | SPI | I2C | IrDA | + * |:------ |:----- |:----- |:----- |:----- | + * | USCI A | ✔ | ✔ | ✗ | ✔ | + * | USCI B | ✗ | ✔ | ✔ | ✗ | */ -#define USCI_ACTL1_SWRST (0x01) -#define USCI_ACTL1_TXBRK (0x02) -#define USCI_ACTL1_TXADDR (0x04) -#define USCI_ACTL1_DORM (0x08) -#define USCI_ACTL1_BRKIE (0x10) -#define USCI_ACTL1_RXEIE (0x20) -#define USCI_ACTL1_SSEL_MASK (0xc0) -#define USCI_ACTL1_SSEL_UCLK (0x00) -#define USCI_ACTL1_SSEL_ACLK (0x40) -#define USCI_ACTL1_SSEL_SMCLK (0xc0) -/** @} */ +static inline msp_usci_b_t * msp430_usci_b_from_usci_a(msp_usci_a_t *usci_a) +{ + uintptr_t usci_b = (uintptr_t)usci_a + offsetof(msp_usci_a_t, CTL0); + return (msp_usci_b_t *)usci_b; +} /** - * @name USCI control register 1 bitmap SPI mode + * @name Typing of base register objects * @{ */ -#define USCI_SPI_CTL1_SWRST (0x01) -#define USCI_SPI_CTL1_SSEL_MASK (0xc0) -#define USCI_SPI_CTL1_SSEL_NA (0x00) -#define USCI_SPI_CTL1_SSEL_ACLK (0x40) -#define USCI_SPI_CTL1_SSEL_SMCLK (0xc0) -/** @} */ - /** - * @name USCI modulation A control register - * @{ + * @brief USCI_A0 register map + * + * @details Provided by linker */ -#define USCI_AMCTL_OS16 (0x01) -#define USCI_AMCTL_BRS_MASK (0xe0) -#define USCI_AMCTL_BRS_SHIFT (1U) -#define USCI_AMCTL_BRF_MASK (0xf0) -#define USCI_AMCTL_BRF_SHIFT (4U) -/** @} */ - +extern msp_usci_a_t USCI_A0; /** - * @name USCI status A register bitmap - * @{ + * @brief USCI_A1 register map + * + * @details Provided by linker */ -#define USCI_ASTAT_BUSY (0x01) -#define USCI_ASTAT_IDLE (0x02) -#define USCI_ASTAT_ADDR (0x02) -#define USCI_ASTAT_RXERR (0x04) -#define USCI_ASTAT_BRK (0x08) -#define USCI_ASTAT_PE (0x10) -#define USCI_ASTAT_OE (0x20) -#define USCI_ASTAT_FE (0x40) -#define USCI_ASTAT_LISTEN (0x80) -/** @} */ +extern msp_usci_a_t USCI_A1; /** - * @name Base register address definitions - * @{ + * @brief USCI_B0 register map + * + * @details Provided by linker */ -#define USCI_0_BASE ((uint16_t)0x005d) -#define USCI_0_A_BASE ((uint16_t)0x0060) -#define USCI_0_B_BASE ((uint16_t)0x0068) -#define USCI_1_BASE ((uint16_t)0x00cd) -#define USCI_1_A_BASE ((uint16_t)0x00d0) -#define USCI_1_B_BASE ((uint16_t)0x00d8) -/** @} */ - +extern msp_usci_a_t USCI_B0; /** - * @name Typing of base register objects - * @{ + * @brief USCI_B1 register map + * + * @details Provided by linker */ -#define USCI_0 ((msp_usci_t *)USCI_0_BASE) -#define USCI_1 ((msp_usci_t *)USCI_1_BASE) -#define USCI_0_A_SPI ((msp_usci_spi_t *)USCI_0_A_BASE) -#define USCI_0_B_SPI ((msp_usci_spi_t *)USCI_0_B_BASE) -#define USCI_1_A ((msp_usci_t *)USCI_1_A_BASE) -#define USCI_1_B ((msp_usci_t *)USCI_1_B_BASE) +extern msp_usci_a_t USCI_B1; /** @} */ #ifdef __cplusplus diff --git a/cpu/msp430/include/f2xx_g2xx/periph_cpu.h b/cpu/msp430/include/f2xx_g2xx/periph_cpu.h index ccfb602675ec..8153592284c6 100644 --- a/cpu/msp430/include/f2xx_g2xx/periph_cpu.h +++ b/cpu/msp430/include/f2xx_g2xx/periph_cpu.h @@ -34,12 +34,17 @@ extern "C" { #define HAVE_SPI_MODE_T /**< MSP430 F2xx/G2xx has a custom spi_mode_t */ /** * @brief Support SPI modes + * + * | Field | Name | Description | + * |:------ |:--------------------- |:----------------------------------------------------- | + * | UCCKPH | Clock phase select | 0 = capture on second edge, 1 = capture on first | + * | UCCKPL | Clock polarity select | 0 = clock is idle-low, 1 = clock is high idle-high | */ typedef enum { - SPI_MODE_0 = (USCI_SPI_CTL0_CKPH), /**< CPOL=0, CPHA=0 */ - SPI_MODE_1 = 0, /**< CPOL=0, CPHA=1 */ - SPI_MODE_2 = (USCI_SPI_CTL0_CKPL | USCI_SPI_CTL0_CKPH), /**< CPOL=1, CPHA=0 */ - SPI_MODE_3 = (USCI_SPI_CTL0_CKPL) /**< CPOL=1, CPHA=1 */ + SPI_MODE_0 = (UCCKPH), /**< CPOL=0, CPHA=0 */ + SPI_MODE_1 = 0, /**< CPOL=0, CPHA=1 */ + SPI_MODE_2 = (UCCKPL | UCCKPH), /**< CPOL=1, CPHA=0 */ + SPI_MODE_3 = (UCCKPL) /**< CPOL=1, CPHA=1 */ } spi_mode_t; /** @} */ diff --git a/cpu/msp430/include/msp430_regs_common.h b/cpu/msp430/include/msp430_regs_common.h index a9e752a121a5..0796e474f451 100644 --- a/cpu/msp430/include/msp430_regs_common.h +++ b/cpu/msp430/include/msp430_regs_common.h @@ -40,39 +40,74 @@ extern "C" { #define REG16 volatile uint16_t /** - * @brief Special function registers + * @name Timer SSEL Values + * + * @details When using the macros in the vendor header files such as TASSEL_0 + * the actually used clock is non-obvious. Hence, provide aliases + * with obvious names. + * @{ */ -typedef struct { - REG8 IE1; /**< interrupt enable 1 */ - REG8 IE2; /**< interrupt enable 2 */ - REG8 IFG1; /**< interrupt flag 1 */ - REG8 IFG2; /**< interrupt flag 2 */ - REG8 ME1; /**< module enable 1 */ - REG8 ME2; /**< module enable 2 */ -} msp_sfr_t; +#define TXSSEL_TXCLK TASSEL_0 /**< External TxCLK as clock source */ +#define TXSSEL_ACLK TASSEL_1 /**< Auxiliary clock as clock source */ +#define TXSSEL_SMCLK TASSEL_2 /**< Sub-system master clock as clock source */ +#define TXSSEL_INCLK TASSEL_3 /**< External INCLK as clock source */ +/** @} */ + +/** + * @name Timer Input Divider Values + * + * @details The vendor header macros are again non-obvious in their naming, so + * provide better alies names. + * @{ + */ +#define TXID_DIV_1 ID_0 /**< Input Divider: Divide by 1 */ +#define TXID_DIV_2 ID_1 /**< Input Divider: Divide by 2 */ +#define TXID_DIV_4 ID_2 /**< Input Divider: Divide by 4 */ +#define TXID_DIV_8 ID_3 /**< Input Divider: Divide by 4 */ +/** @} */ + +/** + * @name Timer Mode Control Values + * + * @details The vendor header macros are again non-obvious in their naming, so + * provide better alies names. + * @{ + */ +#define TXMC_STOP MC_0 /**< Stop Mode */ +#define TXMC_UP MC_1 /**< Up to CCR0 Mode*/ +#define TXMC_CONT MC_2 /**< Continuous Mode */ +#define TXMC_UP_DOWN MC_3 /**< Up/Down Mode */ +#define TXMC_MASK MC_3 /**< Bitmask to retrieve MC field */ +/** @} */ /** - * @brief Digital I/O Port w/o interrupt functionality (P3-P6) + * @brief Common MSP GPIO Port Registers */ typedef struct { REG8 IN; /**< input data */ REG8 OD; /**< output data */ REG8 DIR; /**< pin direction */ - REG8 SEL; /**< alternative function select */ } msp_port_t; /** - * @brief Digital I/O Port with interrupt functionality (P1 & P2) + * @brief GPIO Port 1/2 (with interrupt functionality) */ typedef struct { - REG8 IN; /**< input data */ - REG8 OD; /**< output data */ - REG8 DIR; /**< pin direction */ + msp_port_t base; /**< common GPIO port registers */ REG8 IFG; /**< interrupt flag */ REG8 IES; /**< interrupt edge select */ REG8 IE; /**< interrupt enable */ REG8 SEL; /**< alternative function select */ -} msp_port_isr_t; +} msp_port_p1_p2_t; + +/** + * @brief GPIO Port 3..6 (without interrupt functionality) + */ +typedef struct { + msp_port_t base; /**< common GPIO port registers */ + REG8 SEL; /**< alternative function select */ +} msp_port_p3_p6_t; + /** * @brief Timer interrupt status registers @@ -94,140 +129,51 @@ typedef struct { } msp_timer_t; /** - * @name SFR interrupt enable 1 register bitmap + * @name MSP430 Common Peripheral Register Maps + * + * @details The addresses will be provided by the linker script using the + * vendor files. * @{ */ -#define SFR_IE1_OFIE (0x02) -#define SFR_IE1_URXIE0 (0x40) -#define SFR_IE1_UTXIE0 (0x80) -/** @} */ - /** - * @name SFR interrupt enable 2 register bitmap - * @{ + * @brief Register map of GPIO PORT 1 */ -#define SFR_IE2_UCA0RXIE (0x01) -#define SFR_IE2_UCA0TXIE (0x02) -#define SFR_IE2_URXIE2 (0x10) -#define SFR_IE2_UTXIE2 (0x20) -/** @} */ - +extern msp_port_p1_p2_t PORT_1; /** - * @name SFR interrupt flag 1 register bitmap - * @{ + * @brief Register map of GPIO PORT 2 */ -#define SFR_IFG1_OFIFG (0x02) -#define SFR_IFG1_URXIFG0 (0x40) -#define SFR_IFG1_UTXIFG0 (0x80) -/** @} */ - +extern msp_port_p1_p2_t PORT_2; /** - * @name SFR interrupt flag 2 register bitmap - * @{ + * @brief Register map of GPIO PORT 3 */ -#define SFR_IFG2_UCA0RXIFG (0x01) -#define SFR_IFG2_UCA0TXIFG (0x02) -#define SFR_IFG2_URXIFG1 (0x10) -#define SFR_IFG2_UTXIFG1 (0x20) -/** @} */ - +extern msp_port_p3_p6_t PORT_3; /** - * @name SFR module enable register 1 - * @{ + * @brief Register map of GPIO PORT 4 */ -#define SFR_ME1_USPIE0 (0x40) -/** @} */ - +extern msp_port_p3_p6_t PORT_4; /** - * @name SFR module enable register 2 - * @{ + * @brief Register map of GPIO PORT 5 */ -#define SFR_ME2_USPIE1 (0x10) -/** @} */ - +extern msp_port_p3_p6_t PORT_5; /** - * @name Timer Control register bitmap - * @{ + * @brief Register map of GPIO PORT 6 */ -#define TIMER_CTL_IFG (0x0001) -#define TIMER_CTL_IE (0x0002) -#define TIMER_CTL_CLR (0x0004) -#define TIMER_CTL_MC_MASK (0x0030) -#define TIMER_CTL_MC_STOP (0x0000) -#define TIMER_CTL_MC_UP (0x0010) -#define TIMER_CTL_MC_CONT (0x0020) -#define TIMER_CTL_MC_UPDOWN (0x0030) -#define TIMER_CTL_ID_MASK (0x00c0) -#define TIMER_CTL_ID_DIV1 (0x0000) -#define TIMER_CTL_ID_DIV2 (0x0040) -#define TIMER_CTL_ID_DIV4 (0x0080) -#define TIMER_CTL_ID_DIV8 (0x00c0) -#define TIMER_CTL_TASSEL_MASK (0x0300) -#define TIMER_CTL_TASSEL_TCLK (0x0000) -#define TIMER_CTL_TASSEL_ACLK (0x0100) -#define TIMER_CTL_TASSEL_SMCLK (0x0200) -#define TIMER_CTL_TASSEL_INV_TCLK (0x0300) -/** @} */ +extern msp_port_p3_p6_t PORT_6; /** - * @name Timer Channel Control register bitmap - * @{ + * @brief Register map of the timer interrupt control registers */ -#define TIMER_CCTL_CCIFG (0x0001) -#define TIMER_CCTL_COV (0x0002) -#define TIMER_CCTL_OUT (0x0004) -#define TIMER_CCTL_CCI (0x0008) -#define TIMER_CCTL_CCIE (0x0010) -#define TIMER_CCTL_OUTMOD_MASK (0x00e0) -#define TIMER_CCTL_OUTMOD_OUTVAL (0x0000) -#define TIMER_CCTL_OUTMOD_SET (0x0020) -#define TIMER_CCTL_OUTMOD_TOG_RESET (0x0040) -#define TIMER_CCTL_OUTMOD_SET_RESET (0x0060) -#define TIMER_CCTL_OUTMOD_TOGGLE (0x0080) -#define TIMER_CCTL_OUTMOD_RESET (0x00a0) -#define TIMER_CCTL_OUTMOD_TOG_SET (0x00c0) -#define TIMER_CCTL_OUTMOD_RESET_SET (0x00e0) -#define TIMER_CCTL_CAP (0x0100) -#define TIMER_CCTL_CLLD_MASK (0x0600) -#define TIMER_CCTL_SCS (0x0800) -#define TIMER_CCTL_CCIS_MASK (0x3000) -#define TIMER_CCTL_CM_MASK (0xc000) -/** @} */ +extern msp_timer_ivec_t TIMER_IVEC; /** - * @name Base register address definitions - * @{ + * @brief Register map of the timer A control registers */ -#define SFR_BASE ((uint16_t)0x0000) -#define PORT_1_BASE ((uint16_t)0x0020) -#define PORT_2_BASE ((uint16_t)0x0028) -#define PORT_3_BASE ((uint16_t)0x0018) -#define PORT_4_BASE ((uint16_t)0x001c) -#define PORT_5_BASE ((uint16_t)0x0030) -#define PORT_6_BASE ((uint16_t)0x0034) -#define CLK_BASE ((uint16_t)0x0053) -#define TIMER_IVEC_BASE ((uint16_t)0x011e) -#define TIMER_A_BASE ((uint16_t)0x0160) -#define TIMER_B_BASE ((uint16_t)0x0180) -#define WD_BASE ((uint16_t)0x0120) -/** @} */ +extern msp_timer_t TIMER_A; /** - * @name Typing of base register objects - * @{ + * @brief Register map of the timer B control registers */ -#define SFR ((msp_sfr_t *)SFR_BASE) -#define PORT_1 ((msp_port_t *)PORT_1_BASE) -#define PORT_2 ((msp_port_t *)PORT_2_BASE) -#define PORT_3 ((msp_port_t *)PORT_3_BASE) -#define PORT_4 ((msp_port_t *)PORT_4_BASE) -#define PORT_5 ((msp_port_t *)PORT_5_BASE) -#define PORT_6 ((msp_port_t *)PORT_6_BASE) -#define CLK ((msp_clk_t *)CLK_BASE) -#define TIMER_IVEC ((msp_timer_ivec_t *)TIMER_IVEC_BASE) -#define TIMER_A ((msp_timer_t *)TIMER_A_BASE) -#define TIMER_B ((msp_timer_t *)TIMER_B_BASE) -#define WD ((msp_wd_t *)WD_BASE) +extern msp_timer_t TIMER_B; /** @} */ #ifdef __cplusplus diff --git a/cpu/msp430/include/periph_cpu_common.h b/cpu/msp430/include/periph_cpu_common.h index 777bcbda0d4d..69dbf3628668 100644 --- a/cpu/msp430/include/periph_cpu_common.h +++ b/cpu/msp430/include/periph_cpu_common.h @@ -53,10 +53,13 @@ typedef uint16_t gpio_t; #define SPI_HWCS(x) (SPI_CS_UNDEF) /** - * @brief Override flank selection values + * @name Override flank selection values * @{ */ -#define HAVE_GPIO_FLANK_T +#define HAVE_GPIO_FLANK_T /**< MSP430 has a custom gpio_flank_t */ +/** + * @brief Enumeration of supported GPIO flanks + */ typedef enum { GPIO_FALLING = 0xff, /**< emit interrupt on falling flank */ GPIO_RISING = 0x00, /**< emit interrupt on rising flank */ diff --git a/cpu/msp430/include/x1xx/msp430_regs.h b/cpu/msp430/include/x1xx/msp430_regs.h index 3991d3f5ab72..d16c1b33b1c5 100644 --- a/cpu/msp430/include/x1xx/msp430_regs.h +++ b/cpu/msp430/include/x1xx/msp430_regs.h @@ -30,8 +30,9 @@ #ifdef __cplusplus extern "C" { #endif + /** - * @brief USART (UART, SPI and I2C) registers + * @brief USART (UART, SPI and I2C) Registers */ typedef struct { REG8 CTL; /**< USART control */ @@ -45,63 +46,63 @@ typedef struct { } msp_usart_t; /** - * @name USART control register bitmap - * @{ + * @brief USART Special Function Registers (SFR) + * + * Despite being part of the USART peripheral, the SFR registers location is + * completely different. Even more confusing, the IE register of USART 1 + * follows the IE register of USART 0. Hence, the SFR register map of the two + * USART peripherals will overlap (with the IE register of the second USART + * being located at the first padding of the first USART). The padding bytes + * are intentionally declared as `const` to aid in preventing accidentally + * overwriting registers of the other USART's SFR registers. */ -#define USART_CTL_SWRST (0x01) -#define USART_CTL_MM (0x02) -#define USART_CTL_SYNC (0x04) -#define USART_CTL_LISTEN (0x08) -#define USART_CTL_CHAR (0x10) -#define USART_CTL_SPB (0x20) -#define USART_CTL_PEV (0x40) -#define USART_CTL_PENA (0x80) -/** @} */ +typedef struct { + REG8 IE; /**< USART Interrupt Enable Register */ + const uint8_t _pad1;/**< Padding */ + REG8 IFG; /**< USART Interrupt Flag Register */ + const uint8_t _pad2;/**< Padding */ + REG8 ME; /**< Module Enable Register */ +} msp_usart_sfr_t; /** - * @name USART transmit control register bitmap + * @name USART clock selection + * + * The vendor header files expose clock configurations selection field as one + * bitmask per bit. This is pretty hard to read in the code, so we provide + * alias with better names. + * * @{ */ -#define USART_TCTL_TXEPT (0x01) -#define USART_TCTL_STC (0x02) -#define USART_TCTL_TXWAKE (0x04) -#define USART_TCTL_URXSE (0x08) -#define USART_TCTL_SSEL_MASK (0x30) -#define USART_TCTL_SSEL_UCLKI (0x00) -#define USART_TCTL_SSEL_ACLK (0x10) -#define USART_TCTL_SSEL_SMCLK (0x20) -#define USART_TCTL_CKPL (0x40) -#define USART_TCTL_CKPH (0x80) +#define UXTCTL_SSEL_UCLKI 0 /**< Clock USART using UCLKI clock */ +#define UXTCTL_SSEL_ACLK SSEL0 /**< Clock USART using auxiliary clock */ +#define UXTCTL_SSEL_SMCLK SSEL1 /**< Clock USART using sub-system master clock */ +#define UXTCTL_SSEL_MASK (SSEL0 | SSEL1) /**< Mask to retrieve SSEL field */ /** @} */ /** - * @name USART receive control register bitmap + * @name Typing of base register objects * @{ */ -#define USART_RCTL_RXERR (0x01) -#define USART_RCTL_RXWAKE (0x02) -#define USART_RCTL_URXWIE (0x04) -#define USART_RCTL_URXEIE (0x08) -#define USART_RCTL_BRK (0x10) -#define USART_RCTL_OE (0x20) -#define USART_RCTL_PE (0x40) -#define USART_RCTL_FE (0x80) -/** @} */ - /** - * @name Base register address definitions - * @{ + * @brief USART 0 SFR register map */ -#define USART_0_BASE ((uint16_t)0x0070) -#define USART_1_BASE ((uint16_t)0x0078) -/** @} */ - +extern msp_usart_sfr_t USART_0_SFR; /** - * @name Typing of base register objects - * @{ + * @brief USART 1 SFR register map + */ +extern msp_usart_sfr_t USART_1_SFR; +/** + * @brief USART 0 register map + * + * @details The address is provided by the linker script + */ +extern msp_usart_t USART_0; +/** + * @brief USART 1 register map + * + * @details The address is provided by the linker script */ -#define USART_0 ((msp_usart_t *)USART_0_BASE) -#define USART_1 ((msp_usart_t *)USART_1_BASE) +extern msp_usart_t USART_1; /** @} */ #ifdef __cplusplus diff --git a/cpu/msp430/include/x1xx/periph_cpu.h b/cpu/msp430/include/x1xx/periph_cpu.h index 49da4ddfb92b..700e20aa38f1 100644 --- a/cpu/msp430/include/x1xx/periph_cpu.h +++ b/cpu/msp430/include/x1xx/periph_cpu.h @@ -33,13 +33,18 @@ extern "C" { */ #define HAVE_SPI_MODE_T /**< MSP430 x1xx has a custom spi_mode_t */ /** - * @brief Supported SPI modes + * @brief Support SPI modes + * + * | Field | Name | Description | + * |:------ |:--------------------- |:----------------------------------------------------- | + * | CKPH | Clock phase select | 0 = capture on second edge, 1 = capture on first | + * | CKPL | Clock polarity select | 0 = clock is idle-low, 1 = clock is high idle-high | */ typedef enum { - SPI_MODE_0 = (USART_TCTL_CKPH), /**< CPOL=0, CPHA=0 */ - SPI_MODE_1 = 0, /**< CPOL=0, CPHA=1 */ - SPI_MODE_2 = (USART_TCTL_CKPL | USART_TCTL_CKPH), /**< CPOL=1, CPHA=0 */ - SPI_MODE_3 = (USART_TCTL_CKPL) /**< CPOL=1, CPHA=1 */ + SPI_MODE_0 = (CKPH), /**< CPOL=0, CPHA=0 */ + SPI_MODE_1 = 0, /**< CPOL=0, CPHA=1 */ + SPI_MODE_2 = (CKPL | CKPH), /**< CPOL=1, CPHA=0 */ + SPI_MODE_3 = (CKPL) /**< CPOL=1, CPHA=1 */ } spi_mode_t; /** @} */ diff --git a/cpu/msp430/ldscripts/msp430_common.ld b/cpu/msp430/ldscripts/msp430_common.ld index 93474c22dbc6..a214c2a35de4 100644 --- a/cpu/msp430/ldscripts/msp430_common.ld +++ b/cpu/msp430/ldscripts/msp430_common.ld @@ -20,3 +20,20 @@ SECTIONS _end_fw = . ; } > ROM } + +/* provide address for register maps by taking the address of the first + * register (as provided by the vendor files) */ + +PROVIDE(PORT_1 = P1IN); +PROVIDE(PORT_2 = P2IN); +PROVIDE(PORT_3 = P3IN); +PROVIDE(PORT_3 = P3IN); +PROVIDE(PORT_4 = P4IN); +PROVIDE(PORT_5 = P5IN); +PROVIDE(PORT_6 = P6IN); + +/* no typo: TBIV indeed comes before TAIV in memory, see msp_timer_ivec_t */ +PROVIDE(TIMER_IVEC = TBIV); + +PROVIDE(TIMER_A = TACTL); +PROVIDE(TIMER_B = TBCTL); diff --git a/cpu/msp430/ldscripts/msp430_f2xx_g2xx.ld b/cpu/msp430/ldscripts/msp430_f2xx_g2xx.ld new file mode 100644 index 000000000000..cb90d22587f2 --- /dev/null +++ b/cpu/msp430/ldscripts/msp430_f2xx_g2xx.ld @@ -0,0 +1,6 @@ +/* provide address for USCI register map by taking the address of the first + * register (as provided by the vendor files) */ +PROVIDE(USCI_A0 = UCA0ABCTL); +PROVIDE(USCI_A1 = UCA1ABCTL); +PROVIDE(USCI_B0 = UCB0CTL0); +PROVIDE(USCI_B1 = UCB1CTL0); diff --git a/cpu/msp430/ldscripts/msp430_x1xx.ld b/cpu/msp430/ldscripts/msp430_x1xx.ld new file mode 100644 index 000000000000..1789e7e16734 --- /dev/null +++ b/cpu/msp430/ldscripts/msp430_x1xx.ld @@ -0,0 +1,7 @@ +/* provide address for UASRT register map by taking the address of the first + * register (as provided by the vendor files) */ +PROVIDE(USART_0_SFR = IE1); +PROVIDE(USART_1_SFR = IE2); + +PROVIDE(USART_0 = U0CTL); +PROVIDE(USART_1 = U1CTL); diff --git a/cpu/msp430/ldscripts/riot-msp430f1611.ld b/cpu/msp430/ldscripts/riot-msp430f1611.ld index 1cdecc69ab0e..2a867b97dc69 100644 --- a/cpu/msp430/ldscripts/riot-msp430f1611.ld +++ b/cpu/msp430/ldscripts/riot-msp430f1611.ld @@ -1,3 +1,4 @@ INCLUDE msp430f1611.ld INCLUDE msp430_common.ld +INCLUDE msp430_x1xx.ld INCLUDE xfa.ld diff --git a/cpu/msp430/ldscripts/riot-msp430f1612.ld b/cpu/msp430/ldscripts/riot-msp430f1612.ld index 6f5b4016d4ab..bea375f722d6 100644 --- a/cpu/msp430/ldscripts/riot-msp430f1612.ld +++ b/cpu/msp430/ldscripts/riot-msp430f1612.ld @@ -1,3 +1,4 @@ INCLUDE msp430f1612.ld INCLUDE msp430_common.ld +INCLUDE msp430_x1xx.ld INCLUDE xfa.ld diff --git a/cpu/msp430/ldscripts/riot-msp430f1617.ld b/cpu/msp430/ldscripts/riot-msp430f1617.ld index 97987d26e1ca..b5b6fe3f5edd 100644 --- a/cpu/msp430/ldscripts/riot-msp430f1617.ld +++ b/cpu/msp430/ldscripts/riot-msp430f1617.ld @@ -1,3 +1,4 @@ INCLUDE msp430f1617.ld INCLUDE msp430_common.ld +INCLUDE msp430_x1xx.ld INCLUDE xfa.ld diff --git a/cpu/msp430/ldscripts/riot-msp430f2617.ld b/cpu/msp430/ldscripts/riot-msp430f2617.ld index 5e94f010b367..b475508b1fbc 100644 --- a/cpu/msp430/ldscripts/riot-msp430f2617.ld +++ b/cpu/msp430/ldscripts/riot-msp430f2617.ld @@ -1,3 +1,4 @@ INCLUDE msp430f2617.ld INCLUDE msp430_common.ld +INCLUDE msp430_f2xx_g2xx.ld INCLUDE xfa.ld diff --git a/cpu/msp430/ldscripts/riot-msp430f2618.ld b/cpu/msp430/ldscripts/riot-msp430f2618.ld index a6bf50c33d74..754a0fea746d 100644 --- a/cpu/msp430/ldscripts/riot-msp430f2618.ld +++ b/cpu/msp430/ldscripts/riot-msp430f2618.ld @@ -1,3 +1,4 @@ INCLUDE msp430f2618.ld INCLUDE msp430_common.ld +INCLUDE msp430_f2xx_g2xx.ld INCLUDE xfa.ld diff --git a/cpu/msp430/periph/gpio.c b/cpu/msp430/periph/gpio.c index f2b91042ac3f..fafd69c43a7b 100644 --- a/cpu/msp430/periph/gpio.c +++ b/cpu/msp430/periph/gpio.c @@ -19,8 +19,9 @@ * @} */ -#include "cpu.h" #include "bitarithm.h" +#include "container.h" +#include "cpu.h" #include "periph/gpio.h" /** @@ -36,20 +37,20 @@ static msp_port_t *_port(gpio_t pin) { switch (pin >> 8) { - case 1: - return PORT_1; - case 2: - return PORT_2; - case 3: - return PORT_3; - case 4: - return PORT_4; - case 5: - return PORT_5; - case 6: - return PORT_6; - default: - return NULL; + case 1: + return &PORT_1.base; + case 2: + return &PORT_2.base; + case 3: + return &PORT_3.base; + case 4: + return &PORT_4.base; + case 5: + return &PORT_5.base; + case 6: + return &PORT_6.base; + default: + return NULL; } } @@ -58,12 +59,15 @@ static inline uint8_t _pin(gpio_t pin) return (uint8_t)(pin & 0xff); } -static inline msp_port_isr_t *_isr_port(gpio_t pin) +static inline msp_port_p1_p2_t *_isr_port(gpio_t pin) { - msp_port_t *p = _port(pin); - if ((p == PORT_1) || (p == PORT_2)) { - return (msp_port_isr_t *)p; + /* checking for (pin >> 8) <= 2 requires 6 byte of .text more than + * checking the resulting address */ + msp_port_p1_p2_t *port = container_of(_port(pin), msp_port_p1_p2_t, base); + if ((port == &PORT_1) || (port == &PORT_2)) { + return port; } + return NULL; } @@ -90,12 +94,12 @@ int gpio_init(gpio_t pin, gpio_mode_t mode) void gpio_periph_mode(gpio_t pin, bool enable) { REG8 *sel; - msp_port_isr_t *isrport = _isr_port(pin); + msp_port_p1_p2_t *isrport = _isr_port(pin); if (isrport) { sel = &(isrport->SEL); } else { - msp_port_t *port = _port(pin); + msp_port_p3_p6_t *port = container_of(_port(pin), msp_port_p3_p6_t, base); if (port) { sel = &(port->SEL); } @@ -156,13 +160,13 @@ static gpio_isr_ctx_t isr_ctx[ISR_NUMOF]; static int _ctx(gpio_t pin) { int i = bitarithm_lsb(_pin(pin)); - return (_port(pin) == PORT_1) ? i : (i + 8); + return (_port(pin) == &PORT_1.base) ? i : (i + 8); } int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, gpio_cb_t cb, void *arg) { - msp_port_isr_t *port = _isr_port(pin); + msp_port_p1_p2_t *port = _isr_port(pin); /* check if port, pull resistor and flank configuration are valid */ if ((port == NULL) || (flank == GPIO_BOTH)) { @@ -189,7 +193,7 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, void gpio_irq_enable(gpio_t pin) { - msp_port_isr_t *port = _isr_port(pin); + msp_port_p1_p2_t *port = _isr_port(pin); if (port) { port->IE |= _pin(pin); } @@ -197,13 +201,13 @@ void gpio_irq_enable(gpio_t pin) void gpio_irq_disable(gpio_t pin) { - msp_port_isr_t *port = _isr_port(pin); + msp_port_p1_p2_t *port = _isr_port(pin); if (port) { port->IE &= ~(_pin(pin)); } } -static inline void isr_handler(msp_port_isr_t *port, int ctx) +static inline void isr_handler(msp_port_p1_p2_t *port, int ctx) { for (unsigned i = 0; i < PINS_PER_PORT; i++) { if ((port->IE & (1 << i)) && (port->IFG & (1 << i))) { @@ -216,14 +220,14 @@ static inline void isr_handler(msp_port_isr_t *port, int ctx) ISR(PORT1_VECTOR, isr_port1) { __enter_isr(); - isr_handler((msp_port_isr_t *)PORT_1, 0); + isr_handler(&PORT_1, 0); __exit_isr(); } ISR(PORT2_VECTOR, isr_port2) { __enter_isr(); - isr_handler((msp_port_isr_t *)PORT_2, 8); + isr_handler(&PORT_2, 8); __exit_isr(); } #endif /* MODULE_PERIPH_GPIO_IRQ */ diff --git a/cpu/msp430/periph/spi_usart.c b/cpu/msp430/periph/spi_usart.c index 5a57dea16c97..c3b7170fe539 100644 --- a/cpu/msp430/periph/spi_usart.c +++ b/cpu/msp430/periph/spi_usart.c @@ -39,12 +39,12 @@ void spi_init(spi_t bus) assert((unsigned)bus < SPI_NUMOF); /* put SPI device in reset state */ - SPI_BASE->CTL = USART_CTL_SWRST; - SPI_BASE->CTL |= (USART_CTL_CHAR | USART_CTL_SYNC | USART_CTL_MM); + SPI_BASE->CTL = SWRST; + SPI_BASE->CTL |= (CHAR | SYNC | MM); SPI_BASE->RCTL = 0; SPI_BASE->MCTL = 0; /* enable SPI mode */ - SPI_ME |= SPI_ME_BIT; + SPI_SFR->ME |= SPI_ME_BIT; /* trigger the pin configuration */ spi_init_pins(bus); @@ -80,16 +80,16 @@ void spi_acquire(spi_t bus, spi_cs_t cs, spi_mode_t mode, spi_clk_t clk) /* configure bus mode */ /* configure mode */ - SPI_BASE->TCTL = (USART_TCTL_SSEL_SMCLK | USART_TCTL_STC | mode); + SPI_BASE->TCTL = (UXTCTL_SSEL_SMCLK | STC | mode); /* release from software reset */ - SPI_BASE->CTL &= ~(USART_CTL_SWRST); + SPI_BASE->CTL &= ~(SWRST); } void spi_release(spi_t bus) { (void)bus; /* put SPI device back in reset state */ - SPI_BASE->CTL |= (USART_CTL_SWRST); + SPI_BASE->CTL |= SWRST; /* release the bus */ mutex_unlock(&spi_lock); @@ -112,25 +112,25 @@ void spi_transfer_bytes(spi_t bus, spi_cs_t cs, bool cont, /* if we only send out data, we do this the fast way... */ if (!in_buf) { for (size_t i = 0; i < len; i++) { - while (!(SPI_IF & SPI_IE_TX_BIT)) {} + while (!(SPI_SFR->IFG & SPI_IE_TX_BIT)) {} SPI_BASE->TXBUF = out_buf[i]; } /* finally we need to wait, until all transfers are complete */ - while (!(SPI_IF & SPI_IE_TX_BIT) || !(SPI_IF & SPI_IE_RX_BIT)) {} + while (!(SPI_SFR->IFG & SPI_IE_TX_BIT) || !(SPI_SFR->IFG & SPI_IE_RX_BIT)) {} SPI_BASE->RXBUF; } else if (!out_buf) { for (size_t i = 0; i < len; i++) { SPI_BASE->TXBUF = 0; - while (!(SPI_IF & SPI_IE_RX_BIT)) {} + while (!(SPI_SFR->IFG & SPI_IE_RX_BIT)) {} in_buf[i] = (char)SPI_BASE->RXBUF; } } else { for (size_t i = 0; i < len; i++) { - while (!(SPI_IF & SPI_IE_TX_BIT)) {} + while (!(SPI_SFR->IFG & SPI_IE_TX_BIT)) {} SPI_BASE->TXBUF = out_buf[i]; - while (!(SPI_IF & SPI_IE_RX_BIT)) {} + while (!(SPI_SFR->IFG & SPI_IE_RX_BIT)) {} in_buf[i] = (char)SPI_BASE->RXBUF; } } diff --git a/cpu/msp430/periph/spi_usci.c b/cpu/msp430/periph/spi_usci.c index c894edcf30b6..fbbff950032f 100644 --- a/cpu/msp430/periph/spi_usci.c +++ b/cpu/msp430/periph/spi_usci.c @@ -39,8 +39,8 @@ void spi_init(spi_t bus) assert((unsigned)bus < SPI_NUMOF); /* reset SPI device */ - SPI_BASE->CTL1 = USCI_SPI_CTL1_SWRST; - SPI_BASE->CTL1 |= (USCI_SPI_CTL1_SSEL_SMCLK); + SPI_BASE->CTL1 = UCSWRST; + SPI_BASE->CTL1 |= UCSSEL_SMCLK; /* trigger the pin configuration */ spi_init_pins(bus); @@ -76,17 +76,16 @@ void spi_acquire(spi_t bus, spi_cs_t cs, spi_mode_t mode, spi_clk_t clk) /* configure bus mode */ /* configure mode */ - SPI_BASE->CTL0 = (USCI_SPI_CTL0_UCSYNC | USCI_SPI_CTL0_MST| - USCI_SPI_CTL0_MODE_0 | USCI_SPI_CTL0_MSB | mode); + SPI_BASE->CTL0 = (UCSYNC | UCMST | UCMODE_0 | UCMSB | mode); /* release from software reset */ - SPI_BASE->CTL1 &= ~(USCI_SPI_CTL1_SWRST); + SPI_BASE->CTL1 &= ~(UCSWRST); } void spi_release(spi_t bus) { (void)bus; /* put SPI device back in reset state */ - SPI_BASE->CTL1 |= (USCI_SPI_CTL1_SWRST); + SPI_BASE->CTL1 |= UCSWRST; /* release the bus */ mutex_unlock(&spi_lock); @@ -113,7 +112,7 @@ void spi_transfer_bytes(spi_t bus, spi_cs_t cs, bool cont, SPI_BASE->TXBUF = out_buf[i]; } /* finally we need to wait, until all transfers are complete */ - while (SPI_BASE->STAT & USCI_SPI_STAT_UCBUSY) {} + while (SPI_BASE->STAT & UCBUSY) {} SPI_BASE->RXBUF; } else if (!out_buf) { diff --git a/cpu/msp430/periph/timer.c b/cpu/msp430/periph/timer.c index 93e0b3170cb2..6150a90d7585 100644 --- a/cpu/msp430/periph/timer.c +++ b/cpu/msp430/periph/timer.c @@ -52,18 +52,18 @@ int timer_init(tim_t dev, uint32_t freq, timer_cb_t cb, void *arg) } /* reset the timer A configuration */ - TIMER_BASE->CTL = TIMER_CTL_CLR; + TIMER_BASE->CTL = TACLR; /* save callback */ isr_cb = cb; isr_arg = arg; /* configure timer to use the SMCLK with prescaler of 8 */ - TIMER_BASE->CTL = (TIMER_CTL_TASSEL_SMCLK | TIMER_CTL_ID_DIV8); + TIMER_BASE->CTL = (TXSSEL_SMCLK | TXID_DIV_8); /* configure CC channels */ for (int i = 0; i < TIMER_CHAN; i++) { TIMER_BASE->CCTL[i] = 0; } /* start the timer in continuous mode */ - TIMER_BASE->CTL |= TIMER_CTL_MC_CONT; + TIMER_BASE->CTL |= TXMC_CONT; return 0; } @@ -73,8 +73,8 @@ int timer_set_absolute(tim_t dev, int channel, unsigned int value) return -1; } TIMER_BASE->CCR[channel] = value; - TIMER_BASE->CCTL[channel] &= ~(TIMER_CCTL_CCIFG); - TIMER_BASE->CCTL[channel] |= (TIMER_CCTL_CCIE); + TIMER_BASE->CCTL[channel] &= ~(CCIFG); + TIMER_BASE->CCTL[channel] |= CCIE; return 0; } @@ -83,7 +83,7 @@ int timer_clear(tim_t dev, int channel) if (dev != 0 || channel >= TIMER_CHAN) { return -1; } - TIMER_BASE->CCTL[channel] &= ~(TIMER_CCTL_CCIE); + TIMER_BASE->CCTL[channel] &= ~(CCIE); return 0; } @@ -96,20 +96,20 @@ unsigned int timer_read(tim_t dev) void timer_start(tim_t dev) { (void)dev; - TIMER_BASE->CTL |= TIMER_CTL_MC_CONT; + TIMER_BASE->CTL |= TXMC_CONT; } void timer_stop(tim_t dev) { (void)dev; - TIMER_BASE->CTL &= ~(TIMER_CTL_MC_MASK); + TIMER_BASE->CTL &= ~(TXMC_MASK); } ISR(TIMER_ISR_CC0, isr_timer_a_cc0) { __enter_isr(); - TIMER_BASE->CCTL[0] &= ~(TIMER_CCTL_CCIE); + TIMER_BASE->CCTL[0] &= ~(CCIE); isr_cb(isr_arg, 0); __exit_isr(); @@ -119,8 +119,8 @@ ISR(TIMER_ISR_CCX, isr_timer_a_ccx) { __enter_isr(); - int chan = (int)(TIMER_IVEC->TAIV >> 1); - TIMER_BASE->CCTL[chan] &= ~(TIMER_CCTL_CCIE); + int chan = (int)(TIMER_IVEC.TAIV >> 1); + TIMER_BASE->CCTL[chan] &= ~(CCIE); isr_cb(isr_arg, chan); __exit_isr(); diff --git a/cpu/msp430/periph/uart_usart.c b/cpu/msp430/periph/uart_usart.c index c736d60db0ec..c30618a0bea0 100644 --- a/cpu/msp430/periph/uart_usart.c +++ b/cpu/msp430/periph/uart_usart.c @@ -45,10 +45,10 @@ int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, void *arg) ctx_rx_cb = rx_cb; ctx_isr_arg = arg; /* reset interrupt flags and enable RX interrupt */ - UART_IE &= ~(UART_IE_TX_BIT); - UART_IF &= ~(UART_IE_RX_BIT); - UART_IF |= (UART_IE_TX_BIT); - UART_IE |= (UART_IE_RX_BIT); + UART_SFR->IE &= ~(UART_IE_TX_BIT); + UART_SFR->IFG &= ~(UART_IE_RX_BIT); + UART_SFR->IFG |= (UART_IE_TX_BIT); + UART_SFR->IE |= (UART_IE_RX_BIT); return UART_OK; } @@ -63,10 +63,10 @@ static int init_base(uart_t uart, uint32_t baudrate) /* power off and reset device */ uart_poweroff(uart); - dev->CTL = USART_CTL_SWRST; + dev->CTL = SWRST; /* configure to 8N1 and using the SMCLK*/ - dev->CTL |= USART_CTL_CHAR; - dev->TCTL = (USART_TCTL_TXEPT | USART_TCTL_SSEL_SMCLK); + dev->CTL |= CHAR; + dev->TCTL = (TXEPT | UXTCTL_SSEL_SMCLK); dev->RCTL = 0x00; /* baudrate configuration */ uint16_t br = (uint16_t)(msp430_submain_clock_freq() / baudrate); @@ -76,14 +76,15 @@ static int init_base(uart_t uart, uint32_t baudrate) dev->MCTL = 0; /* configure pins -> TODO: move into GPIO driver (once implemented) */ UART_PORT->SEL |= (UART_RX_PIN | UART_TX_PIN); - UART_PORT->OD |= UART_RX_PIN; - UART_PORT->OD &= ~(UART_TX_PIN); - UART_PORT->DIR |= UART_TX_PIN; - UART_PORT->DIR &= ~(UART_RX_PIN); + msp_port_t *port = &UART_PORT->base; + port->OD |= UART_RX_PIN; + port->OD &= ~(UART_TX_PIN); + port->DIR |= UART_TX_PIN; + port->DIR &= ~(UART_RX_PIN); /* enable receiver and transmitter */ uart_poweron(uart); /* and finally release the software reset bit */ - dev->CTL &= ~(USART_CTL_SWRST); + dev->CTL &= ~(SWRST); return UART_OK; } @@ -93,7 +94,7 @@ void uart_write(uart_t uart, const uint8_t *data, size_t len) msp_usart_t *dev = UART_BASE; for (size_t i = 0; i < len; i++) { - while (!(dev->TCTL & USART_TCTL_TXEPT)) {} + while (!(dev->TCTL & TXEPT)) {} dev->TXBUF = data[i]; } } @@ -101,13 +102,13 @@ void uart_write(uart_t uart, const uint8_t *data, size_t len) void uart_poweron(uart_t uart) { (void)uart; - UART_ME |= UART_ME_BITS; + UART_SFR->ME |= UART_ME_BITS; } void uart_poweroff(uart_t uart) { (void)uart; - UART_ME &= ~(UART_ME_BITS); + UART_SFR->ME &= ~(UART_ME_BITS); } ISR(UART_RX_ISR, isr_uart_0_rx) diff --git a/cpu/msp430/periph/uart_usci.c b/cpu/msp430/periph/uart_usci.c index 4ecb76c4cf3c..9d86d6476736 100644 --- a/cpu/msp430/periph/uart_usci.c +++ b/cpu/msp430/periph/uart_usci.c @@ -58,28 +58,28 @@ static int init_base(uart_t uart, uint32_t baudrate) } /* get the default UART for now -> TODO: enable for multiple devices */ - msp_usci_t *dev = UART_BASE; + msp_usci_a_t *dev = UART_BASE; /* put device in reset mode while configuration is going on */ - dev->ACTL1 = USCI_ACTL1_SWRST; + dev->CTL1 = UCSWRST; /* configure to UART, using SMCLK in 8N1 mode */ - dev->ACTL1 |= USCI_ACTL1_SSEL_SMCLK; - dev->ACTL0 = 0; - dev->ASTAT = 0; + dev->CTL1 |= UCSSEL_SMCLK; + dev->CTL0 = 0; + dev->STAT = 0; /* configure baudrate */ uint32_t base = ((msp430_submain_clock_freq() << 7) / baudrate); uint16_t br = (uint16_t)(base >> 7); uint8_t brs = (((base & 0x3f) * 8) >> 7); - dev->ABR0 = (uint8_t)br; - dev->ABR1 = (uint8_t)(br >> 8); - dev->AMCTL = (brs << USCI_AMCTL_BRS_SHIFT); + dev->BR0 = (uint8_t)br; + dev->BR1 = (uint8_t)(br >> 8); + dev->MCTL = (brs << UCBRS_POS); /* pin configuration -> TODO: move to GPIO driver once implemented */ UART_RX_PORT->SEL |= UART_RX_PIN; UART_TX_PORT->SEL |= UART_TX_PIN; - UART_RX_PORT->DIR &= ~(UART_RX_PIN); - UART_TX_PORT->DIR |= UART_TX_PIN; + UART_RX_PORT->base.DIR &= ~(UART_RX_PIN); + UART_TX_PORT->base.DIR |= UART_TX_PIN; /* releasing the software reset bit starts the UART */ - dev->ACTL1 &= ~(USCI_ACTL1_SWRST); + dev->CTL1 &= ~(UCSWRST); return 0; } @@ -89,7 +89,7 @@ void uart_write(uart_t uart, const uint8_t *data, size_t len) for (size_t i = 0; i < len; i++) { while (!(UART_IF & UART_IE_TX_BIT)) {} - UART_BASE->ATXBUF = data[i]; + UART_BASE->TXBUF = data[i]; } } @@ -109,10 +109,10 @@ ISR(UART_RX_ISR, isr_uart_0_rx) { __enter_isr(); - uint8_t stat = UART_BASE->ASTAT; - uint8_t data = (uint8_t)UART_BASE->ARXBUF; + uint8_t stat = UART_BASE->STAT; + uint8_t data = (uint8_t)UART_BASE->RXBUF; - if (stat & (USCI_ASTAT_FE | USCI_ASTAT_OE | USCI_ASTAT_PE | USCI_ASTAT_BRK)) { + if (stat & (UCFE | UCOE | UCPE | UCBRK)) { /* some error which we do not handle, just do a pseudo read to reset the * status register */ (void)data; diff --git a/dist/tools/doccheck/exclude_simple b/dist/tools/doccheck/exclude_simple index f23f978a1127..9f3f9d56549a 100644 --- a/dist/tools/doccheck/exclude_simple +++ b/dist/tools/doccheck/exclude_simple @@ -1401,12 +1401,10 @@ warning: Member CLK1 (macro definition) of file periph_conf.h is not documented. warning: Member CLK40 (macro definition) of file periph_conf.h is not documented. warning: Member CLK50 (macro definition) of file periph_conf.h is not documented. warning: Member CLK80 (macro definition) of file periph_conf.h is not documented. -warning: Member CLK_BASE (macro definition) of file msp430_regs.h is not documented. warning: Member clk_div_config[] (variable) of file periph_conf.h is not documented. warning: Member CLK_DIV_NUMOF (macro definition) of file periph_conf.h is not documented. warning: Member CLKLOADCTL_LOADDONE (macro definition) of file cc26x0_cc13x0_prcm.h is not documented. warning: Member CLKLOADCTL_LOADDONE (macro definition) of file cc26x2_cc13x2_prcm.h is not documented. -warning: Member CLK (macro definition) of file msp430_regs.h is not documented. warning: Member clk_mux_config[] (variable) of file periph_conf.h is not documented. warning: Member CLK_MUX_NUMOF (macro definition) of file periph_conf.h is not documented. warning: Member CLOCK_8MHZ (macro definition) of file periph_conf.h is not documented. @@ -2565,7 +2563,6 @@ warning: Member GPIO_PIN(x, y) (macro definition) of file periph_cpu_common.h is warning: Member GPIO_PIN(x, y) (macro definition) of file periph_cpu.h is not documented. warning: Member gpio_t (typedef) of file periph_cpu_common.h is not documented. warning: Member gpio_t (typedef) of file periph_cpu.h is not documented. -warning: Member gpio_t (typedef) of group cpu_msp430fxyz is not documented. warning: Member GPRS_PIN (macro definition) of file waspmote_pinmap.h is not documented. warning: Member GPRS_PW (macro definition) of file waspmote_pinmap.h is not documented. warning: Member GPS_ENABLE_MASK (macro definition) of file board.h is not documented. @@ -5627,13 +5624,10 @@ warning: Member PERIPH_INIT_LED0 (macro definition) of group boards_common_nucle warning: Member PERIPH_SPI_NEEDS_INIT_CS (macro definition) of file periph_cpu.h is not documented. warning: Member PERIPH_SPI_NEEDS_TRANSFER_BYTE (macro definition) of file periph_cpu_common.h is not documented. warning: Member PERIPH_SPI_NEEDS_TRANSFER_BYTE (macro definition) of file periph_cpu.h is not documented. -warning: Member PERIPH_SPI_NEEDS_TRANSFER_BYTE (macro definition) of group cpu_msp430fxyz is not documented. warning: Member PERIPH_SPI_NEEDS_TRANSFER_REG (macro definition) of file periph_cpu_common.h is not documented. warning: Member PERIPH_SPI_NEEDS_TRANSFER_REG (macro definition) of file periph_cpu.h is not documented. -warning: Member PERIPH_SPI_NEEDS_TRANSFER_REG (macro definition) of group cpu_msp430fxyz is not documented. warning: Member PERIPH_SPI_NEEDS_TRANSFER_REGS (macro definition) of file periph_cpu_common.h is not documented. warning: Member PERIPH_SPI_NEEDS_TRANSFER_REGS (macro definition) of file periph_cpu.h is not documented. -warning: Member PERIPH_SPI_NEEDS_TRANSFER_REGS (macro definition) of group cpu_msp430fxyz is not documented. warning: Member PHCON1_PDPXMD (macro definition) of file enc28j60_regs.h is not documented. warning: Member PHCON1_PLOOPBK (macro definition) of file enc28j60_regs.h is not documented. warning: Member PHCON1_PPWRSV (macro definition) of file enc28j60_regs.h is not documented. @@ -5711,18 +5705,6 @@ warning: Member PN532_FW_FEATURES(fwver) (macro definition) of group drivers_pn5 warning: Member PN532_FW_REVISION(fwver) (macro definition) of group drivers_pn532 is not documented. warning: Member PN532_FW_VERSION(fwver) (macro definition) of group drivers_pn532 is not documented. warning: Member PN532_IC_VERSION(fwver) (macro definition) of group drivers_pn532 is not documented. -warning: Member PORT_1_BASE (macro definition) of file msp430_regs.h is not documented. -warning: Member PORT_1 (macro definition) of file msp430_regs.h is not documented. -warning: Member PORT_2_BASE (macro definition) of file msp430_regs.h is not documented. -warning: Member PORT_2 (macro definition) of file msp430_regs.h is not documented. -warning: Member PORT_3_BASE (macro definition) of file msp430_regs.h is not documented. -warning: Member PORT_3 (macro definition) of file msp430_regs.h is not documented. -warning: Member PORT_4_BASE (macro definition) of file msp430_regs.h is not documented. -warning: Member PORT_4 (macro definition) of file msp430_regs.h is not documented. -warning: Member PORT_5_BASE (macro definition) of file msp430_regs.h is not documented. -warning: Member PORT_5 (macro definition) of file msp430_regs.h is not documented. -warning: Member PORT_6_BASE (macro definition) of file msp430_regs.h is not documented. -warning: Member PORT_6 (macro definition) of file msp430_regs.h is not documented. warning: Member PORT_delayRx (macro definition) of file board_info.h is not documented. warning: Member PORT_delayTx (macro definition) of file board_info.h is not documented. warning: Member PORT_delayTx (macro definition) of file openwsn_defs.h is not documented. @@ -6397,16 +6379,6 @@ warning: Member SET_MUX_SOCKET1 (macro definition) of file board.h is not docume warning: Member SET_MUX_USB_MODULE (macro definition) of file board.h is not documented. warning: Member setsockopt(int socket, int level, int option_name, const void *option_value, socklen_t option_len) (function) of group posix_sockets is not documented. warning: Member setup_fpu(void) (function) of group cpu_lm4f120 is not documented. -warning: Member SFR_IE1_URXIE0 (macro definition) of file msp430_regs.h is not documented. -warning: Member SFR_IE1_UTXIE0 (macro definition) of file msp430_regs.h is not documented. -warning: Member SFR_IE2_UCA0TXIE (macro definition) of file msp430_regs.h is not documented. -warning: Member SFR_IE2_URXIE2 (macro definition) of file msp430_regs.h is not documented. -warning: Member SFR_IE2_UTXIE2 (macro definition) of file msp430_regs.h is not documented. -warning: Member SFR_IFG1_URXIFG0 (macro definition) of file msp430_regs.h is not documented. -warning: Member SFR_IFG1_UTXIFG0 (macro definition) of file msp430_regs.h is not documented. -warning: Member SFR_IFG2_UCA0TXIFG (macro definition) of file msp430_regs.h is not documented. -warning: Member SFR_IFG2_URXIFG1 (macro definition) of file msp430_regs.h is not documented. -warning: Member SFR_IFG2_UTXIFG1 (macro definition) of file msp430_regs.h is not documented. warning: Member SGP30_PARAM_I2C_DEV (macro definition) of file sgp30_params.h is not documented. warning: Member SGP30_PARAMS (macro definition) of file sgp30_params.h is not documented. warning: Member SGP30_SAUL_INFO (macro definition) of file sgp30_params.h is not documented. @@ -6732,6 +6704,7 @@ warning: Member SOFT_UART_PARAM_TIMER_TX (macro definition) of file soft_uart_pa warning: Member SOFT_UART_PARAM_TX (macro definition) of file soft_uart_params.h is not documented. warning: Member SPEAKER_PIN (macro definition) of file board.h is not documented. warning: Member SPI_BASE (macro definition) of file periph_conf.h is not documented. +warning: Member SPI_SFR (macro definition) of file periph_conf.h is not documented. warning: Member spi_clk_config[] (variable) of file periph_conf_common.h is not documented. warning: Member spi_clk_config[] (variable) of file periph_conf.h is not documented. warning: Member spi_clk_t (enumeration) of file periph_cpu.h is not documented. @@ -8072,29 +8045,7 @@ warning: Member TIMER_2_ISR (macro definition) of file periph_conf.h is not docu warning: Member TIMER_2 (macro definition) of file default_timer_config.h is not documented. warning: Member TIMER_2_MASK (macro definition) of file default_timer_config.h is not documented. warning: Member TIMER_3_ISR (macro definition) of file cfg_timer_default.h is not documented. -warning: Member TIMER_A_BASE (macro definition) of file msp430_regs.h is not documented. -warning: Member TIMER_A (macro definition) of file msp430_regs.h is not documented. warning: Member TIMER_BASE (macro definition) of file periph_conf.h is not documented. -warning: Member TIMER_B_BASE (macro definition) of file msp430_regs.h is not documented. -warning: Member TIMER_B (macro definition) of file msp430_regs.h is not documented. -warning: Member TIMER_CCTL_CAP (macro definition) of file msp430_regs.h is not documented. -warning: Member TIMER_CCTL_CCIE (macro definition) of file msp430_regs.h is not documented. -warning: Member TIMER_CCTL_CCI (macro definition) of file msp430_regs.h is not documented. -warning: Member TIMER_CCTL_CCIS_MASK (macro definition) of file msp430_regs.h is not documented. -warning: Member TIMER_CCTL_CLLD_MASK (macro definition) of file msp430_regs.h is not documented. -warning: Member TIMER_CCTL_CM_MASK (macro definition) of file msp430_regs.h is not documented. -warning: Member TIMER_CCTL_COV (macro definition) of file msp430_regs.h is not documented. -warning: Member TIMER_CCTL_OUT (macro definition) of file msp430_regs.h is not documented. -warning: Member TIMER_CCTL_OUTMOD_MASK (macro definition) of file msp430_regs.h is not documented. -warning: Member TIMER_CCTL_OUTMOD_OUTVAL (macro definition) of file msp430_regs.h is not documented. -warning: Member TIMER_CCTL_OUTMOD_RESET (macro definition) of file msp430_regs.h is not documented. -warning: Member TIMER_CCTL_OUTMOD_RESET_SET (macro definition) of file msp430_regs.h is not documented. -warning: Member TIMER_CCTL_OUTMOD_SET (macro definition) of file msp430_regs.h is not documented. -warning: Member TIMER_CCTL_OUTMOD_SET_RESET (macro definition) of file msp430_regs.h is not documented. -warning: Member TIMER_CCTL_OUTMOD_TOGGLE (macro definition) of file msp430_regs.h is not documented. -warning: Member TIMER_CCTL_OUTMOD_TOG_RESET (macro definition) of file msp430_regs.h is not documented. -warning: Member TIMER_CCTL_OUTMOD_TOG_SET (macro definition) of file msp430_regs.h is not documented. -warning: Member TIMER_CCTL_SCS (macro definition) of file msp430_regs.h is not documented. warning: Member TIMER_CHAN (macro definition) of file periph_conf.h is not documented. warning: Member TIMER_CHANNEL_NUMOF (macro definition) of file default_timer_config.h is not documented. warning: Member TIMER_CHANNEL_NUMOF (macro definition) of file periph_cpu.h is not documented. @@ -8105,30 +8056,11 @@ warning: Member timer_config[] (variable) of file cfg_timer_tim2.h is not docume warning: Member timer_config[] (variable) of file cfg_timer_tim5.h is not documented. warning: Member timer_config[] (variable) of file periph_conf_common.h is not documented. warning: Member timer_config[] (variable) of file periph_conf.h is not documented. -warning: Member TIMER_CTL_CLR (macro definition) of file msp430_regs.h is not documented. -warning: Member TIMER_CTL_ID_DIV1 (macro definition) of file msp430_regs.h is not documented. -warning: Member TIMER_CTL_ID_DIV2 (macro definition) of file msp430_regs.h is not documented. -warning: Member TIMER_CTL_ID_DIV4 (macro definition) of file msp430_regs.h is not documented. -warning: Member TIMER_CTL_ID_DIV8 (macro definition) of file msp430_regs.h is not documented. -warning: Member TIMER_CTL_ID_MASK (macro definition) of file msp430_regs.h is not documented. -warning: Member TIMER_CTL_IE (macro definition) of file msp430_regs.h is not documented. -warning: Member TIMER_CTL_MC_CONT (macro definition) of file msp430_regs.h is not documented. -warning: Member TIMER_CTL_MC_MASK (macro definition) of file msp430_regs.h is not documented. -warning: Member TIMER_CTL_MC_STOP (macro definition) of file msp430_regs.h is not documented. -warning: Member TIMER_CTL_MC_UPDOWN (macro definition) of file msp430_regs.h is not documented. -warning: Member TIMER_CTL_MC_UP (macro definition) of file msp430_regs.h is not documented. -warning: Member TIMER_CTL_TASSEL_ACLK (macro definition) of file msp430_regs.h is not documented. -warning: Member TIMER_CTL_TASSEL_INV_TCLK (macro definition) of file msp430_regs.h is not documented. -warning: Member TIMER_CTL_TASSEL_MASK (macro definition) of file msp430_regs.h is not documented. -warning: Member TIMER_CTL_TASSEL_SMCLK (macro definition) of file msp430_regs.h is not documented. -warning: Member TIMER_CTL_TASSEL_TCLK (macro definition) of file msp430_regs.h is not documented. warning: Member timer_div_t (enumeration) of file periph_cpu_common.h is not documented. warning: Member TIMER_IRQ_PRIO (macro definition) of file cfg_timer_default.h is not documented. warning: Member TIMER_IRQ_PRIO (macro definition) of file periph_conf.h is not documented. warning: Member TIMER_ISR_CC0 (macro definition) of file periph_conf.h is not documented. warning: Member TIMER_ISR_CCX (macro definition) of file periph_conf.h is not documented. -warning: Member TIMER_IVEC_BASE (macro definition) of file msp430_regs.h is not documented. -warning: Member TIMER_IVEC (macro definition) of file msp430_regs.h is not documented. warning: Member TIMER_MAX_VALUE (macro definition) of file periph_cpu.h is not documented. warning: Member TIMER_NUMOF (macro definition) of file cfg_timer_012.h is not documented. warning: Member TIMER_NUMOF (macro definition) of file cfg_timer_01.h is not documented. @@ -8281,6 +8213,7 @@ warning: Member UART_4_ISR (macro definition) of file periph_conf.h is not docum warning: Member UART_6_DMA_ISR (macro definition) of file periph_conf.h is not documented. warning: Member UART_6_ISR (macro definition) of file periph_conf.h is not documented. warning: Member UART_BASE (macro definition) of file periph_conf.h is not documented. +warning: Member UART_SFR (macro definition) of file periph_conf.h is not documented. warning: Member UARTCLKGDS_CLK_EN_UART0 (macro definition) of file cc26x0_cc13x0_prcm.h is not documented. warning: Member UARTCLKGDS_CLK_EN_UART0 (macro definition) of file cc26x2_cc13x2_prcm.h is not documented. warning: Member UARTCLKGDS_CLK_EN_UART1 (macro definition) of file cc26x2_cc13x2_prcm.h is not documented. @@ -8382,33 +8315,6 @@ warning: Member UNLOCK_TCPIP_CORE() (macro definition) of file sys_arch.h is not warning: Member UNLOCK_TCPIP_CORE() (macro definition) of group pkg_lwip_sys is not documented. warning: Member UPDATE_CCA (macro definition) of file board.h is not documented. warning: Member UPDATE_CCA (macro definition) of group boards_common_remote is not documented. -warning: Member USART_0_BASE (macro definition) of file msp430_regs.h is not documented. -warning: Member USART_0 (macro definition) of file msp430_regs.h is not documented. -warning: Member USART_1_BASE (macro definition) of file msp430_regs.h is not documented. -warning: Member USART_1 (macro definition) of file msp430_regs.h is not documented. -warning: Member USART_CTL_CHAR (macro definition) of file msp430_regs.h is not documented. -warning: Member USART_CTL_LISTEN (macro definition) of file msp430_regs.h is not documented. -warning: Member USART_CTL_MM (macro definition) of file msp430_regs.h is not documented. -warning: Member USART_CTL_PENA (macro definition) of file msp430_regs.h is not documented. -warning: Member USART_CTL_PEV (macro definition) of file msp430_regs.h is not documented. -warning: Member USART_CTL_SPB (macro definition) of file msp430_regs.h is not documented. -warning: Member USART_CTL_SYNC (macro definition) of file msp430_regs.h is not documented. -warning: Member USART_RCTL_BRK (macro definition) of file msp430_regs.h is not documented. -warning: Member USART_RCTL_FE (macro definition) of file msp430_regs.h is not documented. -warning: Member USART_RCTL_OE (macro definition) of file msp430_regs.h is not documented. -warning: Member USART_RCTL_PE (macro definition) of file msp430_regs.h is not documented. -warning: Member USART_RCTL_RXWAKE (macro definition) of file msp430_regs.h is not documented. -warning: Member USART_RCTL_URXEIE (macro definition) of file msp430_regs.h is not documented. -warning: Member USART_RCTL_URXWIE (macro definition) of file msp430_regs.h is not documented. -warning: Member USART_TCTL_CKPH (macro definition) of file msp430_regs.h is not documented. -warning: Member USART_TCTL_CKPL (macro definition) of file msp430_regs.h is not documented. -warning: Member USART_TCTL_SSEL_ACLK (macro definition) of file msp430_regs.h is not documented. -warning: Member USART_TCTL_SSEL_MASK (macro definition) of file msp430_regs.h is not documented. -warning: Member USART_TCTL_SSEL_SMCLK (macro definition) of file msp430_regs.h is not documented. -warning: Member USART_TCTL_SSEL_UCLKI (macro definition) of file msp430_regs.h is not documented. -warning: Member USART_TCTL_STC (macro definition) of file msp430_regs.h is not documented. -warning: Member USART_TCTL_TXWAKE (macro definition) of file msp430_regs.h is not documented. -warning: Member USART_TCTL_URXSE (macro definition) of file msp430_regs.h is not documented. warning: Member USB_APP_MODE_SLOT_NAME (macro definition) of file usb_dfu.h is not documented. warning: Member usbdev_mock_ep_state_t (enumeration) of group drivers_usbdev_mock is not documented. warning: Member USB_DFU_DETACH_TIMEOUT_MS (macro definition) of group usb_dfu is not documented. @@ -8431,65 +8337,6 @@ warning: Member USB_HID_SUBCLASS_BOOT (macro definition) of group usb_hid is not warning: Member USB_HID_SUBCLASS_NONE (macro definition) of group usb_hid is not documented. warning: Member USB_XBEE_RX (macro definition) of file waspmote_pinmap.h is not documented. warning: Member USB_XBEE_TX (macro definition) of file waspmote_pinmap.h is not documented. -warning: Member USCI_0_A_BASE (macro definition) of file msp430_regs.h is not documented. -warning: Member USCI_0_A_SPI (macro definition) of file msp430_regs.h is not documented. -warning: Member USCI_0_BASE (macro definition) of file msp430_regs.h is not documented. -warning: Member USCI_0_B_BASE (macro definition) of file msp430_regs.h is not documented. -warning: Member USCI_0_B_SPI (macro definition) of file msp430_regs.h is not documented. -warning: Member USCI_0 (macro definition) of file msp430_regs.h is not documented. -warning: Member USCI_1_A_BASE (macro definition) of file msp430_regs.h is not documented. -warning: Member USCI_1_A (macro definition) of file msp430_regs.h is not documented. -warning: Member USCI_1_BASE (macro definition) of file msp430_regs.h is not documented. -warning: Member USCI_1_B_BASE (macro definition) of file msp430_regs.h is not documented. -warning: Member USCI_1_B (macro definition) of file msp430_regs.h is not documented. -warning: Member USCI_1 (macro definition) of file msp430_regs.h is not documented. -warning: Member USCI_ACTL0_7BIT (macro definition) of file msp430_regs.h is not documented. -warning: Member USCI_ACTL0_MODE_ABMM (macro definition) of file msp430_regs.h is not documented. -warning: Member USCI_ACTL0_MODE_ILMM (macro definition) of file msp430_regs.h is not documented. -warning: Member USCI_ACTL0_MODE_MASK (macro definition) of file msp430_regs.h is not documented. -warning: Member USCI_ACTL0_MODE_UART_ABR (macro definition) of file msp430_regs.h is not documented. -warning: Member USCI_ACTL0_MODE_UART (macro definition) of file msp430_regs.h is not documented. -warning: Member USCI_ACTL0_MSB (macro definition) of file msp430_regs.h is not documented. -warning: Member USCI_ACTL0_PAR (macro definition) of file msp430_regs.h is not documented. -warning: Member USCI_ACTL0_PEN (macro definition) of file msp430_regs.h is not documented. -warning: Member USCI_ACTL0_SPB (macro definition) of file msp430_regs.h is not documented. -warning: Member USCI_ACTL1_BRKIE (macro definition) of file msp430_regs.h is not documented. -warning: Member USCI_ACTL1_DORM (macro definition) of file msp430_regs.h is not documented. -warning: Member USCI_ACTL1_RXEIE (macro definition) of file msp430_regs.h is not documented. -warning: Member USCI_ACTL1_SSEL_ACLK (macro definition) of file msp430_regs.h is not documented. -warning: Member USCI_ACTL1_SSEL_MASK (macro definition) of file msp430_regs.h is not documented. -warning: Member USCI_ACTL1_SSEL_SMCLK (macro definition) of file msp430_regs.h is not documented. -warning: Member USCI_ACTL1_SSEL_UCLK (macro definition) of file msp430_regs.h is not documented. -warning: Member USCI_ACTL1_TXADDR (macro definition) of file msp430_regs.h is not documented. -warning: Member USCI_ACTL1_TXBRK (macro definition) of file msp430_regs.h is not documented. -warning: Member USCI_AMCTL_BRF_MASK (macro definition) of file msp430_regs.h is not documented. -warning: Member USCI_AMCTL_BRF_SHIFT (macro definition) of file msp430_regs.h is not documented. -warning: Member USCI_AMCTL_BRS_MASK (macro definition) of file msp430_regs.h is not documented. -warning: Member USCI_AMCTL_BRS_SHIFT (macro definition) of file msp430_regs.h is not documented. -warning: Member USCI_ASTAT_ADDR (macro definition) of file msp430_regs.h is not documented. -warning: Member USCI_ASTAT_BRK (macro definition) of file msp430_regs.h is not documented. -warning: Member USCI_ASTAT_FE (macro definition) of file msp430_regs.h is not documented. -warning: Member USCI_ASTAT_IDLE (macro definition) of file msp430_regs.h is not documented. -warning: Member USCI_ASTAT_LISTEN (macro definition) of file msp430_regs.h is not documented. -warning: Member USCI_ASTAT_OE (macro definition) of file msp430_regs.h is not documented. -warning: Member USCI_ASTAT_PE (macro definition) of file msp430_regs.h is not documented. -warning: Member USCI_ASTAT_RXERR (macro definition) of file msp430_regs.h is not documented. -warning: Member USCI_SPI_CTL0_7BIT (macro definition) of file msp430_regs.h is not documented. -warning: Member USCI_SPI_CTL0_CKPH (macro definition) of file msp430_regs.h is not documented. -warning: Member USCI_SPI_CTL0_CKPL (macro definition) of file msp430_regs.h is not documented. -warning: Member USCI_SPI_CTL0_MODE_0 (macro definition) of file msp430_regs.h is not documented. -warning: Member USCI_SPI_CTL0_MODE_1 (macro definition) of file msp430_regs.h is not documented. -warning: Member USCI_SPI_CTL0_MODE_2 (macro definition) of file msp430_regs.h is not documented. -warning: Member USCI_SPI_CTL0_MODE_3 (macro definition) of file msp430_regs.h is not documented. -warning: Member USCI_SPI_CTL0_MSB (macro definition) of file msp430_regs.h is not documented. -warning: Member USCI_SPI_CTL0_MST (macro definition) of file msp430_regs.h is not documented. -warning: Member USCI_SPI_CTL1_SSEL_ACLK (macro definition) of file msp430_regs.h is not documented. -warning: Member USCI_SPI_CTL1_SSEL_MASK (macro definition) of file msp430_regs.h is not documented. -warning: Member USCI_SPI_CTL1_SSEL_NA (macro definition) of file msp430_regs.h is not documented. -warning: Member USCI_SPI_CTL1_SSEL_SMCLK (macro definition) of file msp430_regs.h is not documented. -warning: Member USCI_SPI_STAT_UCFE (macro definition) of file msp430_regs.h is not documented. -warning: Member USCI_SPI_STAT_UCLISTEN (macro definition) of file msp430_regs.h is not documented. -warning: Member USCI_SPI_STAT_UCOE (macro definition) of file msp430_regs.h is not documented. warning: Member UUID_VERSION_MASK (macro definition) of group sys_uuid is not documented. warning: Member VCC33 (macro definition) of file board.h is not documented. warning: Member VCNL40X0_AMBIENT_MASK_PARA_AUTO_OFFSET (macro definition) of file vcnl40x0_internals.h is not documented. @@ -8593,8 +8440,6 @@ warning: Member W5100_PARAM_EVT (macro definition) of group boards_common_arduin warning: Member W5100_PARAM_EVT (macro definition) of group boards_common_arduino_due is not documented. warning: Member W5100_PARAMS (macro definition) of file w5100_params.h is not documented. warning: Member Watchdog_IRQn (macro definition) of file cpu_conf.h is not documented. -warning: Member WD_BASE (macro definition) of file msp430_regs.h is not documented. -warning: Member WD (macro definition) of file msp430_regs.h is not documented. warning: Member WDT_CLOCK_HZ (macro definition) of file periph_cpu.h is not documented. warning: Member WDT_HAS_INIT (macro definition) of file periph_cpu.h is not documented. warning: Member WDT_HAS_STOP (macro definition) of file periph_cpu.h is not documented. diff --git a/dist/tools/doccheck/generic_exclude_patterns b/dist/tools/doccheck/generic_exclude_patterns index 4f86b5c7e9d4..45f56c164fd2 100644 --- a/dist/tools/doccheck/generic_exclude_patterns +++ b/dist/tools/doccheck/generic_exclude_patterns @@ -43,9 +43,6 @@ warning: Member LED[0-9]_PIN_NUM \(macro definition\) of warning: Member LED[0-9]_PORT \(macro definition\) of warning: Member LED[0-9]_PORT_NUM \(macro definition\) of warning: Member LED[0-9]_TOGGLE \(macro definition\) of -warning: Member MSP430_HAS_DCOR \(macro definition\) of -warning: Member MSP430_HAS_EXTERNAL_CRYSTAL \(macro definition\) of -warning: Member MSP430_INITIAL_CPU_SPEED \(macro definition\) of warning: Member PIR_PARAM_ACTIVE_HIGH \(macro definition\) of warning: Member PIR_PARAM_GPIO \(macro definition\) of warning: Member PIR_SAUL_INFO \(macro definition\) of diff --git a/makefiles/arch/msp430.inc.mk b/makefiles/arch/msp430.inc.mk index 8f9fbd65693e..c28a1d50e15f 100644 --- a/makefiles/arch/msp430.inc.mk +++ b/makefiles/arch/msp430.inc.mk @@ -26,6 +26,7 @@ ifeq (1,$(NEEDS_NEW_LINKER_SCRIPT)) else LINKFLAGS += -T $(MSP430_SUPPORT_FILES)/include/$(CPU_MODEL).ld LINKFLAGS += -T $(RIOTCPU)/msp430/ldscripts/msp430_common.ld + LINKFLAGS += -T $(RIOTCPU)/msp430/ldscripts/$(CPU_FAM).ld LINKFLAGS += $(RIOTCPU)/msp430/ldscripts/xfa.ld endif