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cmake:core: fix only run adms if depencies change
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qucs-core/src/components/verilog/CMakeLists.txt

Lines changed: 58 additions & 70 deletions
Original file line numberDiff line numberDiff line change
@@ -5,92 +5,80 @@ include_directories(
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${qucs-core_SOURCE_DIR}/src/components # component.h
66
${qucs-core_SOURCE_DIR}/src/components/devices) # devices.h
77

8-
# TODO, test if VA files change, should recompile
9-
108
set(VA_FILES
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andor4x2
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andor4x3
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andor4x4
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binarytogrey4bit
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comp_1bit
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comp_2bit
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comp_4bit
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dff_SR
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DLS_1ton
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DLS_nto1
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dmux2to4
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dmux3to8
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dmux4to16
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EKV26MOS
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fa1b
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fa2b
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gatedDlatch
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greytobinary4bit
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ha1b
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hpribin4bit
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jkff_SR
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log_amp
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logic_0
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logic_1
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MESFET
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mod_amp
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mux2to1
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mux4to1
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mux8to1
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nigbt
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pad2bit
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pad3bit
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pad4bit
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photodiode
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phototransistor
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potentiometer
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tff_SR
48-
vcresistor)
9+
andor4x2.va
10+
andor4x3.va
11+
andor4x4.va
12+
binarytogrey4bit.va
13+
comp_1bit.va
14+
comp_2bit.va
15+
comp_4bit.va
16+
dff_SR.va
17+
DLS_1ton.va
18+
DLS_nto1.va
19+
dmux2to4.va
20+
dmux3to8.va
21+
dmux4to16.va
22+
EKV26MOS.va
23+
fa1b.va
24+
fa2b.va
25+
gatedDlatch.va
26+
greytobinary4bit.va
27+
ha1b.va
28+
hpribin4bit.va
29+
jkff_SR.va
30+
log_amp.va
31+
logic_0.va
32+
logic_1.va
33+
MESFET.va
34+
mod_amp.va
35+
mux2to1.va
36+
mux4to1.va
37+
mux8to1.va
38+
nigbt.va
39+
pad2bit.va
40+
pad3bit.va
41+
pad4bit.va
42+
photodiode.va
43+
phototransistor.va
44+
potentiometer.va
45+
tff_SR.va
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vcresistor.va)
4947

5048
# XML sripts need to build, the order matters
51-
set(XML_BUILD analogfunction.xml qucsVersion.xml qucsMODULEcore.xml
52-
qucsMODULEdefs.xml)
49+
set(XML_BUILD
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analogfunction.xml
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qucsVersion.xml
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qucsMODULEcore.xml
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qucsMODULEdefs.xml)
5354

5455
# Concatenate scripts into command: -e script1 [-e script2]
5556
set(XML_CMD)
5657
foreach(script ${XML_BUILD})
5758
set(XML_CMD ${XML_CMD} -e ${CMAKE_CURRENT_SOURCE_DIR}/${script})
5859
endforeach()
5960

60-
# clear lists of generated files
61-
set(generated_SRC)
62-
63-
# Process each Verilog-A file. * generated files get added to lists (analogfunc,
64-
# core)
65-
foreach(filename ${VA_FILES})
66-
# Default
67-
set(fileout ${filename}.va)
68-
69-
# Verilog-A file basename, strip suffix
70-
get_filename_component(base ${fileout} NAME_WE)
71-
set(base_abs ${CMAKE_CURRENT_BINARY_DIR}/${base})
72-
73-
# set outputs for each Verilog-A input
61+
# Process each Verilog-A file.
62+
set(gen_SRC)
63+
foreach(file ${VA_FILES})
64+
get_filename_component(_name ${file} NAME_WE)
7465
set(output
75-
${base_abs}.analogfunction.cpp ${base_abs}.analogfunction.h
76-
${base_abs}.cpp ${base_abs}.core.cpp ${base_abs}.core.h
77-
${base_abs}.defs.h)
78-
66+
${_name}.${_name}.analogfunction.h
67+
${_name}.${_name}.analogfunction.cpp
68+
${_name}.${_name}.core.cpp
69+
${_name}.core.h
70+
${_name}.cpp
71+
${_name}.defs.h)
7972
# custom command/rule to generate outputs with admsXml
8073
add_custom_command(
8174
OUTPUT ${output}
82-
COMMAND ${ADMSXML} ${CMAKE_CURRENT_SOURCE_DIR}/${filename}.va ${XML_CMD} -o
83-
${filename}
84-
DEPENDS ${filename}.va ${XML_BUILD})
85-
set_source_files_properties(${output} PROPERTIES GENERATED TRUE)
86-
87-
# append outputs list of generated sources
88-
set(generated_SRC ${generated_SRC} ${base_abs}.cpp)
75+
COMMAND ${ADMSXML} ${CMAKE_CURRENT_SOURCE_DIR}/${file} ${XML_CMD} -o
76+
${_name}
77+
DEPENDS ${file} ${XML_BUILD})
78+
list(APPEND gen_SRC ${_name}.cpp)
8979
endforeach()
9080

91-
# MESSAGE(STATUS " ==> generated\n " ${generated_SRC})
92-
93-
add_library(coreVerilog OBJECT ${generated_SRC})
81+
add_library(coreVerilog OBJECT ${gen_SRC})
9482

9583
# Distribute XML scripts
9684
set(XML_DIST ${XML_BUILD} qucsMODULEgui.xml qucsMODULEguiJSONsymbol.xml)

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