@@ -5,92 +5,80 @@ include_directories(
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${qucs-core_SOURCE_DIR}/src/components # component.h
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${qucs-core_SOURCE_DIR}/src/components/devices) # devices.h
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- # TODO, test if VA files change, should recompile
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-
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set (VA_FILES
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- andor4x2
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- andor4x3
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- andor4x4
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- binarytogrey4bit
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- comp_1bit
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- comp_2bit
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- comp_4bit
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- dff_SR
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- DLS_1ton
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- DLS_nto1
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- dmux2to4
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- dmux3to8
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- dmux4to16
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- EKV26MOS
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- fa1b
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- fa2b
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- gatedDlatch
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- greytobinary4bit
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- ha1b
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- hpribin4bit
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- jkff_SR
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- log_amp
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- logic_0
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- logic_1
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- MESFET
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- mod_amp
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- mux2to1
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- mux4to1
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- mux8to1
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- nigbt
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- pad2bit
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- pad3bit
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- pad4bit
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- photodiode
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- phototransistor
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- potentiometer
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- tff_SR
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- vcresistor)
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+ andor4x2.va
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+ andor4x3.va
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+ andor4x4.va
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+ binarytogrey4bit.va
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+ comp_1bit.va
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+ comp_2bit.va
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+ comp_4bit.va
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+ dff_SR.va
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+ DLS_1ton.va
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+ DLS_nto1.va
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+ dmux2to4.va
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+ dmux3to8.va
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+ dmux4to16.va
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+ EKV26MOS.va
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+ fa1b.va
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+ fa2b.va
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+ gatedDlatch.va
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+ greytobinary4bit.va
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+ ha1b.va
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+ hpribin4bit.va
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+ jkff_SR.va
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+ log_amp.va
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+ logic_0.va
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+ logic_1.va
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+ MESFET.va
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+ mod_amp.va
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+ mux2to1.va
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+ mux4to1.va
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+ mux8to1.va
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+ nigbt.va
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+ pad2bit.va
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+ pad3bit.va
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+ pad4bit.va
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+ photodiode.va
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+ phototransistor.va
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+ potentiometer.va
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+ tff_SR.va
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+ vcresistor.va )
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# XML sripts need to build, the order matters
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- set (XML_BUILD analogfunction.xml qucsVersion.xml qucsMODULEcore.xml
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- qucsMODULEdefs.xml)
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+ set (XML_BUILD
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+ analogfunction.xml
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+ qucsVersion.xml
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+ qucsMODULEcore.xml
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+ qucsMODULEdefs.xml)
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# Concatenate scripts into command: -e script1 [-e script2]
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set (XML_CMD)
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foreach (script ${XML_BUILD} )
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set (XML_CMD ${XML_CMD} -e ${CMAKE_CURRENT_SOURCE_DIR} /${script} )
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endforeach ()
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- # clear lists of generated files
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- set (generated_SRC)
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-
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- # Process each Verilog-A file. * generated files get added to lists (analogfunc,
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- # core)
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- foreach (filename ${VA_FILES} )
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- # Default
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- set (fileout ${filename} .va)
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-
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- # Verilog-A file basename, strip suffix
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- get_filename_component (base ${fileout} NAME_WE )
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- set (base_abs ${CMAKE_CURRENT_BINARY_DIR} /${base} )
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-
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- # set outputs for each Verilog-A input
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+ # Process each Verilog-A file.
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+ set (gen_SRC)
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+ foreach (file ${VA_FILES} )
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+ get_filename_component (_name ${file} NAME_WE )
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set (output
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- ${base_abs} .analogfunction.cpp ${base_abs} .analogfunction.h
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- ${base_abs} .cpp ${base_abs} .core.cpp ${base_abs} .core.h
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- ${base_abs} .defs.h)
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-
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+ ${_name} .${_name} .analogfunction.h
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+ ${_name} .${_name} .analogfunction.cpp
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+ ${_name} .${_name} .core.cpp
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+ ${_name} .core.h
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+ ${_name} .cpp
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+ ${_name} .defs.h)
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# custom command/rule to generate outputs with admsXml
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add_custom_command (
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OUTPUT ${output}
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- COMMAND ${ADMSXML} ${CMAKE_CURRENT_SOURCE_DIR} /${filename} .va ${XML_CMD} -o
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- ${filename}
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- DEPENDS ${filename} .va ${XML_BUILD} )
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- set_source_files_properties (${output} PROPERTIES GENERATED TRUE )
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-
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- # append outputs list of generated sources
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- set (generated_SRC ${generated_SRC} ${base_abs} .cpp)
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+ COMMAND ${ADMSXML} ${CMAKE_CURRENT_SOURCE_DIR} /${file} ${XML_CMD} -o
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+ ${_name}
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+ DEPENDS ${file} ${XML_BUILD} )
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+ list (APPEND gen_SRC ${_name} .cpp)
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endforeach ()
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- # MESSAGE(STATUS " ==> generated\n " ${generated_SRC})
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-
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- add_library (coreVerilog OBJECT ${generated_SRC} )
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+ add_library (coreVerilog OBJECT ${gen_SRC} )
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# Distribute XML scripts
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set (XML_DIST ${XML_BUILD} qucsMODULEgui.xml qucsMODULEguiJSONsymbol.xml)
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