diff --git a/README.md b/README.md index a3b267cb..12c58c88 100644 --- a/README.md +++ b/README.md @@ -83,7 +83,7 @@ Requirements -------------------- - Python: 3.7.7 or later - - Python 3.9.5 (via pyenv) is recommended for macOS with Apple Silicon. + - Python 3.9.5 or later version is recommended for macOS with Apple Silicon. - Icarus Verilog: 10.1 or later ``` diff --git a/examples/axi_stream_ultra96v2_pynq/test_axi_stream.py b/examples/axi_stream_ultra96v2_pynq/test_axi_stream.py index a9371005..0b30f66f 100644 --- a/examples/axi_stream_ultra96v2_pynq/test_axi_stream.py +++ b/examples/axi_stream_ultra96v2_pynq/test_axi_stream.py @@ -189,7 +189,7 @@ (axis_maskaddr_13 == 1)? _saxi_resetval_1 : (axis_maskaddr_13 == 2)? _saxi_resetval_2 : (axis_maskaddr_13 == 3)? _saxi_resetval_3 : 'hx; - reg _saxi_cond_0_1; + reg _saxi_rdata_cond_0_1; assign saxi_wready = _saxi_register_fsm == 3; reg [32-1:0] th_comp; localparam th_comp_init = 0; @@ -235,7 +235,6 @@ always @(posedge CLK) begin if(RST) begin - _axi_b_write_data_busy <= 0; axi_b_tdata <= 0; axi_b_tvalid <= 0; axi_b_tlast <= 0; @@ -245,9 +244,6 @@ axi_b_tvalid <= 0; axi_b_tlast <= 0; end - if((th_comp == 12) && _axi_b_write_idle) begin - _axi_b_write_data_busy <= 1; - end if((th_comp == 13) && (axi_b_tready || !axi_b_tvalid)) begin axi_b_tdata <= _th_comp_b_4; axi_b_tvalid <= 1; @@ -258,6 +254,17 @@ axi_b_tvalid <= axi_b_tvalid; axi_b_tlast <= axi_b_tlast; end + end + end + + + always @(posedge CLK) begin + if(RST) begin + _axi_b_write_data_busy <= 0; + end else begin + if((th_comp == 12) && _axi_b_write_idle) begin + _axi_b_write_data_busy <= 1; + end if((th_comp == 13) && (axi_b_tready || !axi_b_tvalid)) begin _axi_b_write_data_busy <= 0; end @@ -280,6 +287,27 @@ end + always @(posedge CLK) begin + if(RST) begin + saxi_rdata <= 0; + saxi_rvalid <= 0; + _saxi_rdata_cond_0_1 <= 0; + end else begin + if(_saxi_rdata_cond_0_1) begin + saxi_rvalid <= 0; + end + if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid)) begin + saxi_rdata <= axislite_rdata_14; + saxi_rvalid <= 1; + end + _saxi_rdata_cond_0_1 <= 1; + if(saxi_rvalid && !saxi_rready) begin + saxi_rvalid <= saxi_rvalid; + end + end + end + + always @(posedge CLK) begin if(RST) begin saxi_bvalid <= 0; @@ -288,9 +316,6 @@ writevalid_9 <= 0; readvalid_10 <= 0; addr_8 <= 0; - saxi_rdata <= 0; - saxi_rvalid <= 0; - _saxi_cond_0_1 <= 0; _saxi_register_0 <= 0; _saxi_flag_0 <= 0; _saxi_register_1 <= 0; @@ -300,9 +325,6 @@ _saxi_register_3 <= 0; _saxi_flag_3 <= 0; end else begin - if(_saxi_cond_0_1) begin - saxi_rvalid <= 0; - end if(saxi_bvalid && saxi_bready) begin saxi_bvalid <= 0; end @@ -320,14 +342,6 @@ addr_8 <= saxi_araddr; readvalid_10 <= 1; end - if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid)) begin - saxi_rdata <= axislite_rdata_14; - saxi_rvalid <= 1; - end - _saxi_cond_0_1 <= 1; - if(saxi_rvalid && !saxi_rready) begin - saxi_rvalid <= saxi_rvalid; - end if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_15 && (axis_maskaddr_13 == 0)) begin _saxi_register_0 <= axislite_resetval_16; _saxi_flag_0 <= 0; diff --git a/examples/axi_stream_ultra96v2_pynq/ultra96v2_pynq/run_on_pynq.py b/examples/axi_stream_ultra96v2_pynq/ultra96v2_pynq/run_on_pynq.py index 12b838f0..c82a46c4 100644 --- a/examples/axi_stream_ultra96v2_pynq/ultra96v2_pynq/run_on_pynq.py +++ b/examples/axi_stream_ultra96v2_pynq/ultra96v2_pynq/run_on_pynq.py @@ -81,4 +81,3 @@ diff_sum = np.sum(expected - dst) print(diff_sum) - diff --git a/examples/chatter_clear/test_chatter_clear.py b/examples/chatter_clear/test_chatter_clear.py index d1b9274c..d64a297e 100644 --- a/examples/chatter_clear/test_chatter_clear.py +++ b/examples/chatter_clear/test_chatter_clear.py @@ -185,6 +185,7 @@ endmodule """ + def test(): veriloggen.reset() test_module = chatter_clear.mkTest() diff --git a/examples/counter/test_counter.py b/examples/counter/test_counter.py index 50888871..2c431447 100644 --- a/examples/counter/test_counter.py +++ b/examples/counter/test_counter.py @@ -90,6 +90,7 @@ endmodule """ + def test(): veriloggen.reset() test_module = counter.mkTest() diff --git a/examples/led/test_led.py b/examples/led/test_led.py index cb5a334a..3f80ba71 100644 --- a/examples/led/test_led.py +++ b/examples/led/test_led.py @@ -82,6 +82,7 @@ endmodule """ + def test(): veriloggen.reset() test_module = led.mkTest() diff --git a/examples/manyled/manyled.py b/examples/manyled/manyled.py index bc3d31e4..dc6a1c2a 100644 --- a/examples/manyled/manyled.py +++ b/examples/manyled/manyled.py @@ -8,6 +8,7 @@ from veriloggen import * + def mkLed(): m = Module('blinkled') width = m.Parameter('WIDTH', 8) @@ -16,8 +17,8 @@ def mkLed(): # function to add an LED port def add_led(postfix, limit=1024): - led = m.OutputReg('LED'+postfix, width) - count = m.Reg('count'+postfix, 32) + led = m.OutputReg('LED' + postfix, width) + count = m.Reg('count' + postfix, 32) m.Always(Posedge(clk))( If(rst)( @@ -29,7 +30,7 @@ def add_led(postfix, limit=1024): count(count + 1) ) )) - + m.Always(Posedge(clk))( If(rst)( led(0) @@ -41,10 +42,11 @@ def add_led(postfix, limit=1024): # call 'add_led' to add LED ports for i in range(4): - add_led('_' + str(i), limit=i*10 + 10) - + add_led('_' + str(i), limit=i * 10 + 10) + return m + if __name__ == '__main__': led = mkLed() verilog = led.to_verilog() diff --git a/examples/manyled/test_manyled.py b/examples/manyled/test_manyled.py index 74d7e4c8..8651bb06 100644 --- a/examples/manyled/test_manyled.py +++ b/examples/manyled/test_manyled.py @@ -103,6 +103,7 @@ endmodule """ + def test(): veriloggen.reset() test_module = manyled.mkLed() diff --git a/examples/read_verilog_code/read_verilog_code.py b/examples/read_verilog_code/read_verilog_code.py index 721a445a..ed079753 100644 --- a/examples/read_verilog_code/read_verilog_code.py +++ b/examples/read_verilog_code/read_verilog_code.py @@ -43,23 +43,25 @@ endmodule ''' + def mkLed(): modules = from_verilog.read_verilog_module_str(led_v) m = modules['blinkled'] - + # change the module name m.name = 'modified_led' - + # add new statements enable = m.Input('enable') busy = m.Output('busy') old_statement = m.always[0].statement[0].false_statement m.always[0].statement[0].false_statement = If(enable)(*old_statement) - m.Assign( busy(m.variable['count'] < 1023) ) - + m.Assign(busy(m.variable['count'] < 1023)) + return m + if __name__ == '__main__': led = mkLed() verilog = led.to_verilog() diff --git a/examples/read_verilog_code/test_read_verilog_code.py b/examples/read_verilog_code/test_read_verilog_code.py index 64e306e4..cf4bac03 100644 --- a/examples/read_verilog_code/test_read_verilog_code.py +++ b/examples/read_verilog_code/test_read_verilog_code.py @@ -40,6 +40,7 @@ endmodule """ + def test(): veriloggen.reset() test_module = read_verilog_code.mkLed() diff --git a/examples/regchain/regchain.py b/examples/regchain/regchain.py index a5ca4560..ef1bde60 100644 --- a/examples/regchain/regchain.py +++ b/examples/regchain/regchain.py @@ -8,6 +8,7 @@ from veriloggen import * + def mkRegChain(length=120, width=8): m = Module("reg_chain") @@ -19,47 +20,48 @@ def mkRegChain(length=120, width=8): seq = Seq(m, 'seq', clk, rst) update_cond_value = m.TmpReg(3, initval=0) - seq( update_cond_value(sw[0:3]) ) + seq(update_cond_value(sw[0:3])) area_size = m.TmpReg(2, initval=0) - seq( area_size(sw[3:5]) ) - + seq(area_size(sw[3:5])) + count = m.TmpReg(2, initval=0) - seq( count.inc() ) - + seq(count.inc()) + update_cond = m.TmpReg(initval=0) - seq( update_cond(count < update_cond_value) ) + seq(update_cond(count < update_cond_value)) orig = m.TmpReg(width, initval=0) prev = orig regs = [] - + for i in range(length): area_id = i // (length // 4) r = m.TmpReg(width, initval=0) regs.append(r) - seq.If(AndList(update_cond, area_id <= area_size))( r(prev + 1) ) + seq.If(AndList(update_cond, area_id <= area_size))(r(prev + 1)) prev = r - seq.If(AndList(update_cond, area_size==0))( orig(regs[1*length//4-1] + 3) ) - seq.If(AndList(update_cond, area_size==1))( orig(regs[2*length//4-1] + 2) ) - seq.If(AndList(update_cond, area_size==2))( orig(regs[3*length//4-1] + 1) ) - seq.If(AndList(update_cond, area_size==3))( orig(regs[4*length//4-1] + 0) ) + seq.If(AndList(update_cond, area_size == 0))(orig(regs[1 * length // 4 - 1] + 3)) + seq.If(AndList(update_cond, area_size == 1))(orig(regs[2 * length // 4 - 1] + 2)) + seq.If(AndList(update_cond, area_size == 2))(orig(regs[3 * length // 4 - 1] + 1)) + seq.If(AndList(update_cond, area_size == 3))(orig(regs[4 * length // 4 - 1] + 0)) seq.make_always() - - m.Assign( dout(orig) ) + + m.Assign(dout(orig)) return m + def mkTest(length=120, width=8): m = Module('test') - + main = mkRegChain(length, width) params = m.copy_params(main) ports = m.copy_sim_ports(main) - + clk = ports['CLK'] rst = ports['RST'] sw = ports['sw'] @@ -67,49 +69,49 @@ def mkTest(length=120, width=8): fsm = FSM(m, 'fsm', clk, rst) count = m.TmpReg(32, initval=0) - - fsm( sw((3 << 3) | 4) ) - fsm( count.inc() ) - fsm.If(count==2000)( count(0) ) - fsm.goto_next(count==2000) - - fsm( sw((2 << 3) | 4) ) - fsm( count.inc() ) - fsm.If(count==2000)( count(0) ) - fsm.goto_next(count==2000) - - fsm( sw((1 << 3) | 4) ) - fsm( count.inc() ) - fsm.If(count==2000)( count(0) ) - fsm.goto_next(count==2000) - - fsm( sw((0 << 3) | 4) ) - fsm( count.inc() ) - fsm.If(count==2000)( count(0) ) - fsm.goto_next(count==2000) - - fsm( sw((2 << 3) | 3) ) - fsm( count.inc() ) - fsm.If(count==2000)( count(0) ) - fsm.goto_next(count==2000) - - fsm( sw((2 << 3) | 2) ) - fsm( count.inc() ) - fsm.If(count==2000)( count(0) ) - fsm.goto_next(count==2000) - - fsm( sw((2 << 3) | 1) ) - fsm( count.inc() ) - fsm.If(count==2000)( count(0) ) - fsm.goto_next(count==2000) - - fsm( sw((2 << 3) | 0) ) - fsm( count.inc() ) - fsm.If(count==2000)( count(0) ) - fsm.goto_next(count==2000) + + fsm(sw((3 << 3) | 4)) + fsm(count.inc()) + fsm.If(count == 2000)(count(0)) + fsm.goto_next(count == 2000) + + fsm(sw((2 << 3) | 4)) + fsm(count.inc()) + fsm.If(count == 2000)(count(0)) + fsm.goto_next(count == 2000) + + fsm(sw((1 << 3) | 4)) + fsm(count.inc()) + fsm.If(count == 2000)(count(0)) + fsm.goto_next(count == 2000) + + fsm(sw((0 << 3) | 4)) + fsm(count.inc()) + fsm.If(count == 2000)(count(0)) + fsm.goto_next(count == 2000) + + fsm(sw((2 << 3) | 3)) + fsm(count.inc()) + fsm.If(count == 2000)(count(0)) + fsm.goto_next(count == 2000) + + fsm(sw((2 << 3) | 2)) + fsm(count.inc()) + fsm.If(count == 2000)(count(0)) + fsm.goto_next(count == 2000) + + fsm(sw((2 << 3) | 1)) + fsm(count.inc()) + fsm.If(count == 2000)(count(0)) + fsm.goto_next(count == 2000) + + fsm(sw((2 << 3) | 0)) + fsm(count.inc()) + fsm.If(count == 2000)(count(0)) + fsm.goto_next(count == 2000) fsm.make_always() - + uut = m.Instance(main, 'uut', params=m.connect_params(main), ports=m.connect_ports(main)) @@ -119,7 +121,7 @@ def mkTest(length=120, width=8): init = simulation.setup_reset(m, rst, m.make_reset(), period=100) nclk = simulation.next_clock - + init.add( sw(0), Delay(1000 * 200), @@ -127,7 +129,8 @@ def mkTest(length=120, width=8): ) return m - + + if __name__ == '__main__': main = mkRegChain(length=120) verilog = main.to_verilog('tmp.v') @@ -135,14 +138,14 @@ def mkTest(length=120, width=8): #test = mkTest() #verilog = test.to_verilog('tmp.v') - #print(verilog) + # print(verilog) # run simulator (Icarus Verilog) #sim = simulation.Simulator(test) - #rslt = sim.run() # display=False + # rslt = sim.run() # display=False ##rslt = sim.run(display=True) - #print(rslt) + # print(rslt) # launch waveform viewer (GTKwave) - #sim.view_waveform() # background=False - #sim.view_waveform(background=True) + # sim.view_waveform() # background=False + # sim.view_waveform(background=True) diff --git a/examples/regchain/test_regchain.py b/examples/regchain/test_regchain.py index c53a0729..c4737b85 100644 --- a/examples/regchain/test_regchain.py +++ b/examples/regchain/test_regchain.py @@ -650,6 +650,7 @@ endmodule """ + def test(): veriloggen.reset() test_module = regchain.mkRegChain(length=120) diff --git a/examples/simulation_verilator/simulation_verilator.py b/examples/simulation_verilator/simulation_verilator.py index 9e781890..da412ca8 100644 --- a/examples/simulation_verilator/simulation_verilator.py +++ b/examples/simulation_verilator/simulation_verilator.py @@ -179,7 +179,7 @@ def fwrite(f, value): if __name__ == '__main__': test = mkTest() #verilog = test.to_verilog('tmp.v') - #print(verilog) + # print(verilog) sim = simulation.Simulator(test, sim='verilator') rslt = sim.run(outputfile='verilator.out') diff --git a/examples/simulation_verilator/test_simulation_verilator.py b/examples/simulation_verilator/test_simulation_verilator.py index 0e10a09e..2f746235 100644 --- a/examples/simulation_verilator/test_simulation_verilator.py +++ b/examples/simulation_verilator/test_simulation_verilator.py @@ -68,6 +68,7 @@ wire [2-1:0] memory_bresp; reg memory_bvalid; wire memory_bready; + assign memory_bresp = 0; wire [32-1:0] memory_araddr; wire [8-1:0] memory_arlen; wire [3-1:0] memory_arsize; @@ -84,7 +85,6 @@ reg memory_rlast; reg memory_rvalid; wire memory_rready; - assign memory_bresp = 0; assign memory_rresp = 0; reg [32-1:0] _memory_waddr_fsm; localparam _memory_waddr_fsm_init = 0; @@ -956,10 +956,10 @@ output [2-1:0] myaxi_awuser, output reg myaxi_awvalid, input myaxi_awready, - output reg [32-1:0] myaxi_wdata, - output reg [4-1:0] myaxi_wstrb, - output reg myaxi_wlast, - output reg myaxi_wvalid, + output [32-1:0] myaxi_wdata, + output [4-1:0] myaxi_wstrb, + output myaxi_wlast, + output myaxi_wvalid, input myaxi_wready, input [2-1:0] myaxi_bresp, input myaxi_bvalid, @@ -1041,6 +1041,44 @@ assign myaxi_awprot = 0; assign myaxi_awqos = 0; assign myaxi_awuser = 0; + reg [32-1:0] _myaxi_wdata_sb_0; + reg [4-1:0] _myaxi_wstrb_sb_0; + reg _myaxi_wlast_sb_0; + reg _myaxi_wvalid_sb_0; + wire _myaxi_wready_sb_0; + wire _sb_myaxi_writedata_s_value_0; + assign _sb_myaxi_writedata_s_value_0 = _myaxi_wlast_sb_0; + wire [4-1:0] _sb_myaxi_writedata_s_value_1; + assign _sb_myaxi_writedata_s_value_1 = _myaxi_wstrb_sb_0; + wire [32-1:0] _sb_myaxi_writedata_s_value_2; + assign _sb_myaxi_writedata_s_value_2 = _myaxi_wdata_sb_0; + wire [37-1:0] _sb_myaxi_writedata_s_data_3; + assign _sb_myaxi_writedata_s_data_3 = { _sb_myaxi_writedata_s_value_0, _sb_myaxi_writedata_s_value_1, _sb_myaxi_writedata_s_value_2 }; + wire _sb_myaxi_writedata_s_valid_4; + assign _sb_myaxi_writedata_s_valid_4 = _myaxi_wvalid_sb_0; + wire _sb_myaxi_writedata_m_ready_5; + assign _sb_myaxi_writedata_m_ready_5 = myaxi_wready; + reg [37-1:0] _sb_myaxi_writedata_data_6; + reg _sb_myaxi_writedata_valid_7; + wire _sb_myaxi_writedata_ready_8; + reg [37-1:0] _sb_myaxi_writedata_tmp_data_9; + reg _sb_myaxi_writedata_tmp_valid_10; + wire [37-1:0] _sb_myaxi_writedata_next_data_11; + wire _sb_myaxi_writedata_next_valid_12; + assign _sb_myaxi_writedata_ready_8 = !_sb_myaxi_writedata_tmp_valid_10; + assign _sb_myaxi_writedata_next_data_11 = (_sb_myaxi_writedata_tmp_valid_10)? _sb_myaxi_writedata_tmp_data_9 : _sb_myaxi_writedata_s_data_3; + assign _sb_myaxi_writedata_next_valid_12 = _sb_myaxi_writedata_tmp_valid_10 || _sb_myaxi_writedata_s_valid_4; + wire _sb_myaxi_writedata_m_value_13; + assign _sb_myaxi_writedata_m_value_13 = _sb_myaxi_writedata_data_6[36:36]; + wire [4-1:0] _sb_myaxi_writedata_m_value_14; + assign _sb_myaxi_writedata_m_value_14 = _sb_myaxi_writedata_data_6[35:32]; + wire [32-1:0] _sb_myaxi_writedata_m_value_15; + assign _sb_myaxi_writedata_m_value_15 = _sb_myaxi_writedata_data_6[31:0]; + assign _myaxi_wready_sb_0 = _sb_myaxi_writedata_ready_8; + assign myaxi_wdata = _sb_myaxi_writedata_m_value_15; + assign myaxi_wstrb = _sb_myaxi_writedata_m_value_14; + assign myaxi_wlast = _sb_myaxi_writedata_m_value_13; + assign myaxi_wvalid = _sb_myaxi_writedata_valid_7; assign myaxi_bready = 1; assign myaxi_arsize = 2; assign myaxi_arburst = 1; @@ -1049,6 +1087,38 @@ assign myaxi_arprot = 0; assign myaxi_arqos = 0; assign myaxi_aruser = 0; + wire [32-1:0] _myaxi_rdata_sb_0; + wire _myaxi_rlast_sb_0; + wire _myaxi_rvalid_sb_0; + wire _myaxi_rready_sb_0; + wire _sb_myaxi_readdata_s_value_16; + assign _sb_myaxi_readdata_s_value_16 = myaxi_rlast; + wire [32-1:0] _sb_myaxi_readdata_s_value_17; + assign _sb_myaxi_readdata_s_value_17 = myaxi_rdata; + wire [33-1:0] _sb_myaxi_readdata_s_data_18; + assign _sb_myaxi_readdata_s_data_18 = { _sb_myaxi_readdata_s_value_16, _sb_myaxi_readdata_s_value_17 }; + wire _sb_myaxi_readdata_s_valid_19; + assign _sb_myaxi_readdata_s_valid_19 = myaxi_rvalid; + wire _sb_myaxi_readdata_m_ready_20; + assign _sb_myaxi_readdata_m_ready_20 = _myaxi_rready_sb_0; + reg [33-1:0] _sb_myaxi_readdata_data_21; + reg _sb_myaxi_readdata_valid_22; + wire _sb_myaxi_readdata_ready_23; + reg [33-1:0] _sb_myaxi_readdata_tmp_data_24; + reg _sb_myaxi_readdata_tmp_valid_25; + wire [33-1:0] _sb_myaxi_readdata_next_data_26; + wire _sb_myaxi_readdata_next_valid_27; + assign _sb_myaxi_readdata_ready_23 = !_sb_myaxi_readdata_tmp_valid_25; + assign _sb_myaxi_readdata_next_data_26 = (_sb_myaxi_readdata_tmp_valid_25)? _sb_myaxi_readdata_tmp_data_24 : _sb_myaxi_readdata_s_data_18; + assign _sb_myaxi_readdata_next_valid_27 = _sb_myaxi_readdata_tmp_valid_25 || _sb_myaxi_readdata_s_valid_19; + wire _sb_myaxi_readdata_m_value_28; + assign _sb_myaxi_readdata_m_value_28 = _sb_myaxi_readdata_data_21[32:32]; + wire [32-1:0] _sb_myaxi_readdata_m_value_29; + assign _sb_myaxi_readdata_m_value_29 = _sb_myaxi_readdata_data_21[31:0]; + assign _myaxi_rdata_sb_0 = _sb_myaxi_readdata_m_value_29; + assign _myaxi_rlast_sb_0 = _sb_myaxi_readdata_m_value_28; + assign _myaxi_rvalid_sb_0 = _sb_myaxi_readdata_valid_22; + assign myaxi_rready = _sb_myaxi_readdata_ready_23; reg [3-1:0] _myaxi_outstanding_wcount; wire _myaxi_has_outstanding_write; assign _myaxi_has_outstanding_write = (_myaxi_outstanding_wcount > 0) || myaxi_awvalid; @@ -1090,21 +1160,21 @@ wire [32-1:0] _myaxi_read_local_stride_fifo; wire [33-1:0] _myaxi_read_local_size_fifo; wire [32-1:0] _myaxi_read_local_blocksize_fifo; - wire [8-1:0] unpack_read_req_op_sel_0; - wire [32-1:0] unpack_read_req_local_addr_1; - wire [32-1:0] unpack_read_req_local_stride_2; - wire [33-1:0] unpack_read_req_local_size_3; - wire [32-1:0] unpack_read_req_local_blocksize_4; - assign unpack_read_req_op_sel_0 = _myaxi_read_req_fifo_rdata[136:129]; - assign unpack_read_req_local_addr_1 = _myaxi_read_req_fifo_rdata[128:97]; - assign unpack_read_req_local_stride_2 = _myaxi_read_req_fifo_rdata[96:65]; - assign unpack_read_req_local_size_3 = _myaxi_read_req_fifo_rdata[64:32]; - assign unpack_read_req_local_blocksize_4 = _myaxi_read_req_fifo_rdata[31:0]; - assign _myaxi_read_op_sel_fifo = unpack_read_req_op_sel_0; - assign _myaxi_read_local_addr_fifo = unpack_read_req_local_addr_1; - assign _myaxi_read_local_stride_fifo = unpack_read_req_local_stride_2; - assign _myaxi_read_local_size_fifo = unpack_read_req_local_size_3; - assign _myaxi_read_local_blocksize_fifo = unpack_read_req_local_blocksize_4; + wire [8-1:0] unpack_read_req_op_sel_30; + wire [32-1:0] unpack_read_req_local_addr_31; + wire [32-1:0] unpack_read_req_local_stride_32; + wire [33-1:0] unpack_read_req_local_size_33; + wire [32-1:0] unpack_read_req_local_blocksize_34; + assign unpack_read_req_op_sel_30 = _myaxi_read_req_fifo_rdata[136:129]; + assign unpack_read_req_local_addr_31 = _myaxi_read_req_fifo_rdata[128:97]; + assign unpack_read_req_local_stride_32 = _myaxi_read_req_fifo_rdata[96:65]; + assign unpack_read_req_local_size_33 = _myaxi_read_req_fifo_rdata[64:32]; + assign unpack_read_req_local_blocksize_34 = _myaxi_read_req_fifo_rdata[31:0]; + assign _myaxi_read_op_sel_fifo = unpack_read_req_op_sel_30; + assign _myaxi_read_local_addr_fifo = unpack_read_req_local_addr_31; + assign _myaxi_read_local_stride_fifo = unpack_read_req_local_stride_32; + assign _myaxi_read_local_size_fifo = unpack_read_req_local_size_33; + assign _myaxi_read_local_blocksize_fifo = unpack_read_req_local_blocksize_34; reg [8-1:0] _myaxi_read_op_sel_buf; reg [32-1:0] _myaxi_read_local_addr_buf; reg [32-1:0] _myaxi_read_local_stride_buf; @@ -1156,21 +1226,21 @@ wire [32-1:0] _myaxi_write_local_stride_fifo; wire [33-1:0] _myaxi_write_size_fifo; wire [32-1:0] _myaxi_write_local_blocksize_fifo; - wire [8-1:0] unpack_write_req_op_sel_5; - wire [32-1:0] unpack_write_req_local_addr_6; - wire [32-1:0] unpack_write_req_local_stride_7; - wire [33-1:0] unpack_write_req_size_8; - wire [32-1:0] unpack_write_req_local_blocksize_9; - assign unpack_write_req_op_sel_5 = _myaxi_write_req_fifo_rdata[136:129]; - assign unpack_write_req_local_addr_6 = _myaxi_write_req_fifo_rdata[128:97]; - assign unpack_write_req_local_stride_7 = _myaxi_write_req_fifo_rdata[96:65]; - assign unpack_write_req_size_8 = _myaxi_write_req_fifo_rdata[64:32]; - assign unpack_write_req_local_blocksize_9 = _myaxi_write_req_fifo_rdata[31:0]; - assign _myaxi_write_op_sel_fifo = unpack_write_req_op_sel_5; - assign _myaxi_write_local_addr_fifo = unpack_write_req_local_addr_6; - assign _myaxi_write_local_stride_fifo = unpack_write_req_local_stride_7; - assign _myaxi_write_size_fifo = unpack_write_req_size_8; - assign _myaxi_write_local_blocksize_fifo = unpack_write_req_local_blocksize_9; + wire [8-1:0] unpack_write_req_op_sel_35; + wire [32-1:0] unpack_write_req_local_addr_36; + wire [32-1:0] unpack_write_req_local_stride_37; + wire [33-1:0] unpack_write_req_size_38; + wire [32-1:0] unpack_write_req_local_blocksize_39; + assign unpack_write_req_op_sel_35 = _myaxi_write_req_fifo_rdata[136:129]; + assign unpack_write_req_local_addr_36 = _myaxi_write_req_fifo_rdata[128:97]; + assign unpack_write_req_local_stride_37 = _myaxi_write_req_fifo_rdata[96:65]; + assign unpack_write_req_size_38 = _myaxi_write_req_fifo_rdata[64:32]; + assign unpack_write_req_local_blocksize_39 = _myaxi_write_req_fifo_rdata[31:0]; + assign _myaxi_write_op_sel_fifo = unpack_write_req_op_sel_35; + assign _myaxi_write_local_addr_fifo = unpack_write_req_local_addr_36; + assign _myaxi_write_local_stride_fifo = unpack_write_req_local_stride_37; + assign _myaxi_write_size_fifo = unpack_write_req_size_38; + assign _myaxi_write_local_blocksize_fifo = unpack_write_req_local_blocksize_39; reg [8-1:0] _myaxi_write_op_sel_buf; reg [32-1:0] _myaxi_write_local_addr_buf; reg [32-1:0] _myaxi_write_local_stride_buf; @@ -1198,190 +1268,190 @@ reg signed [32-1:0] _th_matmul_a_addr_9; reg signed [32-1:0] _th_matmul_c_addr_10; reg signed [32-1:0] _th_matmul_i_11; - wire [32-1:0] mask_addr_shifted_10; - assign mask_addr_shifted_10 = _th_matmul_a_addr_9 >> 2; - wire [32-1:0] mask_addr_masked_11; - assign mask_addr_masked_11 = mask_addr_shifted_10 << 2; + wire [32-1:0] mask_addr_shifted_40; + assign mask_addr_shifted_40 = _th_matmul_a_addr_9 >> 2; + wire [32-1:0] mask_addr_masked_41; + assign mask_addr_masked_41 = mask_addr_shifted_40 << 2; reg [32-1:0] _myaxi_read_req_fsm; localparam _myaxi_read_req_fsm_init = 0; reg [33-1:0] _myaxi_read_cur_global_size; reg _myaxi_read_cont; - wire [8-1:0] pack_read_req_op_sel_12; - wire [32-1:0] pack_read_req_local_addr_13; - wire [32-1:0] pack_read_req_local_stride_14; - wire [33-1:0] pack_read_req_local_size_15; - wire [32-1:0] pack_read_req_local_blocksize_16; - assign pack_read_req_op_sel_12 = _myaxi_read_op_sel; - assign pack_read_req_local_addr_13 = _myaxi_read_local_addr; - assign pack_read_req_local_stride_14 = _myaxi_read_local_stride; - assign pack_read_req_local_size_15 = _myaxi_read_local_size; - assign pack_read_req_local_blocksize_16 = _myaxi_read_local_blocksize; - wire [137-1:0] pack_read_req_packed_17; - assign pack_read_req_packed_17 = { pack_read_req_op_sel_12, pack_read_req_local_addr_13, pack_read_req_local_stride_14, pack_read_req_local_size_15, pack_read_req_local_blocksize_16 }; - assign _myaxi_read_req_fifo_wdata = ((_myaxi_read_req_fsm == 0) && _myaxi_read_start && !_myaxi_read_req_fifo_almost_full)? pack_read_req_packed_17 : 'hx; + wire [8-1:0] pack_read_req_op_sel_42; + wire [32-1:0] pack_read_req_local_addr_43; + wire [32-1:0] pack_read_req_local_stride_44; + wire [33-1:0] pack_read_req_local_size_45; + wire [32-1:0] pack_read_req_local_blocksize_46; + assign pack_read_req_op_sel_42 = _myaxi_read_op_sel; + assign pack_read_req_local_addr_43 = _myaxi_read_local_addr; + assign pack_read_req_local_stride_44 = _myaxi_read_local_stride; + assign pack_read_req_local_size_45 = _myaxi_read_local_size; + assign pack_read_req_local_blocksize_46 = _myaxi_read_local_blocksize; + wire [137-1:0] pack_read_req_packed_47; + assign pack_read_req_packed_47 = { pack_read_req_op_sel_42, pack_read_req_local_addr_43, pack_read_req_local_stride_44, pack_read_req_local_size_45, pack_read_req_local_blocksize_46 }; + assign _myaxi_read_req_fifo_wdata = ((_myaxi_read_req_fsm == 0) && _myaxi_read_start && !_myaxi_read_req_fifo_almost_full)? pack_read_req_packed_47 : 'hx; assign _myaxi_read_req_fifo_enq = ((_myaxi_read_req_fsm == 0) && _myaxi_read_start && !_myaxi_read_req_fifo_almost_full)? (_myaxi_read_req_fsm == 0) && _myaxi_read_start && !_myaxi_read_req_fifo_almost_full && !_myaxi_read_req_fifo_almost_full : 0; - localparam _tmp_18 = 1; - wire [_tmp_18-1:0] _tmp_19; - assign _tmp_19 = !_myaxi_read_req_fifo_almost_full; - reg [_tmp_18-1:0] __tmp_19_1; - wire [32-1:0] mask_addr_shifted_20; - assign mask_addr_shifted_20 = _myaxi_read_global_addr >> 2; - wire [32-1:0] mask_addr_masked_21; - assign mask_addr_masked_21 = mask_addr_shifted_20 << 2; - wire [32-1:0] mask_addr_shifted_22; - assign mask_addr_shifted_22 = _myaxi_read_global_addr >> 2; - wire [32-1:0] mask_addr_masked_23; - assign mask_addr_masked_23 = mask_addr_shifted_22 << 2; - wire [32-1:0] mask_addr_shifted_24; - assign mask_addr_shifted_24 = _myaxi_read_global_addr >> 2; - wire [32-1:0] mask_addr_masked_25; - assign mask_addr_masked_25 = mask_addr_shifted_24 << 2; - wire [32-1:0] mask_addr_shifted_26; - assign mask_addr_shifted_26 = _myaxi_read_global_addr >> 2; - wire [32-1:0] mask_addr_masked_27; - assign mask_addr_masked_27 = mask_addr_shifted_26 << 2; - wire [32-1:0] mask_addr_shifted_28; - assign mask_addr_shifted_28 = _myaxi_read_global_addr >> 2; - wire [32-1:0] mask_addr_masked_29; - assign mask_addr_masked_29 = mask_addr_shifted_28 << 2; - wire [32-1:0] mask_addr_shifted_30; - assign mask_addr_shifted_30 = _myaxi_read_global_addr >> 2; - wire [32-1:0] mask_addr_masked_31; - assign mask_addr_masked_31 = mask_addr_shifted_30 << 2; - reg _myaxi_cond_0_1; + localparam _tmp_48 = 1; + wire [_tmp_48-1:0] _tmp_49; + assign _tmp_49 = !_myaxi_read_req_fifo_almost_full; + reg [_tmp_48-1:0] __tmp_49_1; + wire [32-1:0] mask_addr_shifted_50; + assign mask_addr_shifted_50 = _myaxi_read_global_addr >> 2; + wire [32-1:0] mask_addr_masked_51; + assign mask_addr_masked_51 = mask_addr_shifted_50 << 2; + wire [32-1:0] mask_addr_shifted_52; + assign mask_addr_shifted_52 = _myaxi_read_global_addr >> 2; + wire [32-1:0] mask_addr_masked_53; + assign mask_addr_masked_53 = mask_addr_shifted_52 << 2; + wire [32-1:0] mask_addr_shifted_54; + assign mask_addr_shifted_54 = _myaxi_read_global_addr >> 2; + wire [32-1:0] mask_addr_masked_55; + assign mask_addr_masked_55 = mask_addr_shifted_54 << 2; + wire [32-1:0] mask_addr_shifted_56; + assign mask_addr_shifted_56 = _myaxi_read_global_addr >> 2; + wire [32-1:0] mask_addr_masked_57; + assign mask_addr_masked_57 = mask_addr_shifted_56 << 2; + wire [32-1:0] mask_addr_shifted_58; + assign mask_addr_shifted_58 = _myaxi_read_global_addr >> 2; + wire [32-1:0] mask_addr_masked_59; + assign mask_addr_masked_59 = mask_addr_shifted_58 << 2; + wire [32-1:0] mask_addr_shifted_60; + assign mask_addr_shifted_60 = _myaxi_read_global_addr >> 2; + wire [32-1:0] mask_addr_masked_61; + assign mask_addr_masked_61 = mask_addr_shifted_60 << 2; + reg _myaxi_raddr_cond_0_1; reg [32-1:0] _myaxi_read_data_fsm; localparam _myaxi_read_data_fsm_init = 0; reg [32-1:0] write_burst_fsm_0; localparam write_burst_fsm_0_init = 0; - reg [10-1:0] write_burst_addr_32; - reg [10-1:0] write_burst_stride_33; - reg [33-1:0] write_burst_length_34; - reg write_burst_done_35; - assign ram_a_0_wdata = ((write_burst_fsm_0 == 1) && myaxi_rvalid)? myaxi_rdata : 'hx; - assign ram_a_0_wenable = ((write_burst_fsm_0 == 1) && myaxi_rvalid)? 1'd1 : 0; + reg [10-1:0] write_burst_addr_62; + reg [10-1:0] write_burst_stride_63; + reg [33-1:0] write_burst_length_64; + reg write_burst_done_65; + assign ram_a_0_wdata = ((write_burst_fsm_0 == 1) && _myaxi_rvalid_sb_0)? _myaxi_rdata_sb_0 : 'hx; + assign ram_a_0_wenable = ((write_burst_fsm_0 == 1) && _myaxi_rvalid_sb_0)? 1'd1 : 0; reg signed [32-1:0] _th_matmul_b_addr_12; reg signed [32-1:0] _th_matmul_j_13; - wire [32-1:0] mask_addr_shifted_36; - assign mask_addr_shifted_36 = _th_matmul_b_addr_12 >> 2; - wire [32-1:0] mask_addr_masked_37; - assign mask_addr_masked_37 = mask_addr_shifted_36 << 2; + wire [32-1:0] mask_addr_shifted_66; + assign mask_addr_shifted_66 = _th_matmul_b_addr_12 >> 2; + wire [32-1:0] mask_addr_masked_67; + assign mask_addr_masked_67 = mask_addr_shifted_66 << 2; reg [32-1:0] write_burst_fsm_1; localparam write_burst_fsm_1_init = 0; - reg [10-1:0] write_burst_addr_38; - reg [10-1:0] write_burst_stride_39; - reg [33-1:0] write_burst_length_40; - reg write_burst_done_41; - assign ram_b_0_wdata = ((write_burst_fsm_1 == 1) && myaxi_rvalid)? myaxi_rdata : 'hx; - assign ram_b_0_wenable = ((write_burst_fsm_1 == 1) && myaxi_rvalid)? 1'd1 : 0; + reg [10-1:0] write_burst_addr_68; + reg [10-1:0] write_burst_stride_69; + reg [33-1:0] write_burst_length_70; + reg write_burst_done_71; + assign ram_b_0_wdata = ((write_burst_fsm_1 == 1) && _myaxi_rvalid_sb_0)? _myaxi_rdata_sb_0 : 'hx; + assign ram_b_0_wenable = ((write_burst_fsm_1 == 1) && _myaxi_rvalid_sb_0)? 1'd1 : 0; reg signed [32-1:0] _th_matmul_sum_14; reg signed [32-1:0] _th_matmul_k_15; assign ram_a_0_addr = (th_matmul == 16)? _th_matmul_k_15 : - ((write_burst_fsm_0 == 1) && myaxi_rvalid)? write_burst_addr_32 : 'hx; + ((write_burst_fsm_0 == 1) && _myaxi_rvalid_sb_0)? write_burst_addr_62 : 'hx; assign ram_a_0_enable = (th_matmul == 16)? 1'd1 : - ((write_burst_fsm_0 == 1) && myaxi_rvalid)? 1'd1 : 0; - localparam _tmp_42 = 1; - wire [_tmp_42-1:0] _tmp_43; - assign _tmp_43 = th_matmul == 16; - reg [_tmp_42-1:0] __tmp_43_1; - reg signed [32-1:0] read_rdata_44; + ((write_burst_fsm_0 == 1) && _myaxi_rvalid_sb_0)? 1'd1 : 0; + localparam _tmp_72 = 1; + wire [_tmp_72-1:0] _tmp_73; + assign _tmp_73 = th_matmul == 16; + reg [_tmp_72-1:0] __tmp_73_1; + reg signed [32-1:0] read_rdata_74; reg signed [32-1:0] _th_matmul_x_16; assign ram_b_0_addr = (th_matmul == 18)? _th_matmul_k_15 : - ((write_burst_fsm_1 == 1) && myaxi_rvalid)? write_burst_addr_38 : 'hx; + ((write_burst_fsm_1 == 1) && _myaxi_rvalid_sb_0)? write_burst_addr_68 : 'hx; assign ram_b_0_enable = (th_matmul == 18)? 1'd1 : - ((write_burst_fsm_1 == 1) && myaxi_rvalid)? 1'd1 : 0; - localparam _tmp_45 = 1; - wire [_tmp_45-1:0] _tmp_46; - assign _tmp_46 = th_matmul == 18; - reg [_tmp_45-1:0] __tmp_46_1; - reg signed [32-1:0] read_rdata_47; + ((write_burst_fsm_1 == 1) && _myaxi_rvalid_sb_0)? 1'd1 : 0; + localparam _tmp_75 = 1; + wire [_tmp_75-1:0] _tmp_76; + assign _tmp_76 = th_matmul == 18; + reg [_tmp_75-1:0] __tmp_76_1; + reg signed [32-1:0] read_rdata_77; reg signed [32-1:0] _th_matmul_y_17; - wire [32-1:0] mask_addr_shifted_48; - assign mask_addr_shifted_48 = _th_matmul_c_addr_10 >> 2; - wire [32-1:0] mask_addr_masked_49; - assign mask_addr_masked_49 = mask_addr_shifted_48 << 2; + wire [32-1:0] mask_addr_shifted_78; + assign mask_addr_shifted_78 = _th_matmul_c_addr_10 >> 2; + wire [32-1:0] mask_addr_masked_79; + assign mask_addr_masked_79 = mask_addr_shifted_78 << 2; reg [32-1:0] _myaxi_write_req_fsm; localparam _myaxi_write_req_fsm_init = 0; reg [33-1:0] _myaxi_write_cur_global_size; reg _myaxi_write_cont; - wire [8-1:0] pack_write_req_op_sel_50; - wire [32-1:0] pack_write_req_local_addr_51; - wire [32-1:0] pack_write_req_local_stride_52; - wire [33-1:0] pack_write_req_size_53; - wire [32-1:0] pack_write_req_local_blocksize_54; - assign pack_write_req_op_sel_50 = _myaxi_write_op_sel; - assign pack_write_req_local_addr_51 = _myaxi_write_local_addr; - assign pack_write_req_local_stride_52 = _myaxi_write_local_stride; - assign pack_write_req_size_53 = _myaxi_write_local_size; - assign pack_write_req_local_blocksize_54 = _myaxi_write_local_blocksize; - wire [137-1:0] pack_write_req_packed_55; - assign pack_write_req_packed_55 = { pack_write_req_op_sel_50, pack_write_req_local_addr_51, pack_write_req_local_stride_52, pack_write_req_size_53, pack_write_req_local_blocksize_54 }; - localparam _tmp_56 = 1; - wire [_tmp_56-1:0] _tmp_57; - assign _tmp_57 = !_myaxi_write_req_fifo_almost_full; - reg [_tmp_56-1:0] __tmp_57_1; - wire [32-1:0] mask_addr_shifted_58; - assign mask_addr_shifted_58 = _myaxi_write_global_addr >> 2; - wire [32-1:0] mask_addr_masked_59; - assign mask_addr_masked_59 = mask_addr_shifted_58 << 2; - wire [32-1:0] mask_addr_shifted_60; - assign mask_addr_shifted_60 = _myaxi_write_global_addr >> 2; - wire [32-1:0] mask_addr_masked_61; - assign mask_addr_masked_61 = mask_addr_shifted_60 << 2; - wire [32-1:0] mask_addr_shifted_62; - assign mask_addr_shifted_62 = _myaxi_write_global_addr >> 2; - wire [32-1:0] mask_addr_masked_63; - assign mask_addr_masked_63 = mask_addr_shifted_62 << 2; - wire [32-1:0] mask_addr_shifted_64; - assign mask_addr_shifted_64 = _myaxi_write_global_addr >> 2; - wire [32-1:0] mask_addr_masked_65; - assign mask_addr_masked_65 = mask_addr_shifted_64 << 2; - wire [32-1:0] mask_addr_shifted_66; - assign mask_addr_shifted_66 = _myaxi_write_global_addr >> 2; - wire [32-1:0] mask_addr_masked_67; - assign mask_addr_masked_67 = mask_addr_shifted_66 << 2; - wire [32-1:0] mask_addr_shifted_68; - assign mask_addr_shifted_68 = _myaxi_write_global_addr >> 2; - wire [32-1:0] mask_addr_masked_69; - assign mask_addr_masked_69 = mask_addr_shifted_68 << 2; - wire [8-1:0] pack_write_req_op_sel_70; - wire [32-1:0] pack_write_req_local_addr_71; - wire [32-1:0] pack_write_req_local_stride_72; - wire [33-1:0] pack_write_req_size_73; - wire [32-1:0] pack_write_req_local_blocksize_74; - assign pack_write_req_op_sel_70 = _myaxi_write_op_sel; - assign pack_write_req_local_addr_71 = _myaxi_write_local_addr; - assign pack_write_req_local_stride_72 = _myaxi_write_local_stride; - assign pack_write_req_size_73 = _myaxi_write_cur_global_size; - assign pack_write_req_local_blocksize_74 = _myaxi_write_local_blocksize; - wire [137-1:0] pack_write_req_packed_75; - assign pack_write_req_packed_75 = { pack_write_req_op_sel_70, pack_write_req_local_addr_71, pack_write_req_local_stride_72, pack_write_req_size_73, pack_write_req_local_blocksize_74 }; - assign _myaxi_write_req_fifo_wdata = ((_myaxi_write_req_fsm == 1) && !_myaxi_write_req_fifo_almost_full && (myaxi_awready || !myaxi_awvalid) && (_myaxi_outstanding_wcount < 6))? pack_write_req_packed_75 : - ((_myaxi_write_req_fsm == 0) && _myaxi_write_start && !_myaxi_write_req_fifo_almost_full)? pack_write_req_packed_55 : 'hx; + wire [8-1:0] pack_write_req_op_sel_80; + wire [32-1:0] pack_write_req_local_addr_81; + wire [32-1:0] pack_write_req_local_stride_82; + wire [33-1:0] pack_write_req_size_83; + wire [32-1:0] pack_write_req_local_blocksize_84; + assign pack_write_req_op_sel_80 = _myaxi_write_op_sel; + assign pack_write_req_local_addr_81 = _myaxi_write_local_addr; + assign pack_write_req_local_stride_82 = _myaxi_write_local_stride; + assign pack_write_req_size_83 = _myaxi_write_local_size; + assign pack_write_req_local_blocksize_84 = _myaxi_write_local_blocksize; + wire [137-1:0] pack_write_req_packed_85; + assign pack_write_req_packed_85 = { pack_write_req_op_sel_80, pack_write_req_local_addr_81, pack_write_req_local_stride_82, pack_write_req_size_83, pack_write_req_local_blocksize_84 }; + localparam _tmp_86 = 1; + wire [_tmp_86-1:0] _tmp_87; + assign _tmp_87 = !_myaxi_write_req_fifo_almost_full; + reg [_tmp_86-1:0] __tmp_87_1; + wire [32-1:0] mask_addr_shifted_88; + assign mask_addr_shifted_88 = _myaxi_write_global_addr >> 2; + wire [32-1:0] mask_addr_masked_89; + assign mask_addr_masked_89 = mask_addr_shifted_88 << 2; + wire [32-1:0] mask_addr_shifted_90; + assign mask_addr_shifted_90 = _myaxi_write_global_addr >> 2; + wire [32-1:0] mask_addr_masked_91; + assign mask_addr_masked_91 = mask_addr_shifted_90 << 2; + wire [32-1:0] mask_addr_shifted_92; + assign mask_addr_shifted_92 = _myaxi_write_global_addr >> 2; + wire [32-1:0] mask_addr_masked_93; + assign mask_addr_masked_93 = mask_addr_shifted_92 << 2; + wire [32-1:0] mask_addr_shifted_94; + assign mask_addr_shifted_94 = _myaxi_write_global_addr >> 2; + wire [32-1:0] mask_addr_masked_95; + assign mask_addr_masked_95 = mask_addr_shifted_94 << 2; + wire [32-1:0] mask_addr_shifted_96; + assign mask_addr_shifted_96 = _myaxi_write_global_addr >> 2; + wire [32-1:0] mask_addr_masked_97; + assign mask_addr_masked_97 = mask_addr_shifted_96 << 2; + wire [32-1:0] mask_addr_shifted_98; + assign mask_addr_shifted_98 = _myaxi_write_global_addr >> 2; + wire [32-1:0] mask_addr_masked_99; + assign mask_addr_masked_99 = mask_addr_shifted_98 << 2; + wire [8-1:0] pack_write_req_op_sel_100; + wire [32-1:0] pack_write_req_local_addr_101; + wire [32-1:0] pack_write_req_local_stride_102; + wire [33-1:0] pack_write_req_size_103; + wire [32-1:0] pack_write_req_local_blocksize_104; + assign pack_write_req_op_sel_100 = _myaxi_write_op_sel; + assign pack_write_req_local_addr_101 = _myaxi_write_local_addr; + assign pack_write_req_local_stride_102 = _myaxi_write_local_stride; + assign pack_write_req_size_103 = _myaxi_write_cur_global_size; + assign pack_write_req_local_blocksize_104 = _myaxi_write_local_blocksize; + wire [137-1:0] pack_write_req_packed_105; + assign pack_write_req_packed_105 = { pack_write_req_op_sel_100, pack_write_req_local_addr_101, pack_write_req_local_stride_102, pack_write_req_size_103, pack_write_req_local_blocksize_104 }; + assign _myaxi_write_req_fifo_wdata = ((_myaxi_write_req_fsm == 1) && !_myaxi_write_req_fifo_almost_full && (myaxi_awready || !myaxi_awvalid) && (_myaxi_outstanding_wcount < 6))? pack_write_req_packed_105 : + ((_myaxi_write_req_fsm == 0) && _myaxi_write_start && !_myaxi_write_req_fifo_almost_full)? pack_write_req_packed_85 : 'hx; assign _myaxi_write_req_fifo_enq = ((_myaxi_write_req_fsm == 1) && !_myaxi_write_req_fifo_almost_full && (myaxi_awready || !myaxi_awvalid) && (_myaxi_outstanding_wcount < 6))? (_myaxi_write_req_fsm == 1) && !_myaxi_write_req_fifo_almost_full && (myaxi_awready || !myaxi_awvalid) && (_myaxi_outstanding_wcount < 6) && !_myaxi_write_req_fifo_almost_full : ((_myaxi_write_req_fsm == 0) && _myaxi_write_start && !_myaxi_write_req_fifo_almost_full)? (_myaxi_write_req_fsm == 0) && _myaxi_write_start && !_myaxi_write_req_fifo_almost_full && !_myaxi_write_req_fifo_almost_full : 0; - localparam _tmp_76 = 1; - wire [_tmp_76-1:0] _tmp_77; - assign _tmp_77 = !_myaxi_write_req_fifo_almost_full; - reg [_tmp_76-1:0] __tmp_77_1; - reg _myaxi_cond_1_1; + localparam _tmp_106 = 1; + wire [_tmp_106-1:0] _tmp_107; + assign _tmp_107 = !_myaxi_write_req_fifo_almost_full; + reg [_tmp_106-1:0] __tmp_107_1; + reg _myaxi_waddr_cond_0_1; reg [32-1:0] _myaxi_write_data_fsm; localparam _myaxi_write_data_fsm_init = 0; reg [32-1:0] read_burst_fsm_2; localparam read_burst_fsm_2_init = 0; - reg [10-1:0] read_burst_addr_78; - reg [10-1:0] read_burst_stride_79; - reg [33-1:0] read_burst_length_80; - reg read_burst_rvalid_81; - reg read_burst_rlast_82; - localparam _tmp_83 = 1; - wire [_tmp_83-1:0] _tmp_84; - assign _tmp_84 = (read_burst_fsm_2 == 1) && (!read_burst_rvalid_81 || (myaxi_wready || !myaxi_wvalid) && (_myaxi_write_size_buf > 0)); - reg [_tmp_83-1:0] __tmp_84_1; - wire [32-1:0] read_burst_rdata_85; - assign read_burst_rdata_85 = ram_c_0_rdata; + reg [10-1:0] read_burst_addr_108; + reg [10-1:0] read_burst_stride_109; + reg [33-1:0] read_burst_length_110; + reg read_burst_rvalid_111; + reg read_burst_rlast_112; + localparam _tmp_113 = 1; + wire [_tmp_113-1:0] _tmp_114; + assign _tmp_114 = (read_burst_fsm_2 == 1) && (!read_burst_rvalid_111 || (_myaxi_wready_sb_0 || !_myaxi_wvalid_sb_0) && (_myaxi_write_size_buf > 0)); + reg [_tmp_113-1:0] __tmp_114_1; + wire [32-1:0] read_burst_rdata_115; + assign read_burst_rdata_115 = ram_c_0_rdata; assign _myaxi_write_req_fifo_deq = ((_myaxi_write_data_fsm == 2) && (!_myaxi_write_req_fifo_empty && (_myaxi_write_size_buf == 0)) && !_myaxi_write_req_fifo_empty)? 1 : ((_myaxi_write_data_fsm == 0) && (!_myaxi_write_data_busy && !_myaxi_write_req_fifo_empty && (_myaxi_write_op_sel_fifo == 1)) && !_myaxi_write_req_fifo_empty)? 1 : 0; - reg _myaxi_cond_2_1; + reg _myaxi_wdata_cond_0_1; reg signed [32-1:0] _th_matmul_end_time_18; reg signed [32-1:0] _th_matmul_time_19; reg signed [32-1:0] _th_matmul_matrix_size_20; @@ -1391,38 +1461,38 @@ reg signed [32-1:0] _th_matmul_all_ok_24; reg signed [32-1:0] _th_matmul_c_addr_25; reg signed [32-1:0] _th_matmul_i_26; - wire [32-1:0] mask_addr_shifted_86; - assign mask_addr_shifted_86 = _th_matmul_c_addr_25 >> 2; - wire [32-1:0] mask_addr_masked_87; - assign mask_addr_masked_87 = mask_addr_shifted_86 << 2; + wire [32-1:0] mask_addr_shifted_116; + assign mask_addr_shifted_116 = _th_matmul_c_addr_25 >> 2; + wire [32-1:0] mask_addr_masked_117; + assign mask_addr_masked_117 = mask_addr_shifted_116 << 2; assign _myaxi_read_req_fifo_deq = ((_myaxi_read_data_fsm == 0) && (!_myaxi_read_data_busy && !_myaxi_read_req_fifo_empty && (_myaxi_read_op_sel_fifo == 3)) && !_myaxi_read_req_fifo_empty)? 1 : ((_myaxi_read_data_fsm == 0) && (!_myaxi_read_data_busy && !_myaxi_read_req_fifo_empty && (_myaxi_read_op_sel_fifo == 2)) && !_myaxi_read_req_fifo_empty)? 1 : ((_myaxi_read_data_fsm == 0) && (!_myaxi_read_data_busy && !_myaxi_read_req_fifo_empty && (_myaxi_read_op_sel_fifo == 1)) && !_myaxi_read_req_fifo_empty)? 1 : 0; reg [32-1:0] write_burst_fsm_3; localparam write_burst_fsm_3_init = 0; - reg [10-1:0] write_burst_addr_88; - reg [10-1:0] write_burst_stride_89; - reg [33-1:0] write_burst_length_90; - reg write_burst_done_91; - assign ram_c_0_wdata = ((write_burst_fsm_3 == 1) && myaxi_rvalid)? myaxi_rdata : + reg [10-1:0] write_burst_addr_118; + reg [10-1:0] write_burst_stride_119; + reg [33-1:0] write_burst_length_120; + reg write_burst_done_121; + assign ram_c_0_wdata = ((write_burst_fsm_3 == 1) && _myaxi_rvalid_sb_0)? _myaxi_rdata_sb_0 : (th_matmul == 22)? _th_matmul_sum_14 : 'hx; - assign ram_c_0_wenable = ((write_burst_fsm_3 == 1) && myaxi_rvalid)? 1'd1 : + assign ram_c_0_wenable = ((write_burst_fsm_3 == 1) && _myaxi_rvalid_sb_0)? 1'd1 : (th_matmul == 22)? 1'd1 : 0; - assign myaxi_rready = (_myaxi_read_data_fsm == 2) || (_myaxi_read_data_fsm == 2) || (_myaxi_read_data_fsm == 2); + assign _myaxi_rready_sb_0 = (_myaxi_read_data_fsm == 2) || (_myaxi_read_data_fsm == 2) || (_myaxi_read_data_fsm == 2); reg signed [32-1:0] _th_matmul_j_27; assign ram_c_0_addr = (th_matmul == 42)? _th_matmul_j_27 : - ((write_burst_fsm_3 == 1) && myaxi_rvalid)? write_burst_addr_88 : - ((read_burst_fsm_2 == 1) && (!read_burst_rvalid_81 || (myaxi_wready || !myaxi_wvalid) && (_myaxi_write_size_buf > 0)))? read_burst_addr_78 : + ((write_burst_fsm_3 == 1) && _myaxi_rvalid_sb_0)? write_burst_addr_118 : + ((read_burst_fsm_2 == 1) && (!read_burst_rvalid_111 || (_myaxi_wready_sb_0 || !_myaxi_wvalid_sb_0) && (_myaxi_write_size_buf > 0)))? read_burst_addr_108 : (th_matmul == 22)? _th_matmul_j_13 : 'hx; assign ram_c_0_enable = (th_matmul == 42)? 1'd1 : - ((write_burst_fsm_3 == 1) && myaxi_rvalid)? 1'd1 : - ((read_burst_fsm_2 == 1) && (!read_burst_rvalid_81 || (myaxi_wready || !myaxi_wvalid) && (_myaxi_write_size_buf > 0)))? 1'd1 : + ((write_burst_fsm_3 == 1) && _myaxi_rvalid_sb_0)? 1'd1 : + ((read_burst_fsm_2 == 1) && (!read_burst_rvalid_111 || (_myaxi_wready_sb_0 || !_myaxi_wvalid_sb_0) && (_myaxi_write_size_buf > 0)))? 1'd1 : (th_matmul == 22)? 1'd1 : 0; - localparam _tmp_92 = 1; - wire [_tmp_92-1:0] _tmp_93; - assign _tmp_93 = th_matmul == 42; - reg [_tmp_92-1:0] __tmp_93_1; - reg signed [32-1:0] read_rdata_94; + localparam _tmp_122 = 1; + wire [_tmp_122-1:0] _tmp_123; + assign _tmp_123 = th_matmul == 42; + reg [_tmp_122-1:0] __tmp_123_1; + reg signed [32-1:0] read_rdata_124; reg signed [32-1:0] _th_matmul_v_28; always @(posedge CLK) begin @@ -1436,29 +1506,149 @@ always @(posedge CLK) begin if(RST) begin - __tmp_43_1 <= 0; + __tmp_73_1 <= 0; + end else begin + __tmp_73_1 <= _tmp_73; + end + end + + + always @(posedge CLK) begin + if(RST) begin + __tmp_76_1 <= 0; end else begin - __tmp_43_1 <= _tmp_43; + __tmp_76_1 <= _tmp_76; end end always @(posedge CLK) begin if(RST) begin - __tmp_46_1 <= 0; + __tmp_114_1 <= 0; + __tmp_123_1 <= 0; end else begin - __tmp_46_1 <= _tmp_46; + __tmp_114_1 <= _tmp_114; + __tmp_123_1 <= _tmp_123; end end always @(posedge CLK) begin if(RST) begin - __tmp_84_1 <= 0; - __tmp_93_1 <= 0; + myaxi_awaddr <= 0; + myaxi_awlen <= 0; + myaxi_awvalid <= 0; + _myaxi_waddr_cond_0_1 <= 0; end else begin - __tmp_84_1 <= _tmp_84; - __tmp_93_1 <= _tmp_93; + if(_myaxi_waddr_cond_0_1) begin + myaxi_awvalid <= 0; + end + if((_myaxi_write_req_fsm == 1) && !_myaxi_write_req_fifo_almost_full && (_myaxi_outstanding_wcount < 6) && ((_myaxi_outstanding_wcount < 6) && (myaxi_awready || !myaxi_awvalid))) begin + myaxi_awaddr <= _myaxi_write_global_addr; + myaxi_awlen <= _myaxi_write_cur_global_size - 1; + myaxi_awvalid <= 1; + end + if((_myaxi_write_req_fsm == 1) && !_myaxi_write_req_fifo_almost_full && (_myaxi_outstanding_wcount < 6) && ((_myaxi_outstanding_wcount < 6) && (myaxi_awready || !myaxi_awvalid)) && (_myaxi_write_cur_global_size == 0)) begin + myaxi_awvalid <= 0; + end + _myaxi_waddr_cond_0_1 <= 1; + if(myaxi_awvalid && !myaxi_awready) begin + myaxi_awvalid <= myaxi_awvalid; + end + end + end + + + always @(posedge CLK) begin + if(RST) begin + _myaxi_wdata_sb_0 <= 0; + _myaxi_wvalid_sb_0 <= 0; + _myaxi_wlast_sb_0 <= 0; + _myaxi_wstrb_sb_0 <= 0; + _myaxi_wdata_cond_0_1 <= 0; + end else begin + if(_myaxi_wdata_cond_0_1) begin + _myaxi_wvalid_sb_0 <= 0; + _myaxi_wlast_sb_0 <= 0; + end + if((_myaxi_write_op_sel_buf == 1) && read_burst_rvalid_111 && ((_myaxi_wready_sb_0 || !_myaxi_wvalid_sb_0) && (_myaxi_write_size_buf > 0)) && (_myaxi_wready_sb_0 || !_myaxi_wvalid_sb_0)) begin + _myaxi_wdata_sb_0 <= read_burst_rdata_115; + _myaxi_wvalid_sb_0 <= 1; + _myaxi_wlast_sb_0 <= read_burst_rlast_112 || (_myaxi_write_size_buf == 1); + _myaxi_wstrb_sb_0 <= { 4{ 1'd1 } }; + end + _myaxi_wdata_cond_0_1 <= 1; + if(_myaxi_wvalid_sb_0 && !_myaxi_wready_sb_0) begin + _myaxi_wvalid_sb_0 <= _myaxi_wvalid_sb_0; + _myaxi_wlast_sb_0 <= _myaxi_wlast_sb_0; + end + end + end + + + always @(posedge CLK) begin + if(RST) begin + _sb_myaxi_writedata_data_6 <= 0; + _sb_myaxi_writedata_valid_7 <= 0; + _sb_myaxi_writedata_tmp_data_9 <= 0; + _sb_myaxi_writedata_tmp_valid_10 <= 0; + end else begin + if(_sb_myaxi_writedata_m_ready_5 || !_sb_myaxi_writedata_valid_7) begin + _sb_myaxi_writedata_data_6 <= _sb_myaxi_writedata_next_data_11; + _sb_myaxi_writedata_valid_7 <= _sb_myaxi_writedata_next_valid_12; + end + if(!_sb_myaxi_writedata_tmp_valid_10 && _sb_myaxi_writedata_valid_7 && !_sb_myaxi_writedata_m_ready_5) begin + _sb_myaxi_writedata_tmp_data_9 <= _sb_myaxi_writedata_s_data_3; + _sb_myaxi_writedata_tmp_valid_10 <= _sb_myaxi_writedata_s_valid_4; + end + if(_sb_myaxi_writedata_tmp_valid_10 && _sb_myaxi_writedata_m_ready_5) begin + _sb_myaxi_writedata_tmp_valid_10 <= 0; + end + end + end + + + always @(posedge CLK) begin + if(RST) begin + myaxi_araddr <= 0; + myaxi_arlen <= 0; + myaxi_arvalid <= 0; + _myaxi_raddr_cond_0_1 <= 0; + end else begin + if(_myaxi_raddr_cond_0_1) begin + myaxi_arvalid <= 0; + end + if((_myaxi_read_req_fsm == 1) && (myaxi_arready || !myaxi_arvalid)) begin + myaxi_araddr <= _myaxi_read_global_addr; + myaxi_arlen <= _myaxi_read_cur_global_size - 1; + myaxi_arvalid <= 1; + end + _myaxi_raddr_cond_0_1 <= 1; + if(myaxi_arvalid && !myaxi_arready) begin + myaxi_arvalid <= myaxi_arvalid; + end + end + end + + + always @(posedge CLK) begin + if(RST) begin + _sb_myaxi_readdata_data_21 <= 0; + _sb_myaxi_readdata_valid_22 <= 0; + _sb_myaxi_readdata_tmp_data_24 <= 0; + _sb_myaxi_readdata_tmp_valid_25 <= 0; + end else begin + if(_sb_myaxi_readdata_m_ready_20 || !_sb_myaxi_readdata_valid_22) begin + _sb_myaxi_readdata_data_21 <= _sb_myaxi_readdata_next_data_26; + _sb_myaxi_readdata_valid_22 <= _sb_myaxi_readdata_next_valid_27; + end + if(!_sb_myaxi_readdata_tmp_valid_25 && _sb_myaxi_readdata_valid_22 && !_sb_myaxi_readdata_m_ready_20) begin + _sb_myaxi_readdata_tmp_data_24 <= _sb_myaxi_readdata_s_data_18; + _sb_myaxi_readdata_tmp_valid_25 <= _sb_myaxi_readdata_s_valid_19; + end + if(_sb_myaxi_readdata_tmp_valid_25 && _sb_myaxi_readdata_m_ready_20) begin + _sb_myaxi_readdata_tmp_valid_25 <= 0; + end end end @@ -1477,10 +1667,6 @@ _myaxi_read_local_blocksize <= 0; _myaxi_read_req_busy <= 0; _myaxi_read_cur_global_size <= 0; - myaxi_araddr <= 0; - myaxi_arlen <= 0; - myaxi_arvalid <= 0; - _myaxi_cond_0_1 <= 0; _myaxi_read_data_busy <= 0; _myaxi_read_op_sel_buf <= 0; _myaxi_read_local_addr_buf <= 0; @@ -1496,32 +1682,13 @@ _myaxi_write_local_blocksize <= 0; _myaxi_write_req_busy <= 0; _myaxi_write_cur_global_size <= 0; - myaxi_awaddr <= 0; - myaxi_awlen <= 0; - myaxi_awvalid <= 0; - _myaxi_cond_1_1 <= 0; _myaxi_write_data_busy <= 0; _myaxi_write_op_sel_buf <= 0; _myaxi_write_local_addr_buf <= 0; _myaxi_write_local_stride_buf <= 0; _myaxi_write_size_buf <= 0; _myaxi_write_local_blocksize_buf <= 0; - myaxi_wdata <= 0; - myaxi_wvalid <= 0; - myaxi_wlast <= 0; - myaxi_wstrb <= 0; - _myaxi_cond_2_1 <= 0; end else begin - if(_myaxi_cond_0_1) begin - myaxi_arvalid <= 0; - end - if(_myaxi_cond_1_1) begin - myaxi_awvalid <= 0; - end - if(_myaxi_cond_2_1) begin - myaxi_wvalid <= 0; - myaxi_wlast <= 0; - end if(myaxi_awvalid && myaxi_awready && !(myaxi_bvalid && myaxi_bready) && (_myaxi_outstanding_wcount < 7)) begin _myaxi_outstanding_wcount <= _myaxi_outstanding_wcount + 1; end @@ -1533,7 +1700,7 @@ if((th_matmul == 6) && _myaxi_read_req_idle) begin _myaxi_read_start <= 1; _myaxi_read_op_sel <= 1; - _myaxi_read_global_addr <= mask_addr_masked_11; + _myaxi_read_global_addr <= mask_addr_masked_41; _myaxi_read_global_size <= _th_matmul_matrix_size_5; _myaxi_read_local_addr <= 0; _myaxi_read_local_stride <= 1; @@ -1546,28 +1713,19 @@ if(_myaxi_read_start && _myaxi_read_req_fifo_almost_full) begin _myaxi_read_start <= 1; end - if((_myaxi_read_req_fsm == 0) && (_myaxi_read_start || _myaxi_read_cont) && !_myaxi_read_req_fifo_almost_full && (_myaxi_read_global_size <= 256) && ((mask_addr_masked_21 & 4095) + (_myaxi_read_global_size << 2) >= 4096)) begin - _myaxi_read_cur_global_size <= 4096 - (mask_addr_masked_23 & 4095) >> 2; - _myaxi_read_global_size <= _myaxi_read_global_size - (4096 - (mask_addr_masked_25 & 4095) >> 2); + if((_myaxi_read_req_fsm == 0) && (_myaxi_read_start || _myaxi_read_cont) && !_myaxi_read_req_fifo_almost_full && (_myaxi_read_global_size <= 256) && ((mask_addr_masked_51 & 4095) + (_myaxi_read_global_size << 2) >= 4096)) begin + _myaxi_read_cur_global_size <= 4096 - (mask_addr_masked_53 & 4095) >> 2; + _myaxi_read_global_size <= _myaxi_read_global_size - (4096 - (mask_addr_masked_55 & 4095) >> 2); end else if((_myaxi_read_req_fsm == 0) && (_myaxi_read_start || _myaxi_read_cont) && !_myaxi_read_req_fifo_almost_full && (_myaxi_read_global_size <= 256)) begin _myaxi_read_cur_global_size <= _myaxi_read_global_size; _myaxi_read_global_size <= 0; - end else if((_myaxi_read_req_fsm == 0) && (_myaxi_read_start || _myaxi_read_cont) && !_myaxi_read_req_fifo_almost_full && ((mask_addr_masked_27 & 4095) + 1024 >= 4096)) begin - _myaxi_read_cur_global_size <= 4096 - (mask_addr_masked_29 & 4095) >> 2; - _myaxi_read_global_size <= _myaxi_read_global_size - (4096 - (mask_addr_masked_31 & 4095) >> 2); + end else if((_myaxi_read_req_fsm == 0) && (_myaxi_read_start || _myaxi_read_cont) && !_myaxi_read_req_fifo_almost_full && ((mask_addr_masked_57 & 4095) + 1024 >= 4096)) begin + _myaxi_read_cur_global_size <= 4096 - (mask_addr_masked_59 & 4095) >> 2; + _myaxi_read_global_size <= _myaxi_read_global_size - (4096 - (mask_addr_masked_61 & 4095) >> 2); end else if((_myaxi_read_req_fsm == 0) && (_myaxi_read_start || _myaxi_read_cont) && !_myaxi_read_req_fifo_almost_full) begin _myaxi_read_cur_global_size <= 256; _myaxi_read_global_size <= _myaxi_read_global_size - 256; end - if((_myaxi_read_req_fsm == 1) && (myaxi_arready || !myaxi_arvalid)) begin - myaxi_araddr <= _myaxi_read_global_addr; - myaxi_arlen <= _myaxi_read_cur_global_size - 1; - myaxi_arvalid <= 1; - end - _myaxi_cond_0_1 <= 1; - if(myaxi_arvalid && !myaxi_arready) begin - myaxi_arvalid <= myaxi_arvalid; - end if((_myaxi_read_req_fsm == 1) && (myaxi_arready || !myaxi_arvalid)) begin _myaxi_read_global_addr <= _myaxi_read_global_addr + (_myaxi_read_cur_global_size << 2); end @@ -1582,16 +1740,16 @@ _myaxi_read_local_size_buf <= _myaxi_read_local_size_fifo; _myaxi_read_local_blocksize_buf <= _myaxi_read_local_blocksize_fifo; end - if((_myaxi_read_data_fsm == 2) && myaxi_rvalid) begin + if((_myaxi_read_data_fsm == 2) && _myaxi_rvalid_sb_0) begin _myaxi_read_local_size_buf <= _myaxi_read_local_size_buf - 1; end - if((_myaxi_read_data_fsm == 2) && myaxi_rvalid && (_myaxi_read_local_size_buf <= 1)) begin + if((_myaxi_read_data_fsm == 2) && _myaxi_rvalid_sb_0 && (_myaxi_read_local_size_buf <= 1)) begin _myaxi_read_data_busy <= 0; end if((th_matmul == 11) && _myaxi_read_req_idle) begin _myaxi_read_start <= 1; _myaxi_read_op_sel <= 2; - _myaxi_read_global_addr <= mask_addr_masked_37; + _myaxi_read_global_addr <= mask_addr_masked_67; _myaxi_read_global_size <= _th_matmul_matrix_size_5; _myaxi_read_local_addr <= 0; _myaxi_read_local_stride <= 1; @@ -1606,16 +1764,16 @@ _myaxi_read_local_size_buf <= _myaxi_read_local_size_fifo; _myaxi_read_local_blocksize_buf <= _myaxi_read_local_blocksize_fifo; end - if((_myaxi_read_data_fsm == 2) && myaxi_rvalid) begin + if((_myaxi_read_data_fsm == 2) && _myaxi_rvalid_sb_0) begin _myaxi_read_local_size_buf <= _myaxi_read_local_size_buf - 1; end - if((_myaxi_read_data_fsm == 2) && myaxi_rvalid && (_myaxi_read_local_size_buf <= 1)) begin + if((_myaxi_read_data_fsm == 2) && _myaxi_rvalid_sb_0 && (_myaxi_read_local_size_buf <= 1)) begin _myaxi_read_data_busy <= 0; end if((th_matmul == 25) && _myaxi_write_req_idle) begin _myaxi_write_start <= 1; _myaxi_write_op_sel <= 1; - _myaxi_write_global_addr <= mask_addr_masked_49; + _myaxi_write_global_addr <= mask_addr_masked_79; _myaxi_write_global_size <= _th_matmul_matrix_size_5; _myaxi_write_local_addr <= 0; _myaxi_write_local_stride <= 1; @@ -1628,31 +1786,19 @@ if(_myaxi_write_start && _myaxi_write_req_fifo_almost_full) begin _myaxi_write_start <= 1; end - if((_myaxi_write_req_fsm == 0) && (_myaxi_write_start || _myaxi_write_cont) && !_myaxi_write_req_fifo_almost_full && (_myaxi_write_global_size <= 256) && ((mask_addr_masked_59 & 4095) + (_myaxi_write_global_size << 2) >= 4096)) begin - _myaxi_write_cur_global_size <= 4096 - (mask_addr_masked_61 & 4095) >> 2; - _myaxi_write_global_size <= _myaxi_write_global_size - (4096 - (mask_addr_masked_63 & 4095) >> 2); + if((_myaxi_write_req_fsm == 0) && (_myaxi_write_start || _myaxi_write_cont) && !_myaxi_write_req_fifo_almost_full && (_myaxi_write_global_size <= 256) && ((mask_addr_masked_89 & 4095) + (_myaxi_write_global_size << 2) >= 4096)) begin + _myaxi_write_cur_global_size <= 4096 - (mask_addr_masked_91 & 4095) >> 2; + _myaxi_write_global_size <= _myaxi_write_global_size - (4096 - (mask_addr_masked_93 & 4095) >> 2); end else if((_myaxi_write_req_fsm == 0) && (_myaxi_write_start || _myaxi_write_cont) && !_myaxi_write_req_fifo_almost_full && (_myaxi_write_global_size <= 256)) begin _myaxi_write_cur_global_size <= _myaxi_write_global_size; _myaxi_write_global_size <= 0; - end else if((_myaxi_write_req_fsm == 0) && (_myaxi_write_start || _myaxi_write_cont) && !_myaxi_write_req_fifo_almost_full && ((mask_addr_masked_65 & 4095) + 1024 >= 4096)) begin - _myaxi_write_cur_global_size <= 4096 - (mask_addr_masked_67 & 4095) >> 2; - _myaxi_write_global_size <= _myaxi_write_global_size - (4096 - (mask_addr_masked_69 & 4095) >> 2); + end else if((_myaxi_write_req_fsm == 0) && (_myaxi_write_start || _myaxi_write_cont) && !_myaxi_write_req_fifo_almost_full && ((mask_addr_masked_95 & 4095) + 1024 >= 4096)) begin + _myaxi_write_cur_global_size <= 4096 - (mask_addr_masked_97 & 4095) >> 2; + _myaxi_write_global_size <= _myaxi_write_global_size - (4096 - (mask_addr_masked_99 & 4095) >> 2); end else if((_myaxi_write_req_fsm == 0) && (_myaxi_write_start || _myaxi_write_cont) && !_myaxi_write_req_fifo_almost_full) begin _myaxi_write_cur_global_size <= 256; _myaxi_write_global_size <= _myaxi_write_global_size - 256; end - if((_myaxi_write_req_fsm == 1) && !_myaxi_write_req_fifo_almost_full && (_myaxi_outstanding_wcount < 6) && ((_myaxi_outstanding_wcount < 6) && (myaxi_awready || !myaxi_awvalid))) begin - myaxi_awaddr <= _myaxi_write_global_addr; - myaxi_awlen <= _myaxi_write_cur_global_size - 1; - myaxi_awvalid <= 1; - end - if((_myaxi_write_req_fsm == 1) && !_myaxi_write_req_fifo_almost_full && (_myaxi_outstanding_wcount < 6) && ((_myaxi_outstanding_wcount < 6) && (myaxi_awready || !myaxi_awvalid)) && (_myaxi_write_cur_global_size == 0)) begin - myaxi_awvalid <= 0; - end - _myaxi_cond_1_1 <= 1; - if(myaxi_awvalid && !myaxi_awready) begin - myaxi_awvalid <= myaxi_awvalid; - end if((_myaxi_write_req_fsm == 1) && ((_myaxi_write_req_fsm == 1) && !_myaxi_write_req_fifo_almost_full && (myaxi_awready || !myaxi_awvalid) && (_myaxi_outstanding_wcount < 6))) begin _myaxi_write_global_addr <= _myaxi_write_global_addr + (_myaxi_write_cur_global_size << 2); end @@ -1673,27 +1819,16 @@ if((_myaxi_write_data_fsm == 2) && (!_myaxi_write_req_fifo_empty && (_myaxi_write_size_buf == 0))) begin _myaxi_write_size_buf <= _myaxi_write_size_fifo; end - if((_myaxi_write_op_sel_buf == 1) && read_burst_rvalid_81 && ((myaxi_wready || !myaxi_wvalid) && (_myaxi_write_size_buf > 0)) && (myaxi_wready || !myaxi_wvalid)) begin - myaxi_wdata <= read_burst_rdata_85; - myaxi_wvalid <= 1; - myaxi_wlast <= read_burst_rlast_82 || (_myaxi_write_size_buf == 1); - myaxi_wstrb <= { 4{ 1'd1 } }; - end - _myaxi_cond_2_1 <= 1; - if(myaxi_wvalid && !myaxi_wready) begin - myaxi_wvalid <= myaxi_wvalid; - myaxi_wlast <= myaxi_wlast; - end - if((_myaxi_write_data_fsm == 2) && read_burst_rvalid_81 && ((myaxi_wready || !myaxi_wvalid) && (_myaxi_write_size_buf > 0))) begin + if((_myaxi_write_data_fsm == 2) && read_burst_rvalid_111 && ((_myaxi_wready_sb_0 || !_myaxi_wvalid_sb_0) && (_myaxi_write_size_buf > 0))) begin _myaxi_write_size_buf <= _myaxi_write_size_buf - 1; end - if((_myaxi_write_data_fsm == 2) && ((_myaxi_write_op_sel_buf == 1) && read_burst_rvalid_81 && ((myaxi_wready || !myaxi_wvalid) && (_myaxi_write_size_buf > 0))) && read_burst_rlast_82) begin + if((_myaxi_write_data_fsm == 2) && ((_myaxi_write_op_sel_buf == 1) && read_burst_rvalid_111 && ((_myaxi_wready_sb_0 || !_myaxi_wvalid_sb_0) && (_myaxi_write_size_buf > 0))) && read_burst_rlast_112) begin _myaxi_write_data_busy <= 0; end if((th_matmul == 38) && _myaxi_read_req_idle) begin _myaxi_read_start <= 1; _myaxi_read_op_sel <= 3; - _myaxi_read_global_addr <= mask_addr_masked_87; + _myaxi_read_global_addr <= mask_addr_masked_117; _myaxi_read_global_size <= _th_matmul_matrix_size_20; _myaxi_read_local_addr <= 0; _myaxi_read_local_stride <= 1; @@ -1708,10 +1843,10 @@ _myaxi_read_local_size_buf <= _myaxi_read_local_size_fifo; _myaxi_read_local_blocksize_buf <= _myaxi_read_local_blocksize_fifo; end - if((_myaxi_read_data_fsm == 2) && myaxi_rvalid) begin + if((_myaxi_read_data_fsm == 2) && _myaxi_rvalid_sb_0) begin _myaxi_read_local_size_buf <= _myaxi_read_local_size_buf - 1; end - if((_myaxi_read_data_fsm == 2) && myaxi_rvalid && (_myaxi_read_local_size_buf <= 1)) begin + if((_myaxi_read_data_fsm == 2) && _myaxi_rvalid_sb_0 && (_myaxi_read_local_size_buf <= 1)) begin _myaxi_read_data_busy <= 0; end end @@ -1721,7 +1856,7 @@ always @(posedge CLK) begin if(RST) begin count__myaxi_read_req_fifo <= 0; - __tmp_19_1 <= 0; + __tmp_49_1 <= 0; end else begin if(_myaxi_read_req_fifo_enq && !_myaxi_read_req_fifo_full && (_myaxi_read_req_fifo_deq && !_myaxi_read_req_fifo_empty)) begin count__myaxi_read_req_fifo <= count__myaxi_read_req_fifo; @@ -1730,7 +1865,7 @@ end else if(_myaxi_read_req_fifo_deq && !_myaxi_read_req_fifo_empty) begin count__myaxi_read_req_fifo <= count__myaxi_read_req_fifo - 1; end - __tmp_19_1 <= _tmp_19; + __tmp_49_1 <= _tmp_49; end end @@ -1738,8 +1873,8 @@ always @(posedge CLK) begin if(RST) begin count__myaxi_write_req_fifo <= 0; - __tmp_57_1 <= 0; - __tmp_77_1 <= 0; + __tmp_87_1 <= 0; + __tmp_107_1 <= 0; end else begin if(_myaxi_write_req_fifo_enq && !_myaxi_write_req_fifo_full && (_myaxi_write_req_fifo_deq && !_myaxi_write_req_fifo_empty)) begin count__myaxi_write_req_fifo <= count__myaxi_write_req_fifo; @@ -1748,8 +1883,8 @@ end else if(_myaxi_write_req_fifo_deq && !_myaxi_write_req_fifo_empty) begin count__myaxi_write_req_fifo <= count__myaxi_write_req_fifo - 1; end - __tmp_57_1 <= _tmp_57; - __tmp_77_1 <= _tmp_77; + __tmp_87_1 <= _tmp_87; + __tmp_107_1 <= _tmp_107; end end @@ -1831,9 +1966,9 @@ _th_matmul_j_13 <= 0; _th_matmul_sum_14 <= 0; _th_matmul_k_15 <= 0; - read_rdata_44 <= 0; + read_rdata_74 <= 0; _th_matmul_x_16 <= 0; - read_rdata_47 <= 0; + read_rdata_77 <= 0; _th_matmul_y_17 <= 0; _th_matmul_end_time_18 <= 0; _th_matmul_time_19 <= 0; @@ -1845,7 +1980,7 @@ _th_matmul_c_addr_25 <= 0; _th_matmul_i_26 <= 0; _th_matmul_j_27 <= 0; - read_rdata_94 <= 0; + read_rdata_124 <= 0; _th_matmul_v_28 <= 0; end else begin case(th_matmul) @@ -1934,27 +2069,27 @@ end end th_matmul_16: begin - if(__tmp_43_1) begin - read_rdata_44 <= ram_a_0_rdata; + if(__tmp_73_1) begin + read_rdata_74 <= ram_a_0_rdata; end - if(__tmp_43_1) begin + if(__tmp_73_1) begin th_matmul <= th_matmul_17; end end th_matmul_17: begin - _th_matmul_x_16 <= read_rdata_44; + _th_matmul_x_16 <= read_rdata_74; th_matmul <= th_matmul_18; end th_matmul_18: begin - if(__tmp_46_1) begin - read_rdata_47 <= ram_b_0_rdata; + if(__tmp_76_1) begin + read_rdata_77 <= ram_b_0_rdata; end - if(__tmp_46_1) begin + if(__tmp_76_1) begin th_matmul <= th_matmul_19; end end th_matmul_19: begin - _th_matmul_y_17 <= read_rdata_47; + _th_matmul_y_17 <= read_rdata_77; th_matmul <= th_matmul_20; end th_matmul_20: begin @@ -2058,15 +2193,15 @@ end end th_matmul_42: begin - if(__tmp_93_1) begin - read_rdata_94 <= ram_c_0_rdata; + if(__tmp_123_1) begin + read_rdata_124 <= ram_c_0_rdata; end - if(__tmp_93_1) begin + if(__tmp_123_1) begin th_matmul <= th_matmul_43; end end th_matmul_43: begin - _th_matmul_v_28 <= read_rdata_94; + _th_matmul_v_28 <= read_rdata_124; th_matmul <= th_matmul_44; end th_matmul_44: begin @@ -2190,13 +2325,13 @@ _myaxi_read_data_fsm <= _myaxi_read_data_fsm_2; end _myaxi_read_data_fsm_2: begin - if(myaxi_rvalid && (_myaxi_read_local_size_buf <= 1)) begin + if(_myaxi_rvalid_sb_0 && (_myaxi_read_local_size_buf <= 1)) begin _myaxi_read_data_fsm <= _myaxi_read_data_fsm_init; end - if(myaxi_rvalid && (_myaxi_read_local_size_buf <= 1)) begin + if(_myaxi_rvalid_sb_0 && (_myaxi_read_local_size_buf <= 1)) begin _myaxi_read_data_fsm <= _myaxi_read_data_fsm_init; end - if(myaxi_rvalid && (_myaxi_read_local_size_buf <= 1)) begin + if(_myaxi_rvalid_sb_0 && (_myaxi_read_local_size_buf <= 1)) begin _myaxi_read_data_fsm <= _myaxi_read_data_fsm_init; end end @@ -2209,37 +2344,37 @@ always @(posedge CLK) begin if(RST) begin write_burst_fsm_0 <= write_burst_fsm_0_init; - write_burst_addr_32 <= 0; - write_burst_stride_33 <= 0; - write_burst_length_34 <= 0; - write_burst_done_35 <= 0; + write_burst_addr_62 <= 0; + write_burst_stride_63 <= 0; + write_burst_length_64 <= 0; + write_burst_done_65 <= 0; end else begin case(write_burst_fsm_0) write_burst_fsm_0_init: begin - write_burst_addr_32 <= _myaxi_read_local_addr_buf; - write_burst_stride_33 <= _myaxi_read_local_stride_buf; - write_burst_length_34 <= _myaxi_read_local_size_buf; - write_burst_done_35 <= 0; + write_burst_addr_62 <= _myaxi_read_local_addr_buf; + write_burst_stride_63 <= _myaxi_read_local_stride_buf; + write_burst_length_64 <= _myaxi_read_local_size_buf; + write_burst_done_65 <= 0; if((_myaxi_read_data_fsm == 1) && (_myaxi_read_op_sel_buf == 1) && (_myaxi_read_local_size_buf > 0)) begin write_burst_fsm_0 <= write_burst_fsm_0_1; end end write_burst_fsm_0_1: begin - if(myaxi_rvalid) begin - write_burst_addr_32 <= write_burst_addr_32 + write_burst_stride_33; - write_burst_length_34 <= write_burst_length_34 - 1; - write_burst_done_35 <= 0; + if(_myaxi_rvalid_sb_0) begin + write_burst_addr_62 <= write_burst_addr_62 + write_burst_stride_63; + write_burst_length_64 <= write_burst_length_64 - 1; + write_burst_done_65 <= 0; end - if(myaxi_rvalid && (write_burst_length_34 <= 1)) begin - write_burst_done_35 <= 1; + if(_myaxi_rvalid_sb_0 && (write_burst_length_64 <= 1)) begin + write_burst_done_65 <= 1; end - if(myaxi_rvalid && 0) begin - write_burst_done_35 <= 1; + if(_myaxi_rvalid_sb_0 && 0) begin + write_burst_done_65 <= 1; end - if(myaxi_rvalid && (write_burst_length_34 <= 1)) begin + if(_myaxi_rvalid_sb_0 && (write_burst_length_64 <= 1)) begin write_burst_fsm_0 <= write_burst_fsm_0_init; end - if(myaxi_rvalid && 0) begin + if(_myaxi_rvalid_sb_0 && 0) begin write_burst_fsm_0 <= write_burst_fsm_0_init; end if(0) begin @@ -2255,37 +2390,37 @@ always @(posedge CLK) begin if(RST) begin write_burst_fsm_1 <= write_burst_fsm_1_init; - write_burst_addr_38 <= 0; - write_burst_stride_39 <= 0; - write_burst_length_40 <= 0; - write_burst_done_41 <= 0; + write_burst_addr_68 <= 0; + write_burst_stride_69 <= 0; + write_burst_length_70 <= 0; + write_burst_done_71 <= 0; end else begin case(write_burst_fsm_1) write_burst_fsm_1_init: begin - write_burst_addr_38 <= _myaxi_read_local_addr_buf; - write_burst_stride_39 <= _myaxi_read_local_stride_buf; - write_burst_length_40 <= _myaxi_read_local_size_buf; - write_burst_done_41 <= 0; + write_burst_addr_68 <= _myaxi_read_local_addr_buf; + write_burst_stride_69 <= _myaxi_read_local_stride_buf; + write_burst_length_70 <= _myaxi_read_local_size_buf; + write_burst_done_71 <= 0; if((_myaxi_read_data_fsm == 1) && (_myaxi_read_op_sel_buf == 2) && (_myaxi_read_local_size_buf > 0)) begin write_burst_fsm_1 <= write_burst_fsm_1_1; end end write_burst_fsm_1_1: begin - if(myaxi_rvalid) begin - write_burst_addr_38 <= write_burst_addr_38 + write_burst_stride_39; - write_burst_length_40 <= write_burst_length_40 - 1; - write_burst_done_41 <= 0; + if(_myaxi_rvalid_sb_0) begin + write_burst_addr_68 <= write_burst_addr_68 + write_burst_stride_69; + write_burst_length_70 <= write_burst_length_70 - 1; + write_burst_done_71 <= 0; end - if(myaxi_rvalid && (write_burst_length_40 <= 1)) begin - write_burst_done_41 <= 1; + if(_myaxi_rvalid_sb_0 && (write_burst_length_70 <= 1)) begin + write_burst_done_71 <= 1; end - if(myaxi_rvalid && 0) begin - write_burst_done_41 <= 1; + if(_myaxi_rvalid_sb_0 && 0) begin + write_burst_done_71 <= 1; end - if(myaxi_rvalid && (write_burst_length_40 <= 1)) begin + if(_myaxi_rvalid_sb_0 && (write_burst_length_70 <= 1)) begin write_burst_fsm_1 <= write_burst_fsm_1_init; end - if(myaxi_rvalid && 0) begin + if(_myaxi_rvalid_sb_0 && 0) begin write_burst_fsm_1 <= write_burst_fsm_1_init; end if(0) begin @@ -2341,7 +2476,7 @@ _myaxi_write_data_fsm <= _myaxi_write_data_fsm_2; end _myaxi_write_data_fsm_2: begin - if((_myaxi_write_op_sel_buf == 1) && read_burst_rvalid_81 && ((myaxi_wready || !myaxi_wvalid) && (_myaxi_write_size_buf > 0)) && read_burst_rlast_82) begin + if((_myaxi_write_op_sel_buf == 1) && read_burst_rvalid_111 && ((_myaxi_wready_sb_0 || !_myaxi_wvalid_sb_0) && (_myaxi_write_size_buf > 0)) && read_burst_rlast_112) begin _myaxi_write_data_fsm <= _myaxi_write_data_fsm_init; end end @@ -2354,41 +2489,41 @@ always @(posedge CLK) begin if(RST) begin read_burst_fsm_2 <= read_burst_fsm_2_init; - read_burst_addr_78 <= 0; - read_burst_stride_79 <= 0; - read_burst_length_80 <= 0; - read_burst_rvalid_81 <= 0; - read_burst_rlast_82 <= 0; + read_burst_addr_108 <= 0; + read_burst_stride_109 <= 0; + read_burst_length_110 <= 0; + read_burst_rvalid_111 <= 0; + read_burst_rlast_112 <= 0; end else begin case(read_burst_fsm_2) read_burst_fsm_2_init: begin - read_burst_addr_78 <= _myaxi_write_local_addr_buf; - read_burst_stride_79 <= _myaxi_write_local_stride_buf; - read_burst_length_80 <= _myaxi_write_size_buf; - read_burst_rvalid_81 <= 0; - read_burst_rlast_82 <= 0; + read_burst_addr_108 <= _myaxi_write_local_addr_buf; + read_burst_stride_109 <= _myaxi_write_local_stride_buf; + read_burst_length_110 <= _myaxi_write_size_buf; + read_burst_rvalid_111 <= 0; + read_burst_rlast_112 <= 0; if((_myaxi_write_data_fsm == 1) && (_myaxi_write_op_sel_buf == 1) && (_myaxi_write_size_buf > 0)) begin read_burst_fsm_2 <= read_burst_fsm_2_1; end end read_burst_fsm_2_1: begin - if((myaxi_wready || !myaxi_wvalid) && (_myaxi_write_size_buf > 0) && (read_burst_length_80 > 0)) begin - read_burst_addr_78 <= read_burst_addr_78 + read_burst_stride_79; - read_burst_length_80 <= read_burst_length_80 - 1; - read_burst_rvalid_81 <= 1; + if((_myaxi_wready_sb_0 || !_myaxi_wvalid_sb_0) && (_myaxi_write_size_buf > 0) && (read_burst_length_110 > 0)) begin + read_burst_addr_108 <= read_burst_addr_108 + read_burst_stride_109; + read_burst_length_110 <= read_burst_length_110 - 1; + read_burst_rvalid_111 <= 1; end - if((myaxi_wready || !myaxi_wvalid) && (_myaxi_write_size_buf > 0) && (read_burst_length_80 <= 1)) begin - read_burst_rlast_82 <= 1; + if((_myaxi_wready_sb_0 || !_myaxi_wvalid_sb_0) && (_myaxi_write_size_buf > 0) && (read_burst_length_110 <= 1)) begin + read_burst_rlast_112 <= 1; end - if(read_burst_rlast_82 && read_burst_rvalid_81 && ((myaxi_wready || !myaxi_wvalid) && (_myaxi_write_size_buf > 0))) begin - read_burst_rvalid_81 <= 0; - read_burst_rlast_82 <= 0; + if(read_burst_rlast_112 && read_burst_rvalid_111 && ((_myaxi_wready_sb_0 || !_myaxi_wvalid_sb_0) && (_myaxi_write_size_buf > 0))) begin + read_burst_rvalid_111 <= 0; + read_burst_rlast_112 <= 0; end if(0) begin - read_burst_rvalid_81 <= 0; - read_burst_rlast_82 <= 0; + read_burst_rvalid_111 <= 0; + read_burst_rlast_112 <= 0; end - if(read_burst_rlast_82 && read_burst_rvalid_81 && ((myaxi_wready || !myaxi_wvalid) && (_myaxi_write_size_buf > 0))) begin + if(read_burst_rlast_112 && read_burst_rvalid_111 && ((_myaxi_wready_sb_0 || !_myaxi_wvalid_sb_0) && (_myaxi_write_size_buf > 0))) begin read_burst_fsm_2 <= read_burst_fsm_2_init; end if(0) begin @@ -2404,37 +2539,37 @@ always @(posedge CLK) begin if(RST) begin write_burst_fsm_3 <= write_burst_fsm_3_init; - write_burst_addr_88 <= 0; - write_burst_stride_89 <= 0; - write_burst_length_90 <= 0; - write_burst_done_91 <= 0; + write_burst_addr_118 <= 0; + write_burst_stride_119 <= 0; + write_burst_length_120 <= 0; + write_burst_done_121 <= 0; end else begin case(write_burst_fsm_3) write_burst_fsm_3_init: begin - write_burst_addr_88 <= _myaxi_read_local_addr_buf; - write_burst_stride_89 <= _myaxi_read_local_stride_buf; - write_burst_length_90 <= _myaxi_read_local_size_buf; - write_burst_done_91 <= 0; + write_burst_addr_118 <= _myaxi_read_local_addr_buf; + write_burst_stride_119 <= _myaxi_read_local_stride_buf; + write_burst_length_120 <= _myaxi_read_local_size_buf; + write_burst_done_121 <= 0; if((_myaxi_read_data_fsm == 1) && (_myaxi_read_op_sel_buf == 3) && (_myaxi_read_local_size_buf > 0)) begin write_burst_fsm_3 <= write_burst_fsm_3_1; end end write_burst_fsm_3_1: begin - if(myaxi_rvalid) begin - write_burst_addr_88 <= write_burst_addr_88 + write_burst_stride_89; - write_burst_length_90 <= write_burst_length_90 - 1; - write_burst_done_91 <= 0; + if(_myaxi_rvalid_sb_0) begin + write_burst_addr_118 <= write_burst_addr_118 + write_burst_stride_119; + write_burst_length_120 <= write_burst_length_120 - 1; + write_burst_done_121 <= 0; end - if(myaxi_rvalid && (write_burst_length_90 <= 1)) begin - write_burst_done_91 <= 1; + if(_myaxi_rvalid_sb_0 && (write_burst_length_120 <= 1)) begin + write_burst_done_121 <= 1; end - if(myaxi_rvalid && 0) begin - write_burst_done_91 <= 1; + if(_myaxi_rvalid_sb_0 && 0) begin + write_burst_done_121 <= 1; end - if(myaxi_rvalid && (write_burst_length_90 <= 1)) begin + if(_myaxi_rvalid_sb_0 && (write_burst_length_120 <= 1)) begin write_burst_fsm_3 <= write_burst_fsm_3_init; end - if(myaxi_rvalid && 0) begin + if(_myaxi_rvalid_sb_0 && 0) begin write_burst_fsm_3 <= write_burst_fsm_3_init; end if(0) begin diff --git a/examples/sort/sort.py b/examples/sort/sort.py index 29d71de1..ec5221a5 100644 --- a/examples/sort/sort.py +++ b/examples/sort/sort.py @@ -8,21 +8,24 @@ from veriloggen import * -nclk = simulation.next_clock +nclk = simulation.next_clock + def mkSort(numports=4): m = Module('sort') width = m.Parameter('WIDTH', 32) clk = m.Input('CLK') rst = m.Input('RST') - inputs = [ m.Input('input_' + str(i), width) for i in range(numports) ] - outputs = [ m.Output('output_' + str(i), width) for i in range(numports) ] + inputs = [m.Input('input_' + str(i), width) for i in range(numports)] + outputs = [m.Output('output_' + str(i), width) for i in range(numports)] kick = m.Input('kick') busy = m.OutputReg('busy') - registers = [ m.Reg('registers_' + str(i), width) for i in range(numports) ] - for i in range(numports): m.Assign(outputs[i](registers[i])) - + registers = [m.Reg('registers_' + str(i), width) for i in range(numports)] + for i in range(numports): + m.Assign(outputs[i](registers[i])) + _i = [0] + def mk_pair(): s = m.Wire('small_' + str(_i[0]), width) l = m.Wire('large_' + str(_i[0]), width) @@ -31,19 +34,19 @@ def mk_pair(): def prim_net(a, b): s, l = mk_pair() - m.Assign(s( Cond(a < b, a, b) )) # small - m.Assign(l( Cond(a < b, b, a) )) # large + m.Assign(s(Cond(a < b, a, b))) # small + m.Assign(l(Cond(a < b, b, a))) # large return s, l def chain_net(regs, fsm, e): x = regs[0] for i in range(e): - s, l = prim_net(x, regs[i+1]) - fsm.add( regs[i](s) ) + s, l = prim_net(x, regs[i + 1]) + fsm.add(regs[i](s)) x = l - fsm.add( regs[e](x) ) + fsm.add(regs[e](x)) for i in range(e + 1, len(regs)): - fsm.add( regs[i](regs[i]) ) + fsm.add(regs[i](regs[i])) fsm.goto_next() # build up @@ -57,47 +60,48 @@ def chain_net(regs, fsm, e): # connect network for i in range(numports): - chain_net(registers, fsm, numports-i-1) + chain_net(registers, fsm, numports - i - 1) # finalize fsm.add(busy(0)) fsm.goto(idle) - fsm.make_always([ busy(0) ] + [ r(0) for r in registers ], + fsm.make_always([busy(0)] + [r(0) for r in registers], [Systask('display', r.name + ': %d', r) for r in registers]) - + return m + def mkSimSort(numports=4): m = Module('simsort') width = m.Parameter('WIDTH', 32) clk = m.Reg('CLK') rst = m.Reg('RST') - inputs = [ m.Reg('input_' + str(i), width) for i in range(numports) ] - outputs = [ m.Wire('output_' + str(i), width) for i in range(numports) ] + inputs = [m.Reg('input_' + str(i), width) for i in range(numports)] + outputs = [m.Wire('output_' + str(i), width) for i in range(numports)] kick = m.Reg('kick') busy = m.Wire('busy') uut = m.Instance(mkSort(numports), 'uut', (width,), [clk, rst] + inputs + outputs + [kick, busy]) - + vcd_name = os.path.splitext(os.path.basename(__file__))[0] + '.vcd' simulation.setup_waveform(m, uut, dumpfile=vcd_name) simulation.setup_clock(m, clk) simulation.setup_reset(m, rst) m.Initial( - [ ip(100 - i) for i, ip in enumerate(inputs) ], + [ip(100 - i) for i, ip in enumerate(inputs)], kick(0), - + Wait(rst), nclk(clk), - + Wait(Not(rst)), nclk(clk), nclk(clk), nclk(clk), - + kick(1), nclk(clk), kick(0), @@ -107,18 +111,19 @@ def mkSimSort(numports=4): Delay(100), Wait(kick), nclk(clk), - + Wait(busy), nclk(clk), - + Wait(Not(busy)), nclk(clk), - + Systask('finish'), ) return m + if __name__ == '__main__': sort = mkSimSort() verilog = sort.to_verilog('tmp.v') diff --git a/examples/sort/test_sort.py b/examples/sort/test_sort.py index 2bd2c3a9..091bc5a5 100644 --- a/examples/sort/test_sort.py +++ b/examples/sort/test_sort.py @@ -321,6 +321,7 @@ registers_3: 100 """ + def test(): veriloggen.reset() sort_module = sort.mkSimSort() diff --git a/examples/stream_axi_stream_fifo_ipxact_ultra96v2_pynq/test_stream_axi_stream_fifo_ipxact.py b/examples/stream_axi_stream_fifo_ipxact_ultra96v2_pynq/test_stream_axi_stream_fifo_ipxact.py index 272ea0f8..b56903a5 100644 --- a/examples/stream_axi_stream_fifo_ipxact_ultra96v2_pynq/test_stream_axi_stream_fifo_ipxact.py +++ b/examples/stream_axi_stream_fifo_ipxact_ultra96v2_pynq/test_stream_axi_stream_fifo_ipxact.py @@ -22,10 +22,10 @@ output [2-1:0] maxi_awuser, output reg maxi_awvalid, input maxi_awready, - output reg [32-1:0] maxi_wdata, - output reg [4-1:0] maxi_wstrb, - output reg maxi_wlast, - output reg maxi_wvalid, + output [32-1:0] maxi_wdata, + output [4-1:0] maxi_wstrb, + output maxi_wlast, + output maxi_wvalid, input maxi_wready, input [2-1:0] maxi_bresp, input maxi_bvalid, @@ -84,6 +84,44 @@ assign maxi_awprot = 0; assign maxi_awqos = 0; assign maxi_awuser = 0; + reg [32-1:0] _maxi_wdata_sb_0; + reg [4-1:0] _maxi_wstrb_sb_0; + reg _maxi_wlast_sb_0; + reg _maxi_wvalid_sb_0; + wire _maxi_wready_sb_0; + wire _sb_maxi_writedata_s_value_0; + assign _sb_maxi_writedata_s_value_0 = _maxi_wlast_sb_0; + wire [4-1:0] _sb_maxi_writedata_s_value_1; + assign _sb_maxi_writedata_s_value_1 = _maxi_wstrb_sb_0; + wire [32-1:0] _sb_maxi_writedata_s_value_2; + assign _sb_maxi_writedata_s_value_2 = _maxi_wdata_sb_0; + wire [37-1:0] _sb_maxi_writedata_s_data_3; + assign _sb_maxi_writedata_s_data_3 = { _sb_maxi_writedata_s_value_0, _sb_maxi_writedata_s_value_1, _sb_maxi_writedata_s_value_2 }; + wire _sb_maxi_writedata_s_valid_4; + assign _sb_maxi_writedata_s_valid_4 = _maxi_wvalid_sb_0; + wire _sb_maxi_writedata_m_ready_5; + assign _sb_maxi_writedata_m_ready_5 = maxi_wready; + reg [37-1:0] _sb_maxi_writedata_data_6; + reg _sb_maxi_writedata_valid_7; + wire _sb_maxi_writedata_ready_8; + reg [37-1:0] _sb_maxi_writedata_tmp_data_9; + reg _sb_maxi_writedata_tmp_valid_10; + wire [37-1:0] _sb_maxi_writedata_next_data_11; + wire _sb_maxi_writedata_next_valid_12; + assign _sb_maxi_writedata_ready_8 = !_sb_maxi_writedata_tmp_valid_10; + assign _sb_maxi_writedata_next_data_11 = (_sb_maxi_writedata_tmp_valid_10)? _sb_maxi_writedata_tmp_data_9 : _sb_maxi_writedata_s_data_3; + assign _sb_maxi_writedata_next_valid_12 = _sb_maxi_writedata_tmp_valid_10 || _sb_maxi_writedata_s_valid_4; + wire _sb_maxi_writedata_m_value_13; + assign _sb_maxi_writedata_m_value_13 = _sb_maxi_writedata_data_6[36:36]; + wire [4-1:0] _sb_maxi_writedata_m_value_14; + assign _sb_maxi_writedata_m_value_14 = _sb_maxi_writedata_data_6[35:32]; + wire [32-1:0] _sb_maxi_writedata_m_value_15; + assign _sb_maxi_writedata_m_value_15 = _sb_maxi_writedata_data_6[31:0]; + assign _maxi_wready_sb_0 = _sb_maxi_writedata_ready_8; + assign maxi_wdata = _sb_maxi_writedata_m_value_15; + assign maxi_wstrb = _sb_maxi_writedata_m_value_14; + assign maxi_wlast = _sb_maxi_writedata_m_value_13; + assign maxi_wvalid = _sb_maxi_writedata_valid_7; assign maxi_bready = 1; assign maxi_arsize = 2; assign maxi_arburst = 1; @@ -92,6 +130,38 @@ assign maxi_arprot = 0; assign maxi_arqos = 0; assign maxi_aruser = 0; + wire [32-1:0] _maxi_rdata_sb_0; + wire _maxi_rlast_sb_0; + wire _maxi_rvalid_sb_0; + wire _maxi_rready_sb_0; + wire _sb_maxi_readdata_s_value_16; + assign _sb_maxi_readdata_s_value_16 = maxi_rlast; + wire [32-1:0] _sb_maxi_readdata_s_value_17; + assign _sb_maxi_readdata_s_value_17 = maxi_rdata; + wire [33-1:0] _sb_maxi_readdata_s_data_18; + assign _sb_maxi_readdata_s_data_18 = { _sb_maxi_readdata_s_value_16, _sb_maxi_readdata_s_value_17 }; + wire _sb_maxi_readdata_s_valid_19; + assign _sb_maxi_readdata_s_valid_19 = maxi_rvalid; + wire _sb_maxi_readdata_m_ready_20; + assign _sb_maxi_readdata_m_ready_20 = _maxi_rready_sb_0; + reg [33-1:0] _sb_maxi_readdata_data_21; + reg _sb_maxi_readdata_valid_22; + wire _sb_maxi_readdata_ready_23; + reg [33-1:0] _sb_maxi_readdata_tmp_data_24; + reg _sb_maxi_readdata_tmp_valid_25; + wire [33-1:0] _sb_maxi_readdata_next_data_26; + wire _sb_maxi_readdata_next_valid_27; + assign _sb_maxi_readdata_ready_23 = !_sb_maxi_readdata_tmp_valid_25; + assign _sb_maxi_readdata_next_data_26 = (_sb_maxi_readdata_tmp_valid_25)? _sb_maxi_readdata_tmp_data_24 : _sb_maxi_readdata_s_data_18; + assign _sb_maxi_readdata_next_valid_27 = _sb_maxi_readdata_tmp_valid_25 || _sb_maxi_readdata_s_valid_19; + wire _sb_maxi_readdata_m_value_28; + assign _sb_maxi_readdata_m_value_28 = _sb_maxi_readdata_data_21[32:32]; + wire [32-1:0] _sb_maxi_readdata_m_value_29; + assign _sb_maxi_readdata_m_value_29 = _sb_maxi_readdata_data_21[31:0]; + assign _maxi_rdata_sb_0 = _sb_maxi_readdata_m_value_29; + assign _maxi_rlast_sb_0 = _sb_maxi_readdata_m_value_28; + assign _maxi_rvalid_sb_0 = _sb_maxi_readdata_valid_22; + assign maxi_rready = _sb_maxi_readdata_ready_23; reg [3-1:0] _maxi_outstanding_wcount; wire _maxi_has_outstanding_write; assign _maxi_has_outstanding_write = (_maxi_outstanding_wcount > 0) || maxi_awvalid; @@ -133,21 +203,21 @@ wire [32-1:0] _maxi_read_local_stride_fifo; wire [33-1:0] _maxi_read_local_size_fifo; wire [32-1:0] _maxi_read_local_blocksize_fifo; - wire [8-1:0] unpack_read_req_op_sel_0; - wire [32-1:0] unpack_read_req_local_addr_1; - wire [32-1:0] unpack_read_req_local_stride_2; - wire [33-1:0] unpack_read_req_local_size_3; - wire [32-1:0] unpack_read_req_local_blocksize_4; - assign unpack_read_req_op_sel_0 = _maxi_read_req_fifo_rdata[136:129]; - assign unpack_read_req_local_addr_1 = _maxi_read_req_fifo_rdata[128:97]; - assign unpack_read_req_local_stride_2 = _maxi_read_req_fifo_rdata[96:65]; - assign unpack_read_req_local_size_3 = _maxi_read_req_fifo_rdata[64:32]; - assign unpack_read_req_local_blocksize_4 = _maxi_read_req_fifo_rdata[31:0]; - assign _maxi_read_op_sel_fifo = unpack_read_req_op_sel_0; - assign _maxi_read_local_addr_fifo = unpack_read_req_local_addr_1; - assign _maxi_read_local_stride_fifo = unpack_read_req_local_stride_2; - assign _maxi_read_local_size_fifo = unpack_read_req_local_size_3; - assign _maxi_read_local_blocksize_fifo = unpack_read_req_local_blocksize_4; + wire [8-1:0] unpack_read_req_op_sel_30; + wire [32-1:0] unpack_read_req_local_addr_31; + wire [32-1:0] unpack_read_req_local_stride_32; + wire [33-1:0] unpack_read_req_local_size_33; + wire [32-1:0] unpack_read_req_local_blocksize_34; + assign unpack_read_req_op_sel_30 = _maxi_read_req_fifo_rdata[136:129]; + assign unpack_read_req_local_addr_31 = _maxi_read_req_fifo_rdata[128:97]; + assign unpack_read_req_local_stride_32 = _maxi_read_req_fifo_rdata[96:65]; + assign unpack_read_req_local_size_33 = _maxi_read_req_fifo_rdata[64:32]; + assign unpack_read_req_local_blocksize_34 = _maxi_read_req_fifo_rdata[31:0]; + assign _maxi_read_op_sel_fifo = unpack_read_req_op_sel_30; + assign _maxi_read_local_addr_fifo = unpack_read_req_local_addr_31; + assign _maxi_read_local_stride_fifo = unpack_read_req_local_stride_32; + assign _maxi_read_local_size_fifo = unpack_read_req_local_size_33; + assign _maxi_read_local_blocksize_fifo = unpack_read_req_local_blocksize_34; reg [8-1:0] _maxi_read_op_sel_buf; reg [32-1:0] _maxi_read_local_addr_buf; reg [32-1:0] _maxi_read_local_stride_buf; @@ -202,21 +272,21 @@ wire [32-1:0] _maxi_write_local_stride_fifo; wire [33-1:0] _maxi_write_size_fifo; wire [32-1:0] _maxi_write_local_blocksize_fifo; - wire [8-1:0] unpack_write_req_op_sel_5; - wire [32-1:0] unpack_write_req_local_addr_6; - wire [32-1:0] unpack_write_req_local_stride_7; - wire [33-1:0] unpack_write_req_size_8; - wire [32-1:0] unpack_write_req_local_blocksize_9; - assign unpack_write_req_op_sel_5 = _maxi_write_req_fifo_rdata[136:129]; - assign unpack_write_req_local_addr_6 = _maxi_write_req_fifo_rdata[128:97]; - assign unpack_write_req_local_stride_7 = _maxi_write_req_fifo_rdata[96:65]; - assign unpack_write_req_size_8 = _maxi_write_req_fifo_rdata[64:32]; - assign unpack_write_req_local_blocksize_9 = _maxi_write_req_fifo_rdata[31:0]; - assign _maxi_write_op_sel_fifo = unpack_write_req_op_sel_5; - assign _maxi_write_local_addr_fifo = unpack_write_req_local_addr_6; - assign _maxi_write_local_stride_fifo = unpack_write_req_local_stride_7; - assign _maxi_write_size_fifo = unpack_write_req_size_8; - assign _maxi_write_local_blocksize_fifo = unpack_write_req_local_blocksize_9; + wire [8-1:0] unpack_write_req_op_sel_35; + wire [32-1:0] unpack_write_req_local_addr_36; + wire [32-1:0] unpack_write_req_local_stride_37; + wire [33-1:0] unpack_write_req_size_38; + wire [32-1:0] unpack_write_req_local_blocksize_39; + assign unpack_write_req_op_sel_35 = _maxi_write_req_fifo_rdata[136:129]; + assign unpack_write_req_local_addr_36 = _maxi_write_req_fifo_rdata[128:97]; + assign unpack_write_req_local_stride_37 = _maxi_write_req_fifo_rdata[96:65]; + assign unpack_write_req_size_38 = _maxi_write_req_fifo_rdata[64:32]; + assign unpack_write_req_local_blocksize_39 = _maxi_write_req_fifo_rdata[31:0]; + assign _maxi_write_op_sel_fifo = unpack_write_req_op_sel_35; + assign _maxi_write_local_addr_fifo = unpack_write_req_local_addr_36; + assign _maxi_write_local_stride_fifo = unpack_write_req_local_stride_37; + assign _maxi_write_size_fifo = unpack_write_req_size_38; + assign _maxi_write_local_blocksize_fifo = unpack_write_req_local_blocksize_39; reg [8-1:0] _maxi_write_op_sel_buf; reg [32-1:0] _maxi_write_local_addr_buf; reg [32-1:0] _maxi_write_local_stride_buf; @@ -261,42 +331,42 @@ localparam _saxi_shift = 2; reg [32-1:0] _saxi_register_fsm; localparam _saxi_register_fsm_init = 0; - reg [32-1:0] addr_10; - reg writevalid_11; - reg readvalid_12; - reg prev_awvalid_13; - reg prev_arvalid_14; - assign saxi_awready = (_saxi_register_fsm == 0) && (!writevalid_11 && !readvalid_12 && !saxi_bvalid && prev_awvalid_13); - assign saxi_arready = (_saxi_register_fsm == 0) && (!readvalid_12 && !writevalid_11 && prev_arvalid_14 && !prev_awvalid_13); - reg [_saxi_maskwidth-1:0] axis_maskaddr_15; - wire signed [32-1:0] axislite_rdata_16; - assign axislite_rdata_16 = (axis_maskaddr_15 == 0)? _saxi_register_0 : - (axis_maskaddr_15 == 1)? _saxi_register_1 : - (axis_maskaddr_15 == 2)? _saxi_register_2 : - (axis_maskaddr_15 == 3)? _saxi_register_3 : - (axis_maskaddr_15 == 4)? _saxi_register_4 : - (axis_maskaddr_15 == 5)? _saxi_register_5 : - (axis_maskaddr_15 == 6)? _saxi_register_6 : - (axis_maskaddr_15 == 7)? _saxi_register_7 : 'hx; - wire axislite_flag_17; - assign axislite_flag_17 = (axis_maskaddr_15 == 0)? _saxi_flag_0 : - (axis_maskaddr_15 == 1)? _saxi_flag_1 : - (axis_maskaddr_15 == 2)? _saxi_flag_2 : - (axis_maskaddr_15 == 3)? _saxi_flag_3 : - (axis_maskaddr_15 == 4)? _saxi_flag_4 : - (axis_maskaddr_15 == 5)? _saxi_flag_5 : - (axis_maskaddr_15 == 6)? _saxi_flag_6 : - (axis_maskaddr_15 == 7)? _saxi_flag_7 : 'hx; - wire signed [32-1:0] axislite_resetval_18; - assign axislite_resetval_18 = (axis_maskaddr_15 == 0)? _saxi_resetval_0 : - (axis_maskaddr_15 == 1)? _saxi_resetval_1 : - (axis_maskaddr_15 == 2)? _saxi_resetval_2 : - (axis_maskaddr_15 == 3)? _saxi_resetval_3 : - (axis_maskaddr_15 == 4)? _saxi_resetval_4 : - (axis_maskaddr_15 == 5)? _saxi_resetval_5 : - (axis_maskaddr_15 == 6)? _saxi_resetval_6 : - (axis_maskaddr_15 == 7)? _saxi_resetval_7 : 'hx; - reg _saxi_cond_0_1; + reg [32-1:0] addr_40; + reg writevalid_41; + reg readvalid_42; + reg prev_awvalid_43; + reg prev_arvalid_44; + assign saxi_awready = (_saxi_register_fsm == 0) && (!writevalid_41 && !readvalid_42 && !saxi_bvalid && prev_awvalid_43); + assign saxi_arready = (_saxi_register_fsm == 0) && (!readvalid_42 && !writevalid_41 && prev_arvalid_44 && !prev_awvalid_43); + reg [_saxi_maskwidth-1:0] axis_maskaddr_45; + wire signed [32-1:0] axislite_rdata_46; + assign axislite_rdata_46 = (axis_maskaddr_45 == 0)? _saxi_register_0 : + (axis_maskaddr_45 == 1)? _saxi_register_1 : + (axis_maskaddr_45 == 2)? _saxi_register_2 : + (axis_maskaddr_45 == 3)? _saxi_register_3 : + (axis_maskaddr_45 == 4)? _saxi_register_4 : + (axis_maskaddr_45 == 5)? _saxi_register_5 : + (axis_maskaddr_45 == 6)? _saxi_register_6 : + (axis_maskaddr_45 == 7)? _saxi_register_7 : 'hx; + wire axislite_flag_47; + assign axislite_flag_47 = (axis_maskaddr_45 == 0)? _saxi_flag_0 : + (axis_maskaddr_45 == 1)? _saxi_flag_1 : + (axis_maskaddr_45 == 2)? _saxi_flag_2 : + (axis_maskaddr_45 == 3)? _saxi_flag_3 : + (axis_maskaddr_45 == 4)? _saxi_flag_4 : + (axis_maskaddr_45 == 5)? _saxi_flag_5 : + (axis_maskaddr_45 == 6)? _saxi_flag_6 : + (axis_maskaddr_45 == 7)? _saxi_flag_7 : 'hx; + wire signed [32-1:0] axislite_resetval_48; + assign axislite_resetval_48 = (axis_maskaddr_45 == 0)? _saxi_resetval_0 : + (axis_maskaddr_45 == 1)? _saxi_resetval_1 : + (axis_maskaddr_45 == 2)? _saxi_resetval_2 : + (axis_maskaddr_45 == 3)? _saxi_resetval_3 : + (axis_maskaddr_45 == 4)? _saxi_resetval_4 : + (axis_maskaddr_45 == 5)? _saxi_resetval_5 : + (axis_maskaddr_45 == 6)? _saxi_resetval_6 : + (axis_maskaddr_45 == 7)? _saxi_resetval_7 : 'hx; + reg _saxi_rdata_cond_0_1; assign saxi_wready = _saxi_register_fsm == 3; wire _axi_in_read_req_fifo_enq; wire [41-1:0] _axi_in_read_req_fifo_wdata; @@ -325,12 +395,12 @@ reg [4-1:0] count__axi_in_read_req_fifo; wire [8-1:0] _axi_in_read_op_sel_fifo; wire [33-1:0] _axi_in_read_local_size_fifo; - wire [8-1:0] unpack_read_req_op_sel_19; - wire [33-1:0] unpack_read_req_local_size_20; - assign unpack_read_req_op_sel_19 = _axi_in_read_req_fifo_rdata[40:33]; - assign unpack_read_req_local_size_20 = _axi_in_read_req_fifo_rdata[32:0]; - assign _axi_in_read_op_sel_fifo = unpack_read_req_op_sel_19; - assign _axi_in_read_local_size_fifo = unpack_read_req_local_size_20; + wire [8-1:0] unpack_read_req_op_sel_49; + wire [33-1:0] unpack_read_req_local_size_50; + assign unpack_read_req_op_sel_49 = _axi_in_read_req_fifo_rdata[40:33]; + assign unpack_read_req_local_size_50 = _axi_in_read_req_fifo_rdata[32:0]; + assign _axi_in_read_op_sel_fifo = unpack_read_req_op_sel_49; + assign _axi_in_read_local_size_fifo = unpack_read_req_local_size_50; reg [8-1:0] _axi_in_read_op_sel_buf; reg [33-1:0] _axi_in_read_local_size_buf; reg _axi_in_read_data_busy; @@ -365,12 +435,12 @@ reg [4-1:0] count__axi_out_write_req_fifo; wire [8-1:0] _axi_out_write_op_sel_fifo; wire [33-1:0] _axi_out_write_size_fifo; - wire [8-1:0] unpack_write_req_op_sel_21; - wire [33-1:0] unpack_write_req_local_size_22; - assign unpack_write_req_op_sel_21 = _axi_out_write_req_fifo_rdata[40:33]; - assign unpack_write_req_local_size_22 = _axi_out_write_req_fifo_rdata[32:0]; - assign _axi_out_write_op_sel_fifo = unpack_write_req_op_sel_21; - assign _axi_out_write_size_fifo = unpack_write_req_local_size_22; + wire [8-1:0] unpack_write_req_op_sel_51; + wire [33-1:0] unpack_write_req_local_size_52; + assign unpack_write_req_op_sel_51 = _axi_out_write_req_fifo_rdata[40:33]; + assign unpack_write_req_local_size_52 = _axi_out_write_req_fifo_rdata[32:0]; + assign _axi_out_write_op_sel_fifo = unpack_write_req_op_sel_51; + assign _axi_out_write_size_fifo = unpack_write_req_local_size_52; reg [8-1:0] _axi_out_write_op_sel_buf; reg [33-1:0] _axi_out_write_size_buf; reg _axi_out_write_data_busy; @@ -610,117 +680,117 @@ reg signed [32-1:0] _th_comp_write_size_1; reg signed [32-1:0] _th_comp_reduce_size_2; reg signed [32-1:0] _th_comp_bias_addr_3; - wire [32-1:0] mask_addr_shifted_23; - assign mask_addr_shifted_23 = _th_comp_bias_addr_3 >> 2; - wire [32-1:0] mask_addr_masked_24; - assign mask_addr_masked_24 = mask_addr_shifted_23 << 2; + wire [32-1:0] mask_addr_shifted_53; + assign mask_addr_shifted_53 = _th_comp_bias_addr_3 >> 2; + wire [32-1:0] mask_addr_masked_54; + assign mask_addr_masked_54 = mask_addr_shifted_53 << 2; reg [32-1:0] _maxi_read_req_fsm; localparam _maxi_read_req_fsm_init = 0; reg [33-1:0] _maxi_read_cur_global_size; reg _maxi_read_cont; - wire [8-1:0] pack_read_req_op_sel_25; - wire [32-1:0] pack_read_req_local_addr_26; - wire [32-1:0] pack_read_req_local_stride_27; - wire [33-1:0] pack_read_req_local_size_28; - wire [32-1:0] pack_read_req_local_blocksize_29; - assign pack_read_req_op_sel_25 = _maxi_read_op_sel; - assign pack_read_req_local_addr_26 = _maxi_read_local_addr; - assign pack_read_req_local_stride_27 = _maxi_read_local_stride; - assign pack_read_req_local_size_28 = _maxi_read_local_size; - assign pack_read_req_local_blocksize_29 = _maxi_read_local_blocksize; - wire [137-1:0] pack_read_req_packed_30; - assign pack_read_req_packed_30 = { pack_read_req_op_sel_25, pack_read_req_local_addr_26, pack_read_req_local_stride_27, pack_read_req_local_size_28, pack_read_req_local_blocksize_29 }; - assign _maxi_read_req_fifo_wdata = ((_maxi_read_req_fsm == 0) && _maxi_read_start && !_maxi_read_req_fifo_almost_full)? pack_read_req_packed_30 : 'hx; + wire [8-1:0] pack_read_req_op_sel_55; + wire [32-1:0] pack_read_req_local_addr_56; + wire [32-1:0] pack_read_req_local_stride_57; + wire [33-1:0] pack_read_req_local_size_58; + wire [32-1:0] pack_read_req_local_blocksize_59; + assign pack_read_req_op_sel_55 = _maxi_read_op_sel; + assign pack_read_req_local_addr_56 = _maxi_read_local_addr; + assign pack_read_req_local_stride_57 = _maxi_read_local_stride; + assign pack_read_req_local_size_58 = _maxi_read_local_size; + assign pack_read_req_local_blocksize_59 = _maxi_read_local_blocksize; + wire [137-1:0] pack_read_req_packed_60; + assign pack_read_req_packed_60 = { pack_read_req_op_sel_55, pack_read_req_local_addr_56, pack_read_req_local_stride_57, pack_read_req_local_size_58, pack_read_req_local_blocksize_59 }; + assign _maxi_read_req_fifo_wdata = ((_maxi_read_req_fsm == 0) && _maxi_read_start && !_maxi_read_req_fifo_almost_full)? pack_read_req_packed_60 : 'hx; assign _maxi_read_req_fifo_enq = ((_maxi_read_req_fsm == 0) && _maxi_read_start && !_maxi_read_req_fifo_almost_full)? (_maxi_read_req_fsm == 0) && _maxi_read_start && !_maxi_read_req_fifo_almost_full && !_maxi_read_req_fifo_almost_full : 0; - localparam _tmp_31 = 1; - wire [_tmp_31-1:0] _tmp_32; - assign _tmp_32 = !_maxi_read_req_fifo_almost_full; - reg [_tmp_31-1:0] __tmp_32_1; - wire [32-1:0] mask_addr_shifted_33; - assign mask_addr_shifted_33 = _maxi_read_global_addr >> 2; - wire [32-1:0] mask_addr_masked_34; - assign mask_addr_masked_34 = mask_addr_shifted_33 << 2; - wire [32-1:0] mask_addr_shifted_35; - assign mask_addr_shifted_35 = _maxi_read_global_addr >> 2; - wire [32-1:0] mask_addr_masked_36; - assign mask_addr_masked_36 = mask_addr_shifted_35 << 2; - wire [32-1:0] mask_addr_shifted_37; - assign mask_addr_shifted_37 = _maxi_read_global_addr >> 2; - wire [32-1:0] mask_addr_masked_38; - assign mask_addr_masked_38 = mask_addr_shifted_37 << 2; - wire [32-1:0] mask_addr_shifted_39; - assign mask_addr_shifted_39 = _maxi_read_global_addr >> 2; - wire [32-1:0] mask_addr_masked_40; - assign mask_addr_masked_40 = mask_addr_shifted_39 << 2; - wire [32-1:0] mask_addr_shifted_41; - assign mask_addr_shifted_41 = _maxi_read_global_addr >> 2; - wire [32-1:0] mask_addr_masked_42; - assign mask_addr_masked_42 = mask_addr_shifted_41 << 2; - wire [32-1:0] mask_addr_shifted_43; - assign mask_addr_shifted_43 = _maxi_read_global_addr >> 2; - wire [32-1:0] mask_addr_masked_44; - assign mask_addr_masked_44 = mask_addr_shifted_43 << 2; - reg _maxi_cond_0_1; + localparam _tmp_61 = 1; + wire [_tmp_61-1:0] _tmp_62; + assign _tmp_62 = !_maxi_read_req_fifo_almost_full; + reg [_tmp_61-1:0] __tmp_62_1; + wire [32-1:0] mask_addr_shifted_63; + assign mask_addr_shifted_63 = _maxi_read_global_addr >> 2; + wire [32-1:0] mask_addr_masked_64; + assign mask_addr_masked_64 = mask_addr_shifted_63 << 2; + wire [32-1:0] mask_addr_shifted_65; + assign mask_addr_shifted_65 = _maxi_read_global_addr >> 2; + wire [32-1:0] mask_addr_masked_66; + assign mask_addr_masked_66 = mask_addr_shifted_65 << 2; + wire [32-1:0] mask_addr_shifted_67; + assign mask_addr_shifted_67 = _maxi_read_global_addr >> 2; + wire [32-1:0] mask_addr_masked_68; + assign mask_addr_masked_68 = mask_addr_shifted_67 << 2; + wire [32-1:0] mask_addr_shifted_69; + assign mask_addr_shifted_69 = _maxi_read_global_addr >> 2; + wire [32-1:0] mask_addr_masked_70; + assign mask_addr_masked_70 = mask_addr_shifted_69 << 2; + wire [32-1:0] mask_addr_shifted_71; + assign mask_addr_shifted_71 = _maxi_read_global_addr >> 2; + wire [32-1:0] mask_addr_masked_72; + assign mask_addr_masked_72 = mask_addr_shifted_71 << 2; + wire [32-1:0] mask_addr_shifted_73; + assign mask_addr_shifted_73 = _maxi_read_global_addr >> 2; + wire [32-1:0] mask_addr_masked_74; + assign mask_addr_masked_74 = mask_addr_shifted_73 << 2; + reg _maxi_raddr_cond_0_1; reg [32-1:0] _maxi_read_data_fsm; localparam _maxi_read_data_fsm_init = 0; assign _maxi_read_req_fifo_deq = ((_maxi_read_data_fsm == 0) && (!_maxi_read_data_busy && !_maxi_read_req_fifo_empty && (_maxi_read_op_sel_fifo == 1)) && !_maxi_read_req_fifo_empty)? 1 : 0; reg [32-1:0] write_burst_fsm_0; localparam write_burst_fsm_0_init = 0; - reg [10-1:0] write_burst_addr_45; - reg [10-1:0] write_burst_stride_46; - reg [33-1:0] write_burst_length_47; - reg write_burst_done_48; - assign ram_b_0_wdata = ((write_burst_fsm_0 == 1) && maxi_rvalid)? maxi_rdata : 'hx; - assign ram_b_0_wenable = ((write_burst_fsm_0 == 1) && maxi_rvalid)? 1'd1 : 0; - assign maxi_rready = _maxi_read_data_fsm == 2; - wire [8-1:0] pack_read_req_op_sel_49; - wire [33-1:0] pack_read_req_local_size_50; - assign pack_read_req_op_sel_49 = 1; - assign pack_read_req_local_size_50 = _th_comp_read_size_0; - wire [41-1:0] pack_read_req_packed_51; - assign pack_read_req_packed_51 = { pack_read_req_op_sel_49, pack_read_req_local_size_50 }; - assign _axi_in_read_req_fifo_wdata = ((th_comp == 16) && !_axi_in_read_req_fifo_almost_full)? pack_read_req_packed_51 : 'hx; + reg [10-1:0] write_burst_addr_75; + reg [10-1:0] write_burst_stride_76; + reg [33-1:0] write_burst_length_77; + reg write_burst_done_78; + assign ram_b_0_wdata = ((write_burst_fsm_0 == 1) && _maxi_rvalid_sb_0)? _maxi_rdata_sb_0 : 'hx; + assign ram_b_0_wenable = ((write_burst_fsm_0 == 1) && _maxi_rvalid_sb_0)? 1'd1 : 0; + assign _maxi_rready_sb_0 = _maxi_read_data_fsm == 2; + wire [8-1:0] pack_read_req_op_sel_79; + wire [33-1:0] pack_read_req_local_size_80; + assign pack_read_req_op_sel_79 = 1; + assign pack_read_req_local_size_80 = _th_comp_read_size_0; + wire [41-1:0] pack_read_req_packed_81; + assign pack_read_req_packed_81 = { pack_read_req_op_sel_79, pack_read_req_local_size_80 }; + assign _axi_in_read_req_fifo_wdata = ((th_comp == 16) && !_axi_in_read_req_fifo_almost_full)? pack_read_req_packed_81 : 'hx; assign _axi_in_read_req_fifo_enq = ((th_comp == 16) && !_axi_in_read_req_fifo_almost_full)? (th_comp == 16) && !_axi_in_read_req_fifo_almost_full && !_axi_in_read_req_fifo_almost_full : 0; - localparam _tmp_52 = 1; - wire [_tmp_52-1:0] _tmp_53; - assign _tmp_53 = !_axi_in_read_req_fifo_almost_full; - reg [_tmp_52-1:0] __tmp_53_1; + localparam _tmp_82 = 1; + wire [_tmp_82-1:0] _tmp_83; + assign _tmp_83 = !_axi_in_read_req_fifo_almost_full; + reg [_tmp_82-1:0] __tmp_83_1; reg [32-1:0] _axi_in_read_data_fsm; localparam _axi_in_read_data_fsm_init = 0; assign _axi_in_read_req_fifo_deq = ((_axi_in_read_data_fsm == 0) && (!_axi_in_read_data_busy && !_axi_in_read_req_fifo_empty && (_axi_in_read_op_sel_fifo == 1)) && !_axi_in_read_req_fifo_empty)? 1 : 0; assign axi_in_tready = (_axi_in_read_data_fsm == 1) && !fifo_a_almost_full && (_axi_in_read_op_sel_buf == 1); assign fifo_a_wdata = ((_axi_in_read_data_fsm == 1) && axi_in_tvalid && !fifo_a_almost_full && (_axi_in_read_op_sel_buf == 1))? axi_in_tdata : 'hx; assign fifo_a_enq = ((_axi_in_read_data_fsm == 1) && axi_in_tvalid && !fifo_a_almost_full && (_axi_in_read_op_sel_buf == 1))? (_axi_in_read_data_fsm == 1) && axi_in_tvalid && !fifo_a_almost_full && (_axi_in_read_op_sel_buf == 1) && !fifo_a_almost_full : 0; - localparam _tmp_54 = 1; - wire [_tmp_54-1:0] _tmp_55; - assign _tmp_55 = !fifo_a_almost_full; - reg [_tmp_54-1:0] __tmp_55_1; - wire axistreamout_flag_56; - assign axistreamout_flag_56 = th_comp == 17; - wire [8-1:0] pack_write_req_op_sel_57; - wire [33-1:0] pack_write_req_local_size_58; - assign pack_write_req_op_sel_57 = 1; - assign pack_write_req_local_size_58 = _th_comp_write_size_1; - wire [41-1:0] pack_write_req_packed_59; - assign pack_write_req_packed_59 = { pack_write_req_op_sel_57, pack_write_req_local_size_58 }; - assign _axi_out_write_req_fifo_wdata = (axistreamout_flag_56 && !_axi_out_write_req_fifo_almost_full)? pack_write_req_packed_59 : 'hx; - assign _axi_out_write_req_fifo_enq = (axistreamout_flag_56 && !_axi_out_write_req_fifo_almost_full)? axistreamout_flag_56 && !_axi_out_write_req_fifo_almost_full && !_axi_out_write_req_fifo_almost_full : 0; - localparam _tmp_60 = 1; - wire [_tmp_60-1:0] _tmp_61; - assign _tmp_61 = !_axi_out_write_req_fifo_almost_full; - reg [_tmp_60-1:0] __tmp_61_1; + localparam _tmp_84 = 1; + wire [_tmp_84-1:0] _tmp_85; + assign _tmp_85 = !fifo_a_almost_full; + reg [_tmp_84-1:0] __tmp_85_1; + wire axistreamout_flag_86; + assign axistreamout_flag_86 = th_comp == 17; + wire [8-1:0] pack_write_req_op_sel_87; + wire [33-1:0] pack_write_req_local_size_88; + assign pack_write_req_op_sel_87 = 1; + assign pack_write_req_local_size_88 = _th_comp_write_size_1; + wire [41-1:0] pack_write_req_packed_89; + assign pack_write_req_packed_89 = { pack_write_req_op_sel_87, pack_write_req_local_size_88 }; + assign _axi_out_write_req_fifo_wdata = (axistreamout_flag_86 && !_axi_out_write_req_fifo_almost_full)? pack_write_req_packed_89 : 'hx; + assign _axi_out_write_req_fifo_enq = (axistreamout_flag_86 && !_axi_out_write_req_fifo_almost_full)? axistreamout_flag_86 && !_axi_out_write_req_fifo_almost_full && !_axi_out_write_req_fifo_almost_full : 0; + localparam _tmp_90 = 1; + wire [_tmp_90-1:0] _tmp_91; + assign _tmp_91 = !_axi_out_write_req_fifo_almost_full; + reg [_tmp_90-1:0] __tmp_91_1; reg [32-1:0] _axi_out_write_data_fsm; localparam _axi_out_write_data_fsm_init = 0; assign _axi_out_write_req_fifo_deq = ((_axi_out_write_data_fsm == 0) && (!_axi_out_write_data_busy && !_axi_out_write_req_fifo_empty && (_axi_out_write_op_sel_fifo == 1)) && !_axi_out_write_req_fifo_empty)? 1 : 0; - reg rlast_62; - wire cur_rvalid_63; + reg rlast_92; + wire cur_rvalid_93; assign fifo_c_deq = ((_axi_out_write_data_fsm == 1) && !fifo_c_empty && (_axi_out_write_op_sel_buf == 1) && (_axi_out_write_size_buf > 0) && (axi_out_tready || !axi_out_tvalid) && !fifo_c_empty)? 1 : 0; - localparam _tmp_64 = 1; - wire [_tmp_64-1:0] _tmp_65; - assign _tmp_65 = (_axi_out_write_data_fsm == 1) && !fifo_c_empty && (_axi_out_write_op_sel_buf == 1) && (_axi_out_write_size_buf > 0) && (axi_out_tready || !axi_out_tvalid) && !fifo_c_empty; - reg [_tmp_64-1:0] __tmp_65_1; - reg repeat_rvalid_66; - assign cur_rvalid_63 = __tmp_65_1 || repeat_rvalid_66; + localparam _tmp_94 = 1; + wire [_tmp_94-1:0] _tmp_95; + assign _tmp_95 = (_axi_out_write_data_fsm == 1) && !fifo_c_empty && (_axi_out_write_op_sel_buf == 1) && (_axi_out_write_size_buf > 0) && (axi_out_tready || !axi_out_tvalid) && !fifo_c_empty; + reg [_tmp_94-1:0] __tmp_95_1; + reg repeat_rvalid_96; + assign cur_rvalid_93 = __tmp_95_1 || repeat_rvalid_96; reg _axi_out_cond_0_1; wire signed [32-1:0] mystream_reduce_a_data; wire signed [32-1:0] mystream_reduce_reduce_size_data; @@ -774,42 +844,42 @@ assign mystream_reduce_sum_data = _reduceadd_data_4; wire [1-1:0] mystream_reduce_sum_valid_data; assign mystream_reduce_sum_valid_data = _pulse_data_6; - wire _set_flag_67; - assign _set_flag_67 = th_comp == 18; + wire _set_flag_97; + assign _set_flag_97 = th_comp == 18; assign fifo_a_deq = (_mystream_reduce_stream_oready && _mystream_reduce_a_source_fifo_deq && (_mystream_reduce_a_source_sel == 1) && !fifo_a_empty)? 1 : 0; - localparam _tmp_68 = 1; - wire [_tmp_68-1:0] _tmp_69; - assign _tmp_69 = _mystream_reduce_stream_oready && _mystream_reduce_a_source_fifo_deq && (_mystream_reduce_a_source_sel == 1) && !fifo_a_empty; - reg [_tmp_68-1:0] __tmp_69_1; + localparam _tmp_98 = 1; + wire [_tmp_98-1:0] _tmp_99; + assign _tmp_99 = _mystream_reduce_stream_oready && _mystream_reduce_a_source_fifo_deq && (_mystream_reduce_a_source_sel == 1) && !fifo_a_empty; + reg [_tmp_98-1:0] __tmp_99_1; assign _mystream_reduce_a_source_fifo_rdata = (_mystream_reduce_a_source_sel == 1)? fifo_a_rdata : 'hx; reg signed [32-1:0] __variable_wdata_0; assign mystream_reduce_a_data = __variable_wdata_0; reg [32-1:0] _mystream_reduce_a_source_fsm_0; localparam _mystream_reduce_a_source_fsm_0_init = 0; - wire _set_flag_70; - assign _set_flag_70 = th_comp == 19; + wire _set_flag_100; + assign _set_flag_100 = th_comp == 19; reg signed [32-1:0] __variable_wdata_1; assign mystream_reduce_reduce_size_data = __variable_wdata_1; - wire _set_flag_71; - assign _set_flag_71 = th_comp == 20; - reg _tmp_72; - reg _tmp_73; - reg _tmp_74; - reg _tmp_75; - reg _tmp_76; - reg _tmp_77; - reg signed [32-1:0] _tmp_78; - reg signed [32-1:0] _tmp_79; - reg signed [32-1:0] _tmp_80; - reg signed [32-1:0] _tmp_81; - reg signed [32-1:0] _tmp_82; - reg signed [32-1:0] _tmp_83; + wire _set_flag_101; + assign _set_flag_101 = th_comp == 20; + reg _tmp_102; + reg _tmp_103; + reg _tmp_104; + reg _tmp_105; + reg _tmp_106; + reg _tmp_107; + reg signed [32-1:0] _tmp_108; + reg signed [32-1:0] _tmp_109; + reg signed [32-1:0] _tmp_110; + reg signed [32-1:0] _tmp_111; + reg signed [32-1:0] _tmp_112; + reg signed [32-1:0] _tmp_113; assign fifo_b_wdata = (_mystream_reduce_stream_oready && _mystream_reduce_sum_sink_fifo_enq && (_mystream_reduce_sum_sink_sel == 2))? _mystream_reduce_sum_sink_fifo_wdata : 'hx; assign fifo_b_enq = (_mystream_reduce_stream_oready && _mystream_reduce_sum_sink_fifo_enq && (_mystream_reduce_sum_sink_sel == 2))? _mystream_reduce_stream_oready && _mystream_reduce_sum_sink_fifo_enq && (_mystream_reduce_sum_sink_sel == 2) && !fifo_b_almost_full : 0; - localparam _tmp_84 = 1; - wire [_tmp_84-1:0] _tmp_85; - assign _tmp_85 = !fifo_b_almost_full; - reg [_tmp_84-1:0] __tmp_85_1; + localparam _tmp_114 = 1; + wire [_tmp_114-1:0] _tmp_115; + assign _tmp_115 = !fifo_b_almost_full; + reg [_tmp_114-1:0] __tmp_115_1; assign _mystream_reduce_stream_oready = ((_mystream_reduce_sink_busy && (_mystream_reduce_sum_sink_sel == 2))? !fifo_b_almost_full : 1) && (((_mystream_reduce_source_busy && (_mystream_reduce_a_source_sel == 1))? !fifo_a_empty || _mystream_reduce_a_idle : 1) && _mystream_reduce_stream_internal_oready); reg [32-1:0] _mystream_reduce_sum_sink_fsm_1; localparam _mystream_reduce_sum_sink_fsm_1_init = 0; @@ -819,135 +889,223 @@ reg signed [32-1:0] _plus_data_10; wire signed [32-1:0] mystream_bias_z_data; assign mystream_bias_z_data = _plus_data_10; - wire _set_flag_86; - assign _set_flag_86 = th_comp == 21; + wire _set_flag_116; + assign _set_flag_116 = th_comp == 21; assign fifo_b_deq = (_mystream_bias_stream_oready && _mystream_bias_x_source_fifo_deq && (_mystream_bias_x_source_sel == 1) && !fifo_b_empty)? 1 : 0; - localparam _tmp_87 = 1; - wire [_tmp_87-1:0] _tmp_88; - assign _tmp_88 = _mystream_bias_stream_oready && _mystream_bias_x_source_fifo_deq && (_mystream_bias_x_source_sel == 1) && !fifo_b_empty; - reg [_tmp_87-1:0] __tmp_88_1; + localparam _tmp_117 = 1; + wire [_tmp_117-1:0] _tmp_118; + assign _tmp_118 = _mystream_bias_stream_oready && _mystream_bias_x_source_fifo_deq && (_mystream_bias_x_source_sel == 1) && !fifo_b_empty; + reg [_tmp_117-1:0] __tmp_118_1; assign _mystream_bias_x_source_fifo_rdata = (_mystream_bias_x_source_sel == 1)? fifo_b_rdata : 'hx; reg signed [32-1:0] __variable_wdata_8; assign mystream_bias_x_data = __variable_wdata_8; reg [32-1:0] _mystream_bias_x_source_fsm_0; localparam _mystream_bias_x_source_fsm_0_init = 0; - wire _set_flag_89; - assign _set_flag_89 = th_comp == 22; + wire _set_flag_119; + assign _set_flag_119 = th_comp == 22; assign ram_b_0_addr = (_mystream_bias_stream_oready && _mystream_bias_y_source_ram_renable && (_mystream_bias_y_source_sel == 2))? _mystream_bias_y_source_ram_raddr : - ((write_burst_fsm_0 == 1) && maxi_rvalid)? write_burst_addr_45 : 'hx; + ((write_burst_fsm_0 == 1) && _maxi_rvalid_sb_0)? write_burst_addr_75 : 'hx; assign ram_b_0_enable = (_mystream_bias_stream_oready && _mystream_bias_y_source_ram_renable && (_mystream_bias_y_source_sel == 2))? 1'd1 : - ((write_burst_fsm_0 == 1) && maxi_rvalid)? 1'd1 : 0; - localparam _tmp_90 = 1; - wire [_tmp_90-1:0] _tmp_91; - assign _tmp_91 = _mystream_bias_stream_oready && _mystream_bias_y_source_ram_renable && (_mystream_bias_y_source_sel == 2); - reg [_tmp_90-1:0] __tmp_91_1; + ((write_burst_fsm_0 == 1) && _maxi_rvalid_sb_0)? 1'd1 : 0; + localparam _tmp_120 = 1; + wire [_tmp_120-1:0] _tmp_121; + assign _tmp_121 = _mystream_bias_stream_oready && _mystream_bias_y_source_ram_renable && (_mystream_bias_y_source_sel == 2); + reg [_tmp_120-1:0] __tmp_121_1; assign _mystream_bias_y_source_ram_rdata = (_mystream_bias_y_source_sel == 2)? ram_b_0_rdata : 'hx; reg signed [32-1:0] __variable_wdata_9; assign mystream_bias_y_data = __variable_wdata_9; reg [32-1:0] _mystream_bias_y_source_fsm_1; localparam _mystream_bias_y_source_fsm_1_init = 0; - wire _set_flag_92; - assign _set_flag_92 = th_comp == 23; - reg _tmp_93; - reg _tmp_94; - reg _tmp_95; - reg signed [32-1:0] _tmp_96; - reg signed [32-1:0] _tmp_97; - reg signed [32-1:0] _tmp_98; + wire _set_flag_122; + assign _set_flag_122 = th_comp == 23; + reg _tmp_123; + reg _tmp_124; + reg _tmp_125; + reg signed [32-1:0] _tmp_126; + reg signed [32-1:0] _tmp_127; + reg signed [32-1:0] _tmp_128; assign fifo_c_wdata = (_mystream_bias_stream_oready && _mystream_bias_z_sink_fifo_enq && (_mystream_bias_z_sink_sel == 3))? _mystream_bias_z_sink_fifo_wdata : 'hx; assign fifo_c_enq = (_mystream_bias_stream_oready && _mystream_bias_z_sink_fifo_enq && (_mystream_bias_z_sink_sel == 3))? _mystream_bias_stream_oready && _mystream_bias_z_sink_fifo_enq && (_mystream_bias_z_sink_sel == 3) && !fifo_c_almost_full : 0; - localparam _tmp_99 = 1; - wire [_tmp_99-1:0] _tmp_100; - assign _tmp_100 = !fifo_c_almost_full; - reg [_tmp_99-1:0] __tmp_100_1; + localparam _tmp_129 = 1; + wire [_tmp_129-1:0] _tmp_130; + assign _tmp_130 = !fifo_c_almost_full; + reg [_tmp_129-1:0] __tmp_130_1; assign _mystream_bias_stream_oready = ((_mystream_bias_sink_busy && (_mystream_bias_z_sink_sel == 3))? !fifo_c_almost_full : 1) && (((_mystream_bias_source_busy && (_mystream_bias_x_source_sel == 1))? !fifo_b_empty || _mystream_bias_x_idle : 1) && _mystream_bias_stream_internal_oready); reg [32-1:0] _mystream_bias_z_sink_fsm_2; localparam _mystream_bias_z_sink_fsm_2_init = 0; - wire _set_flag_101; - assign _set_flag_101 = th_comp == 24; - assign _mystream_reduce_run_flag = (_set_flag_101)? 1 : 0; - reg _tmp_102; - reg _tmp_103; - reg _tmp_104; - reg _tmp_105; - reg _tmp_106; - reg _tmp_107; - reg [1-1:0] __variable_wdata_3; - assign mystream_reduce__reduce_reset_data = __variable_wdata_3; - reg _tmp_108; - reg _tmp_109; - reg _tmp_110; - reg _tmp_111; - assign _mystream_reduce_source_stop = _mystream_reduce_stream_oready && (_mystream_reduce_a_idle && (_mystream_reduce_fsm == 3)); - localparam _tmp_112 = 1; - wire [_tmp_112-1:0] _tmp_113; - assign _tmp_113 = _mystream_reduce_a_idle && (_mystream_reduce_fsm == 3); - reg [_tmp_112-1:0] _tmp_114; - localparam _tmp_115 = 1; - wire [_tmp_115-1:0] _tmp_116; - assign _tmp_116 = _mystream_reduce_a_idle && (_mystream_reduce_fsm == 3); - reg [_tmp_115-1:0] _tmp_117; - reg _tmp_118; - reg _tmp_119; - reg _tmp_120; - reg _tmp_121; - reg _tmp_122; - reg _tmp_123; - assign _mystream_reduce_sink_start = _tmp_123; - reg _tmp_124; - reg _tmp_125; - reg _tmp_126; - reg _tmp_127; - reg _tmp_128; - reg _tmp_129; - assign _mystream_reduce_sink_stop = _tmp_129; - reg _tmp_130; - reg _tmp_131; + wire _set_flag_131; + assign _set_flag_131 = th_comp == 24; + assign _mystream_reduce_run_flag = (_set_flag_131)? 1 : 0; reg _tmp_132; reg _tmp_133; reg _tmp_134; reg _tmp_135; - assign _mystream_reduce_sink_busy = _tmp_135; reg _tmp_136; - assign _mystream_reduce_busy = _mystream_reduce_source_busy || _mystream_reduce_sink_busy || _mystream_reduce_busy_reg; - wire _set_flag_137; - assign _set_flag_137 = th_comp == 26; - assign _mystream_bias_run_flag = (_set_flag_137)? 1 : 0; + reg _tmp_137; + reg [1-1:0] __variable_wdata_3; + assign mystream_reduce__reduce_reset_data = __variable_wdata_3; reg _tmp_138; reg _tmp_139; reg _tmp_140; - assign _mystream_bias_source_stop = _mystream_bias_stream_oready && (_mystream_bias_x_idle && _mystream_bias_y_idle && (_mystream_bias_fsm == 3)); - localparam _tmp_141 = 1; - wire [_tmp_141-1:0] _tmp_142; - assign _tmp_142 = _mystream_bias_x_idle && _mystream_bias_y_idle && (_mystream_bias_fsm == 3); - reg [_tmp_141-1:0] _tmp_143; - reg _tmp_144; - reg _tmp_145; - reg _tmp_146; - assign _mystream_bias_sink_start = _tmp_146; - reg _tmp_147; + reg _tmp_141; + assign _mystream_reduce_source_stop = _mystream_reduce_stream_oready && (_mystream_reduce_a_idle && (_mystream_reduce_fsm == 3)); + localparam _tmp_142 = 1; + wire [_tmp_142-1:0] _tmp_143; + assign _tmp_143 = _mystream_reduce_a_idle && (_mystream_reduce_fsm == 3); + reg [_tmp_142-1:0] _tmp_144; + localparam _tmp_145 = 1; + wire [_tmp_145-1:0] _tmp_146; + assign _tmp_146 = _mystream_reduce_a_idle && (_mystream_reduce_fsm == 3); + reg [_tmp_145-1:0] _tmp_147; reg _tmp_148; reg _tmp_149; - assign _mystream_bias_sink_stop = _tmp_149; reg _tmp_150; reg _tmp_151; reg _tmp_152; - assign _mystream_bias_sink_busy = _tmp_152; reg _tmp_153; + assign _mystream_reduce_sink_start = _tmp_153; + reg _tmp_154; + reg _tmp_155; + reg _tmp_156; + reg _tmp_157; + reg _tmp_158; + reg _tmp_159; + assign _mystream_reduce_sink_stop = _tmp_159; + reg _tmp_160; + reg _tmp_161; + reg _tmp_162; + reg _tmp_163; + reg _tmp_164; + reg _tmp_165; + assign _mystream_reduce_sink_busy = _tmp_165; + reg _tmp_166; + assign _mystream_reduce_busy = _mystream_reduce_source_busy || _mystream_reduce_sink_busy || _mystream_reduce_busy_reg; + wire _set_flag_167; + assign _set_flag_167 = th_comp == 26; + assign _mystream_bias_run_flag = (_set_flag_167)? 1 : 0; + reg _tmp_168; + reg _tmp_169; + reg _tmp_170; + assign _mystream_bias_source_stop = _mystream_bias_stream_oready && (_mystream_bias_x_idle && _mystream_bias_y_idle && (_mystream_bias_fsm == 3)); + localparam _tmp_171 = 1; + wire [_tmp_171-1:0] _tmp_172; + assign _tmp_172 = _mystream_bias_x_idle && _mystream_bias_y_idle && (_mystream_bias_fsm == 3); + reg [_tmp_171-1:0] _tmp_173; + reg _tmp_174; + reg _tmp_175; + reg _tmp_176; + assign _mystream_bias_sink_start = _tmp_176; + reg _tmp_177; + reg _tmp_178; + reg _tmp_179; + assign _mystream_bias_sink_stop = _tmp_179; + reg _tmp_180; + reg _tmp_181; + reg _tmp_182; + assign _mystream_bias_sink_busy = _tmp_182; + reg _tmp_183; assign _mystream_bias_busy = _mystream_bias_source_busy || _mystream_bias_sink_busy || _mystream_bias_busy_reg; always @(posedge CLK) begin if(RST) begin - _maxi_outstanding_wcount <= 0; - _maxi_read_start <= 0; - _maxi_write_start <= 0; maxi_awaddr <= 0; maxi_awlen <= 0; maxi_awvalid <= 0; - maxi_wdata <= 0; - maxi_wstrb <= 0; - maxi_wlast <= 0; - maxi_wvalid <= 0; + end else begin + maxi_awaddr <= 0; + maxi_awlen <= 0; + maxi_awvalid <= 0; + end + end + + + always @(posedge CLK) begin + if(RST) begin + _maxi_wdata_sb_0 <= 0; + _maxi_wstrb_sb_0 <= 0; + _maxi_wlast_sb_0 <= 0; + _maxi_wvalid_sb_0 <= 0; + end else begin + _maxi_wdata_sb_0 <= 0; + _maxi_wstrb_sb_0 <= 0; + _maxi_wlast_sb_0 <= 0; + _maxi_wvalid_sb_0 <= 0; + end + end + + + always @(posedge CLK) begin + if(RST) begin + _sb_maxi_writedata_data_6 <= 0; + _sb_maxi_writedata_valid_7 <= 0; + _sb_maxi_writedata_tmp_data_9 <= 0; + _sb_maxi_writedata_tmp_valid_10 <= 0; + end else begin + if(_sb_maxi_writedata_m_ready_5 || !_sb_maxi_writedata_valid_7) begin + _sb_maxi_writedata_data_6 <= _sb_maxi_writedata_next_data_11; + _sb_maxi_writedata_valid_7 <= _sb_maxi_writedata_next_valid_12; + end + if(!_sb_maxi_writedata_tmp_valid_10 && _sb_maxi_writedata_valid_7 && !_sb_maxi_writedata_m_ready_5) begin + _sb_maxi_writedata_tmp_data_9 <= _sb_maxi_writedata_s_data_3; + _sb_maxi_writedata_tmp_valid_10 <= _sb_maxi_writedata_s_valid_4; + end + if(_sb_maxi_writedata_tmp_valid_10 && _sb_maxi_writedata_m_ready_5) begin + _sb_maxi_writedata_tmp_valid_10 <= 0; + end + end + end + + + always @(posedge CLK) begin + if(RST) begin + maxi_araddr <= 0; + maxi_arlen <= 0; + maxi_arvalid <= 0; + _maxi_raddr_cond_0_1 <= 0; + end else begin + if(_maxi_raddr_cond_0_1) begin + maxi_arvalid <= 0; + end + if((_maxi_read_req_fsm == 1) && (maxi_arready || !maxi_arvalid)) begin + maxi_araddr <= _maxi_read_global_addr; + maxi_arlen <= _maxi_read_cur_global_size - 1; + maxi_arvalid <= 1; + end + _maxi_raddr_cond_0_1 <= 1; + if(maxi_arvalid && !maxi_arready) begin + maxi_arvalid <= maxi_arvalid; + end + end + end + + + always @(posedge CLK) begin + if(RST) begin + _sb_maxi_readdata_data_21 <= 0; + _sb_maxi_readdata_valid_22 <= 0; + _sb_maxi_readdata_tmp_data_24 <= 0; + _sb_maxi_readdata_tmp_valid_25 <= 0; + end else begin + if(_sb_maxi_readdata_m_ready_20 || !_sb_maxi_readdata_valid_22) begin + _sb_maxi_readdata_data_21 <= _sb_maxi_readdata_next_data_26; + _sb_maxi_readdata_valid_22 <= _sb_maxi_readdata_next_valid_27; + end + if(!_sb_maxi_readdata_tmp_valid_25 && _sb_maxi_readdata_valid_22 && !_sb_maxi_readdata_m_ready_20) begin + _sb_maxi_readdata_tmp_data_24 <= _sb_maxi_readdata_s_data_18; + _sb_maxi_readdata_tmp_valid_25 <= _sb_maxi_readdata_s_valid_19; + end + if(_sb_maxi_readdata_tmp_valid_25 && _sb_maxi_readdata_m_ready_20) begin + _sb_maxi_readdata_tmp_valid_25 <= 0; + end + end + end + + + always @(posedge CLK) begin + if(RST) begin + _maxi_outstanding_wcount <= 0; + _maxi_read_start <= 0; + _maxi_write_start <= 0; _maxi_read_op_sel <= 0; _maxi_read_global_addr <= 0; _maxi_read_global_size <= 0; @@ -957,10 +1115,6 @@ _maxi_read_local_blocksize <= 0; _maxi_read_req_busy <= 0; _maxi_read_cur_global_size <= 0; - maxi_araddr <= 0; - maxi_arlen <= 0; - maxi_arvalid <= 0; - _maxi_cond_0_1 <= 0; _maxi_read_data_busy <= 0; _maxi_read_op_sel_buf <= 0; _maxi_read_local_addr_buf <= 0; @@ -968,9 +1122,6 @@ _maxi_read_local_size_buf <= 0; _maxi_read_local_blocksize_buf <= 0; end else begin - if(_maxi_cond_0_1) begin - maxi_arvalid <= 0; - end if(maxi_awvalid && maxi_awready && !(maxi_bvalid && maxi_bready) && (_maxi_outstanding_wcount < 7)) begin _maxi_outstanding_wcount <= _maxi_outstanding_wcount + 1; end @@ -979,17 +1130,10 @@ end _maxi_read_start <= 0; _maxi_write_start <= 0; - maxi_awaddr <= 0; - maxi_awlen <= 0; - maxi_awvalid <= 0; - maxi_wdata <= 0; - maxi_wstrb <= 0; - maxi_wlast <= 0; - maxi_wvalid <= 0; if((th_comp == 14) && _maxi_read_req_idle) begin _maxi_read_start <= 1; _maxi_read_op_sel <= 1; - _maxi_read_global_addr <= mask_addr_masked_24; + _maxi_read_global_addr <= mask_addr_masked_54; _maxi_read_global_size <= _th_comp_write_size_1; _maxi_read_local_addr <= 0; _maxi_read_local_stride <= 1; @@ -1002,28 +1146,19 @@ if(_maxi_read_start && _maxi_read_req_fifo_almost_full) begin _maxi_read_start <= 1; end - if((_maxi_read_req_fsm == 0) && (_maxi_read_start || _maxi_read_cont) && !_maxi_read_req_fifo_almost_full && (_maxi_read_global_size <= 256) && ((mask_addr_masked_34 & 4095) + (_maxi_read_global_size << 2) >= 4096)) begin - _maxi_read_cur_global_size <= 4096 - (mask_addr_masked_36 & 4095) >> 2; - _maxi_read_global_size <= _maxi_read_global_size - (4096 - (mask_addr_masked_38 & 4095) >> 2); + if((_maxi_read_req_fsm == 0) && (_maxi_read_start || _maxi_read_cont) && !_maxi_read_req_fifo_almost_full && (_maxi_read_global_size <= 256) && ((mask_addr_masked_64 & 4095) + (_maxi_read_global_size << 2) >= 4096)) begin + _maxi_read_cur_global_size <= 4096 - (mask_addr_masked_66 & 4095) >> 2; + _maxi_read_global_size <= _maxi_read_global_size - (4096 - (mask_addr_masked_68 & 4095) >> 2); end else if((_maxi_read_req_fsm == 0) && (_maxi_read_start || _maxi_read_cont) && !_maxi_read_req_fifo_almost_full && (_maxi_read_global_size <= 256)) begin _maxi_read_cur_global_size <= _maxi_read_global_size; _maxi_read_global_size <= 0; - end else if((_maxi_read_req_fsm == 0) && (_maxi_read_start || _maxi_read_cont) && !_maxi_read_req_fifo_almost_full && ((mask_addr_masked_40 & 4095) + 1024 >= 4096)) begin - _maxi_read_cur_global_size <= 4096 - (mask_addr_masked_42 & 4095) >> 2; - _maxi_read_global_size <= _maxi_read_global_size - (4096 - (mask_addr_masked_44 & 4095) >> 2); + end else if((_maxi_read_req_fsm == 0) && (_maxi_read_start || _maxi_read_cont) && !_maxi_read_req_fifo_almost_full && ((mask_addr_masked_70 & 4095) + 1024 >= 4096)) begin + _maxi_read_cur_global_size <= 4096 - (mask_addr_masked_72 & 4095) >> 2; + _maxi_read_global_size <= _maxi_read_global_size - (4096 - (mask_addr_masked_74 & 4095) >> 2); end else if((_maxi_read_req_fsm == 0) && (_maxi_read_start || _maxi_read_cont) && !_maxi_read_req_fifo_almost_full) begin _maxi_read_cur_global_size <= 256; _maxi_read_global_size <= _maxi_read_global_size - 256; end - if((_maxi_read_req_fsm == 1) && (maxi_arready || !maxi_arvalid)) begin - maxi_araddr <= _maxi_read_global_addr; - maxi_arlen <= _maxi_read_cur_global_size - 1; - maxi_arvalid <= 1; - end - _maxi_cond_0_1 <= 1; - if(maxi_arvalid && !maxi_arready) begin - maxi_arvalid <= maxi_arvalid; - end if((_maxi_read_req_fsm == 1) && (maxi_arready || !maxi_arvalid)) begin _maxi_read_global_addr <= _maxi_read_global_addr + (_maxi_read_cur_global_size << 2); end @@ -1038,10 +1173,10 @@ _maxi_read_local_size_buf <= _maxi_read_local_size_fifo; _maxi_read_local_blocksize_buf <= _maxi_read_local_blocksize_fifo; end - if((_maxi_read_data_fsm == 2) && maxi_rvalid) begin + if((_maxi_read_data_fsm == 2) && _maxi_rvalid_sb_0) begin _maxi_read_local_size_buf <= _maxi_read_local_size_buf - 1; end - if((_maxi_read_data_fsm == 2) && maxi_rvalid && (_maxi_read_local_size_buf <= 1)) begin + if((_maxi_read_data_fsm == 2) && _maxi_rvalid_sb_0 && (_maxi_read_local_size_buf <= 1)) begin _maxi_read_data_busy <= 0; end end @@ -1051,7 +1186,7 @@ always @(posedge CLK) begin if(RST) begin count__maxi_read_req_fifo <= 0; - __tmp_32_1 <= 0; + __tmp_62_1 <= 0; end else begin if(_maxi_read_req_fifo_enq && !_maxi_read_req_fifo_full && (_maxi_read_req_fifo_deq && !_maxi_read_req_fifo_empty)) begin count__maxi_read_req_fifo <= count__maxi_read_req_fifo; @@ -1060,7 +1195,7 @@ end else if(_maxi_read_req_fifo_deq && !_maxi_read_req_fifo_empty) begin count__maxi_read_req_fifo <= count__maxi_read_req_fifo - 1; end - __tmp_32_1 <= _tmp_32; + __tmp_62_1 <= _tmp_62; end end @@ -1082,15 +1217,33 @@ always @(posedge CLK) begin if(RST) begin - saxi_bvalid <= 0; - prev_awvalid_13 <= 0; - prev_arvalid_14 <= 0; - writevalid_11 <= 0; - readvalid_12 <= 0; - addr_10 <= 0; saxi_rdata <= 0; saxi_rvalid <= 0; - _saxi_cond_0_1 <= 0; + _saxi_rdata_cond_0_1 <= 0; + end else begin + if(_saxi_rdata_cond_0_1) begin + saxi_rvalid <= 0; + end + if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid)) begin + saxi_rdata <= axislite_rdata_46; + saxi_rvalid <= 1; + end + _saxi_rdata_cond_0_1 <= 1; + if(saxi_rvalid && !saxi_rready) begin + saxi_rvalid <= saxi_rvalid; + end + end + end + + + always @(posedge CLK) begin + if(RST) begin + saxi_bvalid <= 0; + prev_awvalid_43 <= 0; + prev_arvalid_44 <= 0; + writevalid_41 <= 0; + readvalid_42 <= 0; + addr_40 <= 0; _saxi_register_0 <= 0; _saxi_flag_0 <= 0; _saxi_register_1 <= 0; @@ -1108,88 +1261,77 @@ _saxi_register_7 <= 0; _saxi_flag_7 <= 0; end else begin - if(_saxi_cond_0_1) begin - saxi_rvalid <= 0; - end if(saxi_bvalid && saxi_bready) begin saxi_bvalid <= 0; end if(saxi_wvalid && saxi_wready) begin saxi_bvalid <= 1; end - prev_awvalid_13 <= saxi_awvalid; - prev_arvalid_14 <= saxi_arvalid; - writevalid_11 <= 0; - readvalid_12 <= 0; + prev_awvalid_43 <= saxi_awvalid; + prev_arvalid_44 <= saxi_arvalid; + writevalid_41 <= 0; + readvalid_42 <= 0; if(saxi_awready && saxi_awvalid && !saxi_bvalid) begin - addr_10 <= saxi_awaddr; - writevalid_11 <= 1; + addr_40 <= saxi_awaddr; + writevalid_41 <= 1; end else if(saxi_arready && saxi_arvalid) begin - addr_10 <= saxi_araddr; - readvalid_12 <= 1; + addr_40 <= saxi_araddr; + readvalid_42 <= 1; end - if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid)) begin - saxi_rdata <= axislite_rdata_16; - saxi_rvalid <= 1; - end - _saxi_cond_0_1 <= 1; - if(saxi_rvalid && !saxi_rready) begin - saxi_rvalid <= saxi_rvalid; - end - if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_17 && (axis_maskaddr_15 == 0)) begin - _saxi_register_0 <= axislite_resetval_18; + if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_47 && (axis_maskaddr_45 == 0)) begin + _saxi_register_0 <= axislite_resetval_48; _saxi_flag_0 <= 0; end - if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_17 && (axis_maskaddr_15 == 1)) begin - _saxi_register_1 <= axislite_resetval_18; + if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_47 && (axis_maskaddr_45 == 1)) begin + _saxi_register_1 <= axislite_resetval_48; _saxi_flag_1 <= 0; end - if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_17 && (axis_maskaddr_15 == 2)) begin - _saxi_register_2 <= axislite_resetval_18; + if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_47 && (axis_maskaddr_45 == 2)) begin + _saxi_register_2 <= axislite_resetval_48; _saxi_flag_2 <= 0; end - if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_17 && (axis_maskaddr_15 == 3)) begin - _saxi_register_3 <= axislite_resetval_18; + if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_47 && (axis_maskaddr_45 == 3)) begin + _saxi_register_3 <= axislite_resetval_48; _saxi_flag_3 <= 0; end - if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_17 && (axis_maskaddr_15 == 4)) begin - _saxi_register_4 <= axislite_resetval_18; + if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_47 && (axis_maskaddr_45 == 4)) begin + _saxi_register_4 <= axislite_resetval_48; _saxi_flag_4 <= 0; end - if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_17 && (axis_maskaddr_15 == 5)) begin - _saxi_register_5 <= axislite_resetval_18; + if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_47 && (axis_maskaddr_45 == 5)) begin + _saxi_register_5 <= axislite_resetval_48; _saxi_flag_5 <= 0; end - if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_17 && (axis_maskaddr_15 == 6)) begin - _saxi_register_6 <= axislite_resetval_18; + if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_47 && (axis_maskaddr_45 == 6)) begin + _saxi_register_6 <= axislite_resetval_48; _saxi_flag_6 <= 0; end - if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_17 && (axis_maskaddr_15 == 7)) begin - _saxi_register_7 <= axislite_resetval_18; + if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_47 && (axis_maskaddr_45 == 7)) begin + _saxi_register_7 <= axislite_resetval_48; _saxi_flag_7 <= 0; end - if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_15 == 0)) begin + if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_45 == 0)) begin _saxi_register_0 <= saxi_wdata; end - if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_15 == 1)) begin + if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_45 == 1)) begin _saxi_register_1 <= saxi_wdata; end - if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_15 == 2)) begin + if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_45 == 2)) begin _saxi_register_2 <= saxi_wdata; end - if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_15 == 3)) begin + if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_45 == 3)) begin _saxi_register_3 <= saxi_wdata; end - if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_15 == 4)) begin + if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_45 == 4)) begin _saxi_register_4 <= saxi_wdata; end - if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_15 == 5)) begin + if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_45 == 5)) begin _saxi_register_5 <= saxi_wdata; end - if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_15 == 6)) begin + if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_45 == 6)) begin _saxi_register_6 <= saxi_wdata; end - if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_15 == 7)) begin + if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_45 == 7)) begin _saxi_register_7 <= saxi_wdata; end if((_saxi_register_0 == 1) && (th_comp == 2) && 1) begin @@ -1291,17 +1433,17 @@ always @(posedge CLK) begin if(RST) begin _saxi_register_fsm <= _saxi_register_fsm_init; - axis_maskaddr_15 <= 0; + axis_maskaddr_45 <= 0; end else begin case(_saxi_register_fsm) _saxi_register_fsm_init: begin - if(readvalid_12 || writevalid_11) begin - axis_maskaddr_15 <= (addr_10 >> _saxi_shift) & _saxi_mask; + if(readvalid_42 || writevalid_41) begin + axis_maskaddr_45 <= (addr_40 >> _saxi_shift) & _saxi_mask; end - if(readvalid_12) begin + if(readvalid_42) begin _saxi_register_fsm <= _saxi_register_fsm_1; end - if(writevalid_11) begin + if(writevalid_41) begin _saxi_register_fsm <= _saxi_register_fsm_3; end end @@ -1354,7 +1496,7 @@ always @(posedge CLK) begin if(RST) begin count__axi_in_read_req_fifo <= 0; - __tmp_53_1 <= 0; + __tmp_83_1 <= 0; end else begin if(_axi_in_read_req_fifo_enq && !_axi_in_read_req_fifo_full && (_axi_in_read_req_fifo_deq && !_axi_in_read_req_fifo_empty)) begin count__axi_in_read_req_fifo <= count__axi_in_read_req_fifo; @@ -1363,17 +1505,13 @@ end else if(_axi_in_read_req_fifo_deq && !_axi_in_read_req_fifo_empty) begin count__axi_in_read_req_fifo <= count__axi_in_read_req_fifo - 1; end - __tmp_53_1 <= _tmp_53; + __tmp_83_1 <= _tmp_83; end end always @(posedge CLK) begin if(RST) begin - _axi_out_write_data_busy <= 0; - _axi_out_write_op_sel_buf <= 0; - _axi_out_write_size_buf <= 0; - repeat_rvalid_66 <= 0; axi_out_tdata <= 0; axi_out_tvalid <= 0; axi_out_tlast <= 0; @@ -1383,32 +1521,43 @@ axi_out_tvalid <= 0; axi_out_tlast <= 0; end + if((_axi_out_write_op_sel_buf == 1) && cur_rvalid_93 && (axi_out_tready || !axi_out_tvalid) && (axi_out_tready || !axi_out_tvalid)) begin + axi_out_tdata <= fifo_c_rdata; + axi_out_tvalid <= 1; + axi_out_tlast <= rlast_92; + end + _axi_out_cond_0_1 <= 1; + if(axi_out_tvalid && !axi_out_tready) begin + axi_out_tvalid <= axi_out_tvalid; + axi_out_tlast <= axi_out_tlast; + end + end + end + + + always @(posedge CLK) begin + if(RST) begin + _axi_out_write_data_busy <= 0; + _axi_out_write_op_sel_buf <= 0; + _axi_out_write_size_buf <= 0; + repeat_rvalid_96 <= 0; + end else begin if((_axi_out_write_data_fsm == 0) && (!_axi_out_write_data_busy && !_axi_out_write_req_fifo_empty && (_axi_out_write_op_sel_fifo == 1))) begin _axi_out_write_data_busy <= 1; _axi_out_write_op_sel_buf <= _axi_out_write_op_sel_fifo; _axi_out_write_size_buf <= _axi_out_write_size_fifo; end - repeat_rvalid_66 <= 0; - if(__tmp_65_1 && !(axi_out_tready || !axi_out_tvalid)) begin - repeat_rvalid_66 <= 1; + repeat_rvalid_96 <= 0; + if(__tmp_95_1 && !(axi_out_tready || !axi_out_tvalid)) begin + repeat_rvalid_96 <= 1; end - if(repeat_rvalid_66 && !(axi_out_tready || !axi_out_tvalid)) begin - repeat_rvalid_66 <= 1; + if(repeat_rvalid_96 && !(axi_out_tready || !axi_out_tvalid)) begin + repeat_rvalid_96 <= 1; end if((_axi_out_write_data_fsm == 1) && ((_axi_out_write_data_fsm == 1) && !fifo_c_empty && (_axi_out_write_op_sel_buf == 1) && (_axi_out_write_size_buf > 0) && (axi_out_tready || !axi_out_tvalid))) begin _axi_out_write_size_buf <= _axi_out_write_size_buf - 1; end - if((_axi_out_write_op_sel_buf == 1) && cur_rvalid_63 && (axi_out_tready || !axi_out_tvalid) && (axi_out_tready || !axi_out_tvalid)) begin - axi_out_tdata <= fifo_c_rdata; - axi_out_tvalid <= 1; - axi_out_tlast <= rlast_62; - end - _axi_out_cond_0_1 <= 1; - if(axi_out_tvalid && !axi_out_tready) begin - axi_out_tvalid <= axi_out_tvalid; - axi_out_tlast <= axi_out_tlast; - end - if((_axi_out_write_data_fsm == 1) && ((_axi_out_write_op_sel_buf == 1) && cur_rvalid_63 && (axi_out_tready || !axi_out_tvalid)) && rlast_62) begin + if((_axi_out_write_data_fsm == 1) && ((_axi_out_write_op_sel_buf == 1) && cur_rvalid_93 && (axi_out_tready || !axi_out_tvalid)) && rlast_92) begin _axi_out_write_data_busy <= 0; end end @@ -1418,7 +1567,7 @@ always @(posedge CLK) begin if(RST) begin count__axi_out_write_req_fifo <= 0; - __tmp_61_1 <= 0; + __tmp_91_1 <= 0; end else begin if(_axi_out_write_req_fifo_enq && !_axi_out_write_req_fifo_full && (_axi_out_write_req_fifo_deq && !_axi_out_write_req_fifo_empty)) begin count__axi_out_write_req_fifo <= count__axi_out_write_req_fifo; @@ -1427,7 +1576,7 @@ end else if(_axi_out_write_req_fifo_deq && !_axi_out_write_req_fifo_empty) begin count__axi_out_write_req_fifo <= count__axi_out_write_req_fifo - 1; end - __tmp_61_1 <= _tmp_61; + __tmp_91_1 <= _tmp_91; end end @@ -1435,8 +1584,8 @@ always @(posedge CLK) begin if(RST) begin count_fifo_a <= 0; - __tmp_55_1 <= 0; - __tmp_69_1 <= 0; + __tmp_85_1 <= 0; + __tmp_99_1 <= 0; end else begin if(fifo_a_enq && !fifo_a_full && (fifo_a_deq && !fifo_a_empty)) begin count_fifo_a <= count_fifo_a; @@ -1445,8 +1594,8 @@ end else if(fifo_a_deq && !fifo_a_empty) begin count_fifo_a <= count_fifo_a - 1; end - __tmp_55_1 <= _tmp_55; - __tmp_69_1 <= _tmp_69; + __tmp_85_1 <= _tmp_85; + __tmp_99_1 <= _tmp_99; end end @@ -1454,8 +1603,8 @@ always @(posedge CLK) begin if(RST) begin count_fifo_b <= 0; - __tmp_85_1 <= 0; - __tmp_88_1 <= 0; + __tmp_115_1 <= 0; + __tmp_118_1 <= 0; end else begin if(fifo_b_enq && !fifo_b_full && (fifo_b_deq && !fifo_b_empty)) begin count_fifo_b <= count_fifo_b; @@ -1464,8 +1613,8 @@ end else if(fifo_b_deq && !fifo_b_empty) begin count_fifo_b <= count_fifo_b - 1; end - __tmp_85_1 <= _tmp_85; - __tmp_88_1 <= _tmp_88; + __tmp_115_1 <= _tmp_115; + __tmp_118_1 <= _tmp_118; end end @@ -1473,8 +1622,8 @@ always @(posedge CLK) begin if(RST) begin count_fifo_c <= 0; - __tmp_65_1 <= 0; - __tmp_100_1 <= 0; + __tmp_95_1 <= 0; + __tmp_130_1 <= 0; end else begin if(fifo_c_enq && !fifo_c_full && (fifo_c_deq && !fifo_c_empty)) begin count_fifo_c <= count_fifo_c; @@ -1483,17 +1632,17 @@ end else if(fifo_c_deq && !fifo_c_empty) begin count_fifo_c <= count_fifo_c - 1; end - __tmp_65_1 <= _tmp_65; - __tmp_100_1 <= _tmp_100; + __tmp_95_1 <= _tmp_95; + __tmp_130_1 <= _tmp_130; end end always @(posedge CLK) begin if(RST) begin - __tmp_91_1 <= 0; + __tmp_121_1 <= 0; end else begin - __tmp_91_1 <= _tmp_91; + __tmp_121_1 <= _tmp_121; end end @@ -1532,56 +1681,56 @@ _mystream_reduce_a_source_count <= 0; _mystream_reduce_reduce_size_next_parameter_data <= 0; __variable_wdata_1 <= 0; - _tmp_72 <= 0; - _tmp_73 <= 0; - _tmp_74 <= 0; - _tmp_75 <= 0; - _tmp_76 <= 0; - _tmp_77 <= 0; - _tmp_78 <= 0; - _tmp_79 <= 0; - _tmp_80 <= 0; - _tmp_81 <= 0; - _tmp_82 <= 0; - _tmp_83 <= 0; - _mystream_reduce_sum_sink_mode <= 5'b0; - _mystream_reduce_sum_sink_size <= 0; - _mystream_reduce_sum_sink_sel <= 0; - _mystream_reduce_sum_sink_size_buf <= 0; - _mystream_reduce_sum_sink_count <= 0; - _mystream_reduce_sum_sink_fifo_wdata <= 0; _tmp_102 <= 0; _tmp_103 <= 0; _tmp_104 <= 0; _tmp_105 <= 0; _tmp_106 <= 0; _tmp_107 <= 0; - __variable_wdata_3 <= 0; _tmp_108 <= 0; _tmp_109 <= 0; _tmp_110 <= 0; _tmp_111 <= 0; - _tmp_114 <= 0; - _tmp_117 <= 0; - _tmp_118 <= 0; - _tmp_119 <= 0; - _tmp_120 <= 0; - _tmp_121 <= 0; - _tmp_122 <= 0; - _tmp_123 <= 0; - _tmp_124 <= 0; - _tmp_125 <= 0; - _tmp_126 <= 0; - _tmp_127 <= 0; - _tmp_128 <= 0; - _tmp_129 <= 0; - _tmp_130 <= 0; - _tmp_131 <= 0; + _tmp_112 <= 0; + _tmp_113 <= 0; + _mystream_reduce_sum_sink_mode <= 5'b0; + _mystream_reduce_sum_sink_size <= 0; + _mystream_reduce_sum_sink_sel <= 0; + _mystream_reduce_sum_sink_size_buf <= 0; + _mystream_reduce_sum_sink_count <= 0; + _mystream_reduce_sum_sink_fifo_wdata <= 0; _tmp_132 <= 0; _tmp_133 <= 0; _tmp_134 <= 0; _tmp_135 <= 0; _tmp_136 <= 0; + _tmp_137 <= 0; + __variable_wdata_3 <= 0; + _tmp_138 <= 0; + _tmp_139 <= 0; + _tmp_140 <= 0; + _tmp_141 <= 0; + _tmp_144 <= 0; + _tmp_147 <= 0; + _tmp_148 <= 0; + _tmp_149 <= 0; + _tmp_150 <= 0; + _tmp_151 <= 0; + _tmp_152 <= 0; + _tmp_153 <= 0; + _tmp_154 <= 0; + _tmp_155 <= 0; + _tmp_156 <= 0; + _tmp_157 <= 0; + _tmp_158 <= 0; + _tmp_159 <= 0; + _tmp_160 <= 0; + _tmp_161 <= 0; + _tmp_162 <= 0; + _tmp_163 <= 0; + _tmp_164 <= 0; + _tmp_165 <= 0; + _tmp_166 <= 0; _mystream_reduce_busy_reg <= 0; end else begin if(_mystream_reduce_stream_oready) begin @@ -1654,11 +1803,11 @@ if(__mystream_reduce_stream_ivalid_3 && _mystream_reduce_stream_oready) begin _pulse_data_6 <= _pulse_current_count_6 >= __delay_data_13__delay_12__delay_11__variable_1 - 1; end - if(_set_flag_67) begin + if(_set_flag_97) begin _mystream_reduce_a_source_mode <= 5'b10000; _mystream_reduce_a_source_size <= _th_comp_read_size_0; end - if(_set_flag_67) begin + if(_set_flag_97) begin _mystream_reduce_a_source_sel <= 1; end if(_mystream_reduce_source_start && _mystream_reduce_a_source_mode & 5'b10000 && _mystream_reduce_stream_oready) begin @@ -1684,53 +1833,53 @@ _mystream_reduce_a_source_fifo_deq <= 0; _mystream_reduce_a_idle <= 1; end - if(_set_flag_70) begin + if(_set_flag_100) begin _mystream_reduce_reduce_size_next_parameter_data <= _th_comp_reduce_size_2; end if(_mystream_reduce_source_start) begin __variable_wdata_1 <= _mystream_reduce_reduce_size_next_parameter_data; end if(_mystream_reduce_stream_oready) begin - _tmp_72 <= _set_flag_71; + _tmp_102 <= _set_flag_101; end if(_mystream_reduce_stream_oready) begin - _tmp_73 <= _tmp_72; + _tmp_103 <= _tmp_102; end if(_mystream_reduce_stream_oready) begin - _tmp_74 <= _tmp_73; + _tmp_104 <= _tmp_103; end if(_mystream_reduce_stream_oready) begin - _tmp_75 <= _tmp_74; + _tmp_105 <= _tmp_104; end if(_mystream_reduce_stream_oready) begin - _tmp_76 <= _tmp_75; + _tmp_106 <= _tmp_105; end if(_mystream_reduce_stream_oready) begin - _tmp_77 <= _tmp_76; + _tmp_107 <= _tmp_106; end if(_mystream_reduce_stream_oready) begin - _tmp_78 <= _th_comp_write_size_1; + _tmp_108 <= _th_comp_write_size_1; end if(_mystream_reduce_stream_oready) begin - _tmp_79 <= _tmp_78; + _tmp_109 <= _tmp_108; end if(_mystream_reduce_stream_oready) begin - _tmp_80 <= _tmp_79; + _tmp_110 <= _tmp_109; end if(_mystream_reduce_stream_oready) begin - _tmp_81 <= _tmp_80; + _tmp_111 <= _tmp_110; end if(_mystream_reduce_stream_oready) begin - _tmp_82 <= _tmp_81; + _tmp_112 <= _tmp_111; end if(_mystream_reduce_stream_oready) begin - _tmp_83 <= _tmp_82; + _tmp_113 <= _tmp_112; end - if(_tmp_77) begin + if(_tmp_107) begin _mystream_reduce_sum_sink_mode <= 5'b10000; - _mystream_reduce_sum_sink_size <= _tmp_83; + _mystream_reduce_sum_sink_size <= _tmp_113; end - if(_tmp_77) begin + if(_tmp_107) begin _mystream_reduce_sum_sink_sel <= 2; end if(_mystream_reduce_sink_start && _mystream_reduce_sum_sink_mode & 5'b10000 && _mystream_reduce_stream_oready) begin @@ -1746,108 +1895,108 @@ _mystream_reduce_sum_sink_count <= _mystream_reduce_sum_sink_count - 1; end if(_mystream_reduce_stream_oready) begin - _tmp_102 <= _mystream_reduce_source_start; + _tmp_132 <= _mystream_reduce_source_start; end if(_mystream_reduce_stream_oready) begin - _tmp_103 <= _tmp_102; + _tmp_133 <= _tmp_132; end if(_mystream_reduce_stream_oready) begin - _tmp_104 <= _tmp_103; + _tmp_134 <= _tmp_133; end if(_mystream_reduce_stream_oready) begin - _tmp_105 <= _mystream_reduce_source_start; + _tmp_135 <= _mystream_reduce_source_start; end if(_mystream_reduce_stream_oready) begin - _tmp_106 <= _tmp_105; + _tmp_136 <= _tmp_135; end if(_mystream_reduce_stream_oready) begin - _tmp_107 <= _tmp_106; + _tmp_137 <= _tmp_136; end - if(_mystream_reduce_stream_oready && _tmp_107) begin + if(_mystream_reduce_stream_oready && _tmp_137) begin __variable_wdata_3 <= 1; end if(_mystream_reduce_stream_oready) begin - _tmp_108 <= _mystream_reduce_source_start; + _tmp_138 <= _mystream_reduce_source_start; end if(_mystream_reduce_stream_oready) begin - _tmp_109 <= _tmp_108; + _tmp_139 <= _tmp_138; end if(_mystream_reduce_stream_oready) begin - _tmp_110 <= _tmp_109; + _tmp_140 <= _tmp_139; end if(_mystream_reduce_stream_oready) begin - _tmp_111 <= _tmp_110; + _tmp_141 <= _tmp_140; end - if(_mystream_reduce_stream_oready && _tmp_111) begin + if(_mystream_reduce_stream_oready && _tmp_141) begin __variable_wdata_3 <= 0; end if(_mystream_reduce_stream_oready) begin - _tmp_114 <= _tmp_113; + _tmp_144 <= _tmp_143; end if(_mystream_reduce_stream_oready) begin - _tmp_117 <= _tmp_116; + _tmp_147 <= _tmp_146; end - if(_mystream_reduce_stream_oready && _tmp_117) begin + if(_mystream_reduce_stream_oready && _tmp_147) begin __variable_wdata_3 <= 1; end if(_mystream_reduce_stream_oready) begin - _tmp_118 <= _mystream_reduce_source_start; + _tmp_148 <= _mystream_reduce_source_start; end if(_mystream_reduce_stream_oready) begin - _tmp_119 <= _tmp_118; + _tmp_149 <= _tmp_148; end if(_mystream_reduce_stream_oready) begin - _tmp_120 <= _tmp_119; + _tmp_150 <= _tmp_149; end if(_mystream_reduce_stream_oready) begin - _tmp_121 <= _tmp_120; + _tmp_151 <= _tmp_150; end if(_mystream_reduce_stream_oready) begin - _tmp_122 <= _tmp_121; + _tmp_152 <= _tmp_151; end if(_mystream_reduce_stream_oready) begin - _tmp_123 <= _tmp_122; + _tmp_153 <= _tmp_152; end if(_mystream_reduce_stream_oready) begin - _tmp_124 <= _mystream_reduce_source_stop; + _tmp_154 <= _mystream_reduce_source_stop; end if(_mystream_reduce_stream_oready) begin - _tmp_125 <= _tmp_124; + _tmp_155 <= _tmp_154; end if(_mystream_reduce_stream_oready) begin - _tmp_126 <= _tmp_125; + _tmp_156 <= _tmp_155; end if(_mystream_reduce_stream_oready) begin - _tmp_127 <= _tmp_126; + _tmp_157 <= _tmp_156; end if(_mystream_reduce_stream_oready) begin - _tmp_128 <= _tmp_127; + _tmp_158 <= _tmp_157; end if(_mystream_reduce_stream_oready) begin - _tmp_129 <= _tmp_128; + _tmp_159 <= _tmp_158; end if(_mystream_reduce_stream_oready) begin - _tmp_130 <= _mystream_reduce_source_busy; + _tmp_160 <= _mystream_reduce_source_busy; end if(_mystream_reduce_stream_oready) begin - _tmp_131 <= _tmp_130; + _tmp_161 <= _tmp_160; end if(_mystream_reduce_stream_oready) begin - _tmp_132 <= _tmp_131; + _tmp_162 <= _tmp_161; end if(_mystream_reduce_stream_oready) begin - _tmp_133 <= _tmp_132; + _tmp_163 <= _tmp_162; end if(_mystream_reduce_stream_oready) begin - _tmp_134 <= _tmp_133; + _tmp_164 <= _tmp_163; end if(_mystream_reduce_stream_oready) begin - _tmp_135 <= _tmp_134; + _tmp_165 <= _tmp_164; end if(_mystream_reduce_stream_oready) begin - _tmp_136 <= _mystream_reduce_sink_busy; + _tmp_166 <= _mystream_reduce_sink_busy; end - if(!_mystream_reduce_sink_busy && _tmp_136) begin + if(!_mystream_reduce_sink_busy && _tmp_166) begin _mystream_reduce_busy_reg <= 0; end if(_mystream_reduce_source_busy) begin @@ -1867,10 +2016,10 @@ _mystream_reduce_source_busy <= 0; _mystream_reduce_stream_ivalid <= 0; end else begin - if(_mystream_reduce_stream_oready && _tmp_104) begin + if(_mystream_reduce_stream_oready && _tmp_134) begin _mystream_reduce_stream_ivalid <= 1; end - if(_mystream_reduce_stream_oready && _tmp_114) begin + if(_mystream_reduce_stream_oready && _tmp_144) begin _mystream_reduce_stream_ivalid <= 0; end case(_mystream_reduce_fsm) @@ -1944,32 +2093,32 @@ __variable_wdata_9 <= 0; _mystream_bias_y_source_ram_raddr <= 0; _mystream_bias_y_source_count <= 0; - _tmp_93 <= 0; - _tmp_94 <= 0; - _tmp_95 <= 0; - _tmp_96 <= 0; - _tmp_97 <= 0; - _tmp_98 <= 0; + _tmp_123 <= 0; + _tmp_124 <= 0; + _tmp_125 <= 0; + _tmp_126 <= 0; + _tmp_127 <= 0; + _tmp_128 <= 0; _mystream_bias_z_sink_mode <= 5'b0; _mystream_bias_z_sink_size <= 0; _mystream_bias_z_sink_sel <= 0; _mystream_bias_z_sink_size_buf <= 0; _mystream_bias_z_sink_count <= 0; _mystream_bias_z_sink_fifo_wdata <= 0; - _tmp_138 <= 0; - _tmp_139 <= 0; - _tmp_140 <= 0; - _tmp_143 <= 0; - _tmp_144 <= 0; - _tmp_145 <= 0; - _tmp_146 <= 0; - _tmp_147 <= 0; - _tmp_148 <= 0; - _tmp_149 <= 0; - _tmp_150 <= 0; - _tmp_151 <= 0; - _tmp_152 <= 0; - _tmp_153 <= 0; + _tmp_168 <= 0; + _tmp_169 <= 0; + _tmp_170 <= 0; + _tmp_173 <= 0; + _tmp_174 <= 0; + _tmp_175 <= 0; + _tmp_176 <= 0; + _tmp_177 <= 0; + _tmp_178 <= 0; + _tmp_179 <= 0; + _tmp_180 <= 0; + _tmp_181 <= 0; + _tmp_182 <= 0; + _tmp_183 <= 0; _mystream_bias_busy_reg <= 0; end else begin if(_mystream_bias_stream_oready) begin @@ -1992,11 +2141,11 @@ if(_mystream_bias_stream_oready) begin _plus_data_10 <= mystream_bias_x_data + mystream_bias_y_data; end - if(_set_flag_86) begin + if(_set_flag_116) begin _mystream_bias_x_source_mode <= 5'b10000; _mystream_bias_x_source_size <= _th_comp_write_size_1; end - if(_set_flag_86) begin + if(_set_flag_116) begin _mystream_bias_x_source_sel <= 1; end if(_mystream_bias_source_start && _mystream_bias_x_source_mode & 5'b10000 && _mystream_bias_stream_oready) begin @@ -2022,13 +2171,13 @@ _mystream_bias_x_source_fifo_deq <= 0; _mystream_bias_x_idle <= 1; end - if(_set_flag_89) begin + if(_set_flag_119) begin _mystream_bias_y_source_mode <= 5'b1; _mystream_bias_y_source_offset <= 0; _mystream_bias_y_source_size <= _th_comp_write_size_1; _mystream_bias_y_source_stride <= 1; end - if(_set_flag_89) begin + if(_set_flag_119) begin _mystream_bias_y_source_sel <= 2; end if(_mystream_bias_source_start && _mystream_bias_y_source_mode & 5'b1 && _mystream_bias_stream_oready) begin @@ -2059,28 +2208,28 @@ _mystream_bias_y_idle <= 1; end if(_mystream_bias_stream_oready) begin - _tmp_93 <= _set_flag_92; + _tmp_123 <= _set_flag_122; end if(_mystream_bias_stream_oready) begin - _tmp_94 <= _tmp_93; + _tmp_124 <= _tmp_123; end if(_mystream_bias_stream_oready) begin - _tmp_95 <= _tmp_94; + _tmp_125 <= _tmp_124; end if(_mystream_bias_stream_oready) begin - _tmp_96 <= _th_comp_write_size_1; + _tmp_126 <= _th_comp_write_size_1; end if(_mystream_bias_stream_oready) begin - _tmp_97 <= _tmp_96; + _tmp_127 <= _tmp_126; end if(_mystream_bias_stream_oready) begin - _tmp_98 <= _tmp_97; + _tmp_128 <= _tmp_127; end - if(_tmp_95) begin + if(_tmp_125) begin _mystream_bias_z_sink_mode <= 5'b10000; - _mystream_bias_z_sink_size <= _tmp_98; + _mystream_bias_z_sink_size <= _tmp_128; end - if(_tmp_95) begin + if(_tmp_125) begin _mystream_bias_z_sink_sel <= 3; end if(_mystream_bias_sink_start && _mystream_bias_z_sink_mode & 5'b10000 && _mystream_bias_stream_oready) begin @@ -2096,48 +2245,48 @@ _mystream_bias_z_sink_count <= _mystream_bias_z_sink_count - 1; end if(_mystream_bias_stream_oready) begin - _tmp_138 <= _mystream_bias_source_start; + _tmp_168 <= _mystream_bias_source_start; end if(_mystream_bias_stream_oready) begin - _tmp_139 <= _tmp_138; + _tmp_169 <= _tmp_168; end if(_mystream_bias_stream_oready) begin - _tmp_140 <= _tmp_139; + _tmp_170 <= _tmp_169; end if(_mystream_bias_stream_oready) begin - _tmp_143 <= _tmp_142; + _tmp_173 <= _tmp_172; end if(_mystream_bias_stream_oready) begin - _tmp_144 <= _mystream_bias_source_start; + _tmp_174 <= _mystream_bias_source_start; end if(_mystream_bias_stream_oready) begin - _tmp_145 <= _tmp_144; + _tmp_175 <= _tmp_174; end if(_mystream_bias_stream_oready) begin - _tmp_146 <= _tmp_145; + _tmp_176 <= _tmp_175; end if(_mystream_bias_stream_oready) begin - _tmp_147 <= _mystream_bias_source_stop; + _tmp_177 <= _mystream_bias_source_stop; end if(_mystream_bias_stream_oready) begin - _tmp_148 <= _tmp_147; + _tmp_178 <= _tmp_177; end if(_mystream_bias_stream_oready) begin - _tmp_149 <= _tmp_148; + _tmp_179 <= _tmp_178; end if(_mystream_bias_stream_oready) begin - _tmp_150 <= _mystream_bias_source_busy; + _tmp_180 <= _mystream_bias_source_busy; end if(_mystream_bias_stream_oready) begin - _tmp_151 <= _tmp_150; + _tmp_181 <= _tmp_180; end if(_mystream_bias_stream_oready) begin - _tmp_152 <= _tmp_151; + _tmp_182 <= _tmp_181; end if(_mystream_bias_stream_oready) begin - _tmp_153 <= _mystream_bias_sink_busy; + _tmp_183 <= _mystream_bias_sink_busy; end - if(!_mystream_bias_sink_busy && _tmp_153) begin + if(!_mystream_bias_sink_busy && _tmp_183) begin _mystream_bias_busy_reg <= 0; end if(_mystream_bias_source_busy) begin @@ -2157,10 +2306,10 @@ _mystream_bias_source_busy <= 0; _mystream_bias_stream_ivalid <= 0; end else begin - if(_mystream_bias_stream_oready && _tmp_140) begin + if(_mystream_bias_stream_oready && _tmp_170) begin _mystream_bias_stream_ivalid <= 1; end - if(_mystream_bias_stream_oready && _tmp_143) begin + if(_mystream_bias_stream_oready && _tmp_173) begin _mystream_bias_stream_ivalid <= 0; end case(_mystream_bias_fsm) @@ -2436,7 +2585,7 @@ _maxi_read_data_fsm <= _maxi_read_data_fsm_2; end _maxi_read_data_fsm_2: begin - if(maxi_rvalid && (_maxi_read_local_size_buf <= 1)) begin + if(_maxi_rvalid_sb_0 && (_maxi_read_local_size_buf <= 1)) begin _maxi_read_data_fsm <= _maxi_read_data_fsm_init; end end @@ -2449,37 +2598,37 @@ always @(posedge CLK) begin if(RST) begin write_burst_fsm_0 <= write_burst_fsm_0_init; - write_burst_addr_45 <= 0; - write_burst_stride_46 <= 0; - write_burst_length_47 <= 0; - write_burst_done_48 <= 0; + write_burst_addr_75 <= 0; + write_burst_stride_76 <= 0; + write_burst_length_77 <= 0; + write_burst_done_78 <= 0; end else begin case(write_burst_fsm_0) write_burst_fsm_0_init: begin - write_burst_addr_45 <= _maxi_read_local_addr_buf; - write_burst_stride_46 <= _maxi_read_local_stride_buf; - write_burst_length_47 <= _maxi_read_local_size_buf; - write_burst_done_48 <= 0; + write_burst_addr_75 <= _maxi_read_local_addr_buf; + write_burst_stride_76 <= _maxi_read_local_stride_buf; + write_burst_length_77 <= _maxi_read_local_size_buf; + write_burst_done_78 <= 0; if((_maxi_read_data_fsm == 1) && (_maxi_read_op_sel_buf == 1) && (_maxi_read_local_size_buf > 0)) begin write_burst_fsm_0 <= write_burst_fsm_0_1; end end write_burst_fsm_0_1: begin - if(maxi_rvalid) begin - write_burst_addr_45 <= write_burst_addr_45 + write_burst_stride_46; - write_burst_length_47 <= write_burst_length_47 - 1; - write_burst_done_48 <= 0; + if(_maxi_rvalid_sb_0) begin + write_burst_addr_75 <= write_burst_addr_75 + write_burst_stride_76; + write_burst_length_77 <= write_burst_length_77 - 1; + write_burst_done_78 <= 0; end - if(maxi_rvalid && (write_burst_length_47 <= 1)) begin - write_burst_done_48 <= 1; + if(_maxi_rvalid_sb_0 && (write_burst_length_77 <= 1)) begin + write_burst_done_78 <= 1; end - if(maxi_rvalid && 0) begin - write_burst_done_48 <= 1; + if(_maxi_rvalid_sb_0 && 0) begin + write_burst_done_78 <= 1; end - if(maxi_rvalid && (write_burst_length_47 <= 1)) begin + if(_maxi_rvalid_sb_0 && (write_burst_length_77 <= 1)) begin write_burst_fsm_0 <= write_burst_fsm_0_init; end - if(maxi_rvalid && 0) begin + if(_maxi_rvalid_sb_0 && 0) begin write_burst_fsm_0 <= write_burst_fsm_0_init; end if(0) begin @@ -2516,20 +2665,20 @@ always @(posedge CLK) begin if(RST) begin _axi_out_write_data_fsm <= _axi_out_write_data_fsm_init; - rlast_62 <= 0; + rlast_92 <= 0; end else begin case(_axi_out_write_data_fsm) _axi_out_write_data_fsm_init: begin - rlast_62 <= 0; + rlast_92 <= 0; if(!_axi_out_write_data_busy && !_axi_out_write_req_fifo_empty && (_axi_out_write_op_sel_fifo == 1)) begin _axi_out_write_data_fsm <= _axi_out_write_data_fsm_1; end end _axi_out_write_data_fsm_1: begin if((_axi_out_write_data_fsm == 1) && !fifo_c_empty && (_axi_out_write_op_sel_buf == 1) && (_axi_out_write_size_buf > 0) && (axi_out_tready || !axi_out_tvalid)) begin - rlast_62 <= _axi_out_write_size_buf <= 1; + rlast_92 <= _axi_out_write_size_buf <= 1; end - if((_axi_out_write_op_sel_buf == 1) && cur_rvalid_63 && (axi_out_tready || !axi_out_tvalid) && rlast_62) begin + if((_axi_out_write_op_sel_buf == 1) && cur_rvalid_93 && (axi_out_tready || !axi_out_tvalid) && rlast_92) begin _axi_out_write_data_fsm <= _axi_out_write_data_fsm_init; end end diff --git a/examples/stream_axi_stream_fifo_ipxact_ultra96v2_pynq/ultra96v2_pynq/run_on_pynq.py b/examples/stream_axi_stream_fifo_ipxact_ultra96v2_pynq/ultra96v2_pynq/run_on_pynq.py index 4721e19a..951730ca 100644 --- a/examples/stream_axi_stream_fifo_ipxact_ultra96v2_pynq/ultra96v2_pynq/run_on_pynq.py +++ b/examples/stream_axi_stream_fifo_ipxact_ultra96v2_pynq/ultra96v2_pynq/run_on_pynq.py @@ -86,4 +86,3 @@ diff_sum = np.sum(expected - dst) print(diff_sum) - diff --git a/examples/stream_axi_stream_fifo_ultra96v2_pynq/test_stream_axi_stream_fifo.py b/examples/stream_axi_stream_fifo_ultra96v2_pynq/test_stream_axi_stream_fifo.py index 73814a9e..09527d23 100644 --- a/examples/stream_axi_stream_fifo_ultra96v2_pynq/test_stream_axi_stream_fifo.py +++ b/examples/stream_axi_stream_fifo_ultra96v2_pynq/test_stream_axi_stream_fifo.py @@ -22,10 +22,10 @@ output [2-1:0] maxi_awuser, output reg maxi_awvalid, input maxi_awready, - output reg [32-1:0] maxi_wdata, - output reg [4-1:0] maxi_wstrb, - output reg maxi_wlast, - output reg maxi_wvalid, + output [32-1:0] maxi_wdata, + output [4-1:0] maxi_wstrb, + output maxi_wlast, + output maxi_wvalid, input maxi_wready, input [2-1:0] maxi_bresp, input maxi_bvalid, @@ -84,6 +84,44 @@ assign maxi_awprot = 0; assign maxi_awqos = 0; assign maxi_awuser = 0; + reg [32-1:0] _maxi_wdata_sb_0; + reg [4-1:0] _maxi_wstrb_sb_0; + reg _maxi_wlast_sb_0; + reg _maxi_wvalid_sb_0; + wire _maxi_wready_sb_0; + wire _sb_maxi_writedata_s_value_0; + assign _sb_maxi_writedata_s_value_0 = _maxi_wlast_sb_0; + wire [4-1:0] _sb_maxi_writedata_s_value_1; + assign _sb_maxi_writedata_s_value_1 = _maxi_wstrb_sb_0; + wire [32-1:0] _sb_maxi_writedata_s_value_2; + assign _sb_maxi_writedata_s_value_2 = _maxi_wdata_sb_0; + wire [37-1:0] _sb_maxi_writedata_s_data_3; + assign _sb_maxi_writedata_s_data_3 = { _sb_maxi_writedata_s_value_0, _sb_maxi_writedata_s_value_1, _sb_maxi_writedata_s_value_2 }; + wire _sb_maxi_writedata_s_valid_4; + assign _sb_maxi_writedata_s_valid_4 = _maxi_wvalid_sb_0; + wire _sb_maxi_writedata_m_ready_5; + assign _sb_maxi_writedata_m_ready_5 = maxi_wready; + reg [37-1:0] _sb_maxi_writedata_data_6; + reg _sb_maxi_writedata_valid_7; + wire _sb_maxi_writedata_ready_8; + reg [37-1:0] _sb_maxi_writedata_tmp_data_9; + reg _sb_maxi_writedata_tmp_valid_10; + wire [37-1:0] _sb_maxi_writedata_next_data_11; + wire _sb_maxi_writedata_next_valid_12; + assign _sb_maxi_writedata_ready_8 = !_sb_maxi_writedata_tmp_valid_10; + assign _sb_maxi_writedata_next_data_11 = (_sb_maxi_writedata_tmp_valid_10)? _sb_maxi_writedata_tmp_data_9 : _sb_maxi_writedata_s_data_3; + assign _sb_maxi_writedata_next_valid_12 = _sb_maxi_writedata_tmp_valid_10 || _sb_maxi_writedata_s_valid_4; + wire _sb_maxi_writedata_m_value_13; + assign _sb_maxi_writedata_m_value_13 = _sb_maxi_writedata_data_6[36:36]; + wire [4-1:0] _sb_maxi_writedata_m_value_14; + assign _sb_maxi_writedata_m_value_14 = _sb_maxi_writedata_data_6[35:32]; + wire [32-1:0] _sb_maxi_writedata_m_value_15; + assign _sb_maxi_writedata_m_value_15 = _sb_maxi_writedata_data_6[31:0]; + assign _maxi_wready_sb_0 = _sb_maxi_writedata_ready_8; + assign maxi_wdata = _sb_maxi_writedata_m_value_15; + assign maxi_wstrb = _sb_maxi_writedata_m_value_14; + assign maxi_wlast = _sb_maxi_writedata_m_value_13; + assign maxi_wvalid = _sb_maxi_writedata_valid_7; assign maxi_bready = 1; assign maxi_arsize = 2; assign maxi_arburst = 1; @@ -92,6 +130,38 @@ assign maxi_arprot = 0; assign maxi_arqos = 0; assign maxi_aruser = 0; + wire [32-1:0] _maxi_rdata_sb_0; + wire _maxi_rlast_sb_0; + wire _maxi_rvalid_sb_0; + wire _maxi_rready_sb_0; + wire _sb_maxi_readdata_s_value_16; + assign _sb_maxi_readdata_s_value_16 = maxi_rlast; + wire [32-1:0] _sb_maxi_readdata_s_value_17; + assign _sb_maxi_readdata_s_value_17 = maxi_rdata; + wire [33-1:0] _sb_maxi_readdata_s_data_18; + assign _sb_maxi_readdata_s_data_18 = { _sb_maxi_readdata_s_value_16, _sb_maxi_readdata_s_value_17 }; + wire _sb_maxi_readdata_s_valid_19; + assign _sb_maxi_readdata_s_valid_19 = maxi_rvalid; + wire _sb_maxi_readdata_m_ready_20; + assign _sb_maxi_readdata_m_ready_20 = _maxi_rready_sb_0; + reg [33-1:0] _sb_maxi_readdata_data_21; + reg _sb_maxi_readdata_valid_22; + wire _sb_maxi_readdata_ready_23; + reg [33-1:0] _sb_maxi_readdata_tmp_data_24; + reg _sb_maxi_readdata_tmp_valid_25; + wire [33-1:0] _sb_maxi_readdata_next_data_26; + wire _sb_maxi_readdata_next_valid_27; + assign _sb_maxi_readdata_ready_23 = !_sb_maxi_readdata_tmp_valid_25; + assign _sb_maxi_readdata_next_data_26 = (_sb_maxi_readdata_tmp_valid_25)? _sb_maxi_readdata_tmp_data_24 : _sb_maxi_readdata_s_data_18; + assign _sb_maxi_readdata_next_valid_27 = _sb_maxi_readdata_tmp_valid_25 || _sb_maxi_readdata_s_valid_19; + wire _sb_maxi_readdata_m_value_28; + assign _sb_maxi_readdata_m_value_28 = _sb_maxi_readdata_data_21[32:32]; + wire [32-1:0] _sb_maxi_readdata_m_value_29; + assign _sb_maxi_readdata_m_value_29 = _sb_maxi_readdata_data_21[31:0]; + assign _maxi_rdata_sb_0 = _sb_maxi_readdata_m_value_29; + assign _maxi_rlast_sb_0 = _sb_maxi_readdata_m_value_28; + assign _maxi_rvalid_sb_0 = _sb_maxi_readdata_valid_22; + assign maxi_rready = _sb_maxi_readdata_ready_23; reg [3-1:0] _maxi_outstanding_wcount; wire _maxi_has_outstanding_write; assign _maxi_has_outstanding_write = (_maxi_outstanding_wcount > 0) || maxi_awvalid; @@ -133,21 +203,21 @@ wire [32-1:0] _maxi_read_local_stride_fifo; wire [33-1:0] _maxi_read_local_size_fifo; wire [32-1:0] _maxi_read_local_blocksize_fifo; - wire [8-1:0] unpack_read_req_op_sel_0; - wire [32-1:0] unpack_read_req_local_addr_1; - wire [32-1:0] unpack_read_req_local_stride_2; - wire [33-1:0] unpack_read_req_local_size_3; - wire [32-1:0] unpack_read_req_local_blocksize_4; - assign unpack_read_req_op_sel_0 = _maxi_read_req_fifo_rdata[136:129]; - assign unpack_read_req_local_addr_1 = _maxi_read_req_fifo_rdata[128:97]; - assign unpack_read_req_local_stride_2 = _maxi_read_req_fifo_rdata[96:65]; - assign unpack_read_req_local_size_3 = _maxi_read_req_fifo_rdata[64:32]; - assign unpack_read_req_local_blocksize_4 = _maxi_read_req_fifo_rdata[31:0]; - assign _maxi_read_op_sel_fifo = unpack_read_req_op_sel_0; - assign _maxi_read_local_addr_fifo = unpack_read_req_local_addr_1; - assign _maxi_read_local_stride_fifo = unpack_read_req_local_stride_2; - assign _maxi_read_local_size_fifo = unpack_read_req_local_size_3; - assign _maxi_read_local_blocksize_fifo = unpack_read_req_local_blocksize_4; + wire [8-1:0] unpack_read_req_op_sel_30; + wire [32-1:0] unpack_read_req_local_addr_31; + wire [32-1:0] unpack_read_req_local_stride_32; + wire [33-1:0] unpack_read_req_local_size_33; + wire [32-1:0] unpack_read_req_local_blocksize_34; + assign unpack_read_req_op_sel_30 = _maxi_read_req_fifo_rdata[136:129]; + assign unpack_read_req_local_addr_31 = _maxi_read_req_fifo_rdata[128:97]; + assign unpack_read_req_local_stride_32 = _maxi_read_req_fifo_rdata[96:65]; + assign unpack_read_req_local_size_33 = _maxi_read_req_fifo_rdata[64:32]; + assign unpack_read_req_local_blocksize_34 = _maxi_read_req_fifo_rdata[31:0]; + assign _maxi_read_op_sel_fifo = unpack_read_req_op_sel_30; + assign _maxi_read_local_addr_fifo = unpack_read_req_local_addr_31; + assign _maxi_read_local_stride_fifo = unpack_read_req_local_stride_32; + assign _maxi_read_local_size_fifo = unpack_read_req_local_size_33; + assign _maxi_read_local_blocksize_fifo = unpack_read_req_local_blocksize_34; reg [8-1:0] _maxi_read_op_sel_buf; reg [32-1:0] _maxi_read_local_addr_buf; reg [32-1:0] _maxi_read_local_stride_buf; @@ -202,21 +272,21 @@ wire [32-1:0] _maxi_write_local_stride_fifo; wire [33-1:0] _maxi_write_size_fifo; wire [32-1:0] _maxi_write_local_blocksize_fifo; - wire [8-1:0] unpack_write_req_op_sel_5; - wire [32-1:0] unpack_write_req_local_addr_6; - wire [32-1:0] unpack_write_req_local_stride_7; - wire [33-1:0] unpack_write_req_size_8; - wire [32-1:0] unpack_write_req_local_blocksize_9; - assign unpack_write_req_op_sel_5 = _maxi_write_req_fifo_rdata[136:129]; - assign unpack_write_req_local_addr_6 = _maxi_write_req_fifo_rdata[128:97]; - assign unpack_write_req_local_stride_7 = _maxi_write_req_fifo_rdata[96:65]; - assign unpack_write_req_size_8 = _maxi_write_req_fifo_rdata[64:32]; - assign unpack_write_req_local_blocksize_9 = _maxi_write_req_fifo_rdata[31:0]; - assign _maxi_write_op_sel_fifo = unpack_write_req_op_sel_5; - assign _maxi_write_local_addr_fifo = unpack_write_req_local_addr_6; - assign _maxi_write_local_stride_fifo = unpack_write_req_local_stride_7; - assign _maxi_write_size_fifo = unpack_write_req_size_8; - assign _maxi_write_local_blocksize_fifo = unpack_write_req_local_blocksize_9; + wire [8-1:0] unpack_write_req_op_sel_35; + wire [32-1:0] unpack_write_req_local_addr_36; + wire [32-1:0] unpack_write_req_local_stride_37; + wire [33-1:0] unpack_write_req_size_38; + wire [32-1:0] unpack_write_req_local_blocksize_39; + assign unpack_write_req_op_sel_35 = _maxi_write_req_fifo_rdata[136:129]; + assign unpack_write_req_local_addr_36 = _maxi_write_req_fifo_rdata[128:97]; + assign unpack_write_req_local_stride_37 = _maxi_write_req_fifo_rdata[96:65]; + assign unpack_write_req_size_38 = _maxi_write_req_fifo_rdata[64:32]; + assign unpack_write_req_local_blocksize_39 = _maxi_write_req_fifo_rdata[31:0]; + assign _maxi_write_op_sel_fifo = unpack_write_req_op_sel_35; + assign _maxi_write_local_addr_fifo = unpack_write_req_local_addr_36; + assign _maxi_write_local_stride_fifo = unpack_write_req_local_stride_37; + assign _maxi_write_size_fifo = unpack_write_req_size_38; + assign _maxi_write_local_blocksize_fifo = unpack_write_req_local_blocksize_39; reg [8-1:0] _maxi_write_op_sel_buf; reg [32-1:0] _maxi_write_local_addr_buf; reg [32-1:0] _maxi_write_local_stride_buf; @@ -261,42 +331,42 @@ localparam _saxi_shift = 2; reg [32-1:0] _saxi_register_fsm; localparam _saxi_register_fsm_init = 0; - reg [32-1:0] addr_10; - reg writevalid_11; - reg readvalid_12; - reg prev_awvalid_13; - reg prev_arvalid_14; - assign saxi_awready = (_saxi_register_fsm == 0) && (!writevalid_11 && !readvalid_12 && !saxi_bvalid && prev_awvalid_13); - assign saxi_arready = (_saxi_register_fsm == 0) && (!readvalid_12 && !writevalid_11 && prev_arvalid_14 && !prev_awvalid_13); - reg [_saxi_maskwidth-1:0] axis_maskaddr_15; - wire signed [32-1:0] axislite_rdata_16; - assign axislite_rdata_16 = (axis_maskaddr_15 == 0)? _saxi_register_0 : - (axis_maskaddr_15 == 1)? _saxi_register_1 : - (axis_maskaddr_15 == 2)? _saxi_register_2 : - (axis_maskaddr_15 == 3)? _saxi_register_3 : - (axis_maskaddr_15 == 4)? _saxi_register_4 : - (axis_maskaddr_15 == 5)? _saxi_register_5 : - (axis_maskaddr_15 == 6)? _saxi_register_6 : - (axis_maskaddr_15 == 7)? _saxi_register_7 : 'hx; - wire axislite_flag_17; - assign axislite_flag_17 = (axis_maskaddr_15 == 0)? _saxi_flag_0 : - (axis_maskaddr_15 == 1)? _saxi_flag_1 : - (axis_maskaddr_15 == 2)? _saxi_flag_2 : - (axis_maskaddr_15 == 3)? _saxi_flag_3 : - (axis_maskaddr_15 == 4)? _saxi_flag_4 : - (axis_maskaddr_15 == 5)? _saxi_flag_5 : - (axis_maskaddr_15 == 6)? _saxi_flag_6 : - (axis_maskaddr_15 == 7)? _saxi_flag_7 : 'hx; - wire signed [32-1:0] axislite_resetval_18; - assign axislite_resetval_18 = (axis_maskaddr_15 == 0)? _saxi_resetval_0 : - (axis_maskaddr_15 == 1)? _saxi_resetval_1 : - (axis_maskaddr_15 == 2)? _saxi_resetval_2 : - (axis_maskaddr_15 == 3)? _saxi_resetval_3 : - (axis_maskaddr_15 == 4)? _saxi_resetval_4 : - (axis_maskaddr_15 == 5)? _saxi_resetval_5 : - (axis_maskaddr_15 == 6)? _saxi_resetval_6 : - (axis_maskaddr_15 == 7)? _saxi_resetval_7 : 'hx; - reg _saxi_cond_0_1; + reg [32-1:0] addr_40; + reg writevalid_41; + reg readvalid_42; + reg prev_awvalid_43; + reg prev_arvalid_44; + assign saxi_awready = (_saxi_register_fsm == 0) && (!writevalid_41 && !readvalid_42 && !saxi_bvalid && prev_awvalid_43); + assign saxi_arready = (_saxi_register_fsm == 0) && (!readvalid_42 && !writevalid_41 && prev_arvalid_44 && !prev_awvalid_43); + reg [_saxi_maskwidth-1:0] axis_maskaddr_45; + wire signed [32-1:0] axislite_rdata_46; + assign axislite_rdata_46 = (axis_maskaddr_45 == 0)? _saxi_register_0 : + (axis_maskaddr_45 == 1)? _saxi_register_1 : + (axis_maskaddr_45 == 2)? _saxi_register_2 : + (axis_maskaddr_45 == 3)? _saxi_register_3 : + (axis_maskaddr_45 == 4)? _saxi_register_4 : + (axis_maskaddr_45 == 5)? _saxi_register_5 : + (axis_maskaddr_45 == 6)? _saxi_register_6 : + (axis_maskaddr_45 == 7)? _saxi_register_7 : 'hx; + wire axislite_flag_47; + assign axislite_flag_47 = (axis_maskaddr_45 == 0)? _saxi_flag_0 : + (axis_maskaddr_45 == 1)? _saxi_flag_1 : + (axis_maskaddr_45 == 2)? _saxi_flag_2 : + (axis_maskaddr_45 == 3)? _saxi_flag_3 : + (axis_maskaddr_45 == 4)? _saxi_flag_4 : + (axis_maskaddr_45 == 5)? _saxi_flag_5 : + (axis_maskaddr_45 == 6)? _saxi_flag_6 : + (axis_maskaddr_45 == 7)? _saxi_flag_7 : 'hx; + wire signed [32-1:0] axislite_resetval_48; + assign axislite_resetval_48 = (axis_maskaddr_45 == 0)? _saxi_resetval_0 : + (axis_maskaddr_45 == 1)? _saxi_resetval_1 : + (axis_maskaddr_45 == 2)? _saxi_resetval_2 : + (axis_maskaddr_45 == 3)? _saxi_resetval_3 : + (axis_maskaddr_45 == 4)? _saxi_resetval_4 : + (axis_maskaddr_45 == 5)? _saxi_resetval_5 : + (axis_maskaddr_45 == 6)? _saxi_resetval_6 : + (axis_maskaddr_45 == 7)? _saxi_resetval_7 : 'hx; + reg _saxi_rdata_cond_0_1; assign saxi_wready = _saxi_register_fsm == 3; wire _axi_in_read_req_fifo_enq; wire [41-1:0] _axi_in_read_req_fifo_wdata; @@ -325,12 +395,12 @@ reg [4-1:0] count__axi_in_read_req_fifo; wire [8-1:0] _axi_in_read_op_sel_fifo; wire [33-1:0] _axi_in_read_local_size_fifo; - wire [8-1:0] unpack_read_req_op_sel_19; - wire [33-1:0] unpack_read_req_local_size_20; - assign unpack_read_req_op_sel_19 = _axi_in_read_req_fifo_rdata[40:33]; - assign unpack_read_req_local_size_20 = _axi_in_read_req_fifo_rdata[32:0]; - assign _axi_in_read_op_sel_fifo = unpack_read_req_op_sel_19; - assign _axi_in_read_local_size_fifo = unpack_read_req_local_size_20; + wire [8-1:0] unpack_read_req_op_sel_49; + wire [33-1:0] unpack_read_req_local_size_50; + assign unpack_read_req_op_sel_49 = _axi_in_read_req_fifo_rdata[40:33]; + assign unpack_read_req_local_size_50 = _axi_in_read_req_fifo_rdata[32:0]; + assign _axi_in_read_op_sel_fifo = unpack_read_req_op_sel_49; + assign _axi_in_read_local_size_fifo = unpack_read_req_local_size_50; reg [8-1:0] _axi_in_read_op_sel_buf; reg [33-1:0] _axi_in_read_local_size_buf; reg _axi_in_read_data_busy; @@ -365,12 +435,12 @@ reg [4-1:0] count__axi_out_write_req_fifo; wire [8-1:0] _axi_out_write_op_sel_fifo; wire [33-1:0] _axi_out_write_size_fifo; - wire [8-1:0] unpack_write_req_op_sel_21; - wire [33-1:0] unpack_write_req_local_size_22; - assign unpack_write_req_op_sel_21 = _axi_out_write_req_fifo_rdata[40:33]; - assign unpack_write_req_local_size_22 = _axi_out_write_req_fifo_rdata[32:0]; - assign _axi_out_write_op_sel_fifo = unpack_write_req_op_sel_21; - assign _axi_out_write_size_fifo = unpack_write_req_local_size_22; + wire [8-1:0] unpack_write_req_op_sel_51; + wire [33-1:0] unpack_write_req_local_size_52; + assign unpack_write_req_op_sel_51 = _axi_out_write_req_fifo_rdata[40:33]; + assign unpack_write_req_local_size_52 = _axi_out_write_req_fifo_rdata[32:0]; + assign _axi_out_write_op_sel_fifo = unpack_write_req_op_sel_51; + assign _axi_out_write_size_fifo = unpack_write_req_local_size_52; reg [8-1:0] _axi_out_write_op_sel_buf; reg [33-1:0] _axi_out_write_size_buf; reg _axi_out_write_data_busy; @@ -610,117 +680,117 @@ reg signed [32-1:0] _th_comp_write_size_1; reg signed [32-1:0] _th_comp_reduce_size_2; reg signed [32-1:0] _th_comp_bias_addr_3; - wire [32-1:0] mask_addr_shifted_23; - assign mask_addr_shifted_23 = _th_comp_bias_addr_3 >> 2; - wire [32-1:0] mask_addr_masked_24; - assign mask_addr_masked_24 = mask_addr_shifted_23 << 2; + wire [32-1:0] mask_addr_shifted_53; + assign mask_addr_shifted_53 = _th_comp_bias_addr_3 >> 2; + wire [32-1:0] mask_addr_masked_54; + assign mask_addr_masked_54 = mask_addr_shifted_53 << 2; reg [32-1:0] _maxi_read_req_fsm; localparam _maxi_read_req_fsm_init = 0; reg [33-1:0] _maxi_read_cur_global_size; reg _maxi_read_cont; - wire [8-1:0] pack_read_req_op_sel_25; - wire [32-1:0] pack_read_req_local_addr_26; - wire [32-1:0] pack_read_req_local_stride_27; - wire [33-1:0] pack_read_req_local_size_28; - wire [32-1:0] pack_read_req_local_blocksize_29; - assign pack_read_req_op_sel_25 = _maxi_read_op_sel; - assign pack_read_req_local_addr_26 = _maxi_read_local_addr; - assign pack_read_req_local_stride_27 = _maxi_read_local_stride; - assign pack_read_req_local_size_28 = _maxi_read_local_size; - assign pack_read_req_local_blocksize_29 = _maxi_read_local_blocksize; - wire [137-1:0] pack_read_req_packed_30; - assign pack_read_req_packed_30 = { pack_read_req_op_sel_25, pack_read_req_local_addr_26, pack_read_req_local_stride_27, pack_read_req_local_size_28, pack_read_req_local_blocksize_29 }; - assign _maxi_read_req_fifo_wdata = ((_maxi_read_req_fsm == 0) && _maxi_read_start && !_maxi_read_req_fifo_almost_full)? pack_read_req_packed_30 : 'hx; + wire [8-1:0] pack_read_req_op_sel_55; + wire [32-1:0] pack_read_req_local_addr_56; + wire [32-1:0] pack_read_req_local_stride_57; + wire [33-1:0] pack_read_req_local_size_58; + wire [32-1:0] pack_read_req_local_blocksize_59; + assign pack_read_req_op_sel_55 = _maxi_read_op_sel; + assign pack_read_req_local_addr_56 = _maxi_read_local_addr; + assign pack_read_req_local_stride_57 = _maxi_read_local_stride; + assign pack_read_req_local_size_58 = _maxi_read_local_size; + assign pack_read_req_local_blocksize_59 = _maxi_read_local_blocksize; + wire [137-1:0] pack_read_req_packed_60; + assign pack_read_req_packed_60 = { pack_read_req_op_sel_55, pack_read_req_local_addr_56, pack_read_req_local_stride_57, pack_read_req_local_size_58, pack_read_req_local_blocksize_59 }; + assign _maxi_read_req_fifo_wdata = ((_maxi_read_req_fsm == 0) && _maxi_read_start && !_maxi_read_req_fifo_almost_full)? pack_read_req_packed_60 : 'hx; assign _maxi_read_req_fifo_enq = ((_maxi_read_req_fsm == 0) && _maxi_read_start && !_maxi_read_req_fifo_almost_full)? (_maxi_read_req_fsm == 0) && _maxi_read_start && !_maxi_read_req_fifo_almost_full && !_maxi_read_req_fifo_almost_full : 0; - localparam _tmp_31 = 1; - wire [_tmp_31-1:0] _tmp_32; - assign _tmp_32 = !_maxi_read_req_fifo_almost_full; - reg [_tmp_31-1:0] __tmp_32_1; - wire [32-1:0] mask_addr_shifted_33; - assign mask_addr_shifted_33 = _maxi_read_global_addr >> 2; - wire [32-1:0] mask_addr_masked_34; - assign mask_addr_masked_34 = mask_addr_shifted_33 << 2; - wire [32-1:0] mask_addr_shifted_35; - assign mask_addr_shifted_35 = _maxi_read_global_addr >> 2; - wire [32-1:0] mask_addr_masked_36; - assign mask_addr_masked_36 = mask_addr_shifted_35 << 2; - wire [32-1:0] mask_addr_shifted_37; - assign mask_addr_shifted_37 = _maxi_read_global_addr >> 2; - wire [32-1:0] mask_addr_masked_38; - assign mask_addr_masked_38 = mask_addr_shifted_37 << 2; - wire [32-1:0] mask_addr_shifted_39; - assign mask_addr_shifted_39 = _maxi_read_global_addr >> 2; - wire [32-1:0] mask_addr_masked_40; - assign mask_addr_masked_40 = mask_addr_shifted_39 << 2; - wire [32-1:0] mask_addr_shifted_41; - assign mask_addr_shifted_41 = _maxi_read_global_addr >> 2; - wire [32-1:0] mask_addr_masked_42; - assign mask_addr_masked_42 = mask_addr_shifted_41 << 2; - wire [32-1:0] mask_addr_shifted_43; - assign mask_addr_shifted_43 = _maxi_read_global_addr >> 2; - wire [32-1:0] mask_addr_masked_44; - assign mask_addr_masked_44 = mask_addr_shifted_43 << 2; - reg _maxi_cond_0_1; + localparam _tmp_61 = 1; + wire [_tmp_61-1:0] _tmp_62; + assign _tmp_62 = !_maxi_read_req_fifo_almost_full; + reg [_tmp_61-1:0] __tmp_62_1; + wire [32-1:0] mask_addr_shifted_63; + assign mask_addr_shifted_63 = _maxi_read_global_addr >> 2; + wire [32-1:0] mask_addr_masked_64; + assign mask_addr_masked_64 = mask_addr_shifted_63 << 2; + wire [32-1:0] mask_addr_shifted_65; + assign mask_addr_shifted_65 = _maxi_read_global_addr >> 2; + wire [32-1:0] mask_addr_masked_66; + assign mask_addr_masked_66 = mask_addr_shifted_65 << 2; + wire [32-1:0] mask_addr_shifted_67; + assign mask_addr_shifted_67 = _maxi_read_global_addr >> 2; + wire [32-1:0] mask_addr_masked_68; + assign mask_addr_masked_68 = mask_addr_shifted_67 << 2; + wire [32-1:0] mask_addr_shifted_69; + assign mask_addr_shifted_69 = _maxi_read_global_addr >> 2; + wire [32-1:0] mask_addr_masked_70; + assign mask_addr_masked_70 = mask_addr_shifted_69 << 2; + wire [32-1:0] mask_addr_shifted_71; + assign mask_addr_shifted_71 = _maxi_read_global_addr >> 2; + wire [32-1:0] mask_addr_masked_72; + assign mask_addr_masked_72 = mask_addr_shifted_71 << 2; + wire [32-1:0] mask_addr_shifted_73; + assign mask_addr_shifted_73 = _maxi_read_global_addr >> 2; + wire [32-1:0] mask_addr_masked_74; + assign mask_addr_masked_74 = mask_addr_shifted_73 << 2; + reg _maxi_raddr_cond_0_1; reg [32-1:0] _maxi_read_data_fsm; localparam _maxi_read_data_fsm_init = 0; assign _maxi_read_req_fifo_deq = ((_maxi_read_data_fsm == 0) && (!_maxi_read_data_busy && !_maxi_read_req_fifo_empty && (_maxi_read_op_sel_fifo == 1)) && !_maxi_read_req_fifo_empty)? 1 : 0; reg [32-1:0] write_burst_fsm_0; localparam write_burst_fsm_0_init = 0; - reg [10-1:0] write_burst_addr_45; - reg [10-1:0] write_burst_stride_46; - reg [33-1:0] write_burst_length_47; - reg write_burst_done_48; - assign ram_b_0_wdata = ((write_burst_fsm_0 == 1) && maxi_rvalid)? maxi_rdata : 'hx; - assign ram_b_0_wenable = ((write_burst_fsm_0 == 1) && maxi_rvalid)? 1'd1 : 0; - assign maxi_rready = _maxi_read_data_fsm == 2; - wire [8-1:0] pack_read_req_op_sel_49; - wire [33-1:0] pack_read_req_local_size_50; - assign pack_read_req_op_sel_49 = 1; - assign pack_read_req_local_size_50 = _th_comp_read_size_0; - wire [41-1:0] pack_read_req_packed_51; - assign pack_read_req_packed_51 = { pack_read_req_op_sel_49, pack_read_req_local_size_50 }; - assign _axi_in_read_req_fifo_wdata = ((th_comp == 16) && !_axi_in_read_req_fifo_almost_full)? pack_read_req_packed_51 : 'hx; + reg [10-1:0] write_burst_addr_75; + reg [10-1:0] write_burst_stride_76; + reg [33-1:0] write_burst_length_77; + reg write_burst_done_78; + assign ram_b_0_wdata = ((write_burst_fsm_0 == 1) && _maxi_rvalid_sb_0)? _maxi_rdata_sb_0 : 'hx; + assign ram_b_0_wenable = ((write_burst_fsm_0 == 1) && _maxi_rvalid_sb_0)? 1'd1 : 0; + assign _maxi_rready_sb_0 = _maxi_read_data_fsm == 2; + wire [8-1:0] pack_read_req_op_sel_79; + wire [33-1:0] pack_read_req_local_size_80; + assign pack_read_req_op_sel_79 = 1; + assign pack_read_req_local_size_80 = _th_comp_read_size_0; + wire [41-1:0] pack_read_req_packed_81; + assign pack_read_req_packed_81 = { pack_read_req_op_sel_79, pack_read_req_local_size_80 }; + assign _axi_in_read_req_fifo_wdata = ((th_comp == 16) && !_axi_in_read_req_fifo_almost_full)? pack_read_req_packed_81 : 'hx; assign _axi_in_read_req_fifo_enq = ((th_comp == 16) && !_axi_in_read_req_fifo_almost_full)? (th_comp == 16) && !_axi_in_read_req_fifo_almost_full && !_axi_in_read_req_fifo_almost_full : 0; - localparam _tmp_52 = 1; - wire [_tmp_52-1:0] _tmp_53; - assign _tmp_53 = !_axi_in_read_req_fifo_almost_full; - reg [_tmp_52-1:0] __tmp_53_1; + localparam _tmp_82 = 1; + wire [_tmp_82-1:0] _tmp_83; + assign _tmp_83 = !_axi_in_read_req_fifo_almost_full; + reg [_tmp_82-1:0] __tmp_83_1; reg [32-1:0] _axi_in_read_data_fsm; localparam _axi_in_read_data_fsm_init = 0; assign _axi_in_read_req_fifo_deq = ((_axi_in_read_data_fsm == 0) && (!_axi_in_read_data_busy && !_axi_in_read_req_fifo_empty && (_axi_in_read_op_sel_fifo == 1)) && !_axi_in_read_req_fifo_empty)? 1 : 0; assign axi_in_tready = (_axi_in_read_data_fsm == 1) && !fifo_a_almost_full && (_axi_in_read_op_sel_buf == 1); assign fifo_a_wdata = ((_axi_in_read_data_fsm == 1) && axi_in_tvalid && !fifo_a_almost_full && (_axi_in_read_op_sel_buf == 1))? axi_in_tdata : 'hx; assign fifo_a_enq = ((_axi_in_read_data_fsm == 1) && axi_in_tvalid && !fifo_a_almost_full && (_axi_in_read_op_sel_buf == 1))? (_axi_in_read_data_fsm == 1) && axi_in_tvalid && !fifo_a_almost_full && (_axi_in_read_op_sel_buf == 1) && !fifo_a_almost_full : 0; - localparam _tmp_54 = 1; - wire [_tmp_54-1:0] _tmp_55; - assign _tmp_55 = !fifo_a_almost_full; - reg [_tmp_54-1:0] __tmp_55_1; - wire axistreamout_flag_56; - assign axistreamout_flag_56 = th_comp == 17; - wire [8-1:0] pack_write_req_op_sel_57; - wire [33-1:0] pack_write_req_local_size_58; - assign pack_write_req_op_sel_57 = 1; - assign pack_write_req_local_size_58 = _th_comp_write_size_1; - wire [41-1:0] pack_write_req_packed_59; - assign pack_write_req_packed_59 = { pack_write_req_op_sel_57, pack_write_req_local_size_58 }; - assign _axi_out_write_req_fifo_wdata = (axistreamout_flag_56 && !_axi_out_write_req_fifo_almost_full)? pack_write_req_packed_59 : 'hx; - assign _axi_out_write_req_fifo_enq = (axistreamout_flag_56 && !_axi_out_write_req_fifo_almost_full)? axistreamout_flag_56 && !_axi_out_write_req_fifo_almost_full && !_axi_out_write_req_fifo_almost_full : 0; - localparam _tmp_60 = 1; - wire [_tmp_60-1:0] _tmp_61; - assign _tmp_61 = !_axi_out_write_req_fifo_almost_full; - reg [_tmp_60-1:0] __tmp_61_1; + localparam _tmp_84 = 1; + wire [_tmp_84-1:0] _tmp_85; + assign _tmp_85 = !fifo_a_almost_full; + reg [_tmp_84-1:0] __tmp_85_1; + wire axistreamout_flag_86; + assign axistreamout_flag_86 = th_comp == 17; + wire [8-1:0] pack_write_req_op_sel_87; + wire [33-1:0] pack_write_req_local_size_88; + assign pack_write_req_op_sel_87 = 1; + assign pack_write_req_local_size_88 = _th_comp_write_size_1; + wire [41-1:0] pack_write_req_packed_89; + assign pack_write_req_packed_89 = { pack_write_req_op_sel_87, pack_write_req_local_size_88 }; + assign _axi_out_write_req_fifo_wdata = (axistreamout_flag_86 && !_axi_out_write_req_fifo_almost_full)? pack_write_req_packed_89 : 'hx; + assign _axi_out_write_req_fifo_enq = (axistreamout_flag_86 && !_axi_out_write_req_fifo_almost_full)? axistreamout_flag_86 && !_axi_out_write_req_fifo_almost_full && !_axi_out_write_req_fifo_almost_full : 0; + localparam _tmp_90 = 1; + wire [_tmp_90-1:0] _tmp_91; + assign _tmp_91 = !_axi_out_write_req_fifo_almost_full; + reg [_tmp_90-1:0] __tmp_91_1; reg [32-1:0] _axi_out_write_data_fsm; localparam _axi_out_write_data_fsm_init = 0; assign _axi_out_write_req_fifo_deq = ((_axi_out_write_data_fsm == 0) && (!_axi_out_write_data_busy && !_axi_out_write_req_fifo_empty && (_axi_out_write_op_sel_fifo == 1)) && !_axi_out_write_req_fifo_empty)? 1 : 0; - reg rlast_62; - wire cur_rvalid_63; + reg rlast_92; + wire cur_rvalid_93; assign fifo_c_deq = ((_axi_out_write_data_fsm == 1) && !fifo_c_empty && (_axi_out_write_op_sel_buf == 1) && (_axi_out_write_size_buf > 0) && (axi_out_tready || !axi_out_tvalid) && !fifo_c_empty)? 1 : 0; - localparam _tmp_64 = 1; - wire [_tmp_64-1:0] _tmp_65; - assign _tmp_65 = (_axi_out_write_data_fsm == 1) && !fifo_c_empty && (_axi_out_write_op_sel_buf == 1) && (_axi_out_write_size_buf > 0) && (axi_out_tready || !axi_out_tvalid) && !fifo_c_empty; - reg [_tmp_64-1:0] __tmp_65_1; - reg repeat_rvalid_66; - assign cur_rvalid_63 = __tmp_65_1 || repeat_rvalid_66; + localparam _tmp_94 = 1; + wire [_tmp_94-1:0] _tmp_95; + assign _tmp_95 = (_axi_out_write_data_fsm == 1) && !fifo_c_empty && (_axi_out_write_op_sel_buf == 1) && (_axi_out_write_size_buf > 0) && (axi_out_tready || !axi_out_tvalid) && !fifo_c_empty; + reg [_tmp_94-1:0] __tmp_95_1; + reg repeat_rvalid_96; + assign cur_rvalid_93 = __tmp_95_1 || repeat_rvalid_96; reg _axi_out_cond_0_1; wire signed [32-1:0] mystream_reduce_a_data; wire signed [32-1:0] mystream_reduce_reduce_size_data; @@ -774,42 +844,42 @@ assign mystream_reduce_sum_data = _reduceadd_data_4; wire [1-1:0] mystream_reduce_sum_valid_data; assign mystream_reduce_sum_valid_data = _pulse_data_6; - wire _set_flag_67; - assign _set_flag_67 = th_comp == 18; + wire _set_flag_97; + assign _set_flag_97 = th_comp == 18; assign fifo_a_deq = (_mystream_reduce_stream_oready && _mystream_reduce_a_source_fifo_deq && (_mystream_reduce_a_source_sel == 1) && !fifo_a_empty)? 1 : 0; - localparam _tmp_68 = 1; - wire [_tmp_68-1:0] _tmp_69; - assign _tmp_69 = _mystream_reduce_stream_oready && _mystream_reduce_a_source_fifo_deq && (_mystream_reduce_a_source_sel == 1) && !fifo_a_empty; - reg [_tmp_68-1:0] __tmp_69_1; + localparam _tmp_98 = 1; + wire [_tmp_98-1:0] _tmp_99; + assign _tmp_99 = _mystream_reduce_stream_oready && _mystream_reduce_a_source_fifo_deq && (_mystream_reduce_a_source_sel == 1) && !fifo_a_empty; + reg [_tmp_98-1:0] __tmp_99_1; assign _mystream_reduce_a_source_fifo_rdata = (_mystream_reduce_a_source_sel == 1)? fifo_a_rdata : 'hx; reg signed [32-1:0] __variable_wdata_0; assign mystream_reduce_a_data = __variable_wdata_0; reg [32-1:0] _mystream_reduce_a_source_fsm_0; localparam _mystream_reduce_a_source_fsm_0_init = 0; - wire _set_flag_70; - assign _set_flag_70 = th_comp == 19; + wire _set_flag_100; + assign _set_flag_100 = th_comp == 19; reg signed [32-1:0] __variable_wdata_1; assign mystream_reduce_reduce_size_data = __variable_wdata_1; - wire _set_flag_71; - assign _set_flag_71 = th_comp == 20; - reg _tmp_72; - reg _tmp_73; - reg _tmp_74; - reg _tmp_75; - reg _tmp_76; - reg _tmp_77; - reg signed [32-1:0] _tmp_78; - reg signed [32-1:0] _tmp_79; - reg signed [32-1:0] _tmp_80; - reg signed [32-1:0] _tmp_81; - reg signed [32-1:0] _tmp_82; - reg signed [32-1:0] _tmp_83; + wire _set_flag_101; + assign _set_flag_101 = th_comp == 20; + reg _tmp_102; + reg _tmp_103; + reg _tmp_104; + reg _tmp_105; + reg _tmp_106; + reg _tmp_107; + reg signed [32-1:0] _tmp_108; + reg signed [32-1:0] _tmp_109; + reg signed [32-1:0] _tmp_110; + reg signed [32-1:0] _tmp_111; + reg signed [32-1:0] _tmp_112; + reg signed [32-1:0] _tmp_113; assign fifo_b_wdata = (_mystream_reduce_stream_oready && _mystream_reduce_sum_sink_fifo_enq && (_mystream_reduce_sum_sink_sel == 2))? _mystream_reduce_sum_sink_fifo_wdata : 'hx; assign fifo_b_enq = (_mystream_reduce_stream_oready && _mystream_reduce_sum_sink_fifo_enq && (_mystream_reduce_sum_sink_sel == 2))? _mystream_reduce_stream_oready && _mystream_reduce_sum_sink_fifo_enq && (_mystream_reduce_sum_sink_sel == 2) && !fifo_b_almost_full : 0; - localparam _tmp_84 = 1; - wire [_tmp_84-1:0] _tmp_85; - assign _tmp_85 = !fifo_b_almost_full; - reg [_tmp_84-1:0] __tmp_85_1; + localparam _tmp_114 = 1; + wire [_tmp_114-1:0] _tmp_115; + assign _tmp_115 = !fifo_b_almost_full; + reg [_tmp_114-1:0] __tmp_115_1; assign _mystream_reduce_stream_oready = ((_mystream_reduce_sink_busy && (_mystream_reduce_sum_sink_sel == 2))? !fifo_b_almost_full : 1) && (((_mystream_reduce_source_busy && (_mystream_reduce_a_source_sel == 1))? !fifo_a_empty || _mystream_reduce_a_idle : 1) && _mystream_reduce_stream_internal_oready); reg [32-1:0] _mystream_reduce_sum_sink_fsm_1; localparam _mystream_reduce_sum_sink_fsm_1_init = 0; @@ -819,135 +889,223 @@ reg signed [32-1:0] _plus_data_10; wire signed [32-1:0] mystream_bias_z_data; assign mystream_bias_z_data = _plus_data_10; - wire _set_flag_86; - assign _set_flag_86 = th_comp == 21; + wire _set_flag_116; + assign _set_flag_116 = th_comp == 21; assign fifo_b_deq = (_mystream_bias_stream_oready && _mystream_bias_x_source_fifo_deq && (_mystream_bias_x_source_sel == 1) && !fifo_b_empty)? 1 : 0; - localparam _tmp_87 = 1; - wire [_tmp_87-1:0] _tmp_88; - assign _tmp_88 = _mystream_bias_stream_oready && _mystream_bias_x_source_fifo_deq && (_mystream_bias_x_source_sel == 1) && !fifo_b_empty; - reg [_tmp_87-1:0] __tmp_88_1; + localparam _tmp_117 = 1; + wire [_tmp_117-1:0] _tmp_118; + assign _tmp_118 = _mystream_bias_stream_oready && _mystream_bias_x_source_fifo_deq && (_mystream_bias_x_source_sel == 1) && !fifo_b_empty; + reg [_tmp_117-1:0] __tmp_118_1; assign _mystream_bias_x_source_fifo_rdata = (_mystream_bias_x_source_sel == 1)? fifo_b_rdata : 'hx; reg signed [32-1:0] __variable_wdata_8; assign mystream_bias_x_data = __variable_wdata_8; reg [32-1:0] _mystream_bias_x_source_fsm_0; localparam _mystream_bias_x_source_fsm_0_init = 0; - wire _set_flag_89; - assign _set_flag_89 = th_comp == 22; + wire _set_flag_119; + assign _set_flag_119 = th_comp == 22; assign ram_b_0_addr = (_mystream_bias_stream_oready && _mystream_bias_y_source_ram_renable && (_mystream_bias_y_source_sel == 2))? _mystream_bias_y_source_ram_raddr : - ((write_burst_fsm_0 == 1) && maxi_rvalid)? write_burst_addr_45 : 'hx; + ((write_burst_fsm_0 == 1) && _maxi_rvalid_sb_0)? write_burst_addr_75 : 'hx; assign ram_b_0_enable = (_mystream_bias_stream_oready && _mystream_bias_y_source_ram_renable && (_mystream_bias_y_source_sel == 2))? 1'd1 : - ((write_burst_fsm_0 == 1) && maxi_rvalid)? 1'd1 : 0; - localparam _tmp_90 = 1; - wire [_tmp_90-1:0] _tmp_91; - assign _tmp_91 = _mystream_bias_stream_oready && _mystream_bias_y_source_ram_renable && (_mystream_bias_y_source_sel == 2); - reg [_tmp_90-1:0] __tmp_91_1; + ((write_burst_fsm_0 == 1) && _maxi_rvalid_sb_0)? 1'd1 : 0; + localparam _tmp_120 = 1; + wire [_tmp_120-1:0] _tmp_121; + assign _tmp_121 = _mystream_bias_stream_oready && _mystream_bias_y_source_ram_renable && (_mystream_bias_y_source_sel == 2); + reg [_tmp_120-1:0] __tmp_121_1; assign _mystream_bias_y_source_ram_rdata = (_mystream_bias_y_source_sel == 2)? ram_b_0_rdata : 'hx; reg signed [32-1:0] __variable_wdata_9; assign mystream_bias_y_data = __variable_wdata_9; reg [32-1:0] _mystream_bias_y_source_fsm_1; localparam _mystream_bias_y_source_fsm_1_init = 0; - wire _set_flag_92; - assign _set_flag_92 = th_comp == 23; - reg _tmp_93; - reg _tmp_94; - reg _tmp_95; - reg signed [32-1:0] _tmp_96; - reg signed [32-1:0] _tmp_97; - reg signed [32-1:0] _tmp_98; + wire _set_flag_122; + assign _set_flag_122 = th_comp == 23; + reg _tmp_123; + reg _tmp_124; + reg _tmp_125; + reg signed [32-1:0] _tmp_126; + reg signed [32-1:0] _tmp_127; + reg signed [32-1:0] _tmp_128; assign fifo_c_wdata = (_mystream_bias_stream_oready && _mystream_bias_z_sink_fifo_enq && (_mystream_bias_z_sink_sel == 3))? _mystream_bias_z_sink_fifo_wdata : 'hx; assign fifo_c_enq = (_mystream_bias_stream_oready && _mystream_bias_z_sink_fifo_enq && (_mystream_bias_z_sink_sel == 3))? _mystream_bias_stream_oready && _mystream_bias_z_sink_fifo_enq && (_mystream_bias_z_sink_sel == 3) && !fifo_c_almost_full : 0; - localparam _tmp_99 = 1; - wire [_tmp_99-1:0] _tmp_100; - assign _tmp_100 = !fifo_c_almost_full; - reg [_tmp_99-1:0] __tmp_100_1; + localparam _tmp_129 = 1; + wire [_tmp_129-1:0] _tmp_130; + assign _tmp_130 = !fifo_c_almost_full; + reg [_tmp_129-1:0] __tmp_130_1; assign _mystream_bias_stream_oready = ((_mystream_bias_sink_busy && (_mystream_bias_z_sink_sel == 3))? !fifo_c_almost_full : 1) && (((_mystream_bias_source_busy && (_mystream_bias_x_source_sel == 1))? !fifo_b_empty || _mystream_bias_x_idle : 1) && _mystream_bias_stream_internal_oready); reg [32-1:0] _mystream_bias_z_sink_fsm_2; localparam _mystream_bias_z_sink_fsm_2_init = 0; - wire _set_flag_101; - assign _set_flag_101 = th_comp == 24; - assign _mystream_reduce_run_flag = (_set_flag_101)? 1 : 0; - reg _tmp_102; - reg _tmp_103; - reg _tmp_104; - reg _tmp_105; - reg _tmp_106; - reg _tmp_107; - reg [1-1:0] __variable_wdata_3; - assign mystream_reduce__reduce_reset_data = __variable_wdata_3; - reg _tmp_108; - reg _tmp_109; - reg _tmp_110; - reg _tmp_111; - assign _mystream_reduce_source_stop = _mystream_reduce_stream_oready && (_mystream_reduce_a_idle && (_mystream_reduce_fsm == 3)); - localparam _tmp_112 = 1; - wire [_tmp_112-1:0] _tmp_113; - assign _tmp_113 = _mystream_reduce_a_idle && (_mystream_reduce_fsm == 3); - reg [_tmp_112-1:0] _tmp_114; - localparam _tmp_115 = 1; - wire [_tmp_115-1:0] _tmp_116; - assign _tmp_116 = _mystream_reduce_a_idle && (_mystream_reduce_fsm == 3); - reg [_tmp_115-1:0] _tmp_117; - reg _tmp_118; - reg _tmp_119; - reg _tmp_120; - reg _tmp_121; - reg _tmp_122; - reg _tmp_123; - assign _mystream_reduce_sink_start = _tmp_123; - reg _tmp_124; - reg _tmp_125; - reg _tmp_126; - reg _tmp_127; - reg _tmp_128; - reg _tmp_129; - assign _mystream_reduce_sink_stop = _tmp_129; - reg _tmp_130; - reg _tmp_131; + wire _set_flag_131; + assign _set_flag_131 = th_comp == 24; + assign _mystream_reduce_run_flag = (_set_flag_131)? 1 : 0; reg _tmp_132; reg _tmp_133; reg _tmp_134; reg _tmp_135; - assign _mystream_reduce_sink_busy = _tmp_135; reg _tmp_136; - assign _mystream_reduce_busy = _mystream_reduce_source_busy || _mystream_reduce_sink_busy || _mystream_reduce_busy_reg; - wire _set_flag_137; - assign _set_flag_137 = th_comp == 26; - assign _mystream_bias_run_flag = (_set_flag_137)? 1 : 0; + reg _tmp_137; + reg [1-1:0] __variable_wdata_3; + assign mystream_reduce__reduce_reset_data = __variable_wdata_3; reg _tmp_138; reg _tmp_139; reg _tmp_140; - assign _mystream_bias_source_stop = _mystream_bias_stream_oready && (_mystream_bias_x_idle && _mystream_bias_y_idle && (_mystream_bias_fsm == 3)); - localparam _tmp_141 = 1; - wire [_tmp_141-1:0] _tmp_142; - assign _tmp_142 = _mystream_bias_x_idle && _mystream_bias_y_idle && (_mystream_bias_fsm == 3); - reg [_tmp_141-1:0] _tmp_143; - reg _tmp_144; - reg _tmp_145; - reg _tmp_146; - assign _mystream_bias_sink_start = _tmp_146; - reg _tmp_147; + reg _tmp_141; + assign _mystream_reduce_source_stop = _mystream_reduce_stream_oready && (_mystream_reduce_a_idle && (_mystream_reduce_fsm == 3)); + localparam _tmp_142 = 1; + wire [_tmp_142-1:0] _tmp_143; + assign _tmp_143 = _mystream_reduce_a_idle && (_mystream_reduce_fsm == 3); + reg [_tmp_142-1:0] _tmp_144; + localparam _tmp_145 = 1; + wire [_tmp_145-1:0] _tmp_146; + assign _tmp_146 = _mystream_reduce_a_idle && (_mystream_reduce_fsm == 3); + reg [_tmp_145-1:0] _tmp_147; reg _tmp_148; reg _tmp_149; - assign _mystream_bias_sink_stop = _tmp_149; reg _tmp_150; reg _tmp_151; reg _tmp_152; - assign _mystream_bias_sink_busy = _tmp_152; reg _tmp_153; + assign _mystream_reduce_sink_start = _tmp_153; + reg _tmp_154; + reg _tmp_155; + reg _tmp_156; + reg _tmp_157; + reg _tmp_158; + reg _tmp_159; + assign _mystream_reduce_sink_stop = _tmp_159; + reg _tmp_160; + reg _tmp_161; + reg _tmp_162; + reg _tmp_163; + reg _tmp_164; + reg _tmp_165; + assign _mystream_reduce_sink_busy = _tmp_165; + reg _tmp_166; + assign _mystream_reduce_busy = _mystream_reduce_source_busy || _mystream_reduce_sink_busy || _mystream_reduce_busy_reg; + wire _set_flag_167; + assign _set_flag_167 = th_comp == 26; + assign _mystream_bias_run_flag = (_set_flag_167)? 1 : 0; + reg _tmp_168; + reg _tmp_169; + reg _tmp_170; + assign _mystream_bias_source_stop = _mystream_bias_stream_oready && (_mystream_bias_x_idle && _mystream_bias_y_idle && (_mystream_bias_fsm == 3)); + localparam _tmp_171 = 1; + wire [_tmp_171-1:0] _tmp_172; + assign _tmp_172 = _mystream_bias_x_idle && _mystream_bias_y_idle && (_mystream_bias_fsm == 3); + reg [_tmp_171-1:0] _tmp_173; + reg _tmp_174; + reg _tmp_175; + reg _tmp_176; + assign _mystream_bias_sink_start = _tmp_176; + reg _tmp_177; + reg _tmp_178; + reg _tmp_179; + assign _mystream_bias_sink_stop = _tmp_179; + reg _tmp_180; + reg _tmp_181; + reg _tmp_182; + assign _mystream_bias_sink_busy = _tmp_182; + reg _tmp_183; assign _mystream_bias_busy = _mystream_bias_source_busy || _mystream_bias_sink_busy || _mystream_bias_busy_reg; always @(posedge CLK) begin if(RST) begin - _maxi_outstanding_wcount <= 0; - _maxi_read_start <= 0; - _maxi_write_start <= 0; maxi_awaddr <= 0; maxi_awlen <= 0; maxi_awvalid <= 0; - maxi_wdata <= 0; - maxi_wstrb <= 0; - maxi_wlast <= 0; - maxi_wvalid <= 0; + end else begin + maxi_awaddr <= 0; + maxi_awlen <= 0; + maxi_awvalid <= 0; + end + end + + + always @(posedge CLK) begin + if(RST) begin + _maxi_wdata_sb_0 <= 0; + _maxi_wstrb_sb_0 <= 0; + _maxi_wlast_sb_0 <= 0; + _maxi_wvalid_sb_0 <= 0; + end else begin + _maxi_wdata_sb_0 <= 0; + _maxi_wstrb_sb_0 <= 0; + _maxi_wlast_sb_0 <= 0; + _maxi_wvalid_sb_0 <= 0; + end + end + + + always @(posedge CLK) begin + if(RST) begin + _sb_maxi_writedata_data_6 <= 0; + _sb_maxi_writedata_valid_7 <= 0; + _sb_maxi_writedata_tmp_data_9 <= 0; + _sb_maxi_writedata_tmp_valid_10 <= 0; + end else begin + if(_sb_maxi_writedata_m_ready_5 || !_sb_maxi_writedata_valid_7) begin + _sb_maxi_writedata_data_6 <= _sb_maxi_writedata_next_data_11; + _sb_maxi_writedata_valid_7 <= _sb_maxi_writedata_next_valid_12; + end + if(!_sb_maxi_writedata_tmp_valid_10 && _sb_maxi_writedata_valid_7 && !_sb_maxi_writedata_m_ready_5) begin + _sb_maxi_writedata_tmp_data_9 <= _sb_maxi_writedata_s_data_3; + _sb_maxi_writedata_tmp_valid_10 <= _sb_maxi_writedata_s_valid_4; + end + if(_sb_maxi_writedata_tmp_valid_10 && _sb_maxi_writedata_m_ready_5) begin + _sb_maxi_writedata_tmp_valid_10 <= 0; + end + end + end + + + always @(posedge CLK) begin + if(RST) begin + maxi_araddr <= 0; + maxi_arlen <= 0; + maxi_arvalid <= 0; + _maxi_raddr_cond_0_1 <= 0; + end else begin + if(_maxi_raddr_cond_0_1) begin + maxi_arvalid <= 0; + end + if((_maxi_read_req_fsm == 1) && (maxi_arready || !maxi_arvalid)) begin + maxi_araddr <= _maxi_read_global_addr; + maxi_arlen <= _maxi_read_cur_global_size - 1; + maxi_arvalid <= 1; + end + _maxi_raddr_cond_0_1 <= 1; + if(maxi_arvalid && !maxi_arready) begin + maxi_arvalid <= maxi_arvalid; + end + end + end + + + always @(posedge CLK) begin + if(RST) begin + _sb_maxi_readdata_data_21 <= 0; + _sb_maxi_readdata_valid_22 <= 0; + _sb_maxi_readdata_tmp_data_24 <= 0; + _sb_maxi_readdata_tmp_valid_25 <= 0; + end else begin + if(_sb_maxi_readdata_m_ready_20 || !_sb_maxi_readdata_valid_22) begin + _sb_maxi_readdata_data_21 <= _sb_maxi_readdata_next_data_26; + _sb_maxi_readdata_valid_22 <= _sb_maxi_readdata_next_valid_27; + end + if(!_sb_maxi_readdata_tmp_valid_25 && _sb_maxi_readdata_valid_22 && !_sb_maxi_readdata_m_ready_20) begin + _sb_maxi_readdata_tmp_data_24 <= _sb_maxi_readdata_s_data_18; + _sb_maxi_readdata_tmp_valid_25 <= _sb_maxi_readdata_s_valid_19; + end + if(_sb_maxi_readdata_tmp_valid_25 && _sb_maxi_readdata_m_ready_20) begin + _sb_maxi_readdata_tmp_valid_25 <= 0; + end + end + end + + + always @(posedge CLK) begin + if(RST) begin + _maxi_outstanding_wcount <= 0; + _maxi_read_start <= 0; + _maxi_write_start <= 0; _maxi_read_op_sel <= 0; _maxi_read_global_addr <= 0; _maxi_read_global_size <= 0; @@ -957,10 +1115,6 @@ _maxi_read_local_blocksize <= 0; _maxi_read_req_busy <= 0; _maxi_read_cur_global_size <= 0; - maxi_araddr <= 0; - maxi_arlen <= 0; - maxi_arvalid <= 0; - _maxi_cond_0_1 <= 0; _maxi_read_data_busy <= 0; _maxi_read_op_sel_buf <= 0; _maxi_read_local_addr_buf <= 0; @@ -968,9 +1122,6 @@ _maxi_read_local_size_buf <= 0; _maxi_read_local_blocksize_buf <= 0; end else begin - if(_maxi_cond_0_1) begin - maxi_arvalid <= 0; - end if(maxi_awvalid && maxi_awready && !(maxi_bvalid && maxi_bready) && (_maxi_outstanding_wcount < 7)) begin _maxi_outstanding_wcount <= _maxi_outstanding_wcount + 1; end @@ -979,17 +1130,10 @@ end _maxi_read_start <= 0; _maxi_write_start <= 0; - maxi_awaddr <= 0; - maxi_awlen <= 0; - maxi_awvalid <= 0; - maxi_wdata <= 0; - maxi_wstrb <= 0; - maxi_wlast <= 0; - maxi_wvalid <= 0; if((th_comp == 14) && _maxi_read_req_idle) begin _maxi_read_start <= 1; _maxi_read_op_sel <= 1; - _maxi_read_global_addr <= mask_addr_masked_24; + _maxi_read_global_addr <= mask_addr_masked_54; _maxi_read_global_size <= _th_comp_write_size_1; _maxi_read_local_addr <= 0; _maxi_read_local_stride <= 1; @@ -1002,28 +1146,19 @@ if(_maxi_read_start && _maxi_read_req_fifo_almost_full) begin _maxi_read_start <= 1; end - if((_maxi_read_req_fsm == 0) && (_maxi_read_start || _maxi_read_cont) && !_maxi_read_req_fifo_almost_full && (_maxi_read_global_size <= 256) && ((mask_addr_masked_34 & 4095) + (_maxi_read_global_size << 2) >= 4096)) begin - _maxi_read_cur_global_size <= 4096 - (mask_addr_masked_36 & 4095) >> 2; - _maxi_read_global_size <= _maxi_read_global_size - (4096 - (mask_addr_masked_38 & 4095) >> 2); + if((_maxi_read_req_fsm == 0) && (_maxi_read_start || _maxi_read_cont) && !_maxi_read_req_fifo_almost_full && (_maxi_read_global_size <= 256) && ((mask_addr_masked_64 & 4095) + (_maxi_read_global_size << 2) >= 4096)) begin + _maxi_read_cur_global_size <= 4096 - (mask_addr_masked_66 & 4095) >> 2; + _maxi_read_global_size <= _maxi_read_global_size - (4096 - (mask_addr_masked_68 & 4095) >> 2); end else if((_maxi_read_req_fsm == 0) && (_maxi_read_start || _maxi_read_cont) && !_maxi_read_req_fifo_almost_full && (_maxi_read_global_size <= 256)) begin _maxi_read_cur_global_size <= _maxi_read_global_size; _maxi_read_global_size <= 0; - end else if((_maxi_read_req_fsm == 0) && (_maxi_read_start || _maxi_read_cont) && !_maxi_read_req_fifo_almost_full && ((mask_addr_masked_40 & 4095) + 1024 >= 4096)) begin - _maxi_read_cur_global_size <= 4096 - (mask_addr_masked_42 & 4095) >> 2; - _maxi_read_global_size <= _maxi_read_global_size - (4096 - (mask_addr_masked_44 & 4095) >> 2); + end else if((_maxi_read_req_fsm == 0) && (_maxi_read_start || _maxi_read_cont) && !_maxi_read_req_fifo_almost_full && ((mask_addr_masked_70 & 4095) + 1024 >= 4096)) begin + _maxi_read_cur_global_size <= 4096 - (mask_addr_masked_72 & 4095) >> 2; + _maxi_read_global_size <= _maxi_read_global_size - (4096 - (mask_addr_masked_74 & 4095) >> 2); end else if((_maxi_read_req_fsm == 0) && (_maxi_read_start || _maxi_read_cont) && !_maxi_read_req_fifo_almost_full) begin _maxi_read_cur_global_size <= 256; _maxi_read_global_size <= _maxi_read_global_size - 256; end - if((_maxi_read_req_fsm == 1) && (maxi_arready || !maxi_arvalid)) begin - maxi_araddr <= _maxi_read_global_addr; - maxi_arlen <= _maxi_read_cur_global_size - 1; - maxi_arvalid <= 1; - end - _maxi_cond_0_1 <= 1; - if(maxi_arvalid && !maxi_arready) begin - maxi_arvalid <= maxi_arvalid; - end if((_maxi_read_req_fsm == 1) && (maxi_arready || !maxi_arvalid)) begin _maxi_read_global_addr <= _maxi_read_global_addr + (_maxi_read_cur_global_size << 2); end @@ -1038,10 +1173,10 @@ _maxi_read_local_size_buf <= _maxi_read_local_size_fifo; _maxi_read_local_blocksize_buf <= _maxi_read_local_blocksize_fifo; end - if((_maxi_read_data_fsm == 2) && maxi_rvalid) begin + if((_maxi_read_data_fsm == 2) && _maxi_rvalid_sb_0) begin _maxi_read_local_size_buf <= _maxi_read_local_size_buf - 1; end - if((_maxi_read_data_fsm == 2) && maxi_rvalid && (_maxi_read_local_size_buf <= 1)) begin + if((_maxi_read_data_fsm == 2) && _maxi_rvalid_sb_0 && (_maxi_read_local_size_buf <= 1)) begin _maxi_read_data_busy <= 0; end end @@ -1051,7 +1186,7 @@ always @(posedge CLK) begin if(RST) begin count__maxi_read_req_fifo <= 0; - __tmp_32_1 <= 0; + __tmp_62_1 <= 0; end else begin if(_maxi_read_req_fifo_enq && !_maxi_read_req_fifo_full && (_maxi_read_req_fifo_deq && !_maxi_read_req_fifo_empty)) begin count__maxi_read_req_fifo <= count__maxi_read_req_fifo; @@ -1060,7 +1195,7 @@ end else if(_maxi_read_req_fifo_deq && !_maxi_read_req_fifo_empty) begin count__maxi_read_req_fifo <= count__maxi_read_req_fifo - 1; end - __tmp_32_1 <= _tmp_32; + __tmp_62_1 <= _tmp_62; end end @@ -1082,15 +1217,33 @@ always @(posedge CLK) begin if(RST) begin - saxi_bvalid <= 0; - prev_awvalid_13 <= 0; - prev_arvalid_14 <= 0; - writevalid_11 <= 0; - readvalid_12 <= 0; - addr_10 <= 0; saxi_rdata <= 0; saxi_rvalid <= 0; - _saxi_cond_0_1 <= 0; + _saxi_rdata_cond_0_1 <= 0; + end else begin + if(_saxi_rdata_cond_0_1) begin + saxi_rvalid <= 0; + end + if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid)) begin + saxi_rdata <= axislite_rdata_46; + saxi_rvalid <= 1; + end + _saxi_rdata_cond_0_1 <= 1; + if(saxi_rvalid && !saxi_rready) begin + saxi_rvalid <= saxi_rvalid; + end + end + end + + + always @(posedge CLK) begin + if(RST) begin + saxi_bvalid <= 0; + prev_awvalid_43 <= 0; + prev_arvalid_44 <= 0; + writevalid_41 <= 0; + readvalid_42 <= 0; + addr_40 <= 0; _saxi_register_0 <= 0; _saxi_flag_0 <= 0; _saxi_register_1 <= 0; @@ -1108,88 +1261,77 @@ _saxi_register_7 <= 0; _saxi_flag_7 <= 0; end else begin - if(_saxi_cond_0_1) begin - saxi_rvalid <= 0; - end if(saxi_bvalid && saxi_bready) begin saxi_bvalid <= 0; end if(saxi_wvalid && saxi_wready) begin saxi_bvalid <= 1; end - prev_awvalid_13 <= saxi_awvalid; - prev_arvalid_14 <= saxi_arvalid; - writevalid_11 <= 0; - readvalid_12 <= 0; + prev_awvalid_43 <= saxi_awvalid; + prev_arvalid_44 <= saxi_arvalid; + writevalid_41 <= 0; + readvalid_42 <= 0; if(saxi_awready && saxi_awvalid && !saxi_bvalid) begin - addr_10 <= saxi_awaddr; - writevalid_11 <= 1; + addr_40 <= saxi_awaddr; + writevalid_41 <= 1; end else if(saxi_arready && saxi_arvalid) begin - addr_10 <= saxi_araddr; - readvalid_12 <= 1; + addr_40 <= saxi_araddr; + readvalid_42 <= 1; end - if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid)) begin - saxi_rdata <= axislite_rdata_16; - saxi_rvalid <= 1; - end - _saxi_cond_0_1 <= 1; - if(saxi_rvalid && !saxi_rready) begin - saxi_rvalid <= saxi_rvalid; - end - if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_17 && (axis_maskaddr_15 == 0)) begin - _saxi_register_0 <= axislite_resetval_18; + if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_47 && (axis_maskaddr_45 == 0)) begin + _saxi_register_0 <= axislite_resetval_48; _saxi_flag_0 <= 0; end - if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_17 && (axis_maskaddr_15 == 1)) begin - _saxi_register_1 <= axislite_resetval_18; + if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_47 && (axis_maskaddr_45 == 1)) begin + _saxi_register_1 <= axislite_resetval_48; _saxi_flag_1 <= 0; end - if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_17 && (axis_maskaddr_15 == 2)) begin - _saxi_register_2 <= axislite_resetval_18; + if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_47 && (axis_maskaddr_45 == 2)) begin + _saxi_register_2 <= axislite_resetval_48; _saxi_flag_2 <= 0; end - if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_17 && (axis_maskaddr_15 == 3)) begin - _saxi_register_3 <= axislite_resetval_18; + if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_47 && (axis_maskaddr_45 == 3)) begin + _saxi_register_3 <= axislite_resetval_48; _saxi_flag_3 <= 0; end - if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_17 && (axis_maskaddr_15 == 4)) begin - _saxi_register_4 <= axislite_resetval_18; + if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_47 && (axis_maskaddr_45 == 4)) begin + _saxi_register_4 <= axislite_resetval_48; _saxi_flag_4 <= 0; end - if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_17 && (axis_maskaddr_15 == 5)) begin - _saxi_register_5 <= axislite_resetval_18; + if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_47 && (axis_maskaddr_45 == 5)) begin + _saxi_register_5 <= axislite_resetval_48; _saxi_flag_5 <= 0; end - if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_17 && (axis_maskaddr_15 == 6)) begin - _saxi_register_6 <= axislite_resetval_18; + if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_47 && (axis_maskaddr_45 == 6)) begin + _saxi_register_6 <= axislite_resetval_48; _saxi_flag_6 <= 0; end - if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_17 && (axis_maskaddr_15 == 7)) begin - _saxi_register_7 <= axislite_resetval_18; + if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_47 && (axis_maskaddr_45 == 7)) begin + _saxi_register_7 <= axislite_resetval_48; _saxi_flag_7 <= 0; end - if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_15 == 0)) begin + if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_45 == 0)) begin _saxi_register_0 <= saxi_wdata; end - if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_15 == 1)) begin + if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_45 == 1)) begin _saxi_register_1 <= saxi_wdata; end - if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_15 == 2)) begin + if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_45 == 2)) begin _saxi_register_2 <= saxi_wdata; end - if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_15 == 3)) begin + if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_45 == 3)) begin _saxi_register_3 <= saxi_wdata; end - if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_15 == 4)) begin + if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_45 == 4)) begin _saxi_register_4 <= saxi_wdata; end - if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_15 == 5)) begin + if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_45 == 5)) begin _saxi_register_5 <= saxi_wdata; end - if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_15 == 6)) begin + if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_45 == 6)) begin _saxi_register_6 <= saxi_wdata; end - if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_15 == 7)) begin + if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_45 == 7)) begin _saxi_register_7 <= saxi_wdata; end if((_saxi_register_0 == 1) && (th_comp == 2) && 1) begin @@ -1291,17 +1433,17 @@ always @(posedge CLK) begin if(RST) begin _saxi_register_fsm <= _saxi_register_fsm_init; - axis_maskaddr_15 <= 0; + axis_maskaddr_45 <= 0; end else begin case(_saxi_register_fsm) _saxi_register_fsm_init: begin - if(readvalid_12 || writevalid_11) begin - axis_maskaddr_15 <= (addr_10 >> _saxi_shift) & _saxi_mask; + if(readvalid_42 || writevalid_41) begin + axis_maskaddr_45 <= (addr_40 >> _saxi_shift) & _saxi_mask; end - if(readvalid_12) begin + if(readvalid_42) begin _saxi_register_fsm <= _saxi_register_fsm_1; end - if(writevalid_11) begin + if(writevalid_41) begin _saxi_register_fsm <= _saxi_register_fsm_3; end end @@ -1354,7 +1496,7 @@ always @(posedge CLK) begin if(RST) begin count__axi_in_read_req_fifo <= 0; - __tmp_53_1 <= 0; + __tmp_83_1 <= 0; end else begin if(_axi_in_read_req_fifo_enq && !_axi_in_read_req_fifo_full && (_axi_in_read_req_fifo_deq && !_axi_in_read_req_fifo_empty)) begin count__axi_in_read_req_fifo <= count__axi_in_read_req_fifo; @@ -1363,17 +1505,13 @@ end else if(_axi_in_read_req_fifo_deq && !_axi_in_read_req_fifo_empty) begin count__axi_in_read_req_fifo <= count__axi_in_read_req_fifo - 1; end - __tmp_53_1 <= _tmp_53; + __tmp_83_1 <= _tmp_83; end end always @(posedge CLK) begin if(RST) begin - _axi_out_write_data_busy <= 0; - _axi_out_write_op_sel_buf <= 0; - _axi_out_write_size_buf <= 0; - repeat_rvalid_66 <= 0; axi_out_tdata <= 0; axi_out_tvalid <= 0; axi_out_tlast <= 0; @@ -1383,32 +1521,43 @@ axi_out_tvalid <= 0; axi_out_tlast <= 0; end + if((_axi_out_write_op_sel_buf == 1) && cur_rvalid_93 && (axi_out_tready || !axi_out_tvalid) && (axi_out_tready || !axi_out_tvalid)) begin + axi_out_tdata <= fifo_c_rdata; + axi_out_tvalid <= 1; + axi_out_tlast <= rlast_92; + end + _axi_out_cond_0_1 <= 1; + if(axi_out_tvalid && !axi_out_tready) begin + axi_out_tvalid <= axi_out_tvalid; + axi_out_tlast <= axi_out_tlast; + end + end + end + + + always @(posedge CLK) begin + if(RST) begin + _axi_out_write_data_busy <= 0; + _axi_out_write_op_sel_buf <= 0; + _axi_out_write_size_buf <= 0; + repeat_rvalid_96 <= 0; + end else begin if((_axi_out_write_data_fsm == 0) && (!_axi_out_write_data_busy && !_axi_out_write_req_fifo_empty && (_axi_out_write_op_sel_fifo == 1))) begin _axi_out_write_data_busy <= 1; _axi_out_write_op_sel_buf <= _axi_out_write_op_sel_fifo; _axi_out_write_size_buf <= _axi_out_write_size_fifo; end - repeat_rvalid_66 <= 0; - if(__tmp_65_1 && !(axi_out_tready || !axi_out_tvalid)) begin - repeat_rvalid_66 <= 1; + repeat_rvalid_96 <= 0; + if(__tmp_95_1 && !(axi_out_tready || !axi_out_tvalid)) begin + repeat_rvalid_96 <= 1; end - if(repeat_rvalid_66 && !(axi_out_tready || !axi_out_tvalid)) begin - repeat_rvalid_66 <= 1; + if(repeat_rvalid_96 && !(axi_out_tready || !axi_out_tvalid)) begin + repeat_rvalid_96 <= 1; end if((_axi_out_write_data_fsm == 1) && ((_axi_out_write_data_fsm == 1) && !fifo_c_empty && (_axi_out_write_op_sel_buf == 1) && (_axi_out_write_size_buf > 0) && (axi_out_tready || !axi_out_tvalid))) begin _axi_out_write_size_buf <= _axi_out_write_size_buf - 1; end - if((_axi_out_write_op_sel_buf == 1) && cur_rvalid_63 && (axi_out_tready || !axi_out_tvalid) && (axi_out_tready || !axi_out_tvalid)) begin - axi_out_tdata <= fifo_c_rdata; - axi_out_tvalid <= 1; - axi_out_tlast <= rlast_62; - end - _axi_out_cond_0_1 <= 1; - if(axi_out_tvalid && !axi_out_tready) begin - axi_out_tvalid <= axi_out_tvalid; - axi_out_tlast <= axi_out_tlast; - end - if((_axi_out_write_data_fsm == 1) && ((_axi_out_write_op_sel_buf == 1) && cur_rvalid_63 && (axi_out_tready || !axi_out_tvalid)) && rlast_62) begin + if((_axi_out_write_data_fsm == 1) && ((_axi_out_write_op_sel_buf == 1) && cur_rvalid_93 && (axi_out_tready || !axi_out_tvalid)) && rlast_92) begin _axi_out_write_data_busy <= 0; end end @@ -1418,7 +1567,7 @@ always @(posedge CLK) begin if(RST) begin count__axi_out_write_req_fifo <= 0; - __tmp_61_1 <= 0; + __tmp_91_1 <= 0; end else begin if(_axi_out_write_req_fifo_enq && !_axi_out_write_req_fifo_full && (_axi_out_write_req_fifo_deq && !_axi_out_write_req_fifo_empty)) begin count__axi_out_write_req_fifo <= count__axi_out_write_req_fifo; @@ -1427,7 +1576,7 @@ end else if(_axi_out_write_req_fifo_deq && !_axi_out_write_req_fifo_empty) begin count__axi_out_write_req_fifo <= count__axi_out_write_req_fifo - 1; end - __tmp_61_1 <= _tmp_61; + __tmp_91_1 <= _tmp_91; end end @@ -1435,8 +1584,8 @@ always @(posedge CLK) begin if(RST) begin count_fifo_a <= 0; - __tmp_55_1 <= 0; - __tmp_69_1 <= 0; + __tmp_85_1 <= 0; + __tmp_99_1 <= 0; end else begin if(fifo_a_enq && !fifo_a_full && (fifo_a_deq && !fifo_a_empty)) begin count_fifo_a <= count_fifo_a; @@ -1445,8 +1594,8 @@ end else if(fifo_a_deq && !fifo_a_empty) begin count_fifo_a <= count_fifo_a - 1; end - __tmp_55_1 <= _tmp_55; - __tmp_69_1 <= _tmp_69; + __tmp_85_1 <= _tmp_85; + __tmp_99_1 <= _tmp_99; end end @@ -1454,8 +1603,8 @@ always @(posedge CLK) begin if(RST) begin count_fifo_b <= 0; - __tmp_85_1 <= 0; - __tmp_88_1 <= 0; + __tmp_115_1 <= 0; + __tmp_118_1 <= 0; end else begin if(fifo_b_enq && !fifo_b_full && (fifo_b_deq && !fifo_b_empty)) begin count_fifo_b <= count_fifo_b; @@ -1464,8 +1613,8 @@ end else if(fifo_b_deq && !fifo_b_empty) begin count_fifo_b <= count_fifo_b - 1; end - __tmp_85_1 <= _tmp_85; - __tmp_88_1 <= _tmp_88; + __tmp_115_1 <= _tmp_115; + __tmp_118_1 <= _tmp_118; end end @@ -1473,8 +1622,8 @@ always @(posedge CLK) begin if(RST) begin count_fifo_c <= 0; - __tmp_65_1 <= 0; - __tmp_100_1 <= 0; + __tmp_95_1 <= 0; + __tmp_130_1 <= 0; end else begin if(fifo_c_enq && !fifo_c_full && (fifo_c_deq && !fifo_c_empty)) begin count_fifo_c <= count_fifo_c; @@ -1483,17 +1632,17 @@ end else if(fifo_c_deq && !fifo_c_empty) begin count_fifo_c <= count_fifo_c - 1; end - __tmp_65_1 <= _tmp_65; - __tmp_100_1 <= _tmp_100; + __tmp_95_1 <= _tmp_95; + __tmp_130_1 <= _tmp_130; end end always @(posedge CLK) begin if(RST) begin - __tmp_91_1 <= 0; + __tmp_121_1 <= 0; end else begin - __tmp_91_1 <= _tmp_91; + __tmp_121_1 <= _tmp_121; end end @@ -1532,56 +1681,56 @@ _mystream_reduce_a_source_count <= 0; _mystream_reduce_reduce_size_next_parameter_data <= 0; __variable_wdata_1 <= 0; - _tmp_72 <= 0; - _tmp_73 <= 0; - _tmp_74 <= 0; - _tmp_75 <= 0; - _tmp_76 <= 0; - _tmp_77 <= 0; - _tmp_78 <= 0; - _tmp_79 <= 0; - _tmp_80 <= 0; - _tmp_81 <= 0; - _tmp_82 <= 0; - _tmp_83 <= 0; - _mystream_reduce_sum_sink_mode <= 5'b0; - _mystream_reduce_sum_sink_size <= 0; - _mystream_reduce_sum_sink_sel <= 0; - _mystream_reduce_sum_sink_size_buf <= 0; - _mystream_reduce_sum_sink_count <= 0; - _mystream_reduce_sum_sink_fifo_wdata <= 0; _tmp_102 <= 0; _tmp_103 <= 0; _tmp_104 <= 0; _tmp_105 <= 0; _tmp_106 <= 0; _tmp_107 <= 0; - __variable_wdata_3 <= 0; _tmp_108 <= 0; _tmp_109 <= 0; _tmp_110 <= 0; _tmp_111 <= 0; - _tmp_114 <= 0; - _tmp_117 <= 0; - _tmp_118 <= 0; - _tmp_119 <= 0; - _tmp_120 <= 0; - _tmp_121 <= 0; - _tmp_122 <= 0; - _tmp_123 <= 0; - _tmp_124 <= 0; - _tmp_125 <= 0; - _tmp_126 <= 0; - _tmp_127 <= 0; - _tmp_128 <= 0; - _tmp_129 <= 0; - _tmp_130 <= 0; - _tmp_131 <= 0; + _tmp_112 <= 0; + _tmp_113 <= 0; + _mystream_reduce_sum_sink_mode <= 5'b0; + _mystream_reduce_sum_sink_size <= 0; + _mystream_reduce_sum_sink_sel <= 0; + _mystream_reduce_sum_sink_size_buf <= 0; + _mystream_reduce_sum_sink_count <= 0; + _mystream_reduce_sum_sink_fifo_wdata <= 0; _tmp_132 <= 0; _tmp_133 <= 0; _tmp_134 <= 0; _tmp_135 <= 0; _tmp_136 <= 0; + _tmp_137 <= 0; + __variable_wdata_3 <= 0; + _tmp_138 <= 0; + _tmp_139 <= 0; + _tmp_140 <= 0; + _tmp_141 <= 0; + _tmp_144 <= 0; + _tmp_147 <= 0; + _tmp_148 <= 0; + _tmp_149 <= 0; + _tmp_150 <= 0; + _tmp_151 <= 0; + _tmp_152 <= 0; + _tmp_153 <= 0; + _tmp_154 <= 0; + _tmp_155 <= 0; + _tmp_156 <= 0; + _tmp_157 <= 0; + _tmp_158 <= 0; + _tmp_159 <= 0; + _tmp_160 <= 0; + _tmp_161 <= 0; + _tmp_162 <= 0; + _tmp_163 <= 0; + _tmp_164 <= 0; + _tmp_165 <= 0; + _tmp_166 <= 0; _mystream_reduce_busy_reg <= 0; end else begin if(_mystream_reduce_stream_oready) begin @@ -1654,11 +1803,11 @@ if(__mystream_reduce_stream_ivalid_3 && _mystream_reduce_stream_oready) begin _pulse_data_6 <= _pulse_current_count_6 >= __delay_data_13__delay_12__delay_11__variable_1 - 1; end - if(_set_flag_67) begin + if(_set_flag_97) begin _mystream_reduce_a_source_mode <= 5'b10000; _mystream_reduce_a_source_size <= _th_comp_read_size_0; end - if(_set_flag_67) begin + if(_set_flag_97) begin _mystream_reduce_a_source_sel <= 1; end if(_mystream_reduce_source_start && _mystream_reduce_a_source_mode & 5'b10000 && _mystream_reduce_stream_oready) begin @@ -1684,53 +1833,53 @@ _mystream_reduce_a_source_fifo_deq <= 0; _mystream_reduce_a_idle <= 1; end - if(_set_flag_70) begin + if(_set_flag_100) begin _mystream_reduce_reduce_size_next_parameter_data <= _th_comp_reduce_size_2; end if(_mystream_reduce_source_start) begin __variable_wdata_1 <= _mystream_reduce_reduce_size_next_parameter_data; end if(_mystream_reduce_stream_oready) begin - _tmp_72 <= _set_flag_71; + _tmp_102 <= _set_flag_101; end if(_mystream_reduce_stream_oready) begin - _tmp_73 <= _tmp_72; + _tmp_103 <= _tmp_102; end if(_mystream_reduce_stream_oready) begin - _tmp_74 <= _tmp_73; + _tmp_104 <= _tmp_103; end if(_mystream_reduce_stream_oready) begin - _tmp_75 <= _tmp_74; + _tmp_105 <= _tmp_104; end if(_mystream_reduce_stream_oready) begin - _tmp_76 <= _tmp_75; + _tmp_106 <= _tmp_105; end if(_mystream_reduce_stream_oready) begin - _tmp_77 <= _tmp_76; + _tmp_107 <= _tmp_106; end if(_mystream_reduce_stream_oready) begin - _tmp_78 <= _th_comp_write_size_1; + _tmp_108 <= _th_comp_write_size_1; end if(_mystream_reduce_stream_oready) begin - _tmp_79 <= _tmp_78; + _tmp_109 <= _tmp_108; end if(_mystream_reduce_stream_oready) begin - _tmp_80 <= _tmp_79; + _tmp_110 <= _tmp_109; end if(_mystream_reduce_stream_oready) begin - _tmp_81 <= _tmp_80; + _tmp_111 <= _tmp_110; end if(_mystream_reduce_stream_oready) begin - _tmp_82 <= _tmp_81; + _tmp_112 <= _tmp_111; end if(_mystream_reduce_stream_oready) begin - _tmp_83 <= _tmp_82; + _tmp_113 <= _tmp_112; end - if(_tmp_77) begin + if(_tmp_107) begin _mystream_reduce_sum_sink_mode <= 5'b10000; - _mystream_reduce_sum_sink_size <= _tmp_83; + _mystream_reduce_sum_sink_size <= _tmp_113; end - if(_tmp_77) begin + if(_tmp_107) begin _mystream_reduce_sum_sink_sel <= 2; end if(_mystream_reduce_sink_start && _mystream_reduce_sum_sink_mode & 5'b10000 && _mystream_reduce_stream_oready) begin @@ -1746,108 +1895,108 @@ _mystream_reduce_sum_sink_count <= _mystream_reduce_sum_sink_count - 1; end if(_mystream_reduce_stream_oready) begin - _tmp_102 <= _mystream_reduce_source_start; + _tmp_132 <= _mystream_reduce_source_start; end if(_mystream_reduce_stream_oready) begin - _tmp_103 <= _tmp_102; + _tmp_133 <= _tmp_132; end if(_mystream_reduce_stream_oready) begin - _tmp_104 <= _tmp_103; + _tmp_134 <= _tmp_133; end if(_mystream_reduce_stream_oready) begin - _tmp_105 <= _mystream_reduce_source_start; + _tmp_135 <= _mystream_reduce_source_start; end if(_mystream_reduce_stream_oready) begin - _tmp_106 <= _tmp_105; + _tmp_136 <= _tmp_135; end if(_mystream_reduce_stream_oready) begin - _tmp_107 <= _tmp_106; + _tmp_137 <= _tmp_136; end - if(_mystream_reduce_stream_oready && _tmp_107) begin + if(_mystream_reduce_stream_oready && _tmp_137) begin __variable_wdata_3 <= 1; end if(_mystream_reduce_stream_oready) begin - _tmp_108 <= _mystream_reduce_source_start; + _tmp_138 <= _mystream_reduce_source_start; end if(_mystream_reduce_stream_oready) begin - _tmp_109 <= _tmp_108; + _tmp_139 <= _tmp_138; end if(_mystream_reduce_stream_oready) begin - _tmp_110 <= _tmp_109; + _tmp_140 <= _tmp_139; end if(_mystream_reduce_stream_oready) begin - _tmp_111 <= _tmp_110; + _tmp_141 <= _tmp_140; end - if(_mystream_reduce_stream_oready && _tmp_111) begin + if(_mystream_reduce_stream_oready && _tmp_141) begin __variable_wdata_3 <= 0; end if(_mystream_reduce_stream_oready) begin - _tmp_114 <= _tmp_113; + _tmp_144 <= _tmp_143; end if(_mystream_reduce_stream_oready) begin - _tmp_117 <= _tmp_116; + _tmp_147 <= _tmp_146; end - if(_mystream_reduce_stream_oready && _tmp_117) begin + if(_mystream_reduce_stream_oready && _tmp_147) begin __variable_wdata_3 <= 1; end if(_mystream_reduce_stream_oready) begin - _tmp_118 <= _mystream_reduce_source_start; + _tmp_148 <= _mystream_reduce_source_start; end if(_mystream_reduce_stream_oready) begin - _tmp_119 <= _tmp_118; + _tmp_149 <= _tmp_148; end if(_mystream_reduce_stream_oready) begin - _tmp_120 <= _tmp_119; + _tmp_150 <= _tmp_149; end if(_mystream_reduce_stream_oready) begin - _tmp_121 <= _tmp_120; + _tmp_151 <= _tmp_150; end if(_mystream_reduce_stream_oready) begin - _tmp_122 <= _tmp_121; + _tmp_152 <= _tmp_151; end if(_mystream_reduce_stream_oready) begin - _tmp_123 <= _tmp_122; + _tmp_153 <= _tmp_152; end if(_mystream_reduce_stream_oready) begin - _tmp_124 <= _mystream_reduce_source_stop; + _tmp_154 <= _mystream_reduce_source_stop; end if(_mystream_reduce_stream_oready) begin - _tmp_125 <= _tmp_124; + _tmp_155 <= _tmp_154; end if(_mystream_reduce_stream_oready) begin - _tmp_126 <= _tmp_125; + _tmp_156 <= _tmp_155; end if(_mystream_reduce_stream_oready) begin - _tmp_127 <= _tmp_126; + _tmp_157 <= _tmp_156; end if(_mystream_reduce_stream_oready) begin - _tmp_128 <= _tmp_127; + _tmp_158 <= _tmp_157; end if(_mystream_reduce_stream_oready) begin - _tmp_129 <= _tmp_128; + _tmp_159 <= _tmp_158; end if(_mystream_reduce_stream_oready) begin - _tmp_130 <= _mystream_reduce_source_busy; + _tmp_160 <= _mystream_reduce_source_busy; end if(_mystream_reduce_stream_oready) begin - _tmp_131 <= _tmp_130; + _tmp_161 <= _tmp_160; end if(_mystream_reduce_stream_oready) begin - _tmp_132 <= _tmp_131; + _tmp_162 <= _tmp_161; end if(_mystream_reduce_stream_oready) begin - _tmp_133 <= _tmp_132; + _tmp_163 <= _tmp_162; end if(_mystream_reduce_stream_oready) begin - _tmp_134 <= _tmp_133; + _tmp_164 <= _tmp_163; end if(_mystream_reduce_stream_oready) begin - _tmp_135 <= _tmp_134; + _tmp_165 <= _tmp_164; end if(_mystream_reduce_stream_oready) begin - _tmp_136 <= _mystream_reduce_sink_busy; + _tmp_166 <= _mystream_reduce_sink_busy; end - if(!_mystream_reduce_sink_busy && _tmp_136) begin + if(!_mystream_reduce_sink_busy && _tmp_166) begin _mystream_reduce_busy_reg <= 0; end if(_mystream_reduce_source_busy) begin @@ -1867,10 +2016,10 @@ _mystream_reduce_source_busy <= 0; _mystream_reduce_stream_ivalid <= 0; end else begin - if(_mystream_reduce_stream_oready && _tmp_104) begin + if(_mystream_reduce_stream_oready && _tmp_134) begin _mystream_reduce_stream_ivalid <= 1; end - if(_mystream_reduce_stream_oready && _tmp_114) begin + if(_mystream_reduce_stream_oready && _tmp_144) begin _mystream_reduce_stream_ivalid <= 0; end case(_mystream_reduce_fsm) @@ -1944,32 +2093,32 @@ __variable_wdata_9 <= 0; _mystream_bias_y_source_ram_raddr <= 0; _mystream_bias_y_source_count <= 0; - _tmp_93 <= 0; - _tmp_94 <= 0; - _tmp_95 <= 0; - _tmp_96 <= 0; - _tmp_97 <= 0; - _tmp_98 <= 0; + _tmp_123 <= 0; + _tmp_124 <= 0; + _tmp_125 <= 0; + _tmp_126 <= 0; + _tmp_127 <= 0; + _tmp_128 <= 0; _mystream_bias_z_sink_mode <= 5'b0; _mystream_bias_z_sink_size <= 0; _mystream_bias_z_sink_sel <= 0; _mystream_bias_z_sink_size_buf <= 0; _mystream_bias_z_sink_count <= 0; _mystream_bias_z_sink_fifo_wdata <= 0; - _tmp_138 <= 0; - _tmp_139 <= 0; - _tmp_140 <= 0; - _tmp_143 <= 0; - _tmp_144 <= 0; - _tmp_145 <= 0; - _tmp_146 <= 0; - _tmp_147 <= 0; - _tmp_148 <= 0; - _tmp_149 <= 0; - _tmp_150 <= 0; - _tmp_151 <= 0; - _tmp_152 <= 0; - _tmp_153 <= 0; + _tmp_168 <= 0; + _tmp_169 <= 0; + _tmp_170 <= 0; + _tmp_173 <= 0; + _tmp_174 <= 0; + _tmp_175 <= 0; + _tmp_176 <= 0; + _tmp_177 <= 0; + _tmp_178 <= 0; + _tmp_179 <= 0; + _tmp_180 <= 0; + _tmp_181 <= 0; + _tmp_182 <= 0; + _tmp_183 <= 0; _mystream_bias_busy_reg <= 0; end else begin if(_mystream_bias_stream_oready) begin @@ -1992,11 +2141,11 @@ if(_mystream_bias_stream_oready) begin _plus_data_10 <= mystream_bias_x_data + mystream_bias_y_data; end - if(_set_flag_86) begin + if(_set_flag_116) begin _mystream_bias_x_source_mode <= 5'b10000; _mystream_bias_x_source_size <= _th_comp_write_size_1; end - if(_set_flag_86) begin + if(_set_flag_116) begin _mystream_bias_x_source_sel <= 1; end if(_mystream_bias_source_start && _mystream_bias_x_source_mode & 5'b10000 && _mystream_bias_stream_oready) begin @@ -2022,13 +2171,13 @@ _mystream_bias_x_source_fifo_deq <= 0; _mystream_bias_x_idle <= 1; end - if(_set_flag_89) begin + if(_set_flag_119) begin _mystream_bias_y_source_mode <= 5'b1; _mystream_bias_y_source_offset <= 0; _mystream_bias_y_source_size <= _th_comp_write_size_1; _mystream_bias_y_source_stride <= 1; end - if(_set_flag_89) begin + if(_set_flag_119) begin _mystream_bias_y_source_sel <= 2; end if(_mystream_bias_source_start && _mystream_bias_y_source_mode & 5'b1 && _mystream_bias_stream_oready) begin @@ -2059,28 +2208,28 @@ _mystream_bias_y_idle <= 1; end if(_mystream_bias_stream_oready) begin - _tmp_93 <= _set_flag_92; + _tmp_123 <= _set_flag_122; end if(_mystream_bias_stream_oready) begin - _tmp_94 <= _tmp_93; + _tmp_124 <= _tmp_123; end if(_mystream_bias_stream_oready) begin - _tmp_95 <= _tmp_94; + _tmp_125 <= _tmp_124; end if(_mystream_bias_stream_oready) begin - _tmp_96 <= _th_comp_write_size_1; + _tmp_126 <= _th_comp_write_size_1; end if(_mystream_bias_stream_oready) begin - _tmp_97 <= _tmp_96; + _tmp_127 <= _tmp_126; end if(_mystream_bias_stream_oready) begin - _tmp_98 <= _tmp_97; + _tmp_128 <= _tmp_127; end - if(_tmp_95) begin + if(_tmp_125) begin _mystream_bias_z_sink_mode <= 5'b10000; - _mystream_bias_z_sink_size <= _tmp_98; + _mystream_bias_z_sink_size <= _tmp_128; end - if(_tmp_95) begin + if(_tmp_125) begin _mystream_bias_z_sink_sel <= 3; end if(_mystream_bias_sink_start && _mystream_bias_z_sink_mode & 5'b10000 && _mystream_bias_stream_oready) begin @@ -2096,48 +2245,48 @@ _mystream_bias_z_sink_count <= _mystream_bias_z_sink_count - 1; end if(_mystream_bias_stream_oready) begin - _tmp_138 <= _mystream_bias_source_start; + _tmp_168 <= _mystream_bias_source_start; end if(_mystream_bias_stream_oready) begin - _tmp_139 <= _tmp_138; + _tmp_169 <= _tmp_168; end if(_mystream_bias_stream_oready) begin - _tmp_140 <= _tmp_139; + _tmp_170 <= _tmp_169; end if(_mystream_bias_stream_oready) begin - _tmp_143 <= _tmp_142; + _tmp_173 <= _tmp_172; end if(_mystream_bias_stream_oready) begin - _tmp_144 <= _mystream_bias_source_start; + _tmp_174 <= _mystream_bias_source_start; end if(_mystream_bias_stream_oready) begin - _tmp_145 <= _tmp_144; + _tmp_175 <= _tmp_174; end if(_mystream_bias_stream_oready) begin - _tmp_146 <= _tmp_145; + _tmp_176 <= _tmp_175; end if(_mystream_bias_stream_oready) begin - _tmp_147 <= _mystream_bias_source_stop; + _tmp_177 <= _mystream_bias_source_stop; end if(_mystream_bias_stream_oready) begin - _tmp_148 <= _tmp_147; + _tmp_178 <= _tmp_177; end if(_mystream_bias_stream_oready) begin - _tmp_149 <= _tmp_148; + _tmp_179 <= _tmp_178; end if(_mystream_bias_stream_oready) begin - _tmp_150 <= _mystream_bias_source_busy; + _tmp_180 <= _mystream_bias_source_busy; end if(_mystream_bias_stream_oready) begin - _tmp_151 <= _tmp_150; + _tmp_181 <= _tmp_180; end if(_mystream_bias_stream_oready) begin - _tmp_152 <= _tmp_151; + _tmp_182 <= _tmp_181; end if(_mystream_bias_stream_oready) begin - _tmp_153 <= _mystream_bias_sink_busy; + _tmp_183 <= _mystream_bias_sink_busy; end - if(!_mystream_bias_sink_busy && _tmp_153) begin + if(!_mystream_bias_sink_busy && _tmp_183) begin _mystream_bias_busy_reg <= 0; end if(_mystream_bias_source_busy) begin @@ -2157,10 +2306,10 @@ _mystream_bias_source_busy <= 0; _mystream_bias_stream_ivalid <= 0; end else begin - if(_mystream_bias_stream_oready && _tmp_140) begin + if(_mystream_bias_stream_oready && _tmp_170) begin _mystream_bias_stream_ivalid <= 1; end - if(_mystream_bias_stream_oready && _tmp_143) begin + if(_mystream_bias_stream_oready && _tmp_173) begin _mystream_bias_stream_ivalid <= 0; end case(_mystream_bias_fsm) @@ -2436,7 +2585,7 @@ _maxi_read_data_fsm <= _maxi_read_data_fsm_2; end _maxi_read_data_fsm_2: begin - if(maxi_rvalid && (_maxi_read_local_size_buf <= 1)) begin + if(_maxi_rvalid_sb_0 && (_maxi_read_local_size_buf <= 1)) begin _maxi_read_data_fsm <= _maxi_read_data_fsm_init; end end @@ -2449,37 +2598,37 @@ always @(posedge CLK) begin if(RST) begin write_burst_fsm_0 <= write_burst_fsm_0_init; - write_burst_addr_45 <= 0; - write_burst_stride_46 <= 0; - write_burst_length_47 <= 0; - write_burst_done_48 <= 0; + write_burst_addr_75 <= 0; + write_burst_stride_76 <= 0; + write_burst_length_77 <= 0; + write_burst_done_78 <= 0; end else begin case(write_burst_fsm_0) write_burst_fsm_0_init: begin - write_burst_addr_45 <= _maxi_read_local_addr_buf; - write_burst_stride_46 <= _maxi_read_local_stride_buf; - write_burst_length_47 <= _maxi_read_local_size_buf; - write_burst_done_48 <= 0; + write_burst_addr_75 <= _maxi_read_local_addr_buf; + write_burst_stride_76 <= _maxi_read_local_stride_buf; + write_burst_length_77 <= _maxi_read_local_size_buf; + write_burst_done_78 <= 0; if((_maxi_read_data_fsm == 1) && (_maxi_read_op_sel_buf == 1) && (_maxi_read_local_size_buf > 0)) begin write_burst_fsm_0 <= write_burst_fsm_0_1; end end write_burst_fsm_0_1: begin - if(maxi_rvalid) begin - write_burst_addr_45 <= write_burst_addr_45 + write_burst_stride_46; - write_burst_length_47 <= write_burst_length_47 - 1; - write_burst_done_48 <= 0; + if(_maxi_rvalid_sb_0) begin + write_burst_addr_75 <= write_burst_addr_75 + write_burst_stride_76; + write_burst_length_77 <= write_burst_length_77 - 1; + write_burst_done_78 <= 0; end - if(maxi_rvalid && (write_burst_length_47 <= 1)) begin - write_burst_done_48 <= 1; + if(_maxi_rvalid_sb_0 && (write_burst_length_77 <= 1)) begin + write_burst_done_78 <= 1; end - if(maxi_rvalid && 0) begin - write_burst_done_48 <= 1; + if(_maxi_rvalid_sb_0 && 0) begin + write_burst_done_78 <= 1; end - if(maxi_rvalid && (write_burst_length_47 <= 1)) begin + if(_maxi_rvalid_sb_0 && (write_burst_length_77 <= 1)) begin write_burst_fsm_0 <= write_burst_fsm_0_init; end - if(maxi_rvalid && 0) begin + if(_maxi_rvalid_sb_0 && 0) begin write_burst_fsm_0 <= write_burst_fsm_0_init; end if(0) begin @@ -2516,20 +2665,20 @@ always @(posedge CLK) begin if(RST) begin _axi_out_write_data_fsm <= _axi_out_write_data_fsm_init; - rlast_62 <= 0; + rlast_92 <= 0; end else begin case(_axi_out_write_data_fsm) _axi_out_write_data_fsm_init: begin - rlast_62 <= 0; + rlast_92 <= 0; if(!_axi_out_write_data_busy && !_axi_out_write_req_fifo_empty && (_axi_out_write_op_sel_fifo == 1)) begin _axi_out_write_data_fsm <= _axi_out_write_data_fsm_1; end end _axi_out_write_data_fsm_1: begin if((_axi_out_write_data_fsm == 1) && !fifo_c_empty && (_axi_out_write_op_sel_buf == 1) && (_axi_out_write_size_buf > 0) && (axi_out_tready || !axi_out_tvalid)) begin - rlast_62 <= _axi_out_write_size_buf <= 1; + rlast_92 <= _axi_out_write_size_buf <= 1; end - if((_axi_out_write_op_sel_buf == 1) && cur_rvalid_63 && (axi_out_tready || !axi_out_tvalid) && rlast_62) begin + if((_axi_out_write_op_sel_buf == 1) && cur_rvalid_93 && (axi_out_tready || !axi_out_tvalid) && rlast_92) begin _axi_out_write_data_fsm <= _axi_out_write_data_fsm_init; end end diff --git a/examples/stream_axi_stream_fifo_ultra96v2_pynq/ultra96v2_pynq/run_on_pynq.py b/examples/stream_axi_stream_fifo_ultra96v2_pynq/ultra96v2_pynq/run_on_pynq.py index e5d37668..e5dcb85c 100644 --- a/examples/stream_axi_stream_fifo_ultra96v2_pynq/ultra96v2_pynq/run_on_pynq.py +++ b/examples/stream_axi_stream_fifo_ultra96v2_pynq/ultra96v2_pynq/run_on_pynq.py @@ -86,4 +86,3 @@ diff_sum = np.sum(expected - dst) print(diff_sum) - diff --git a/examples/stream_matmul_ultra96v2_pynq/stream_matmul.py b/examples/stream_matmul_ultra96v2_pynq/stream_matmul.py index dff1b05b..14a1030c 100644 --- a/examples/stream_matmul_ultra96v2_pynq/stream_matmul.py +++ b/examples/stream_matmul_ultra96v2_pynq/stream_matmul.py @@ -241,9 +241,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/examples/stream_matmul_ultra96v2_pynq/test_stream_matmul.py b/examples/stream_matmul_ultra96v2_pynq/test_stream_matmul.py index 39607326..0cb45a59 100644 --- a/examples/stream_matmul_ultra96v2_pynq/test_stream_matmul.py +++ b/examples/stream_matmul_ultra96v2_pynq/test_stream_matmul.py @@ -14,5 +14,5 @@ def test(request): rslt = stream_matmul.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/examples/stream_matmul_ultra96v2_pynq/ultra96v2_pynq/run_on_pynq.py b/examples/stream_matmul_ultra96v2_pynq/ultra96v2_pynq/run_on_pynq.py index 332301d8..219a4112 100644 --- a/examples/stream_matmul_ultra96v2_pynq/ultra96v2_pynq/run_on_pynq.py +++ b/examples/stream_matmul_ultra96v2_pynq/ultra96v2_pynq/run_on_pynq.py @@ -83,4 +83,3 @@ diff_sum = np.sum(expected - c) print(diff_sum) - diff --git a/examples/thread_add_ipxact/test_thread_add_ipxact.py b/examples/thread_add_ipxact/test_thread_add_ipxact.py index 40eb2ce7..daea6642 100644 --- a/examples/thread_add_ipxact/test_thread_add_ipxact.py +++ b/examples/thread_add_ipxact/test_thread_add_ipxact.py @@ -34,127 +34,185 @@ wire [3-1:0] _saxi_awprot; reg _saxi_awvalid; wire _saxi_awready; - reg [32-1:0] _saxi_wdata; - reg [4-1:0] _saxi_wstrb; - reg _saxi_wvalid; + assign _saxi_awcache = 3; + assign _saxi_awprot = 0; + wire [32-1:0] _saxi_wdata; + wire [4-1:0] _saxi_wstrb; + wire _saxi_wvalid; wire _saxi_wready; + reg [32-1:0] __saxi_wdata_sb_0; + reg [4-1:0] __saxi_wstrb_sb_0; + reg __saxi_wvalid_sb_0; + wire __saxi_wready_sb_0; + wire [4-1:0] _sb__saxi_writedata_s_value_0; + assign _sb__saxi_writedata_s_value_0 = __saxi_wstrb_sb_0; + wire [32-1:0] _sb__saxi_writedata_s_value_1; + assign _sb__saxi_writedata_s_value_1 = __saxi_wdata_sb_0; + wire [36-1:0] _sb__saxi_writedata_s_data_2; + assign _sb__saxi_writedata_s_data_2 = { _sb__saxi_writedata_s_value_0, _sb__saxi_writedata_s_value_1 }; + wire _sb__saxi_writedata_s_valid_3; + assign _sb__saxi_writedata_s_valid_3 = __saxi_wvalid_sb_0; + wire _sb__saxi_writedata_m_ready_4; + assign _sb__saxi_writedata_m_ready_4 = _saxi_wready; + reg [36-1:0] _sb__saxi_writedata_data_5; + reg _sb__saxi_writedata_valid_6; + wire _sb__saxi_writedata_ready_7; + reg [36-1:0] _sb__saxi_writedata_tmp_data_8; + reg _sb__saxi_writedata_tmp_valid_9; + wire [36-1:0] _sb__saxi_writedata_next_data_10; + wire _sb__saxi_writedata_next_valid_11; + assign _sb__saxi_writedata_ready_7 = !_sb__saxi_writedata_tmp_valid_9; + assign _sb__saxi_writedata_next_data_10 = (_sb__saxi_writedata_tmp_valid_9)? _sb__saxi_writedata_tmp_data_8 : _sb__saxi_writedata_s_data_2; + assign _sb__saxi_writedata_next_valid_11 = _sb__saxi_writedata_tmp_valid_9 || _sb__saxi_writedata_s_valid_3; + wire [4-1:0] _sb__saxi_writedata_m_value_12; + assign _sb__saxi_writedata_m_value_12 = _sb__saxi_writedata_data_5[35:32]; + wire [32-1:0] _sb__saxi_writedata_m_value_13; + assign _sb__saxi_writedata_m_value_13 = _sb__saxi_writedata_data_5[31:0]; + assign __saxi_wready_sb_0 = _sb__saxi_writedata_ready_7; + assign _saxi_wdata = _sb__saxi_writedata_m_value_13; + assign _saxi_wstrb = _sb__saxi_writedata_m_value_12; + assign _saxi_wvalid = _sb__saxi_writedata_valid_6; wire [2-1:0] _saxi_bresp; wire _saxi_bvalid; wire _saxi_bready; + assign _saxi_bready = 1; reg [32-1:0] _saxi_araddr; wire [4-1:0] _saxi_arcache; wire [3-1:0] _saxi_arprot; reg _saxi_arvalid; wire _saxi_arready; + assign _saxi_arcache = 3; + assign _saxi_arprot = 0; wire [32-1:0] _saxi_rdata; wire [2-1:0] _saxi_rresp; wire _saxi_rvalid; wire _saxi_rready; - assign _saxi_awcache = 3; - assign _saxi_awprot = 0; - assign _saxi_bready = 1; - assign _saxi_arcache = 3; - assign _saxi_arprot = 0; + wire [32-1:0] __saxi_rdata_sb_0; + wire __saxi_rvalid_sb_0; + wire __saxi_rready_sb_0; + wire [32-1:0] _sb__saxi_readdata_s_value_14; + assign _sb__saxi_readdata_s_value_14 = _saxi_rdata; + wire [32-1:0] _sb__saxi_readdata_s_data_15; + assign _sb__saxi_readdata_s_data_15 = { _sb__saxi_readdata_s_value_14 }; + wire _sb__saxi_readdata_s_valid_16; + assign _sb__saxi_readdata_s_valid_16 = _saxi_rvalid; + wire _sb__saxi_readdata_m_ready_17; + assign _sb__saxi_readdata_m_ready_17 = __saxi_rready_sb_0; + reg [32-1:0] _sb__saxi_readdata_data_18; + reg _sb__saxi_readdata_valid_19; + wire _sb__saxi_readdata_ready_20; + reg [32-1:0] _sb__saxi_readdata_tmp_data_21; + reg _sb__saxi_readdata_tmp_valid_22; + wire [32-1:0] _sb__saxi_readdata_next_data_23; + wire _sb__saxi_readdata_next_valid_24; + assign _sb__saxi_readdata_ready_20 = !_sb__saxi_readdata_tmp_valid_22; + assign _sb__saxi_readdata_next_data_23 = (_sb__saxi_readdata_tmp_valid_22)? _sb__saxi_readdata_tmp_data_21 : _sb__saxi_readdata_s_data_15; + assign _sb__saxi_readdata_next_valid_24 = _sb__saxi_readdata_tmp_valid_22 || _sb__saxi_readdata_s_valid_16; + wire [32-1:0] _sb__saxi_readdata_m_value_25; + assign _sb__saxi_readdata_m_value_25 = _sb__saxi_readdata_data_18[31:0]; + assign __saxi_rdata_sb_0 = _sb__saxi_readdata_m_value_25; + assign __saxi_rvalid_sb_0 = _sb__saxi_readdata_valid_19; + assign _saxi_rready = _sb__saxi_readdata_ready_20; reg [3-1:0] __saxi_outstanding_wcount; wire __saxi_has_outstanding_write; assign __saxi_has_outstanding_write = (__saxi_outstanding_wcount > 0) || _saxi_awvalid; - wire [32-1:0] _tmp_0; - assign _tmp_0 = _saxi_awaddr; + wire [32-1:0] _tmp_26; + assign _tmp_26 = _saxi_awaddr; always @(*) begin - saxi_awaddr = _tmp_0; + saxi_awaddr = _tmp_26; end - wire [4-1:0] _tmp_1; - assign _tmp_1 = _saxi_awcache; + wire [4-1:0] _tmp_27; + assign _tmp_27 = _saxi_awcache; always @(*) begin - saxi_awcache = _tmp_1; + saxi_awcache = _tmp_27; end - wire [3-1:0] _tmp_2; - assign _tmp_2 = _saxi_awprot; + wire [3-1:0] _tmp_28; + assign _tmp_28 = _saxi_awprot; always @(*) begin - saxi_awprot = _tmp_2; + saxi_awprot = _tmp_28; end - wire _tmp_3; - assign _tmp_3 = _saxi_awvalid; + wire _tmp_29; + assign _tmp_29 = _saxi_awvalid; always @(*) begin - saxi_awvalid = _tmp_3; + saxi_awvalid = _tmp_29; end assign _saxi_awready = saxi_awready; - wire [32-1:0] _tmp_4; - assign _tmp_4 = _saxi_wdata; + wire [32-1:0] _tmp_30; + assign _tmp_30 = _saxi_wdata; always @(*) begin - saxi_wdata = _tmp_4; + saxi_wdata = _tmp_30; end - wire [4-1:0] _tmp_5; - assign _tmp_5 = _saxi_wstrb; + wire [4-1:0] _tmp_31; + assign _tmp_31 = _saxi_wstrb; always @(*) begin - saxi_wstrb = _tmp_5; + saxi_wstrb = _tmp_31; end - wire _tmp_6; - assign _tmp_6 = _saxi_wvalid; + wire _tmp_32; + assign _tmp_32 = _saxi_wvalid; always @(*) begin - saxi_wvalid = _tmp_6; + saxi_wvalid = _tmp_32; end assign _saxi_wready = saxi_wready; assign _saxi_bresp = saxi_bresp; assign _saxi_bvalid = saxi_bvalid; - wire _tmp_7; - assign _tmp_7 = _saxi_bready; + wire _tmp_33; + assign _tmp_33 = _saxi_bready; always @(*) begin - saxi_bready = _tmp_7; + saxi_bready = _tmp_33; end - wire [32-1:0] _tmp_8; - assign _tmp_8 = _saxi_araddr; + wire [32-1:0] _tmp_34; + assign _tmp_34 = _saxi_araddr; always @(*) begin - saxi_araddr = _tmp_8; + saxi_araddr = _tmp_34; end - wire [4-1:0] _tmp_9; - assign _tmp_9 = _saxi_arcache; + wire [4-1:0] _tmp_35; + assign _tmp_35 = _saxi_arcache; always @(*) begin - saxi_arcache = _tmp_9; + saxi_arcache = _tmp_35; end - wire [3-1:0] _tmp_10; - assign _tmp_10 = _saxi_arprot; + wire [3-1:0] _tmp_36; + assign _tmp_36 = _saxi_arprot; always @(*) begin - saxi_arprot = _tmp_10; + saxi_arprot = _tmp_36; end - wire _tmp_11; - assign _tmp_11 = _saxi_arvalid; + wire _tmp_37; + assign _tmp_37 = _saxi_arvalid; always @(*) begin - saxi_arvalid = _tmp_11; + saxi_arvalid = _tmp_37; end assign _saxi_arready = saxi_arready; assign _saxi_rdata = saxi_rdata; assign _saxi_rresp = saxi_rresp; assign _saxi_rvalid = saxi_rvalid; - wire _tmp_12; - assign _tmp_12 = _saxi_rready; + wire _tmp_38; + assign _tmp_38 = _saxi_rready; always @(*) begin - saxi_rready = _tmp_12; + saxi_rready = _tmp_38; end reg [32-1:0] counter; @@ -163,21 +221,21 @@ reg signed [32-1:0] _th_ctrl_i_3; reg signed [32-1:0] _th_ctrl_awaddr_4; reg signed [32-1:0] _th_ctrl_a_5; - reg __saxi_cond_0_1; - reg __saxi_cond_1_1; + reg __saxi_waddr_cond_0_1; + reg __saxi_wdata_cond_0_1; reg signed [32-1:0] _th_ctrl_b_6; - reg __saxi_cond_2_1; - reg __saxi_cond_3_1; + reg __saxi_waddr_cond_1_1; + reg __saxi_wdata_cond_1_1; reg signed [32-1:0] _th_ctrl_start_time_7; - reg __saxi_cond_4_1; - reg __saxi_cond_5_1; + reg __saxi_waddr_cond_2_1; + reg __saxi_wdata_cond_2_1; reg signed [32-1:0] _th_ctrl_araddr_8; - reg __saxi_cond_6_1; - reg signed [32-1:0] axim_rdata_13; + reg __saxi_raddr_cond_0_1; + reg signed [32-1:0] axim_rdata_39; reg signed [32-1:0] _th_ctrl_busy_9; - reg __saxi_cond_7_1; - reg signed [32-1:0] axim_rdata_14; - assign _saxi_rready = (th_ctrl == 32) || (th_ctrl == 40); + reg __saxi_raddr_cond_1_1; + reg signed [32-1:0] axim_rdata_40; + assign __saxi_rready_sb_0 = (th_ctrl == 32) || (th_ctrl == 40); reg signed [32-1:0] _th_ctrl_c_10; reg signed [32-1:0] _th_ctrl_end_time_11; reg signed [32-1:0] _th_ctrl_time_12; @@ -229,31 +287,39 @@ RST = 0; _saxi_awaddr = 0; _saxi_awvalid = 0; - _saxi_wdata = 0; - _saxi_wstrb = 0; - _saxi_wvalid = 0; + __saxi_wdata_sb_0 = 0; + __saxi_wstrb_sb_0 = 0; + __saxi_wvalid_sb_0 = 0; + _sb__saxi_writedata_data_5 = 0; + _sb__saxi_writedata_valid_6 = 0; + _sb__saxi_writedata_tmp_data_8 = 0; + _sb__saxi_writedata_tmp_valid_9 = 0; _saxi_araddr = 0; _saxi_arvalid = 0; + _sb__saxi_readdata_data_18 = 0; + _sb__saxi_readdata_valid_19 = 0; + _sb__saxi_readdata_tmp_data_21 = 0; + _sb__saxi_readdata_tmp_valid_22 = 0; __saxi_outstanding_wcount = 0; counter = 0; th_ctrl = th_ctrl_init; _th_ctrl_i_3 = 0; _th_ctrl_awaddr_4 = 0; _th_ctrl_a_5 = 0; - __saxi_cond_0_1 = 0; - __saxi_cond_1_1 = 0; + __saxi_waddr_cond_0_1 = 0; + __saxi_wdata_cond_0_1 = 0; _th_ctrl_b_6 = 0; - __saxi_cond_2_1 = 0; - __saxi_cond_3_1 = 0; + __saxi_waddr_cond_1_1 = 0; + __saxi_wdata_cond_1_1 = 0; _th_ctrl_start_time_7 = 0; - __saxi_cond_4_1 = 0; - __saxi_cond_5_1 = 0; + __saxi_waddr_cond_2_1 = 0; + __saxi_wdata_cond_2_1 = 0; _th_ctrl_araddr_8 = 0; - __saxi_cond_6_1 = 0; - axim_rdata_13 = 0; + __saxi_raddr_cond_0_1 = 0; + axim_rdata_39 = 0; _th_ctrl_busy_9 = 0; - __saxi_cond_7_1 = 0; - axim_rdata_14 = 0; + __saxi_raddr_cond_1_1 = 0; + axim_rdata_40 = 0; _th_ctrl_c_10 = 0; _th_ctrl_end_time_11 = 0; _th_ctrl_time_12 = 0; @@ -268,109 +334,138 @@ always @(posedge CLK) begin if(RST) begin - __saxi_outstanding_wcount <= 0; _saxi_awaddr <= 0; _saxi_awvalid <= 0; - __saxi_cond_0_1 <= 0; - _saxi_wdata <= 0; - _saxi_wvalid <= 0; - _saxi_wstrb <= 0; - __saxi_cond_1_1 <= 0; - __saxi_cond_2_1 <= 0; - __saxi_cond_3_1 <= 0; - __saxi_cond_4_1 <= 0; - __saxi_cond_5_1 <= 0; - _saxi_araddr <= 0; - _saxi_arvalid <= 0; - __saxi_cond_6_1 <= 0; - __saxi_cond_7_1 <= 0; + __saxi_waddr_cond_0_1 <= 0; + __saxi_waddr_cond_1_1 <= 0; + __saxi_waddr_cond_2_1 <= 0; end else begin - if(__saxi_cond_0_1) begin + if(__saxi_waddr_cond_0_1) begin _saxi_awvalid <= 0; end - if(__saxi_cond_1_1) begin - _saxi_wvalid <= 0; - end - if(__saxi_cond_2_1) begin + if(__saxi_waddr_cond_1_1) begin _saxi_awvalid <= 0; end - if(__saxi_cond_3_1) begin - _saxi_wvalid <= 0; - end - if(__saxi_cond_4_1) begin + if(__saxi_waddr_cond_2_1) begin _saxi_awvalid <= 0; end - if(__saxi_cond_5_1) begin - _saxi_wvalid <= 0; - end - if(__saxi_cond_6_1) begin - _saxi_arvalid <= 0; - end - if(__saxi_cond_7_1) begin - _saxi_arvalid <= 0; - end - if(_saxi_awvalid && _saxi_awready && !(_saxi_bvalid && _saxi_bready) && (__saxi_outstanding_wcount < 7)) begin - __saxi_outstanding_wcount <= __saxi_outstanding_wcount + 1; - end - if(!(_saxi_awvalid && _saxi_awready) && (_saxi_bvalid && _saxi_bready) && (__saxi_outstanding_wcount > 0)) begin - __saxi_outstanding_wcount <= __saxi_outstanding_wcount - 1; - end if((th_ctrl == 7) && ((__saxi_outstanding_wcount == 0) && (_saxi_awready || !_saxi_awvalid))) begin _saxi_awaddr <= _th_ctrl_awaddr_4; _saxi_awvalid <= 1; end - __saxi_cond_0_1 <= 1; + __saxi_waddr_cond_0_1 <= 1; if(_saxi_awvalid && !_saxi_awready) begin _saxi_awvalid <= _saxi_awvalid; end - if((th_ctrl == 9) && (_saxi_wready || !_saxi_wvalid)) begin - _saxi_wdata <= _th_ctrl_a_5; - _saxi_wvalid <= 1; - _saxi_wstrb <= { 4{ 1'd1 } }; - end - __saxi_cond_1_1 <= 1; - if(_saxi_wvalid && !_saxi_wready) begin - _saxi_wvalid <= _saxi_wvalid; - end if((th_ctrl == 15) && ((__saxi_outstanding_wcount == 0) && (_saxi_awready || !_saxi_awvalid))) begin _saxi_awaddr <= _th_ctrl_awaddr_4; _saxi_awvalid <= 1; end - __saxi_cond_2_1 <= 1; + __saxi_waddr_cond_1_1 <= 1; if(_saxi_awvalid && !_saxi_awready) begin _saxi_awvalid <= _saxi_awvalid; end - if((th_ctrl == 17) && (_saxi_wready || !_saxi_wvalid)) begin - _saxi_wdata <= _th_ctrl_b_6; - _saxi_wvalid <= 1; - _saxi_wstrb <= { 4{ 1'd1 } }; - end - __saxi_cond_3_1 <= 1; - if(_saxi_wvalid && !_saxi_wready) begin - _saxi_wvalid <= _saxi_wvalid; - end if((th_ctrl == 23) && ((__saxi_outstanding_wcount == 0) && (_saxi_awready || !_saxi_awvalid))) begin _saxi_awaddr <= _th_ctrl_awaddr_4; _saxi_awvalid <= 1; end - __saxi_cond_4_1 <= 1; + __saxi_waddr_cond_2_1 <= 1; if(_saxi_awvalid && !_saxi_awready) begin _saxi_awvalid <= _saxi_awvalid; end - if((th_ctrl == 25) && (_saxi_wready || !_saxi_wvalid)) begin - _saxi_wdata <= 1; - _saxi_wvalid <= 1; - _saxi_wstrb <= { 4{ 1'd1 } }; + end + end + + + always @(posedge CLK) begin + if(RST) begin + __saxi_wdata_sb_0 <= 0; + __saxi_wvalid_sb_0 <= 0; + __saxi_wstrb_sb_0 <= 0; + __saxi_wdata_cond_0_1 <= 0; + __saxi_wdata_cond_1_1 <= 0; + __saxi_wdata_cond_2_1 <= 0; + end else begin + if(__saxi_wdata_cond_0_1) begin + __saxi_wvalid_sb_0 <= 0; + end + if(__saxi_wdata_cond_1_1) begin + __saxi_wvalid_sb_0 <= 0; + end + if(__saxi_wdata_cond_2_1) begin + __saxi_wvalid_sb_0 <= 0; + end + if((th_ctrl == 9) && (__saxi_wready_sb_0 || !__saxi_wvalid_sb_0)) begin + __saxi_wdata_sb_0 <= _th_ctrl_a_5; + __saxi_wvalid_sb_0 <= 1; + __saxi_wstrb_sb_0 <= { 4{ 1'd1 } }; + end + __saxi_wdata_cond_0_1 <= 1; + if(__saxi_wvalid_sb_0 && !__saxi_wready_sb_0) begin + __saxi_wvalid_sb_0 <= __saxi_wvalid_sb_0; + end + if((th_ctrl == 17) && (__saxi_wready_sb_0 || !__saxi_wvalid_sb_0)) begin + __saxi_wdata_sb_0 <= _th_ctrl_b_6; + __saxi_wvalid_sb_0 <= 1; + __saxi_wstrb_sb_0 <= { 4{ 1'd1 } }; + end + __saxi_wdata_cond_1_1 <= 1; + if(__saxi_wvalid_sb_0 && !__saxi_wready_sb_0) begin + __saxi_wvalid_sb_0 <= __saxi_wvalid_sb_0; + end + if((th_ctrl == 25) && (__saxi_wready_sb_0 || !__saxi_wvalid_sb_0)) begin + __saxi_wdata_sb_0 <= 1; + __saxi_wvalid_sb_0 <= 1; + __saxi_wstrb_sb_0 <= { 4{ 1'd1 } }; + end + __saxi_wdata_cond_2_1 <= 1; + if(__saxi_wvalid_sb_0 && !__saxi_wready_sb_0) begin + __saxi_wvalid_sb_0 <= __saxi_wvalid_sb_0; + end + end + end + + + always @(posedge CLK) begin + if(RST) begin + _sb__saxi_writedata_data_5 <= 0; + _sb__saxi_writedata_valid_6 <= 0; + _sb__saxi_writedata_tmp_data_8 <= 0; + _sb__saxi_writedata_tmp_valid_9 <= 0; + end else begin + if(_sb__saxi_writedata_m_ready_4 || !_sb__saxi_writedata_valid_6) begin + _sb__saxi_writedata_data_5 <= _sb__saxi_writedata_next_data_10; + _sb__saxi_writedata_valid_6 <= _sb__saxi_writedata_next_valid_11; + end + if(!_sb__saxi_writedata_tmp_valid_9 && _sb__saxi_writedata_valid_6 && !_sb__saxi_writedata_m_ready_4) begin + _sb__saxi_writedata_tmp_data_8 <= _sb__saxi_writedata_s_data_2; + _sb__saxi_writedata_tmp_valid_9 <= _sb__saxi_writedata_s_valid_3; + end + if(_sb__saxi_writedata_tmp_valid_9 && _sb__saxi_writedata_m_ready_4) begin + _sb__saxi_writedata_tmp_valid_9 <= 0; + end + end + end + + + always @(posedge CLK) begin + if(RST) begin + _saxi_araddr <= 0; + _saxi_arvalid <= 0; + __saxi_raddr_cond_0_1 <= 0; + __saxi_raddr_cond_1_1 <= 0; + end else begin + if(__saxi_raddr_cond_0_1) begin + _saxi_arvalid <= 0; end - __saxi_cond_5_1 <= 1; - if(_saxi_wvalid && !_saxi_wready) begin - _saxi_wvalid <= _saxi_wvalid; + if(__saxi_raddr_cond_1_1) begin + _saxi_arvalid <= 0; end if((th_ctrl == 30) && (_saxi_arready || !_saxi_arvalid)) begin _saxi_araddr <= _th_ctrl_araddr_8; _saxi_arvalid <= 1; end - __saxi_cond_6_1 <= 1; + __saxi_raddr_cond_0_1 <= 1; if(_saxi_arvalid && !_saxi_arready) begin _saxi_arvalid <= _saxi_arvalid; end @@ -378,7 +473,7 @@ _saxi_araddr <= _th_ctrl_araddr_8; _saxi_arvalid <= 1; end - __saxi_cond_7_1 <= 1; + __saxi_raddr_cond_1_1 <= 1; if(_saxi_arvalid && !_saxi_arready) begin _saxi_arvalid <= _saxi_arvalid; end @@ -386,6 +481,42 @@ end + always @(posedge CLK) begin + if(RST) begin + _sb__saxi_readdata_data_18 <= 0; + _sb__saxi_readdata_valid_19 <= 0; + _sb__saxi_readdata_tmp_data_21 <= 0; + _sb__saxi_readdata_tmp_valid_22 <= 0; + end else begin + if(_sb__saxi_readdata_m_ready_17 || !_sb__saxi_readdata_valid_19) begin + _sb__saxi_readdata_data_18 <= _sb__saxi_readdata_next_data_23; + _sb__saxi_readdata_valid_19 <= _sb__saxi_readdata_next_valid_24; + end + if(!_sb__saxi_readdata_tmp_valid_22 && _sb__saxi_readdata_valid_19 && !_sb__saxi_readdata_m_ready_17) begin + _sb__saxi_readdata_tmp_data_21 <= _sb__saxi_readdata_s_data_15; + _sb__saxi_readdata_tmp_valid_22 <= _sb__saxi_readdata_s_valid_16; + end + if(_sb__saxi_readdata_tmp_valid_22 && _sb__saxi_readdata_m_ready_17) begin + _sb__saxi_readdata_tmp_valid_22 <= 0; + end + end + end + + + always @(posedge CLK) begin + if(RST) begin + __saxi_outstanding_wcount <= 0; + end else begin + if(_saxi_awvalid && _saxi_awready && !(_saxi_bvalid && _saxi_bready) && (__saxi_outstanding_wcount < 7)) begin + __saxi_outstanding_wcount <= __saxi_outstanding_wcount + 1; + end + if(!(_saxi_awvalid && _saxi_awready) && (_saxi_bvalid && _saxi_bready) && (__saxi_outstanding_wcount > 0)) begin + __saxi_outstanding_wcount <= __saxi_outstanding_wcount - 1; + end + end + end + + always @(posedge CLK) begin if(RST) begin counter <= 0; @@ -451,9 +582,9 @@ _th_ctrl_b_6 <= 0; _th_ctrl_start_time_7 <= 0; _th_ctrl_araddr_8 <= 0; - axim_rdata_13 <= 0; + axim_rdata_39 <= 0; _th_ctrl_busy_9 <= 0; - axim_rdata_14 <= 0; + axim_rdata_40 <= 0; _th_ctrl_c_10 <= 0; _th_ctrl_end_time_11 <= 0; _th_ctrl_time_12 <= 0; @@ -500,12 +631,12 @@ end end th_ctrl_9: begin - if(_saxi_wready || !_saxi_wvalid) begin + if(__saxi_wready_sb_0 || !__saxi_wvalid_sb_0) begin th_ctrl <= th_ctrl_10; end end th_ctrl_10: begin - if(_saxi_wvalid && _saxi_wready) begin + if(__saxi_wvalid_sb_0 && __saxi_wready_sb_0) begin th_ctrl <= th_ctrl_11; end end @@ -537,12 +668,12 @@ end end th_ctrl_17: begin - if(_saxi_wready || !_saxi_wvalid) begin + if(__saxi_wready_sb_0 || !__saxi_wvalid_sb_0) begin th_ctrl <= th_ctrl_18; end end th_ctrl_18: begin - if(_saxi_wvalid && _saxi_wready) begin + if(__saxi_wvalid_sb_0 && __saxi_wready_sb_0) begin th_ctrl <= th_ctrl_19; end end @@ -574,12 +705,12 @@ end end th_ctrl_25: begin - if(_saxi_wready || !_saxi_wvalid) begin + if(__saxi_wready_sb_0 || !__saxi_wvalid_sb_0) begin th_ctrl <= th_ctrl_26; end end th_ctrl_26: begin - if(_saxi_wvalid && _saxi_wready) begin + if(__saxi_wvalid_sb_0 && __saxi_wready_sb_0) begin th_ctrl <= th_ctrl_27; end end @@ -610,15 +741,15 @@ end end th_ctrl_32: begin - if(_saxi_rvalid) begin - axim_rdata_13 <= _saxi_rdata; + if(__saxi_rvalid_sb_0) begin + axim_rdata_39 <= __saxi_rdata_sb_0; end - if(_saxi_rvalid) begin + if(__saxi_rvalid_sb_0) begin th_ctrl <= th_ctrl_33; end end th_ctrl_33: begin - _th_ctrl_busy_9 <= axim_rdata_13; + _th_ctrl_busy_9 <= axim_rdata_39; th_ctrl <= th_ctrl_34; end th_ctrl_34: begin @@ -649,15 +780,15 @@ end end th_ctrl_40: begin - if(_saxi_rvalid) begin - axim_rdata_14 <= _saxi_rdata; + if(__saxi_rvalid_sb_0) begin + axim_rdata_40 <= __saxi_rdata_sb_0; end - if(_saxi_rvalid) begin + if(__saxi_rvalid_sb_0) begin th_ctrl <= th_ctrl_41; end end th_ctrl_41: begin - _th_ctrl_c_10 <= axim_rdata_14; + _th_ctrl_c_10 <= axim_rdata_40; th_ctrl <= th_ctrl_42; end th_ctrl_42: begin @@ -782,7 +913,7 @@ (axis_maskaddr_5 == 5)? _saxi_resetval_5 : (axis_maskaddr_5 == 6)? _saxi_resetval_6 : (axis_maskaddr_5 == 7)? _saxi_resetval_7 : 'hx; - reg _saxi_cond_0_1; + reg _saxi_rdata_cond_0_1; assign saxi_wready = _saxi_register_fsm == 3; reg [32-1:0] th_add; localparam th_add_init = 0; @@ -790,6 +921,27 @@ reg signed [32-1:0] _th_add_b_1; reg signed [32-1:0] _th_add_c_2; + always @(posedge CLK) begin + if(RST) begin + saxi_rdata <= 0; + saxi_rvalid <= 0; + _saxi_rdata_cond_0_1 <= 0; + end else begin + if(_saxi_rdata_cond_0_1) begin + saxi_rvalid <= 0; + end + if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid)) begin + saxi_rdata <= axislite_rdata_6; + saxi_rvalid <= 1; + end + _saxi_rdata_cond_0_1 <= 1; + if(saxi_rvalid && !saxi_rready) begin + saxi_rvalid <= saxi_rvalid; + end + end + end + + always @(posedge CLK) begin if(RST) begin saxi_bvalid <= 0; @@ -798,9 +950,6 @@ writevalid_1 <= 0; readvalid_2 <= 0; addr_0 <= 0; - saxi_rdata <= 0; - saxi_rvalid <= 0; - _saxi_cond_0_1 <= 0; _saxi_register_0 <= 0; _saxi_flag_0 <= 0; _saxi_register_1 <= 0; @@ -818,9 +967,6 @@ _saxi_register_7 <= 0; _saxi_flag_7 <= 0; end else begin - if(_saxi_cond_0_1) begin - saxi_rvalid <= 0; - end if(saxi_bvalid && saxi_bready) begin saxi_bvalid <= 0; end @@ -838,14 +984,6 @@ addr_0 <= saxi_araddr; readvalid_2 <= 1; end - if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid)) begin - saxi_rdata <= axislite_rdata_6; - saxi_rvalid <= 1; - end - _saxi_cond_0_1 <= 1; - if(saxi_rvalid && !saxi_rready) begin - saxi_rvalid <= saxi_rvalid; - end if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_7 && (axis_maskaddr_5 == 0)) begin _saxi_register_0 <= axislite_resetval_8; _saxi_flag_0 <= 0; diff --git a/examples/thread_axi_slave_ipxact/test_thread_axi_slave_ipxact.py b/examples/thread_axi_slave_ipxact/test_thread_axi_slave_ipxact.py index 08aa3c4c..e7fb975e 100644 --- a/examples/thread_axi_slave_ipxact/test_thread_axi_slave_ipxact.py +++ b/examples/thread_axi_slave_ipxact/test_thread_axi_slave_ipxact.py @@ -35,127 +35,185 @@ wire [3-1:0] _saxi_awprot; reg _saxi_awvalid; wire _saxi_awready; - reg [32-1:0] _saxi_wdata; - reg [4-1:0] _saxi_wstrb; - reg _saxi_wvalid; + assign _saxi_awcache = 3; + assign _saxi_awprot = 0; + wire [32-1:0] _saxi_wdata; + wire [4-1:0] _saxi_wstrb; + wire _saxi_wvalid; wire _saxi_wready; + reg [32-1:0] __saxi_wdata_sb_0; + reg [4-1:0] __saxi_wstrb_sb_0; + reg __saxi_wvalid_sb_0; + wire __saxi_wready_sb_0; + wire [4-1:0] _sb__saxi_writedata_s_value_0; + assign _sb__saxi_writedata_s_value_0 = __saxi_wstrb_sb_0; + wire [32-1:0] _sb__saxi_writedata_s_value_1; + assign _sb__saxi_writedata_s_value_1 = __saxi_wdata_sb_0; + wire [36-1:0] _sb__saxi_writedata_s_data_2; + assign _sb__saxi_writedata_s_data_2 = { _sb__saxi_writedata_s_value_0, _sb__saxi_writedata_s_value_1 }; + wire _sb__saxi_writedata_s_valid_3; + assign _sb__saxi_writedata_s_valid_3 = __saxi_wvalid_sb_0; + wire _sb__saxi_writedata_m_ready_4; + assign _sb__saxi_writedata_m_ready_4 = _saxi_wready; + reg [36-1:0] _sb__saxi_writedata_data_5; + reg _sb__saxi_writedata_valid_6; + wire _sb__saxi_writedata_ready_7; + reg [36-1:0] _sb__saxi_writedata_tmp_data_8; + reg _sb__saxi_writedata_tmp_valid_9; + wire [36-1:0] _sb__saxi_writedata_next_data_10; + wire _sb__saxi_writedata_next_valid_11; + assign _sb__saxi_writedata_ready_7 = !_sb__saxi_writedata_tmp_valid_9; + assign _sb__saxi_writedata_next_data_10 = (_sb__saxi_writedata_tmp_valid_9)? _sb__saxi_writedata_tmp_data_8 : _sb__saxi_writedata_s_data_2; + assign _sb__saxi_writedata_next_valid_11 = _sb__saxi_writedata_tmp_valid_9 || _sb__saxi_writedata_s_valid_3; + wire [4-1:0] _sb__saxi_writedata_m_value_12; + assign _sb__saxi_writedata_m_value_12 = _sb__saxi_writedata_data_5[35:32]; + wire [32-1:0] _sb__saxi_writedata_m_value_13; + assign _sb__saxi_writedata_m_value_13 = _sb__saxi_writedata_data_5[31:0]; + assign __saxi_wready_sb_0 = _sb__saxi_writedata_ready_7; + assign _saxi_wdata = _sb__saxi_writedata_m_value_13; + assign _saxi_wstrb = _sb__saxi_writedata_m_value_12; + assign _saxi_wvalid = _sb__saxi_writedata_valid_6; wire [2-1:0] _saxi_bresp; wire _saxi_bvalid; wire _saxi_bready; + assign _saxi_bready = 1; reg [32-1:0] _saxi_araddr; wire [4-1:0] _saxi_arcache; wire [3-1:0] _saxi_arprot; reg _saxi_arvalid; wire _saxi_arready; + assign _saxi_arcache = 3; + assign _saxi_arprot = 0; wire [32-1:0] _saxi_rdata; wire [2-1:0] _saxi_rresp; wire _saxi_rvalid; wire _saxi_rready; - assign _saxi_awcache = 3; - assign _saxi_awprot = 0; - assign _saxi_bready = 1; - assign _saxi_arcache = 3; - assign _saxi_arprot = 0; + wire [32-1:0] __saxi_rdata_sb_0; + wire __saxi_rvalid_sb_0; + wire __saxi_rready_sb_0; + wire [32-1:0] _sb__saxi_readdata_s_value_14; + assign _sb__saxi_readdata_s_value_14 = _saxi_rdata; + wire [32-1:0] _sb__saxi_readdata_s_data_15; + assign _sb__saxi_readdata_s_data_15 = { _sb__saxi_readdata_s_value_14 }; + wire _sb__saxi_readdata_s_valid_16; + assign _sb__saxi_readdata_s_valid_16 = _saxi_rvalid; + wire _sb__saxi_readdata_m_ready_17; + assign _sb__saxi_readdata_m_ready_17 = __saxi_rready_sb_0; + reg [32-1:0] _sb__saxi_readdata_data_18; + reg _sb__saxi_readdata_valid_19; + wire _sb__saxi_readdata_ready_20; + reg [32-1:0] _sb__saxi_readdata_tmp_data_21; + reg _sb__saxi_readdata_tmp_valid_22; + wire [32-1:0] _sb__saxi_readdata_next_data_23; + wire _sb__saxi_readdata_next_valid_24; + assign _sb__saxi_readdata_ready_20 = !_sb__saxi_readdata_tmp_valid_22; + assign _sb__saxi_readdata_next_data_23 = (_sb__saxi_readdata_tmp_valid_22)? _sb__saxi_readdata_tmp_data_21 : _sb__saxi_readdata_s_data_15; + assign _sb__saxi_readdata_next_valid_24 = _sb__saxi_readdata_tmp_valid_22 || _sb__saxi_readdata_s_valid_16; + wire [32-1:0] _sb__saxi_readdata_m_value_25; + assign _sb__saxi_readdata_m_value_25 = _sb__saxi_readdata_data_18[31:0]; + assign __saxi_rdata_sb_0 = _sb__saxi_readdata_m_value_25; + assign __saxi_rvalid_sb_0 = _sb__saxi_readdata_valid_19; + assign _saxi_rready = _sb__saxi_readdata_ready_20; reg [3-1:0] __saxi_outstanding_wcount; wire __saxi_has_outstanding_write; assign __saxi_has_outstanding_write = (__saxi_outstanding_wcount > 0) || _saxi_awvalid; - wire [32-1:0] _tmp_0; - assign _tmp_0 = _saxi_awaddr; + wire [32-1:0] _tmp_26; + assign _tmp_26 = _saxi_awaddr; always @(*) begin - saxi_awaddr = _tmp_0; + saxi_awaddr = _tmp_26; end - wire [4-1:0] _tmp_1; - assign _tmp_1 = _saxi_awcache; + wire [4-1:0] _tmp_27; + assign _tmp_27 = _saxi_awcache; always @(*) begin - saxi_awcache = _tmp_1; + saxi_awcache = _tmp_27; end - wire [3-1:0] _tmp_2; - assign _tmp_2 = _saxi_awprot; + wire [3-1:0] _tmp_28; + assign _tmp_28 = _saxi_awprot; always @(*) begin - saxi_awprot = _tmp_2; + saxi_awprot = _tmp_28; end - wire _tmp_3; - assign _tmp_3 = _saxi_awvalid; + wire _tmp_29; + assign _tmp_29 = _saxi_awvalid; always @(*) begin - saxi_awvalid = _tmp_3; + saxi_awvalid = _tmp_29; end assign _saxi_awready = saxi_awready; - wire [32-1:0] _tmp_4; - assign _tmp_4 = _saxi_wdata; + wire [32-1:0] _tmp_30; + assign _tmp_30 = _saxi_wdata; always @(*) begin - saxi_wdata = _tmp_4; + saxi_wdata = _tmp_30; end - wire [4-1:0] _tmp_5; - assign _tmp_5 = _saxi_wstrb; + wire [4-1:0] _tmp_31; + assign _tmp_31 = _saxi_wstrb; always @(*) begin - saxi_wstrb = _tmp_5; + saxi_wstrb = _tmp_31; end - wire _tmp_6; - assign _tmp_6 = _saxi_wvalid; + wire _tmp_32; + assign _tmp_32 = _saxi_wvalid; always @(*) begin - saxi_wvalid = _tmp_6; + saxi_wvalid = _tmp_32; end assign _saxi_wready = saxi_wready; assign _saxi_bresp = saxi_bresp; assign _saxi_bvalid = saxi_bvalid; - wire _tmp_7; - assign _tmp_7 = _saxi_bready; + wire _tmp_33; + assign _tmp_33 = _saxi_bready; always @(*) begin - saxi_bready = _tmp_7; + saxi_bready = _tmp_33; end - wire [32-1:0] _tmp_8; - assign _tmp_8 = _saxi_araddr; + wire [32-1:0] _tmp_34; + assign _tmp_34 = _saxi_araddr; always @(*) begin - saxi_araddr = _tmp_8; + saxi_araddr = _tmp_34; end - wire [4-1:0] _tmp_9; - assign _tmp_9 = _saxi_arcache; + wire [4-1:0] _tmp_35; + assign _tmp_35 = _saxi_arcache; always @(*) begin - saxi_arcache = _tmp_9; + saxi_arcache = _tmp_35; end - wire [3-1:0] _tmp_10; - assign _tmp_10 = _saxi_arprot; + wire [3-1:0] _tmp_36; + assign _tmp_36 = _saxi_arprot; always @(*) begin - saxi_arprot = _tmp_10; + saxi_arprot = _tmp_36; end - wire _tmp_11; - assign _tmp_11 = _saxi_arvalid; + wire _tmp_37; + assign _tmp_37 = _saxi_arvalid; always @(*) begin - saxi_arvalid = _tmp_11; + saxi_arvalid = _tmp_37; end assign _saxi_arready = saxi_arready; assign _saxi_rdata = saxi_rdata; assign _saxi_rresp = saxi_rresp; assign _saxi_rvalid = saxi_rvalid; - wire _tmp_12; - assign _tmp_12 = _saxi_rready; + wire _tmp_38; + assign _tmp_38 = _saxi_rready; always @(*) begin - saxi_rready = _tmp_12; + saxi_rready = _tmp_38; end reg [32-1:0] counter; @@ -164,18 +222,18 @@ reg signed [32-1:0] _th_ctrl_i_3; reg signed [32-1:0] _th_ctrl_awaddr_4; reg signed [32-1:0] _th_ctrl_sleep_5; - reg __saxi_cond_0_1; - reg __saxi_cond_1_1; + reg __saxi_waddr_cond_0_1; + reg __saxi_wdata_cond_0_1; reg signed [32-1:0] _th_ctrl_size_6; - reg __saxi_cond_2_1; - reg __saxi_cond_3_1; + reg __saxi_waddr_cond_1_1; + reg __saxi_wdata_cond_1_1; reg signed [32-1:0] _th_ctrl_start_time_7; - reg __saxi_cond_4_1; - reg __saxi_cond_5_1; + reg __saxi_waddr_cond_2_1; + reg __saxi_wdata_cond_2_1; reg signed [32-1:0] _th_ctrl_araddr_8; - reg __saxi_cond_6_1; - reg signed [32-1:0] axim_rdata_13; - assign _saxi_rready = th_ctrl == 32; + reg __saxi_raddr_cond_0_1; + reg signed [32-1:0] axim_rdata_39; + assign __saxi_rready_sb_0 = th_ctrl == 32; reg signed [32-1:0] _th_ctrl_busy_9; reg signed [32-1:0] _th_ctrl_end_time_10; reg signed [32-1:0] _th_ctrl_time_11; @@ -228,28 +286,36 @@ RST = 0; _saxi_awaddr = 0; _saxi_awvalid = 0; - _saxi_wdata = 0; - _saxi_wstrb = 0; - _saxi_wvalid = 0; + __saxi_wdata_sb_0 = 0; + __saxi_wstrb_sb_0 = 0; + __saxi_wvalid_sb_0 = 0; + _sb__saxi_writedata_data_5 = 0; + _sb__saxi_writedata_valid_6 = 0; + _sb__saxi_writedata_tmp_data_8 = 0; + _sb__saxi_writedata_tmp_valid_9 = 0; _saxi_araddr = 0; _saxi_arvalid = 0; + _sb__saxi_readdata_data_18 = 0; + _sb__saxi_readdata_valid_19 = 0; + _sb__saxi_readdata_tmp_data_21 = 0; + _sb__saxi_readdata_tmp_valid_22 = 0; __saxi_outstanding_wcount = 0; counter = 0; th_ctrl = th_ctrl_init; _th_ctrl_i_3 = 0; _th_ctrl_awaddr_4 = 0; _th_ctrl_sleep_5 = 0; - __saxi_cond_0_1 = 0; - __saxi_cond_1_1 = 0; + __saxi_waddr_cond_0_1 = 0; + __saxi_wdata_cond_0_1 = 0; _th_ctrl_size_6 = 0; - __saxi_cond_2_1 = 0; - __saxi_cond_3_1 = 0; + __saxi_waddr_cond_1_1 = 0; + __saxi_wdata_cond_1_1 = 0; _th_ctrl_start_time_7 = 0; - __saxi_cond_4_1 = 0; - __saxi_cond_5_1 = 0; + __saxi_waddr_cond_2_1 = 0; + __saxi_wdata_cond_2_1 = 0; _th_ctrl_araddr_8 = 0; - __saxi_cond_6_1 = 0; - axim_rdata_13 = 0; + __saxi_raddr_cond_0_1 = 0; + axim_rdata_39 = 0; _th_ctrl_busy_9 = 0; _th_ctrl_end_time_10 = 0; _th_ctrl_time_11 = 0; @@ -264,105 +330,134 @@ always @(posedge CLK) begin if(RST) begin - __saxi_outstanding_wcount <= 0; _saxi_awaddr <= 0; _saxi_awvalid <= 0; - __saxi_cond_0_1 <= 0; - _saxi_wdata <= 0; - _saxi_wvalid <= 0; - _saxi_wstrb <= 0; - __saxi_cond_1_1 <= 0; - __saxi_cond_2_1 <= 0; - __saxi_cond_3_1 <= 0; - __saxi_cond_4_1 <= 0; - __saxi_cond_5_1 <= 0; - _saxi_araddr <= 0; - _saxi_arvalid <= 0; - __saxi_cond_6_1 <= 0; + __saxi_waddr_cond_0_1 <= 0; + __saxi_waddr_cond_1_1 <= 0; + __saxi_waddr_cond_2_1 <= 0; end else begin - if(__saxi_cond_0_1) begin + if(__saxi_waddr_cond_0_1) begin _saxi_awvalid <= 0; end - if(__saxi_cond_1_1) begin - _saxi_wvalid <= 0; - end - if(__saxi_cond_2_1) begin + if(__saxi_waddr_cond_1_1) begin _saxi_awvalid <= 0; end - if(__saxi_cond_3_1) begin - _saxi_wvalid <= 0; - end - if(__saxi_cond_4_1) begin + if(__saxi_waddr_cond_2_1) begin _saxi_awvalid <= 0; end - if(__saxi_cond_5_1) begin - _saxi_wvalid <= 0; - end - if(__saxi_cond_6_1) begin - _saxi_arvalid <= 0; - end - if(_saxi_awvalid && _saxi_awready && !(_saxi_bvalid && _saxi_bready) && (__saxi_outstanding_wcount < 7)) begin - __saxi_outstanding_wcount <= __saxi_outstanding_wcount + 1; - end - if(!(_saxi_awvalid && _saxi_awready) && (_saxi_bvalid && _saxi_bready) && (__saxi_outstanding_wcount > 0)) begin - __saxi_outstanding_wcount <= __saxi_outstanding_wcount - 1; - end if((th_ctrl == 7) && ((__saxi_outstanding_wcount == 0) && (_saxi_awready || !_saxi_awvalid))) begin _saxi_awaddr <= _th_ctrl_awaddr_4; _saxi_awvalid <= 1; end - __saxi_cond_0_1 <= 1; + __saxi_waddr_cond_0_1 <= 1; if(_saxi_awvalid && !_saxi_awready) begin _saxi_awvalid <= _saxi_awvalid; end - if((th_ctrl == 9) && (_saxi_wready || !_saxi_wvalid)) begin - _saxi_wdata <= _th_ctrl_sleep_5; - _saxi_wvalid <= 1; - _saxi_wstrb <= { 4{ 1'd1 } }; - end - __saxi_cond_1_1 <= 1; - if(_saxi_wvalid && !_saxi_wready) begin - _saxi_wvalid <= _saxi_wvalid; - end if((th_ctrl == 15) && ((__saxi_outstanding_wcount == 0) && (_saxi_awready || !_saxi_awvalid))) begin _saxi_awaddr <= _th_ctrl_awaddr_4; _saxi_awvalid <= 1; end - __saxi_cond_2_1 <= 1; + __saxi_waddr_cond_1_1 <= 1; if(_saxi_awvalid && !_saxi_awready) begin _saxi_awvalid <= _saxi_awvalid; end - if((th_ctrl == 17) && (_saxi_wready || !_saxi_wvalid)) begin - _saxi_wdata <= _th_ctrl_size_6; - _saxi_wvalid <= 1; - _saxi_wstrb <= { 4{ 1'd1 } }; - end - __saxi_cond_3_1 <= 1; - if(_saxi_wvalid && !_saxi_wready) begin - _saxi_wvalid <= _saxi_wvalid; - end if((th_ctrl == 23) && ((__saxi_outstanding_wcount == 0) && (_saxi_awready || !_saxi_awvalid))) begin _saxi_awaddr <= _th_ctrl_awaddr_4; _saxi_awvalid <= 1; end - __saxi_cond_4_1 <= 1; + __saxi_waddr_cond_2_1 <= 1; if(_saxi_awvalid && !_saxi_awready) begin _saxi_awvalid <= _saxi_awvalid; end - if((th_ctrl == 25) && (_saxi_wready || !_saxi_wvalid)) begin - _saxi_wdata <= 1; - _saxi_wvalid <= 1; - _saxi_wstrb <= { 4{ 1'd1 } }; + end + end + + + always @(posedge CLK) begin + if(RST) begin + __saxi_wdata_sb_0 <= 0; + __saxi_wvalid_sb_0 <= 0; + __saxi_wstrb_sb_0 <= 0; + __saxi_wdata_cond_0_1 <= 0; + __saxi_wdata_cond_1_1 <= 0; + __saxi_wdata_cond_2_1 <= 0; + end else begin + if(__saxi_wdata_cond_0_1) begin + __saxi_wvalid_sb_0 <= 0; + end + if(__saxi_wdata_cond_1_1) begin + __saxi_wvalid_sb_0 <= 0; + end + if(__saxi_wdata_cond_2_1) begin + __saxi_wvalid_sb_0 <= 0; end - __saxi_cond_5_1 <= 1; - if(_saxi_wvalid && !_saxi_wready) begin - _saxi_wvalid <= _saxi_wvalid; + if((th_ctrl == 9) && (__saxi_wready_sb_0 || !__saxi_wvalid_sb_0)) begin + __saxi_wdata_sb_0 <= _th_ctrl_sleep_5; + __saxi_wvalid_sb_0 <= 1; + __saxi_wstrb_sb_0 <= { 4{ 1'd1 } }; + end + __saxi_wdata_cond_0_1 <= 1; + if(__saxi_wvalid_sb_0 && !__saxi_wready_sb_0) begin + __saxi_wvalid_sb_0 <= __saxi_wvalid_sb_0; + end + if((th_ctrl == 17) && (__saxi_wready_sb_0 || !__saxi_wvalid_sb_0)) begin + __saxi_wdata_sb_0 <= _th_ctrl_size_6; + __saxi_wvalid_sb_0 <= 1; + __saxi_wstrb_sb_0 <= { 4{ 1'd1 } }; + end + __saxi_wdata_cond_1_1 <= 1; + if(__saxi_wvalid_sb_0 && !__saxi_wready_sb_0) begin + __saxi_wvalid_sb_0 <= __saxi_wvalid_sb_0; + end + if((th_ctrl == 25) && (__saxi_wready_sb_0 || !__saxi_wvalid_sb_0)) begin + __saxi_wdata_sb_0 <= 1; + __saxi_wvalid_sb_0 <= 1; + __saxi_wstrb_sb_0 <= { 4{ 1'd1 } }; + end + __saxi_wdata_cond_2_1 <= 1; + if(__saxi_wvalid_sb_0 && !__saxi_wready_sb_0) begin + __saxi_wvalid_sb_0 <= __saxi_wvalid_sb_0; + end + end + end + + + always @(posedge CLK) begin + if(RST) begin + _sb__saxi_writedata_data_5 <= 0; + _sb__saxi_writedata_valid_6 <= 0; + _sb__saxi_writedata_tmp_data_8 <= 0; + _sb__saxi_writedata_tmp_valid_9 <= 0; + end else begin + if(_sb__saxi_writedata_m_ready_4 || !_sb__saxi_writedata_valid_6) begin + _sb__saxi_writedata_data_5 <= _sb__saxi_writedata_next_data_10; + _sb__saxi_writedata_valid_6 <= _sb__saxi_writedata_next_valid_11; + end + if(!_sb__saxi_writedata_tmp_valid_9 && _sb__saxi_writedata_valid_6 && !_sb__saxi_writedata_m_ready_4) begin + _sb__saxi_writedata_tmp_data_8 <= _sb__saxi_writedata_s_data_2; + _sb__saxi_writedata_tmp_valid_9 <= _sb__saxi_writedata_s_valid_3; + end + if(_sb__saxi_writedata_tmp_valid_9 && _sb__saxi_writedata_m_ready_4) begin + _sb__saxi_writedata_tmp_valid_9 <= 0; + end + end + end + + + always @(posedge CLK) begin + if(RST) begin + _saxi_araddr <= 0; + _saxi_arvalid <= 0; + __saxi_raddr_cond_0_1 <= 0; + end else begin + if(__saxi_raddr_cond_0_1) begin + _saxi_arvalid <= 0; end if((th_ctrl == 30) && (_saxi_arready || !_saxi_arvalid)) begin _saxi_araddr <= _th_ctrl_araddr_8; _saxi_arvalid <= 1; end - __saxi_cond_6_1 <= 1; + __saxi_raddr_cond_0_1 <= 1; if(_saxi_arvalid && !_saxi_arready) begin _saxi_arvalid <= _saxi_arvalid; end @@ -370,6 +465,42 @@ end + always @(posedge CLK) begin + if(RST) begin + _sb__saxi_readdata_data_18 <= 0; + _sb__saxi_readdata_valid_19 <= 0; + _sb__saxi_readdata_tmp_data_21 <= 0; + _sb__saxi_readdata_tmp_valid_22 <= 0; + end else begin + if(_sb__saxi_readdata_m_ready_17 || !_sb__saxi_readdata_valid_19) begin + _sb__saxi_readdata_data_18 <= _sb__saxi_readdata_next_data_23; + _sb__saxi_readdata_valid_19 <= _sb__saxi_readdata_next_valid_24; + end + if(!_sb__saxi_readdata_tmp_valid_22 && _sb__saxi_readdata_valid_19 && !_sb__saxi_readdata_m_ready_17) begin + _sb__saxi_readdata_tmp_data_21 <= _sb__saxi_readdata_s_data_15; + _sb__saxi_readdata_tmp_valid_22 <= _sb__saxi_readdata_s_valid_16; + end + if(_sb__saxi_readdata_tmp_valid_22 && _sb__saxi_readdata_m_ready_17) begin + _sb__saxi_readdata_tmp_valid_22 <= 0; + end + end + end + + + always @(posedge CLK) begin + if(RST) begin + __saxi_outstanding_wcount <= 0; + end else begin + if(_saxi_awvalid && _saxi_awready && !(_saxi_bvalid && _saxi_bready) && (__saxi_outstanding_wcount < 7)) begin + __saxi_outstanding_wcount <= __saxi_outstanding_wcount + 1; + end + if(!(_saxi_awvalid && _saxi_awready) && (_saxi_bvalid && _saxi_bready) && (__saxi_outstanding_wcount > 0)) begin + __saxi_outstanding_wcount <= __saxi_outstanding_wcount - 1; + end + end + end + + always @(posedge CLK) begin if(RST) begin counter <= 0; @@ -429,7 +560,7 @@ _th_ctrl_size_6 <= 0; _th_ctrl_start_time_7 <= 0; _th_ctrl_araddr_8 <= 0; - axim_rdata_13 <= 0; + axim_rdata_39 <= 0; _th_ctrl_busy_9 <= 0; _th_ctrl_end_time_10 <= 0; _th_ctrl_time_11 <= 0; @@ -476,12 +607,12 @@ end end th_ctrl_9: begin - if(_saxi_wready || !_saxi_wvalid) begin + if(__saxi_wready_sb_0 || !__saxi_wvalid_sb_0) begin th_ctrl <= th_ctrl_10; end end th_ctrl_10: begin - if(_saxi_wvalid && _saxi_wready) begin + if(__saxi_wvalid_sb_0 && __saxi_wready_sb_0) begin th_ctrl <= th_ctrl_11; end end @@ -513,12 +644,12 @@ end end th_ctrl_17: begin - if(_saxi_wready || !_saxi_wvalid) begin + if(__saxi_wready_sb_0 || !__saxi_wvalid_sb_0) begin th_ctrl <= th_ctrl_18; end end th_ctrl_18: begin - if(_saxi_wvalid && _saxi_wready) begin + if(__saxi_wvalid_sb_0 && __saxi_wready_sb_0) begin th_ctrl <= th_ctrl_19; end end @@ -550,12 +681,12 @@ end end th_ctrl_25: begin - if(_saxi_wready || !_saxi_wvalid) begin + if(__saxi_wready_sb_0 || !__saxi_wvalid_sb_0) begin th_ctrl <= th_ctrl_26; end end th_ctrl_26: begin - if(_saxi_wvalid && _saxi_wready) begin + if(__saxi_wvalid_sb_0 && __saxi_wready_sb_0) begin th_ctrl <= th_ctrl_27; end end @@ -586,15 +717,15 @@ end end th_ctrl_32: begin - if(_saxi_rvalid) begin - axim_rdata_13 <= _saxi_rdata; + if(__saxi_rvalid_sb_0) begin + axim_rdata_39 <= __saxi_rdata_sb_0; end - if(_saxi_rvalid) begin + if(__saxi_rvalid_sb_0) begin th_ctrl <= th_ctrl_33; end end th_ctrl_33: begin - _th_ctrl_busy_9 <= axim_rdata_13; + _th_ctrl_busy_9 <= axim_rdata_39; th_ctrl <= th_ctrl_34; end th_ctrl_34: begin @@ -705,7 +836,7 @@ (axis_maskaddr_5 == 1)? _saxi_resetval_1 : (axis_maskaddr_5 == 2)? _saxi_resetval_2 : (axis_maskaddr_5 == 3)? _saxi_resetval_3 : 'hx; - reg _saxi_cond_0_1; + reg _saxi_rdata_cond_0_1; assign saxi_wready = _saxi_register_fsm == 3; reg [32-1:0] th_blink; localparam th_blink_init = 0; @@ -714,6 +845,27 @@ reg signed [32-1:0] _th_blink_i_2; reg [32-1:0] _tmp_9; + always @(posedge CLK) begin + if(RST) begin + saxi_rdata <= 0; + saxi_rvalid <= 0; + _saxi_rdata_cond_0_1 <= 0; + end else begin + if(_saxi_rdata_cond_0_1) begin + saxi_rvalid <= 0; + end + if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid)) begin + saxi_rdata <= axislite_rdata_6; + saxi_rvalid <= 1; + end + _saxi_rdata_cond_0_1 <= 1; + if(saxi_rvalid && !saxi_rready) begin + saxi_rvalid <= saxi_rvalid; + end + end + end + + always @(posedge CLK) begin if(RST) begin saxi_bvalid <= 0; @@ -722,9 +874,6 @@ writevalid_1 <= 0; readvalid_2 <= 0; addr_0 <= 0; - saxi_rdata <= 0; - saxi_rvalid <= 0; - _saxi_cond_0_1 <= 0; _saxi_register_0 <= 0; _saxi_flag_0 <= 0; _saxi_register_1 <= 0; @@ -734,9 +883,6 @@ _saxi_register_3 <= 0; _saxi_flag_3 <= 0; end else begin - if(_saxi_cond_0_1) begin - saxi_rvalid <= 0; - end if(saxi_bvalid && saxi_bready) begin saxi_bvalid <= 0; end @@ -754,14 +900,6 @@ addr_0 <= saxi_araddr; readvalid_2 <= 1; end - if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid)) begin - saxi_rdata <= axislite_rdata_6; - saxi_rvalid <= 1; - end - _saxi_cond_0_1 <= 1; - if(saxi_rvalid && !saxi_rready) begin - saxi_rvalid <= saxi_rvalid; - end if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_7 && (axis_maskaddr_5 == 0)) begin _saxi_register_0 <= axislite_resetval_8; _saxi_flag_0 <= 0; diff --git a/examples/thread_axi_slave_ipxact/thread_axi_slave_ipxact.py b/examples/thread_axi_slave_ipxact/thread_axi_slave_ipxact.py index 4b03d947..50ce756f 100644 --- a/examples/thread_axi_slave_ipxact/thread_axi_slave_ipxact.py +++ b/examples/thread_axi_slave_ipxact/thread_axi_slave_ipxact.py @@ -128,6 +128,7 @@ def ctrl(): return m + if __name__ == '__main__': test = mkTest() verilog = test.to_verilog('tmp.v') diff --git a/examples/thread_embedded_verilog_ipxact/test_thread_embedded_verilog_ipxact.py b/examples/thread_embedded_verilog_ipxact/test_thread_embedded_verilog_ipxact.py index 00dbda20..4135804e 100644 --- a/examples/thread_embedded_verilog_ipxact/test_thread_embedded_verilog_ipxact.py +++ b/examples/thread_embedded_verilog_ipxact/test_thread_embedded_verilog_ipxact.py @@ -149,6 +149,7 @@ wire [2-1:0] memory_bresp; reg memory_bvalid; wire memory_bready; + assign memory_bresp = 0; wire [32-1:0] memory_araddr; wire [8-1:0] memory_arlen; wire [3-1:0] memory_arsize; @@ -165,7 +166,6 @@ reg memory_rlast; reg memory_rvalid; wire memory_rready; - assign memory_bresp = 0; assign memory_rresp = 0; reg [32-1:0] _memory_waddr_fsm; localparam _memory_waddr_fsm_init = 0; @@ -418,127 +418,185 @@ wire [3-1:0] _saxi_awprot; reg _saxi_awvalid; wire _saxi_awready; - reg [32-1:0] _saxi_wdata; - reg [4-1:0] _saxi_wstrb; - reg _saxi_wvalid; + assign _saxi_awcache = 3; + assign _saxi_awprot = 0; + wire [32-1:0] _saxi_wdata; + wire [4-1:0] _saxi_wstrb; + wire _saxi_wvalid; wire _saxi_wready; + reg [32-1:0] __saxi_wdata_sb_0; + reg [4-1:0] __saxi_wstrb_sb_0; + reg __saxi_wvalid_sb_0; + wire __saxi_wready_sb_0; + wire [4-1:0] _sb__saxi_writedata_s_value_34; + assign _sb__saxi_writedata_s_value_34 = __saxi_wstrb_sb_0; + wire [32-1:0] _sb__saxi_writedata_s_value_35; + assign _sb__saxi_writedata_s_value_35 = __saxi_wdata_sb_0; + wire [36-1:0] _sb__saxi_writedata_s_data_36; + assign _sb__saxi_writedata_s_data_36 = { _sb__saxi_writedata_s_value_34, _sb__saxi_writedata_s_value_35 }; + wire _sb__saxi_writedata_s_valid_37; + assign _sb__saxi_writedata_s_valid_37 = __saxi_wvalid_sb_0; + wire _sb__saxi_writedata_m_ready_38; + assign _sb__saxi_writedata_m_ready_38 = _saxi_wready; + reg [36-1:0] _sb__saxi_writedata_data_39; + reg _sb__saxi_writedata_valid_40; + wire _sb__saxi_writedata_ready_41; + reg [36-1:0] _sb__saxi_writedata_tmp_data_42; + reg _sb__saxi_writedata_tmp_valid_43; + wire [36-1:0] _sb__saxi_writedata_next_data_44; + wire _sb__saxi_writedata_next_valid_45; + assign _sb__saxi_writedata_ready_41 = !_sb__saxi_writedata_tmp_valid_43; + assign _sb__saxi_writedata_next_data_44 = (_sb__saxi_writedata_tmp_valid_43)? _sb__saxi_writedata_tmp_data_42 : _sb__saxi_writedata_s_data_36; + assign _sb__saxi_writedata_next_valid_45 = _sb__saxi_writedata_tmp_valid_43 || _sb__saxi_writedata_s_valid_37; + wire [4-1:0] _sb__saxi_writedata_m_value_46; + assign _sb__saxi_writedata_m_value_46 = _sb__saxi_writedata_data_39[35:32]; + wire [32-1:0] _sb__saxi_writedata_m_value_47; + assign _sb__saxi_writedata_m_value_47 = _sb__saxi_writedata_data_39[31:0]; + assign __saxi_wready_sb_0 = _sb__saxi_writedata_ready_41; + assign _saxi_wdata = _sb__saxi_writedata_m_value_47; + assign _saxi_wstrb = _sb__saxi_writedata_m_value_46; + assign _saxi_wvalid = _sb__saxi_writedata_valid_40; wire [2-1:0] _saxi_bresp; wire _saxi_bvalid; wire _saxi_bready; + assign _saxi_bready = 1; reg [32-1:0] _saxi_araddr; wire [4-1:0] _saxi_arcache; wire [3-1:0] _saxi_arprot; reg _saxi_arvalid; wire _saxi_arready; + assign _saxi_arcache = 3; + assign _saxi_arprot = 0; wire [32-1:0] _saxi_rdata; wire [2-1:0] _saxi_rresp; wire _saxi_rvalid; wire _saxi_rready; - assign _saxi_awcache = 3; - assign _saxi_awprot = 0; - assign _saxi_bready = 1; - assign _saxi_arcache = 3; - assign _saxi_arprot = 0; + wire [32-1:0] __saxi_rdata_sb_0; + wire __saxi_rvalid_sb_0; + wire __saxi_rready_sb_0; + wire [32-1:0] _sb__saxi_readdata_s_value_48; + assign _sb__saxi_readdata_s_value_48 = _saxi_rdata; + wire [32-1:0] _sb__saxi_readdata_s_data_49; + assign _sb__saxi_readdata_s_data_49 = { _sb__saxi_readdata_s_value_48 }; + wire _sb__saxi_readdata_s_valid_50; + assign _sb__saxi_readdata_s_valid_50 = _saxi_rvalid; + wire _sb__saxi_readdata_m_ready_51; + assign _sb__saxi_readdata_m_ready_51 = __saxi_rready_sb_0; + reg [32-1:0] _sb__saxi_readdata_data_52; + reg _sb__saxi_readdata_valid_53; + wire _sb__saxi_readdata_ready_54; + reg [32-1:0] _sb__saxi_readdata_tmp_data_55; + reg _sb__saxi_readdata_tmp_valid_56; + wire [32-1:0] _sb__saxi_readdata_next_data_57; + wire _sb__saxi_readdata_next_valid_58; + assign _sb__saxi_readdata_ready_54 = !_sb__saxi_readdata_tmp_valid_56; + assign _sb__saxi_readdata_next_data_57 = (_sb__saxi_readdata_tmp_valid_56)? _sb__saxi_readdata_tmp_data_55 : _sb__saxi_readdata_s_data_49; + assign _sb__saxi_readdata_next_valid_58 = _sb__saxi_readdata_tmp_valid_56 || _sb__saxi_readdata_s_valid_50; + wire [32-1:0] _sb__saxi_readdata_m_value_59; + assign _sb__saxi_readdata_m_value_59 = _sb__saxi_readdata_data_52[31:0]; + assign __saxi_rdata_sb_0 = _sb__saxi_readdata_m_value_59; + assign __saxi_rvalid_sb_0 = _sb__saxi_readdata_valid_53; + assign _saxi_rready = _sb__saxi_readdata_ready_54; reg [3-1:0] __saxi_outstanding_wcount; wire __saxi_has_outstanding_write; assign __saxi_has_outstanding_write = (__saxi_outstanding_wcount > 0) || _saxi_awvalid; - wire [32-1:0] _tmp_34; - assign _tmp_34 = _saxi_awaddr; + wire [32-1:0] _tmp_60; + assign _tmp_60 = _saxi_awaddr; always @(*) begin - uut_saxi_awaddr = _tmp_34; + uut_saxi_awaddr = _tmp_60; end - wire [4-1:0] _tmp_35; - assign _tmp_35 = _saxi_awcache; + wire [4-1:0] _tmp_61; + assign _tmp_61 = _saxi_awcache; always @(*) begin - uut_saxi_awcache = _tmp_35; + uut_saxi_awcache = _tmp_61; end - wire [3-1:0] _tmp_36; - assign _tmp_36 = _saxi_awprot; + wire [3-1:0] _tmp_62; + assign _tmp_62 = _saxi_awprot; always @(*) begin - uut_saxi_awprot = _tmp_36; + uut_saxi_awprot = _tmp_62; end - wire _tmp_37; - assign _tmp_37 = _saxi_awvalid; + wire _tmp_63; + assign _tmp_63 = _saxi_awvalid; always @(*) begin - uut_saxi_awvalid = _tmp_37; + uut_saxi_awvalid = _tmp_63; end assign _saxi_awready = uut_saxi_awready; - wire [32-1:0] _tmp_38; - assign _tmp_38 = _saxi_wdata; + wire [32-1:0] _tmp_64; + assign _tmp_64 = _saxi_wdata; always @(*) begin - uut_saxi_wdata = _tmp_38; + uut_saxi_wdata = _tmp_64; end - wire [4-1:0] _tmp_39; - assign _tmp_39 = _saxi_wstrb; + wire [4-1:0] _tmp_65; + assign _tmp_65 = _saxi_wstrb; always @(*) begin - uut_saxi_wstrb = _tmp_39; + uut_saxi_wstrb = _tmp_65; end - wire _tmp_40; - assign _tmp_40 = _saxi_wvalid; + wire _tmp_66; + assign _tmp_66 = _saxi_wvalid; always @(*) begin - uut_saxi_wvalid = _tmp_40; + uut_saxi_wvalid = _tmp_66; end assign _saxi_wready = uut_saxi_wready; assign _saxi_bresp = uut_saxi_bresp; assign _saxi_bvalid = uut_saxi_bvalid; - wire _tmp_41; - assign _tmp_41 = _saxi_bready; + wire _tmp_67; + assign _tmp_67 = _saxi_bready; always @(*) begin - uut_saxi_bready = _tmp_41; + uut_saxi_bready = _tmp_67; end - wire [32-1:0] _tmp_42; - assign _tmp_42 = _saxi_araddr; + wire [32-1:0] _tmp_68; + assign _tmp_68 = _saxi_araddr; always @(*) begin - uut_saxi_araddr = _tmp_42; + uut_saxi_araddr = _tmp_68; end - wire [4-1:0] _tmp_43; - assign _tmp_43 = _saxi_arcache; + wire [4-1:0] _tmp_69; + assign _tmp_69 = _saxi_arcache; always @(*) begin - uut_saxi_arcache = _tmp_43; + uut_saxi_arcache = _tmp_69; end - wire [3-1:0] _tmp_44; - assign _tmp_44 = _saxi_arprot; + wire [3-1:0] _tmp_70; + assign _tmp_70 = _saxi_arprot; always @(*) begin - uut_saxi_arprot = _tmp_44; + uut_saxi_arprot = _tmp_70; end - wire _tmp_45; - assign _tmp_45 = _saxi_arvalid; + wire _tmp_71; + assign _tmp_71 = _saxi_arvalid; always @(*) begin - uut_saxi_arvalid = _tmp_45; + uut_saxi_arvalid = _tmp_71; end assign _saxi_arready = uut_saxi_arready; assign _saxi_rdata = uut_saxi_rdata; assign _saxi_rresp = uut_saxi_rresp; assign _saxi_rvalid = uut_saxi_rvalid; - wire _tmp_46; - assign _tmp_46 = _saxi_rready; + wire _tmp_72; + assign _tmp_72 = _saxi_rready; always @(*) begin - uut_saxi_rready = _tmp_46; + uut_saxi_rready = _tmp_72; end reg [32-1:0] counter; @@ -546,21 +604,21 @@ localparam th_ctrl_init = 0; reg signed [32-1:0] _th_ctrl_i_11; reg signed [32-1:0] _th_ctrl_awaddr_12; - reg __saxi_cond_0_1; - reg __saxi_cond_1_1; + reg __saxi_waddr_cond_0_1; + reg __saxi_wdata_cond_0_1; reg signed [32-1:0] _th_ctrl_src_offset_13; - reg __saxi_cond_2_1; - reg __saxi_cond_3_1; + reg __saxi_waddr_cond_1_1; + reg __saxi_wdata_cond_1_1; reg signed [32-1:0] _th_ctrl_dst_offset_14; - reg __saxi_cond_4_1; - reg __saxi_cond_5_1; + reg __saxi_waddr_cond_2_1; + reg __saxi_wdata_cond_2_1; reg signed [32-1:0] _th_ctrl_start_time_15; - reg __saxi_cond_6_1; - reg __saxi_cond_7_1; + reg __saxi_waddr_cond_3_1; + reg __saxi_wdata_cond_3_1; reg signed [32-1:0] _th_ctrl_araddr_16; - reg __saxi_cond_8_1; - reg signed [32-1:0] axim_rdata_47; - assign _saxi_rready = th_ctrl == 39; + reg __saxi_raddr_cond_0_1; + reg signed [32-1:0] axim_rdata_73; + assign __saxi_rready_sb_0 = th_ctrl == 39; reg signed [32-1:0] _th_ctrl_busy_17; reg signed [32-1:0] _th_ctrl_end_time_18; reg signed [32-1:0] _th_ctrl_time_19; @@ -607,30 +665,38 @@ __memory_rdata_fsm_cond_11_0_1 = 0; _saxi_awaddr = 0; _saxi_awvalid = 0; - _saxi_wdata = 0; - _saxi_wstrb = 0; - _saxi_wvalid = 0; + __saxi_wdata_sb_0 = 0; + __saxi_wstrb_sb_0 = 0; + __saxi_wvalid_sb_0 = 0; + _sb__saxi_writedata_data_39 = 0; + _sb__saxi_writedata_valid_40 = 0; + _sb__saxi_writedata_tmp_data_42 = 0; + _sb__saxi_writedata_tmp_valid_43 = 0; _saxi_araddr = 0; _saxi_arvalid = 0; + _sb__saxi_readdata_data_52 = 0; + _sb__saxi_readdata_valid_53 = 0; + _sb__saxi_readdata_tmp_data_55 = 0; + _sb__saxi_readdata_tmp_valid_56 = 0; __saxi_outstanding_wcount = 0; counter = 0; th_ctrl = th_ctrl_init; _th_ctrl_i_11 = 0; _th_ctrl_awaddr_12 = 0; - __saxi_cond_0_1 = 0; - __saxi_cond_1_1 = 0; + __saxi_waddr_cond_0_1 = 0; + __saxi_wdata_cond_0_1 = 0; _th_ctrl_src_offset_13 = 0; - __saxi_cond_2_1 = 0; - __saxi_cond_3_1 = 0; + __saxi_waddr_cond_1_1 = 0; + __saxi_wdata_cond_1_1 = 0; _th_ctrl_dst_offset_14 = 0; - __saxi_cond_4_1 = 0; - __saxi_cond_5_1 = 0; + __saxi_waddr_cond_2_1 = 0; + __saxi_wdata_cond_2_1 = 0; _th_ctrl_start_time_15 = 0; - __saxi_cond_6_1 = 0; - __saxi_cond_7_1 = 0; + __saxi_waddr_cond_3_1 = 0; + __saxi_wdata_cond_3_1 = 0; _th_ctrl_araddr_16 = 0; - __saxi_cond_8_1 = 0; - axim_rdata_47 = 0; + __saxi_raddr_cond_0_1 = 0; + axim_rdata_73 = 0; _th_ctrl_busy_17 = 0; _th_ctrl_end_time_18 = 0; _th_ctrl_time_19 = 0; @@ -986,130 +1052,159 @@ always @(posedge uut_CLK) begin if(uut_RST) begin - __saxi_outstanding_wcount <= 0; _saxi_awaddr <= 0; _saxi_awvalid <= 0; - __saxi_cond_0_1 <= 0; - _saxi_wdata <= 0; - _saxi_wvalid <= 0; - _saxi_wstrb <= 0; - __saxi_cond_1_1 <= 0; - __saxi_cond_2_1 <= 0; - __saxi_cond_3_1 <= 0; - __saxi_cond_4_1 <= 0; - __saxi_cond_5_1 <= 0; - __saxi_cond_6_1 <= 0; - __saxi_cond_7_1 <= 0; - _saxi_araddr <= 0; - _saxi_arvalid <= 0; - __saxi_cond_8_1 <= 0; + __saxi_waddr_cond_0_1 <= 0; + __saxi_waddr_cond_1_1 <= 0; + __saxi_waddr_cond_2_1 <= 0; + __saxi_waddr_cond_3_1 <= 0; end else begin - if(__saxi_cond_0_1) begin + if(__saxi_waddr_cond_0_1) begin _saxi_awvalid <= 0; end - if(__saxi_cond_1_1) begin - _saxi_wvalid <= 0; - end - if(__saxi_cond_2_1) begin + if(__saxi_waddr_cond_1_1) begin _saxi_awvalid <= 0; end - if(__saxi_cond_3_1) begin - _saxi_wvalid <= 0; - end - if(__saxi_cond_4_1) begin + if(__saxi_waddr_cond_2_1) begin _saxi_awvalid <= 0; end - if(__saxi_cond_5_1) begin - _saxi_wvalid <= 0; - end - if(__saxi_cond_6_1) begin + if(__saxi_waddr_cond_3_1) begin _saxi_awvalid <= 0; end - if(__saxi_cond_7_1) begin - _saxi_wvalid <= 0; - end - if(__saxi_cond_8_1) begin - _saxi_arvalid <= 0; - end - if(_saxi_awvalid && _saxi_awready && !(_saxi_bvalid && _saxi_bready) && (__saxi_outstanding_wcount < 7)) begin - __saxi_outstanding_wcount <= __saxi_outstanding_wcount + 1; - end - if(!(_saxi_awvalid && _saxi_awready) && (_saxi_bvalid && _saxi_bready) && (__saxi_outstanding_wcount > 0)) begin - __saxi_outstanding_wcount <= __saxi_outstanding_wcount - 1; - end if((th_ctrl == 6) && ((__saxi_outstanding_wcount == 0) && (_saxi_awready || !_saxi_awvalid))) begin _saxi_awaddr <= _th_ctrl_awaddr_12; _saxi_awvalid <= 1; end - __saxi_cond_0_1 <= 1; + __saxi_waddr_cond_0_1 <= 1; if(_saxi_awvalid && !_saxi_awready) begin _saxi_awvalid <= _saxi_awvalid; end - if((th_ctrl == 8) && (_saxi_wready || !_saxi_wvalid)) begin - _saxi_wdata <= 4096; - _saxi_wvalid <= 1; - _saxi_wstrb <= { 4{ 1'd1 } }; - end - __saxi_cond_1_1 <= 1; - if(_saxi_wvalid && !_saxi_wready) begin - _saxi_wvalid <= _saxi_wvalid; - end if((th_ctrl == 14) && ((__saxi_outstanding_wcount == 0) && (_saxi_awready || !_saxi_awvalid))) begin _saxi_awaddr <= _th_ctrl_awaddr_12; _saxi_awvalid <= 1; end - __saxi_cond_2_1 <= 1; + __saxi_waddr_cond_1_1 <= 1; if(_saxi_awvalid && !_saxi_awready) begin _saxi_awvalid <= _saxi_awvalid; end - if((th_ctrl == 16) && (_saxi_wready || !_saxi_wvalid)) begin - _saxi_wdata <= _th_ctrl_src_offset_13; - _saxi_wvalid <= 1; - _saxi_wstrb <= { 4{ 1'd1 } }; - end - __saxi_cond_3_1 <= 1; - if(_saxi_wvalid && !_saxi_wready) begin - _saxi_wvalid <= _saxi_wvalid; - end if((th_ctrl == 22) && ((__saxi_outstanding_wcount == 0) && (_saxi_awready || !_saxi_awvalid))) begin _saxi_awaddr <= _th_ctrl_awaddr_12; _saxi_awvalid <= 1; end - __saxi_cond_4_1 <= 1; + __saxi_waddr_cond_2_1 <= 1; if(_saxi_awvalid && !_saxi_awready) begin _saxi_awvalid <= _saxi_awvalid; end - if((th_ctrl == 24) && (_saxi_wready || !_saxi_wvalid)) begin - _saxi_wdata <= _th_ctrl_dst_offset_14; - _saxi_wvalid <= 1; - _saxi_wstrb <= { 4{ 1'd1 } }; - end - __saxi_cond_5_1 <= 1; - if(_saxi_wvalid && !_saxi_wready) begin - _saxi_wvalid <= _saxi_wvalid; - end if((th_ctrl == 30) && ((__saxi_outstanding_wcount == 0) && (_saxi_awready || !_saxi_awvalid))) begin _saxi_awaddr <= _th_ctrl_awaddr_12; _saxi_awvalid <= 1; end - __saxi_cond_6_1 <= 1; + __saxi_waddr_cond_3_1 <= 1; if(_saxi_awvalid && !_saxi_awready) begin _saxi_awvalid <= _saxi_awvalid; end - if((th_ctrl == 32) && (_saxi_wready || !_saxi_wvalid)) begin - _saxi_wdata <= 1; - _saxi_wvalid <= 1; - _saxi_wstrb <= { 4{ 1'd1 } }; + end + end + + + always @(posedge uut_CLK) begin + if(uut_RST) begin + __saxi_wdata_sb_0 <= 0; + __saxi_wvalid_sb_0 <= 0; + __saxi_wstrb_sb_0 <= 0; + __saxi_wdata_cond_0_1 <= 0; + __saxi_wdata_cond_1_1 <= 0; + __saxi_wdata_cond_2_1 <= 0; + __saxi_wdata_cond_3_1 <= 0; + end else begin + if(__saxi_wdata_cond_0_1) begin + __saxi_wvalid_sb_0 <= 0; + end + if(__saxi_wdata_cond_1_1) begin + __saxi_wvalid_sb_0 <= 0; + end + if(__saxi_wdata_cond_2_1) begin + __saxi_wvalid_sb_0 <= 0; + end + if(__saxi_wdata_cond_3_1) begin + __saxi_wvalid_sb_0 <= 0; + end + if((th_ctrl == 8) && (__saxi_wready_sb_0 || !__saxi_wvalid_sb_0)) begin + __saxi_wdata_sb_0 <= 4096; + __saxi_wvalid_sb_0 <= 1; + __saxi_wstrb_sb_0 <= { 4{ 1'd1 } }; + end + __saxi_wdata_cond_0_1 <= 1; + if(__saxi_wvalid_sb_0 && !__saxi_wready_sb_0) begin + __saxi_wvalid_sb_0 <= __saxi_wvalid_sb_0; + end + if((th_ctrl == 16) && (__saxi_wready_sb_0 || !__saxi_wvalid_sb_0)) begin + __saxi_wdata_sb_0 <= _th_ctrl_src_offset_13; + __saxi_wvalid_sb_0 <= 1; + __saxi_wstrb_sb_0 <= { 4{ 1'd1 } }; + end + __saxi_wdata_cond_1_1 <= 1; + if(__saxi_wvalid_sb_0 && !__saxi_wready_sb_0) begin + __saxi_wvalid_sb_0 <= __saxi_wvalid_sb_0; + end + if((th_ctrl == 24) && (__saxi_wready_sb_0 || !__saxi_wvalid_sb_0)) begin + __saxi_wdata_sb_0 <= _th_ctrl_dst_offset_14; + __saxi_wvalid_sb_0 <= 1; + __saxi_wstrb_sb_0 <= { 4{ 1'd1 } }; + end + __saxi_wdata_cond_2_1 <= 1; + if(__saxi_wvalid_sb_0 && !__saxi_wready_sb_0) begin + __saxi_wvalid_sb_0 <= __saxi_wvalid_sb_0; + end + if((th_ctrl == 32) && (__saxi_wready_sb_0 || !__saxi_wvalid_sb_0)) begin + __saxi_wdata_sb_0 <= 1; + __saxi_wvalid_sb_0 <= 1; + __saxi_wstrb_sb_0 <= { 4{ 1'd1 } }; + end + __saxi_wdata_cond_3_1 <= 1; + if(__saxi_wvalid_sb_0 && !__saxi_wready_sb_0) begin + __saxi_wvalid_sb_0 <= __saxi_wvalid_sb_0; + end + end + end + + + always @(posedge uut_CLK) begin + if(uut_RST) begin + _sb__saxi_writedata_data_39 <= 0; + _sb__saxi_writedata_valid_40 <= 0; + _sb__saxi_writedata_tmp_data_42 <= 0; + _sb__saxi_writedata_tmp_valid_43 <= 0; + end else begin + if(_sb__saxi_writedata_m_ready_38 || !_sb__saxi_writedata_valid_40) begin + _sb__saxi_writedata_data_39 <= _sb__saxi_writedata_next_data_44; + _sb__saxi_writedata_valid_40 <= _sb__saxi_writedata_next_valid_45; + end + if(!_sb__saxi_writedata_tmp_valid_43 && _sb__saxi_writedata_valid_40 && !_sb__saxi_writedata_m_ready_38) begin + _sb__saxi_writedata_tmp_data_42 <= _sb__saxi_writedata_s_data_36; + _sb__saxi_writedata_tmp_valid_43 <= _sb__saxi_writedata_s_valid_37; + end + if(_sb__saxi_writedata_tmp_valid_43 && _sb__saxi_writedata_m_ready_38) begin + _sb__saxi_writedata_tmp_valid_43 <= 0; end - __saxi_cond_7_1 <= 1; - if(_saxi_wvalid && !_saxi_wready) begin - _saxi_wvalid <= _saxi_wvalid; + end + end + + + always @(posedge uut_CLK) begin + if(uut_RST) begin + _saxi_araddr <= 0; + _saxi_arvalid <= 0; + __saxi_raddr_cond_0_1 <= 0; + end else begin + if(__saxi_raddr_cond_0_1) begin + _saxi_arvalid <= 0; end if((th_ctrl == 37) && (_saxi_arready || !_saxi_arvalid)) begin _saxi_araddr <= _th_ctrl_araddr_16; _saxi_arvalid <= 1; end - __saxi_cond_8_1 <= 1; + __saxi_raddr_cond_0_1 <= 1; if(_saxi_arvalid && !_saxi_arready) begin _saxi_arvalid <= _saxi_arvalid; end @@ -1117,6 +1212,42 @@ end + always @(posedge uut_CLK) begin + if(uut_RST) begin + _sb__saxi_readdata_data_52 <= 0; + _sb__saxi_readdata_valid_53 <= 0; + _sb__saxi_readdata_tmp_data_55 <= 0; + _sb__saxi_readdata_tmp_valid_56 <= 0; + end else begin + if(_sb__saxi_readdata_m_ready_51 || !_sb__saxi_readdata_valid_53) begin + _sb__saxi_readdata_data_52 <= _sb__saxi_readdata_next_data_57; + _sb__saxi_readdata_valid_53 <= _sb__saxi_readdata_next_valid_58; + end + if(!_sb__saxi_readdata_tmp_valid_56 && _sb__saxi_readdata_valid_53 && !_sb__saxi_readdata_m_ready_51) begin + _sb__saxi_readdata_tmp_data_55 <= _sb__saxi_readdata_s_data_49; + _sb__saxi_readdata_tmp_valid_56 <= _sb__saxi_readdata_s_valid_50; + end + if(_sb__saxi_readdata_tmp_valid_56 && _sb__saxi_readdata_m_ready_51) begin + _sb__saxi_readdata_tmp_valid_56 <= 0; + end + end + end + + + always @(posedge uut_CLK) begin + if(uut_RST) begin + __saxi_outstanding_wcount <= 0; + end else begin + if(_saxi_awvalid && _saxi_awready && !(_saxi_bvalid && _saxi_bready) && (__saxi_outstanding_wcount < 7)) begin + __saxi_outstanding_wcount <= __saxi_outstanding_wcount + 1; + end + if(!(_saxi_awvalid && _saxi_awready) && (_saxi_bvalid && _saxi_bready) && (__saxi_outstanding_wcount > 0)) begin + __saxi_outstanding_wcount <= __saxi_outstanding_wcount - 1; + end + end + end + + always @(posedge uut_CLK) begin if(uut_RST) begin counter <= 0; @@ -1183,7 +1314,7 @@ _th_ctrl_dst_offset_14 <= 0; _th_ctrl_start_time_15 <= 0; _th_ctrl_araddr_16 <= 0; - axim_rdata_47 <= 0; + axim_rdata_73 <= 0; _th_ctrl_busy_17 <= 0; _th_ctrl_end_time_18 <= 0; _th_ctrl_time_19 <= 0; @@ -1226,12 +1357,12 @@ end end th_ctrl_8: begin - if(_saxi_wready || !_saxi_wvalid) begin + if(__saxi_wready_sb_0 || !__saxi_wvalid_sb_0) begin th_ctrl <= th_ctrl_9; end end th_ctrl_9: begin - if(_saxi_wvalid && _saxi_wready) begin + if(__saxi_wvalid_sb_0 && __saxi_wready_sb_0) begin th_ctrl <= th_ctrl_10; end end @@ -1263,12 +1394,12 @@ end end th_ctrl_16: begin - if(_saxi_wready || !_saxi_wvalid) begin + if(__saxi_wready_sb_0 || !__saxi_wvalid_sb_0) begin th_ctrl <= th_ctrl_17; end end th_ctrl_17: begin - if(_saxi_wvalid && _saxi_wready) begin + if(__saxi_wvalid_sb_0 && __saxi_wready_sb_0) begin th_ctrl <= th_ctrl_18; end end @@ -1300,12 +1431,12 @@ end end th_ctrl_24: begin - if(_saxi_wready || !_saxi_wvalid) begin + if(__saxi_wready_sb_0 || !__saxi_wvalid_sb_0) begin th_ctrl <= th_ctrl_25; end end th_ctrl_25: begin - if(_saxi_wvalid && _saxi_wready) begin + if(__saxi_wvalid_sb_0 && __saxi_wready_sb_0) begin th_ctrl <= th_ctrl_26; end end @@ -1337,12 +1468,12 @@ end end th_ctrl_32: begin - if(_saxi_wready || !_saxi_wvalid) begin + if(__saxi_wready_sb_0 || !__saxi_wvalid_sb_0) begin th_ctrl <= th_ctrl_33; end end th_ctrl_33: begin - if(_saxi_wvalid && _saxi_wready) begin + if(__saxi_wvalid_sb_0 && __saxi_wready_sb_0) begin th_ctrl <= th_ctrl_34; end end @@ -1373,15 +1504,15 @@ end end th_ctrl_39: begin - if(_saxi_rvalid) begin - axim_rdata_47 <= _saxi_rdata; + if(__saxi_rvalid_sb_0) begin + axim_rdata_73 <= __saxi_rdata_sb_0; end - if(_saxi_rvalid) begin + if(__saxi_rvalid_sb_0) begin th_ctrl <= th_ctrl_40; end end th_ctrl_40: begin - _th_ctrl_busy_17 <= axim_rdata_47; + _th_ctrl_busy_17 <= axim_rdata_73; th_ctrl <= th_ctrl_41; end th_ctrl_41: begin @@ -1438,10 +1569,10 @@ output [2-1:0] maxi_awuser, output reg maxi_awvalid, input maxi_awready, - output reg [32-1:0] maxi_wdata, - output reg [4-1:0] maxi_wstrb, - output reg maxi_wlast, - output reg maxi_wvalid, + output [32-1:0] maxi_wdata, + output [4-1:0] maxi_wstrb, + output maxi_wlast, + output maxi_wvalid, input maxi_wready, input [2-1:0] maxi_bresp, input maxi_bvalid, @@ -1509,6 +1640,44 @@ assign maxi_awprot = 0; assign maxi_awqos = 0; assign maxi_awuser = 0; + reg [32-1:0] _maxi_wdata_sb_0; + reg [4-1:0] _maxi_wstrb_sb_0; + reg _maxi_wlast_sb_0; + reg _maxi_wvalid_sb_0; + wire _maxi_wready_sb_0; + wire _sb_maxi_writedata_s_value_0; + assign _sb_maxi_writedata_s_value_0 = _maxi_wlast_sb_0; + wire [4-1:0] _sb_maxi_writedata_s_value_1; + assign _sb_maxi_writedata_s_value_1 = _maxi_wstrb_sb_0; + wire [32-1:0] _sb_maxi_writedata_s_value_2; + assign _sb_maxi_writedata_s_value_2 = _maxi_wdata_sb_0; + wire [37-1:0] _sb_maxi_writedata_s_data_3; + assign _sb_maxi_writedata_s_data_3 = { _sb_maxi_writedata_s_value_0, _sb_maxi_writedata_s_value_1, _sb_maxi_writedata_s_value_2 }; + wire _sb_maxi_writedata_s_valid_4; + assign _sb_maxi_writedata_s_valid_4 = _maxi_wvalid_sb_0; + wire _sb_maxi_writedata_m_ready_5; + assign _sb_maxi_writedata_m_ready_5 = maxi_wready; + reg [37-1:0] _sb_maxi_writedata_data_6; + reg _sb_maxi_writedata_valid_7; + wire _sb_maxi_writedata_ready_8; + reg [37-1:0] _sb_maxi_writedata_tmp_data_9; + reg _sb_maxi_writedata_tmp_valid_10; + wire [37-1:0] _sb_maxi_writedata_next_data_11; + wire _sb_maxi_writedata_next_valid_12; + assign _sb_maxi_writedata_ready_8 = !_sb_maxi_writedata_tmp_valid_10; + assign _sb_maxi_writedata_next_data_11 = (_sb_maxi_writedata_tmp_valid_10)? _sb_maxi_writedata_tmp_data_9 : _sb_maxi_writedata_s_data_3; + assign _sb_maxi_writedata_next_valid_12 = _sb_maxi_writedata_tmp_valid_10 || _sb_maxi_writedata_s_valid_4; + wire _sb_maxi_writedata_m_value_13; + assign _sb_maxi_writedata_m_value_13 = _sb_maxi_writedata_data_6[36:36]; + wire [4-1:0] _sb_maxi_writedata_m_value_14; + assign _sb_maxi_writedata_m_value_14 = _sb_maxi_writedata_data_6[35:32]; + wire [32-1:0] _sb_maxi_writedata_m_value_15; + assign _sb_maxi_writedata_m_value_15 = _sb_maxi_writedata_data_6[31:0]; + assign _maxi_wready_sb_0 = _sb_maxi_writedata_ready_8; + assign maxi_wdata = _sb_maxi_writedata_m_value_15; + assign maxi_wstrb = _sb_maxi_writedata_m_value_14; + assign maxi_wlast = _sb_maxi_writedata_m_value_13; + assign maxi_wvalid = _sb_maxi_writedata_valid_7; assign maxi_bready = 1; assign maxi_arsize = 2; assign maxi_arburst = 1; @@ -1517,6 +1686,38 @@ assign maxi_arprot = 0; assign maxi_arqos = 0; assign maxi_aruser = 0; + wire [32-1:0] _maxi_rdata_sb_0; + wire _maxi_rlast_sb_0; + wire _maxi_rvalid_sb_0; + wire _maxi_rready_sb_0; + wire _sb_maxi_readdata_s_value_16; + assign _sb_maxi_readdata_s_value_16 = maxi_rlast; + wire [32-1:0] _sb_maxi_readdata_s_value_17; + assign _sb_maxi_readdata_s_value_17 = maxi_rdata; + wire [33-1:0] _sb_maxi_readdata_s_data_18; + assign _sb_maxi_readdata_s_data_18 = { _sb_maxi_readdata_s_value_16, _sb_maxi_readdata_s_value_17 }; + wire _sb_maxi_readdata_s_valid_19; + assign _sb_maxi_readdata_s_valid_19 = maxi_rvalid; + wire _sb_maxi_readdata_m_ready_20; + assign _sb_maxi_readdata_m_ready_20 = _maxi_rready_sb_0; + reg [33-1:0] _sb_maxi_readdata_data_21; + reg _sb_maxi_readdata_valid_22; + wire _sb_maxi_readdata_ready_23; + reg [33-1:0] _sb_maxi_readdata_tmp_data_24; + reg _sb_maxi_readdata_tmp_valid_25; + wire [33-1:0] _sb_maxi_readdata_next_data_26; + wire _sb_maxi_readdata_next_valid_27; + assign _sb_maxi_readdata_ready_23 = !_sb_maxi_readdata_tmp_valid_25; + assign _sb_maxi_readdata_next_data_26 = (_sb_maxi_readdata_tmp_valid_25)? _sb_maxi_readdata_tmp_data_24 : _sb_maxi_readdata_s_data_18; + assign _sb_maxi_readdata_next_valid_27 = _sb_maxi_readdata_tmp_valid_25 || _sb_maxi_readdata_s_valid_19; + wire _sb_maxi_readdata_m_value_28; + assign _sb_maxi_readdata_m_value_28 = _sb_maxi_readdata_data_21[32:32]; + wire [32-1:0] _sb_maxi_readdata_m_value_29; + assign _sb_maxi_readdata_m_value_29 = _sb_maxi_readdata_data_21[31:0]; + assign _maxi_rdata_sb_0 = _sb_maxi_readdata_m_value_29; + assign _maxi_rlast_sb_0 = _sb_maxi_readdata_m_value_28; + assign _maxi_rvalid_sb_0 = _sb_maxi_readdata_valid_22; + assign maxi_rready = _sb_maxi_readdata_ready_23; reg [3-1:0] _maxi_outstanding_wcount; wire _maxi_has_outstanding_write; assign _maxi_has_outstanding_write = (_maxi_outstanding_wcount > 0) || maxi_awvalid; @@ -1558,21 +1759,21 @@ wire [32-1:0] _maxi_read_local_stride_fifo; wire [33-1:0] _maxi_read_local_size_fifo; wire [32-1:0] _maxi_read_local_blocksize_fifo; - wire [8-1:0] unpack_read_req_op_sel_0; - wire [32-1:0] unpack_read_req_local_addr_1; - wire [32-1:0] unpack_read_req_local_stride_2; - wire [33-1:0] unpack_read_req_local_size_3; - wire [32-1:0] unpack_read_req_local_blocksize_4; - assign unpack_read_req_op_sel_0 = _maxi_read_req_fifo_rdata[136:129]; - assign unpack_read_req_local_addr_1 = _maxi_read_req_fifo_rdata[128:97]; - assign unpack_read_req_local_stride_2 = _maxi_read_req_fifo_rdata[96:65]; - assign unpack_read_req_local_size_3 = _maxi_read_req_fifo_rdata[64:32]; - assign unpack_read_req_local_blocksize_4 = _maxi_read_req_fifo_rdata[31:0]; - assign _maxi_read_op_sel_fifo = unpack_read_req_op_sel_0; - assign _maxi_read_local_addr_fifo = unpack_read_req_local_addr_1; - assign _maxi_read_local_stride_fifo = unpack_read_req_local_stride_2; - assign _maxi_read_local_size_fifo = unpack_read_req_local_size_3; - assign _maxi_read_local_blocksize_fifo = unpack_read_req_local_blocksize_4; + wire [8-1:0] unpack_read_req_op_sel_30; + wire [32-1:0] unpack_read_req_local_addr_31; + wire [32-1:0] unpack_read_req_local_stride_32; + wire [33-1:0] unpack_read_req_local_size_33; + wire [32-1:0] unpack_read_req_local_blocksize_34; + assign unpack_read_req_op_sel_30 = _maxi_read_req_fifo_rdata[136:129]; + assign unpack_read_req_local_addr_31 = _maxi_read_req_fifo_rdata[128:97]; + assign unpack_read_req_local_stride_32 = _maxi_read_req_fifo_rdata[96:65]; + assign unpack_read_req_local_size_33 = _maxi_read_req_fifo_rdata[64:32]; + assign unpack_read_req_local_blocksize_34 = _maxi_read_req_fifo_rdata[31:0]; + assign _maxi_read_op_sel_fifo = unpack_read_req_op_sel_30; + assign _maxi_read_local_addr_fifo = unpack_read_req_local_addr_31; + assign _maxi_read_local_stride_fifo = unpack_read_req_local_stride_32; + assign _maxi_read_local_size_fifo = unpack_read_req_local_size_33; + assign _maxi_read_local_blocksize_fifo = unpack_read_req_local_blocksize_34; reg [8-1:0] _maxi_read_op_sel_buf; reg [32-1:0] _maxi_read_local_addr_buf; reg [32-1:0] _maxi_read_local_stride_buf; @@ -1624,21 +1825,21 @@ wire [32-1:0] _maxi_write_local_stride_fifo; wire [33-1:0] _maxi_write_size_fifo; wire [32-1:0] _maxi_write_local_blocksize_fifo; - wire [8-1:0] unpack_write_req_op_sel_5; - wire [32-1:0] unpack_write_req_local_addr_6; - wire [32-1:0] unpack_write_req_local_stride_7; - wire [33-1:0] unpack_write_req_size_8; - wire [32-1:0] unpack_write_req_local_blocksize_9; - assign unpack_write_req_op_sel_5 = _maxi_write_req_fifo_rdata[136:129]; - assign unpack_write_req_local_addr_6 = _maxi_write_req_fifo_rdata[128:97]; - assign unpack_write_req_local_stride_7 = _maxi_write_req_fifo_rdata[96:65]; - assign unpack_write_req_size_8 = _maxi_write_req_fifo_rdata[64:32]; - assign unpack_write_req_local_blocksize_9 = _maxi_write_req_fifo_rdata[31:0]; - assign _maxi_write_op_sel_fifo = unpack_write_req_op_sel_5; - assign _maxi_write_local_addr_fifo = unpack_write_req_local_addr_6; - assign _maxi_write_local_stride_fifo = unpack_write_req_local_stride_7; - assign _maxi_write_size_fifo = unpack_write_req_size_8; - assign _maxi_write_local_blocksize_fifo = unpack_write_req_local_blocksize_9; + wire [8-1:0] unpack_write_req_op_sel_35; + wire [32-1:0] unpack_write_req_local_addr_36; + wire [32-1:0] unpack_write_req_local_stride_37; + wire [33-1:0] unpack_write_req_size_38; + wire [32-1:0] unpack_write_req_local_blocksize_39; + assign unpack_write_req_op_sel_35 = _maxi_write_req_fifo_rdata[136:129]; + assign unpack_write_req_local_addr_36 = _maxi_write_req_fifo_rdata[128:97]; + assign unpack_write_req_local_stride_37 = _maxi_write_req_fifo_rdata[96:65]; + assign unpack_write_req_size_38 = _maxi_write_req_fifo_rdata[64:32]; + assign unpack_write_req_local_blocksize_39 = _maxi_write_req_fifo_rdata[31:0]; + assign _maxi_write_op_sel_fifo = unpack_write_req_op_sel_35; + assign _maxi_write_local_addr_fifo = unpack_write_req_local_addr_36; + assign _maxi_write_local_stride_fifo = unpack_write_req_local_stride_37; + assign _maxi_write_size_fifo = unpack_write_req_size_38; + assign _maxi_write_local_blocksize_fifo = unpack_write_req_local_blocksize_39; reg [8-1:0] _maxi_write_op_sel_buf; reg [32-1:0] _maxi_write_local_addr_buf; reg [32-1:0] _maxi_write_local_stride_buf; @@ -1683,42 +1884,42 @@ localparam _saxi_shift = 2; reg [32-1:0] _saxi_register_fsm; localparam _saxi_register_fsm_init = 0; - reg [32-1:0] addr_10; - reg writevalid_11; - reg readvalid_12; - reg prev_awvalid_13; - reg prev_arvalid_14; - assign saxi_awready = (_saxi_register_fsm == 0) && (!writevalid_11 && !readvalid_12 && !saxi_bvalid && prev_awvalid_13); - assign saxi_arready = (_saxi_register_fsm == 0) && (!readvalid_12 && !writevalid_11 && prev_arvalid_14 && !prev_awvalid_13); - reg [_saxi_maskwidth-1:0] axis_maskaddr_15; - wire signed [32-1:0] axislite_rdata_16; - assign axislite_rdata_16 = (axis_maskaddr_15 == 0)? _saxi_register_0 : - (axis_maskaddr_15 == 1)? _saxi_register_1 : - (axis_maskaddr_15 == 2)? _saxi_register_2 : - (axis_maskaddr_15 == 3)? _saxi_register_3 : - (axis_maskaddr_15 == 4)? _saxi_register_4 : - (axis_maskaddr_15 == 5)? _saxi_register_5 : - (axis_maskaddr_15 == 6)? _saxi_register_6 : - (axis_maskaddr_15 == 7)? _saxi_register_7 : 'hx; - wire axislite_flag_17; - assign axislite_flag_17 = (axis_maskaddr_15 == 0)? _saxi_flag_0 : - (axis_maskaddr_15 == 1)? _saxi_flag_1 : - (axis_maskaddr_15 == 2)? _saxi_flag_2 : - (axis_maskaddr_15 == 3)? _saxi_flag_3 : - (axis_maskaddr_15 == 4)? _saxi_flag_4 : - (axis_maskaddr_15 == 5)? _saxi_flag_5 : - (axis_maskaddr_15 == 6)? _saxi_flag_6 : - (axis_maskaddr_15 == 7)? _saxi_flag_7 : 'hx; - wire signed [32-1:0] axislite_resetval_18; - assign axislite_resetval_18 = (axis_maskaddr_15 == 0)? _saxi_resetval_0 : - (axis_maskaddr_15 == 1)? _saxi_resetval_1 : - (axis_maskaddr_15 == 2)? _saxi_resetval_2 : - (axis_maskaddr_15 == 3)? _saxi_resetval_3 : - (axis_maskaddr_15 == 4)? _saxi_resetval_4 : - (axis_maskaddr_15 == 5)? _saxi_resetval_5 : - (axis_maskaddr_15 == 6)? _saxi_resetval_6 : - (axis_maskaddr_15 == 7)? _saxi_resetval_7 : 'hx; - reg _saxi_cond_0_1; + reg [32-1:0] addr_40; + reg writevalid_41; + reg readvalid_42; + reg prev_awvalid_43; + reg prev_arvalid_44; + assign saxi_awready = (_saxi_register_fsm == 0) && (!writevalid_41 && !readvalid_42 && !saxi_bvalid && prev_awvalid_43); + assign saxi_arready = (_saxi_register_fsm == 0) && (!readvalid_42 && !writevalid_41 && prev_arvalid_44 && !prev_awvalid_43); + reg [_saxi_maskwidth-1:0] axis_maskaddr_45; + wire signed [32-1:0] axislite_rdata_46; + assign axislite_rdata_46 = (axis_maskaddr_45 == 0)? _saxi_register_0 : + (axis_maskaddr_45 == 1)? _saxi_register_1 : + (axis_maskaddr_45 == 2)? _saxi_register_2 : + (axis_maskaddr_45 == 3)? _saxi_register_3 : + (axis_maskaddr_45 == 4)? _saxi_register_4 : + (axis_maskaddr_45 == 5)? _saxi_register_5 : + (axis_maskaddr_45 == 6)? _saxi_register_6 : + (axis_maskaddr_45 == 7)? _saxi_register_7 : 'hx; + wire axislite_flag_47; + assign axislite_flag_47 = (axis_maskaddr_45 == 0)? _saxi_flag_0 : + (axis_maskaddr_45 == 1)? _saxi_flag_1 : + (axis_maskaddr_45 == 2)? _saxi_flag_2 : + (axis_maskaddr_45 == 3)? _saxi_flag_3 : + (axis_maskaddr_45 == 4)? _saxi_flag_4 : + (axis_maskaddr_45 == 5)? _saxi_flag_5 : + (axis_maskaddr_45 == 6)? _saxi_flag_6 : + (axis_maskaddr_45 == 7)? _saxi_flag_7 : 'hx; + wire signed [32-1:0] axislite_resetval_48; + assign axislite_resetval_48 = (axis_maskaddr_45 == 0)? _saxi_resetval_0 : + (axis_maskaddr_45 == 1)? _saxi_resetval_1 : + (axis_maskaddr_45 == 2)? _saxi_resetval_2 : + (axis_maskaddr_45 == 3)? _saxi_resetval_3 : + (axis_maskaddr_45 == 4)? _saxi_resetval_4 : + (axis_maskaddr_45 == 5)? _saxi_resetval_5 : + (axis_maskaddr_45 == 6)? _saxi_resetval_6 : + (axis_maskaddr_45 == 7)? _saxi_resetval_7 : 'hx; + reg _saxi_rdata_cond_0_1; assign saxi_wready = _saxi_register_fsm == 3; reg [31:0] sum; @@ -1747,166 +1948,286 @@ reg signed [32-1:0] _th_memcpy_dst_global_addr_8; reg signed [32-1:0] _th_memcpy_local_addr_9; reg signed [32-1:0] _th_memcpy_dma_size_10; - wire [32-1:0] mask_addr_shifted_19; - assign mask_addr_shifted_19 = _th_memcpy_src_global_addr_7 >> 2; - wire [32-1:0] mask_addr_masked_20; - assign mask_addr_masked_20 = mask_addr_shifted_19 << 2; + wire [32-1:0] mask_addr_shifted_49; + assign mask_addr_shifted_49 = _th_memcpy_src_global_addr_7 >> 2; + wire [32-1:0] mask_addr_masked_50; + assign mask_addr_masked_50 = mask_addr_shifted_49 << 2; reg [32-1:0] _maxi_read_req_fsm; localparam _maxi_read_req_fsm_init = 0; reg [33-1:0] _maxi_read_cur_global_size; reg _maxi_read_cont; - wire [8-1:0] pack_read_req_op_sel_21; - wire [32-1:0] pack_read_req_local_addr_22; - wire [32-1:0] pack_read_req_local_stride_23; - wire [33-1:0] pack_read_req_local_size_24; - wire [32-1:0] pack_read_req_local_blocksize_25; - assign pack_read_req_op_sel_21 = _maxi_read_op_sel; - assign pack_read_req_local_addr_22 = _maxi_read_local_addr; - assign pack_read_req_local_stride_23 = _maxi_read_local_stride; - assign pack_read_req_local_size_24 = _maxi_read_local_size; - assign pack_read_req_local_blocksize_25 = _maxi_read_local_blocksize; - wire [137-1:0] pack_read_req_packed_26; - assign pack_read_req_packed_26 = { pack_read_req_op_sel_21, pack_read_req_local_addr_22, pack_read_req_local_stride_23, pack_read_req_local_size_24, pack_read_req_local_blocksize_25 }; - assign _maxi_read_req_fifo_wdata = ((_maxi_read_req_fsm == 0) && _maxi_read_start && !_maxi_read_req_fifo_almost_full)? pack_read_req_packed_26 : 'hx; + wire [8-1:0] pack_read_req_op_sel_51; + wire [32-1:0] pack_read_req_local_addr_52; + wire [32-1:0] pack_read_req_local_stride_53; + wire [33-1:0] pack_read_req_local_size_54; + wire [32-1:0] pack_read_req_local_blocksize_55; + assign pack_read_req_op_sel_51 = _maxi_read_op_sel; + assign pack_read_req_local_addr_52 = _maxi_read_local_addr; + assign pack_read_req_local_stride_53 = _maxi_read_local_stride; + assign pack_read_req_local_size_54 = _maxi_read_local_size; + assign pack_read_req_local_blocksize_55 = _maxi_read_local_blocksize; + wire [137-1:0] pack_read_req_packed_56; + assign pack_read_req_packed_56 = { pack_read_req_op_sel_51, pack_read_req_local_addr_52, pack_read_req_local_stride_53, pack_read_req_local_size_54, pack_read_req_local_blocksize_55 }; + assign _maxi_read_req_fifo_wdata = ((_maxi_read_req_fsm == 0) && _maxi_read_start && !_maxi_read_req_fifo_almost_full)? pack_read_req_packed_56 : 'hx; assign _maxi_read_req_fifo_enq = ((_maxi_read_req_fsm == 0) && _maxi_read_start && !_maxi_read_req_fifo_almost_full)? (_maxi_read_req_fsm == 0) && _maxi_read_start && !_maxi_read_req_fifo_almost_full && !_maxi_read_req_fifo_almost_full : 0; - localparam _tmp_27 = 1; - wire [_tmp_27-1:0] _tmp_28; - assign _tmp_28 = !_maxi_read_req_fifo_almost_full; - reg [_tmp_27-1:0] __tmp_28_1; - wire [32-1:0] mask_addr_shifted_29; - assign mask_addr_shifted_29 = _maxi_read_global_addr >> 2; - wire [32-1:0] mask_addr_masked_30; - assign mask_addr_masked_30 = mask_addr_shifted_29 << 2; - wire [32-1:0] mask_addr_shifted_31; - assign mask_addr_shifted_31 = _maxi_read_global_addr >> 2; - wire [32-1:0] mask_addr_masked_32; - assign mask_addr_masked_32 = mask_addr_shifted_31 << 2; - wire [32-1:0] mask_addr_shifted_33; - assign mask_addr_shifted_33 = _maxi_read_global_addr >> 2; - wire [32-1:0] mask_addr_masked_34; - assign mask_addr_masked_34 = mask_addr_shifted_33 << 2; - wire [32-1:0] mask_addr_shifted_35; - assign mask_addr_shifted_35 = _maxi_read_global_addr >> 2; - wire [32-1:0] mask_addr_masked_36; - assign mask_addr_masked_36 = mask_addr_shifted_35 << 2; - wire [32-1:0] mask_addr_shifted_37; - assign mask_addr_shifted_37 = _maxi_read_global_addr >> 2; - wire [32-1:0] mask_addr_masked_38; - assign mask_addr_masked_38 = mask_addr_shifted_37 << 2; - wire [32-1:0] mask_addr_shifted_39; - assign mask_addr_shifted_39 = _maxi_read_global_addr >> 2; - wire [32-1:0] mask_addr_masked_40; - assign mask_addr_masked_40 = mask_addr_shifted_39 << 2; - reg _maxi_cond_0_1; - reg [32-1:0] _maxi_read_data_fsm; - localparam _maxi_read_data_fsm_init = 0; - assign _maxi_read_req_fifo_deq = ((_maxi_read_data_fsm == 0) && (!_maxi_read_data_busy && !_maxi_read_req_fifo_empty && (_maxi_read_op_sel_fifo == 1)) && !_maxi_read_req_fifo_empty)? 1 : 0; - reg [32-1:0] write_burst_fsm_0; - localparam write_burst_fsm_0_init = 0; - reg [10-1:0] write_burst_addr_41; - reg [10-1:0] write_burst_stride_42; - reg [33-1:0] write_burst_length_43; - reg write_burst_done_44; - assign ram_a_0_wdata = ((write_burst_fsm_0 == 1) && maxi_rvalid)? maxi_rdata : 'hx; - assign ram_a_0_wenable = ((write_burst_fsm_0 == 1) && maxi_rvalid)? 1'd1 : 0; - assign maxi_rready = _maxi_read_data_fsm == 2; - wire [32-1:0] mask_addr_shifted_45; - assign mask_addr_shifted_45 = _th_memcpy_dst_global_addr_8 >> 2; - wire [32-1:0] mask_addr_masked_46; - assign mask_addr_masked_46 = mask_addr_shifted_45 << 2; - reg [32-1:0] _maxi_write_req_fsm; - localparam _maxi_write_req_fsm_init = 0; - reg [33-1:0] _maxi_write_cur_global_size; - reg _maxi_write_cont; - wire [8-1:0] pack_write_req_op_sel_47; - wire [32-1:0] pack_write_req_local_addr_48; - wire [32-1:0] pack_write_req_local_stride_49; - wire [33-1:0] pack_write_req_size_50; - wire [32-1:0] pack_write_req_local_blocksize_51; - assign pack_write_req_op_sel_47 = _maxi_write_op_sel; - assign pack_write_req_local_addr_48 = _maxi_write_local_addr; - assign pack_write_req_local_stride_49 = _maxi_write_local_stride; - assign pack_write_req_size_50 = _maxi_write_local_size; - assign pack_write_req_local_blocksize_51 = _maxi_write_local_blocksize; - wire [137-1:0] pack_write_req_packed_52; - assign pack_write_req_packed_52 = { pack_write_req_op_sel_47, pack_write_req_local_addr_48, pack_write_req_local_stride_49, pack_write_req_size_50, pack_write_req_local_blocksize_51 }; - localparam _tmp_53 = 1; - wire [_tmp_53-1:0] _tmp_54; - assign _tmp_54 = !_maxi_write_req_fifo_almost_full; - reg [_tmp_53-1:0] __tmp_54_1; - wire [32-1:0] mask_addr_shifted_55; - assign mask_addr_shifted_55 = _maxi_write_global_addr >> 2; - wire [32-1:0] mask_addr_masked_56; - assign mask_addr_masked_56 = mask_addr_shifted_55 << 2; - wire [32-1:0] mask_addr_shifted_57; - assign mask_addr_shifted_57 = _maxi_write_global_addr >> 2; - wire [32-1:0] mask_addr_masked_58; - assign mask_addr_masked_58 = mask_addr_shifted_57 << 2; + localparam _tmp_57 = 1; + wire [_tmp_57-1:0] _tmp_58; + assign _tmp_58 = !_maxi_read_req_fifo_almost_full; + reg [_tmp_57-1:0] __tmp_58_1; wire [32-1:0] mask_addr_shifted_59; - assign mask_addr_shifted_59 = _maxi_write_global_addr >> 2; + assign mask_addr_shifted_59 = _maxi_read_global_addr >> 2; wire [32-1:0] mask_addr_masked_60; assign mask_addr_masked_60 = mask_addr_shifted_59 << 2; wire [32-1:0] mask_addr_shifted_61; - assign mask_addr_shifted_61 = _maxi_write_global_addr >> 2; + assign mask_addr_shifted_61 = _maxi_read_global_addr >> 2; wire [32-1:0] mask_addr_masked_62; assign mask_addr_masked_62 = mask_addr_shifted_61 << 2; wire [32-1:0] mask_addr_shifted_63; - assign mask_addr_shifted_63 = _maxi_write_global_addr >> 2; + assign mask_addr_shifted_63 = _maxi_read_global_addr >> 2; wire [32-1:0] mask_addr_masked_64; assign mask_addr_masked_64 = mask_addr_shifted_63 << 2; wire [32-1:0] mask_addr_shifted_65; - assign mask_addr_shifted_65 = _maxi_write_global_addr >> 2; + assign mask_addr_shifted_65 = _maxi_read_global_addr >> 2; wire [32-1:0] mask_addr_masked_66; assign mask_addr_masked_66 = mask_addr_shifted_65 << 2; - wire [8-1:0] pack_write_req_op_sel_67; - wire [32-1:0] pack_write_req_local_addr_68; - wire [32-1:0] pack_write_req_local_stride_69; - wire [33-1:0] pack_write_req_size_70; - wire [32-1:0] pack_write_req_local_blocksize_71; - assign pack_write_req_op_sel_67 = _maxi_write_op_sel; - assign pack_write_req_local_addr_68 = _maxi_write_local_addr; - assign pack_write_req_local_stride_69 = _maxi_write_local_stride; - assign pack_write_req_size_70 = _maxi_write_cur_global_size; - assign pack_write_req_local_blocksize_71 = _maxi_write_local_blocksize; - wire [137-1:0] pack_write_req_packed_72; - assign pack_write_req_packed_72 = { pack_write_req_op_sel_67, pack_write_req_local_addr_68, pack_write_req_local_stride_69, pack_write_req_size_70, pack_write_req_local_blocksize_71 }; - assign _maxi_write_req_fifo_wdata = ((_maxi_write_req_fsm == 1) && !_maxi_write_req_fifo_almost_full && (maxi_awready || !maxi_awvalid) && (_maxi_outstanding_wcount < 6))? pack_write_req_packed_72 : - ((_maxi_write_req_fsm == 0) && _maxi_write_start && !_maxi_write_req_fifo_almost_full)? pack_write_req_packed_52 : 'hx; + wire [32-1:0] mask_addr_shifted_67; + assign mask_addr_shifted_67 = _maxi_read_global_addr >> 2; + wire [32-1:0] mask_addr_masked_68; + assign mask_addr_masked_68 = mask_addr_shifted_67 << 2; + wire [32-1:0] mask_addr_shifted_69; + assign mask_addr_shifted_69 = _maxi_read_global_addr >> 2; + wire [32-1:0] mask_addr_masked_70; + assign mask_addr_masked_70 = mask_addr_shifted_69 << 2; + reg _maxi_raddr_cond_0_1; + reg [32-1:0] _maxi_read_data_fsm; + localparam _maxi_read_data_fsm_init = 0; + assign _maxi_read_req_fifo_deq = ((_maxi_read_data_fsm == 0) && (!_maxi_read_data_busy && !_maxi_read_req_fifo_empty && (_maxi_read_op_sel_fifo == 1)) && !_maxi_read_req_fifo_empty)? 1 : 0; + reg [32-1:0] write_burst_fsm_0; + localparam write_burst_fsm_0_init = 0; + reg [10-1:0] write_burst_addr_71; + reg [10-1:0] write_burst_stride_72; + reg [33-1:0] write_burst_length_73; + reg write_burst_done_74; + assign ram_a_0_wdata = ((write_burst_fsm_0 == 1) && _maxi_rvalid_sb_0)? _maxi_rdata_sb_0 : 'hx; + assign ram_a_0_wenable = ((write_burst_fsm_0 == 1) && _maxi_rvalid_sb_0)? 1'd1 : 0; + assign _maxi_rready_sb_0 = _maxi_read_data_fsm == 2; + wire [32-1:0] mask_addr_shifted_75; + assign mask_addr_shifted_75 = _th_memcpy_dst_global_addr_8 >> 2; + wire [32-1:0] mask_addr_masked_76; + assign mask_addr_masked_76 = mask_addr_shifted_75 << 2; + reg [32-1:0] _maxi_write_req_fsm; + localparam _maxi_write_req_fsm_init = 0; + reg [33-1:0] _maxi_write_cur_global_size; + reg _maxi_write_cont; + wire [8-1:0] pack_write_req_op_sel_77; + wire [32-1:0] pack_write_req_local_addr_78; + wire [32-1:0] pack_write_req_local_stride_79; + wire [33-1:0] pack_write_req_size_80; + wire [32-1:0] pack_write_req_local_blocksize_81; + assign pack_write_req_op_sel_77 = _maxi_write_op_sel; + assign pack_write_req_local_addr_78 = _maxi_write_local_addr; + assign pack_write_req_local_stride_79 = _maxi_write_local_stride; + assign pack_write_req_size_80 = _maxi_write_local_size; + assign pack_write_req_local_blocksize_81 = _maxi_write_local_blocksize; + wire [137-1:0] pack_write_req_packed_82; + assign pack_write_req_packed_82 = { pack_write_req_op_sel_77, pack_write_req_local_addr_78, pack_write_req_local_stride_79, pack_write_req_size_80, pack_write_req_local_blocksize_81 }; + localparam _tmp_83 = 1; + wire [_tmp_83-1:0] _tmp_84; + assign _tmp_84 = !_maxi_write_req_fifo_almost_full; + reg [_tmp_83-1:0] __tmp_84_1; + wire [32-1:0] mask_addr_shifted_85; + assign mask_addr_shifted_85 = _maxi_write_global_addr >> 2; + wire [32-1:0] mask_addr_masked_86; + assign mask_addr_masked_86 = mask_addr_shifted_85 << 2; + wire [32-1:0] mask_addr_shifted_87; + assign mask_addr_shifted_87 = _maxi_write_global_addr >> 2; + wire [32-1:0] mask_addr_masked_88; + assign mask_addr_masked_88 = mask_addr_shifted_87 << 2; + wire [32-1:0] mask_addr_shifted_89; + assign mask_addr_shifted_89 = _maxi_write_global_addr >> 2; + wire [32-1:0] mask_addr_masked_90; + assign mask_addr_masked_90 = mask_addr_shifted_89 << 2; + wire [32-1:0] mask_addr_shifted_91; + assign mask_addr_shifted_91 = _maxi_write_global_addr >> 2; + wire [32-1:0] mask_addr_masked_92; + assign mask_addr_masked_92 = mask_addr_shifted_91 << 2; + wire [32-1:0] mask_addr_shifted_93; + assign mask_addr_shifted_93 = _maxi_write_global_addr >> 2; + wire [32-1:0] mask_addr_masked_94; + assign mask_addr_masked_94 = mask_addr_shifted_93 << 2; + wire [32-1:0] mask_addr_shifted_95; + assign mask_addr_shifted_95 = _maxi_write_global_addr >> 2; + wire [32-1:0] mask_addr_masked_96; + assign mask_addr_masked_96 = mask_addr_shifted_95 << 2; + wire [8-1:0] pack_write_req_op_sel_97; + wire [32-1:0] pack_write_req_local_addr_98; + wire [32-1:0] pack_write_req_local_stride_99; + wire [33-1:0] pack_write_req_size_100; + wire [32-1:0] pack_write_req_local_blocksize_101; + assign pack_write_req_op_sel_97 = _maxi_write_op_sel; + assign pack_write_req_local_addr_98 = _maxi_write_local_addr; + assign pack_write_req_local_stride_99 = _maxi_write_local_stride; + assign pack_write_req_size_100 = _maxi_write_cur_global_size; + assign pack_write_req_local_blocksize_101 = _maxi_write_local_blocksize; + wire [137-1:0] pack_write_req_packed_102; + assign pack_write_req_packed_102 = { pack_write_req_op_sel_97, pack_write_req_local_addr_98, pack_write_req_local_stride_99, pack_write_req_size_100, pack_write_req_local_blocksize_101 }; + assign _maxi_write_req_fifo_wdata = ((_maxi_write_req_fsm == 1) && !_maxi_write_req_fifo_almost_full && (maxi_awready || !maxi_awvalid) && (_maxi_outstanding_wcount < 6))? pack_write_req_packed_102 : + ((_maxi_write_req_fsm == 0) && _maxi_write_start && !_maxi_write_req_fifo_almost_full)? pack_write_req_packed_82 : 'hx; assign _maxi_write_req_fifo_enq = ((_maxi_write_req_fsm == 1) && !_maxi_write_req_fifo_almost_full && (maxi_awready || !maxi_awvalid) && (_maxi_outstanding_wcount < 6))? (_maxi_write_req_fsm == 1) && !_maxi_write_req_fifo_almost_full && (maxi_awready || !maxi_awvalid) && (_maxi_outstanding_wcount < 6) && !_maxi_write_req_fifo_almost_full : ((_maxi_write_req_fsm == 0) && _maxi_write_start && !_maxi_write_req_fifo_almost_full)? (_maxi_write_req_fsm == 0) && _maxi_write_start && !_maxi_write_req_fifo_almost_full && !_maxi_write_req_fifo_almost_full : 0; - localparam _tmp_73 = 1; - wire [_tmp_73-1:0] _tmp_74; - assign _tmp_74 = !_maxi_write_req_fifo_almost_full; - reg [_tmp_73-1:0] __tmp_74_1; - reg _maxi_cond_1_1; + localparam _tmp_103 = 1; + wire [_tmp_103-1:0] _tmp_104; + assign _tmp_104 = !_maxi_write_req_fifo_almost_full; + reg [_tmp_103-1:0] __tmp_104_1; + reg _maxi_waddr_cond_0_1; reg [32-1:0] _maxi_write_data_fsm; localparam _maxi_write_data_fsm_init = 0; reg [32-1:0] read_burst_fsm_1; localparam read_burst_fsm_1_init = 0; - reg [10-1:0] read_burst_addr_75; - reg [10-1:0] read_burst_stride_76; - reg [33-1:0] read_burst_length_77; - reg read_burst_rvalid_78; - reg read_burst_rlast_79; - assign ram_a_0_addr = ((read_burst_fsm_1 == 1) && (!read_burst_rvalid_78 || (maxi_wready || !maxi_wvalid) && (_maxi_write_size_buf > 0)))? read_burst_addr_75 : - ((write_burst_fsm_0 == 1) && maxi_rvalid)? write_burst_addr_41 : 'hx; - assign ram_a_0_enable = ((read_burst_fsm_1 == 1) && (!read_burst_rvalid_78 || (maxi_wready || !maxi_wvalid) && (_maxi_write_size_buf > 0)))? 1'd1 : - ((write_burst_fsm_0 == 1) && maxi_rvalid)? 1'd1 : 0; - localparam _tmp_80 = 1; - wire [_tmp_80-1:0] _tmp_81; - assign _tmp_81 = (read_burst_fsm_1 == 1) && (!read_burst_rvalid_78 || (maxi_wready || !maxi_wvalid) && (_maxi_write_size_buf > 0)); - reg [_tmp_80-1:0] __tmp_81_1; - wire [32-1:0] read_burst_rdata_82; - assign read_burst_rdata_82 = ram_a_0_rdata; + reg [10-1:0] read_burst_addr_105; + reg [10-1:0] read_burst_stride_106; + reg [33-1:0] read_burst_length_107; + reg read_burst_rvalid_108; + reg read_burst_rlast_109; + assign ram_a_0_addr = ((read_burst_fsm_1 == 1) && (!read_burst_rvalid_108 || (_maxi_wready_sb_0 || !_maxi_wvalid_sb_0) && (_maxi_write_size_buf > 0)))? read_burst_addr_105 : + ((write_burst_fsm_0 == 1) && _maxi_rvalid_sb_0)? write_burst_addr_71 : 'hx; + assign ram_a_0_enable = ((read_burst_fsm_1 == 1) && (!read_burst_rvalid_108 || (_maxi_wready_sb_0 || !_maxi_wvalid_sb_0) && (_maxi_write_size_buf > 0)))? 1'd1 : + ((write_burst_fsm_0 == 1) && _maxi_rvalid_sb_0)? 1'd1 : 0; + localparam _tmp_110 = 1; + wire [_tmp_110-1:0] _tmp_111; + assign _tmp_111 = (read_burst_fsm_1 == 1) && (!read_burst_rvalid_108 || (_maxi_wready_sb_0 || !_maxi_wvalid_sb_0) && (_maxi_write_size_buf > 0)); + reg [_tmp_110-1:0] __tmp_111_1; + wire [32-1:0] read_burst_rdata_112; + assign read_burst_rdata_112 = ram_a_0_rdata; assign _maxi_write_req_fifo_deq = ((_maxi_write_data_fsm == 2) && (!_maxi_write_req_fifo_empty && (_maxi_write_size_buf == 0)) && !_maxi_write_req_fifo_empty)? 1 : ((_maxi_write_data_fsm == 0) && (!_maxi_write_data_busy && !_maxi_write_req_fifo_empty && (_maxi_write_op_sel_fifo == 1)) && !_maxi_write_req_fifo_empty)? 1 : 0; - reg _maxi_cond_2_1; + reg _maxi_wdata_cond_0_1; always @(posedge CLK) begin if(RST) begin - __tmp_81_1 <= 0; + __tmp_111_1 <= 0; end else begin - __tmp_81_1 <= _tmp_81; + __tmp_111_1 <= _tmp_111; + end + end + + + always @(posedge CLK) begin + if(RST) begin + maxi_awaddr <= 0; + maxi_awlen <= 0; + maxi_awvalid <= 0; + _maxi_waddr_cond_0_1 <= 0; + end else begin + if(_maxi_waddr_cond_0_1) begin + maxi_awvalid <= 0; + end + if((_maxi_write_req_fsm == 1) && !_maxi_write_req_fifo_almost_full && (_maxi_outstanding_wcount < 6) && ((_maxi_outstanding_wcount < 6) && (maxi_awready || !maxi_awvalid))) begin + maxi_awaddr <= _maxi_write_global_addr; + maxi_awlen <= _maxi_write_cur_global_size - 1; + maxi_awvalid <= 1; + end + if((_maxi_write_req_fsm == 1) && !_maxi_write_req_fifo_almost_full && (_maxi_outstanding_wcount < 6) && ((_maxi_outstanding_wcount < 6) && (maxi_awready || !maxi_awvalid)) && (_maxi_write_cur_global_size == 0)) begin + maxi_awvalid <= 0; + end + _maxi_waddr_cond_0_1 <= 1; + if(maxi_awvalid && !maxi_awready) begin + maxi_awvalid <= maxi_awvalid; + end + end + end + + + always @(posedge CLK) begin + if(RST) begin + _maxi_wdata_sb_0 <= 0; + _maxi_wvalid_sb_0 <= 0; + _maxi_wlast_sb_0 <= 0; + _maxi_wstrb_sb_0 <= 0; + _maxi_wdata_cond_0_1 <= 0; + end else begin + if(_maxi_wdata_cond_0_1) begin + _maxi_wvalid_sb_0 <= 0; + _maxi_wlast_sb_0 <= 0; + end + if((_maxi_write_op_sel_buf == 1) && read_burst_rvalid_108 && ((_maxi_wready_sb_0 || !_maxi_wvalid_sb_0) && (_maxi_write_size_buf > 0)) && (_maxi_wready_sb_0 || !_maxi_wvalid_sb_0)) begin + _maxi_wdata_sb_0 <= read_burst_rdata_112; + _maxi_wvalid_sb_0 <= 1; + _maxi_wlast_sb_0 <= read_burst_rlast_109 || (_maxi_write_size_buf == 1); + _maxi_wstrb_sb_0 <= { 4{ 1'd1 } }; + end + _maxi_wdata_cond_0_1 <= 1; + if(_maxi_wvalid_sb_0 && !_maxi_wready_sb_0) begin + _maxi_wvalid_sb_0 <= _maxi_wvalid_sb_0; + _maxi_wlast_sb_0 <= _maxi_wlast_sb_0; + end + end + end + + + always @(posedge CLK) begin + if(RST) begin + _sb_maxi_writedata_data_6 <= 0; + _sb_maxi_writedata_valid_7 <= 0; + _sb_maxi_writedata_tmp_data_9 <= 0; + _sb_maxi_writedata_tmp_valid_10 <= 0; + end else begin + if(_sb_maxi_writedata_m_ready_5 || !_sb_maxi_writedata_valid_7) begin + _sb_maxi_writedata_data_6 <= _sb_maxi_writedata_next_data_11; + _sb_maxi_writedata_valid_7 <= _sb_maxi_writedata_next_valid_12; + end + if(!_sb_maxi_writedata_tmp_valid_10 && _sb_maxi_writedata_valid_7 && !_sb_maxi_writedata_m_ready_5) begin + _sb_maxi_writedata_tmp_data_9 <= _sb_maxi_writedata_s_data_3; + _sb_maxi_writedata_tmp_valid_10 <= _sb_maxi_writedata_s_valid_4; + end + if(_sb_maxi_writedata_tmp_valid_10 && _sb_maxi_writedata_m_ready_5) begin + _sb_maxi_writedata_tmp_valid_10 <= 0; + end + end + end + + + always @(posedge CLK) begin + if(RST) begin + maxi_araddr <= 0; + maxi_arlen <= 0; + maxi_arvalid <= 0; + _maxi_raddr_cond_0_1 <= 0; + end else begin + if(_maxi_raddr_cond_0_1) begin + maxi_arvalid <= 0; + end + if((_maxi_read_req_fsm == 1) && (maxi_arready || !maxi_arvalid)) begin + maxi_araddr <= _maxi_read_global_addr; + maxi_arlen <= _maxi_read_cur_global_size - 1; + maxi_arvalid <= 1; + end + _maxi_raddr_cond_0_1 <= 1; + if(maxi_arvalid && !maxi_arready) begin + maxi_arvalid <= maxi_arvalid; + end + end + end + + + always @(posedge CLK) begin + if(RST) begin + _sb_maxi_readdata_data_21 <= 0; + _sb_maxi_readdata_valid_22 <= 0; + _sb_maxi_readdata_tmp_data_24 <= 0; + _sb_maxi_readdata_tmp_valid_25 <= 0; + end else begin + if(_sb_maxi_readdata_m_ready_20 || !_sb_maxi_readdata_valid_22) begin + _sb_maxi_readdata_data_21 <= _sb_maxi_readdata_next_data_26; + _sb_maxi_readdata_valid_22 <= _sb_maxi_readdata_next_valid_27; + end + if(!_sb_maxi_readdata_tmp_valid_25 && _sb_maxi_readdata_valid_22 && !_sb_maxi_readdata_m_ready_20) begin + _sb_maxi_readdata_tmp_data_24 <= _sb_maxi_readdata_s_data_18; + _sb_maxi_readdata_tmp_valid_25 <= _sb_maxi_readdata_s_valid_19; + end + if(_sb_maxi_readdata_tmp_valid_25 && _sb_maxi_readdata_m_ready_20) begin + _sb_maxi_readdata_tmp_valid_25 <= 0; + end end end @@ -1925,10 +2246,6 @@ _maxi_read_local_blocksize <= 0; _maxi_read_req_busy <= 0; _maxi_read_cur_global_size <= 0; - maxi_araddr <= 0; - maxi_arlen <= 0; - maxi_arvalid <= 0; - _maxi_cond_0_1 <= 0; _maxi_read_data_busy <= 0; _maxi_read_op_sel_buf <= 0; _maxi_read_local_addr_buf <= 0; @@ -1944,32 +2261,13 @@ _maxi_write_local_blocksize <= 0; _maxi_write_req_busy <= 0; _maxi_write_cur_global_size <= 0; - maxi_awaddr <= 0; - maxi_awlen <= 0; - maxi_awvalid <= 0; - _maxi_cond_1_1 <= 0; _maxi_write_data_busy <= 0; _maxi_write_op_sel_buf <= 0; _maxi_write_local_addr_buf <= 0; _maxi_write_local_stride_buf <= 0; _maxi_write_size_buf <= 0; _maxi_write_local_blocksize_buf <= 0; - maxi_wdata <= 0; - maxi_wvalid <= 0; - maxi_wlast <= 0; - maxi_wstrb <= 0; - _maxi_cond_2_1 <= 0; end else begin - if(_maxi_cond_0_1) begin - maxi_arvalid <= 0; - end - if(_maxi_cond_1_1) begin - maxi_awvalid <= 0; - end - if(_maxi_cond_2_1) begin - maxi_wvalid <= 0; - maxi_wlast <= 0; - end if(maxi_awvalid && maxi_awready && !(maxi_bvalid && maxi_bready) && (_maxi_outstanding_wcount < 7)) begin _maxi_outstanding_wcount <= _maxi_outstanding_wcount + 1; end @@ -1981,7 +2279,7 @@ if((th_memcpy == 17) && _maxi_read_req_idle) begin _maxi_read_start <= 1; _maxi_read_op_sel <= 1; - _maxi_read_global_addr <= mask_addr_masked_20; + _maxi_read_global_addr <= mask_addr_masked_50; _maxi_read_global_size <= _th_memcpy_dma_size_10; _maxi_read_local_addr <= _th_memcpy_local_addr_9; _maxi_read_local_stride <= 1; @@ -1994,28 +2292,19 @@ if(_maxi_read_start && _maxi_read_req_fifo_almost_full) begin _maxi_read_start <= 1; end - if((_maxi_read_req_fsm == 0) && (_maxi_read_start || _maxi_read_cont) && !_maxi_read_req_fifo_almost_full && (_maxi_read_global_size <= 256) && ((mask_addr_masked_30 & 4095) + (_maxi_read_global_size << 2) >= 4096)) begin - _maxi_read_cur_global_size <= 4096 - (mask_addr_masked_32 & 4095) >> 2; - _maxi_read_global_size <= _maxi_read_global_size - (4096 - (mask_addr_masked_34 & 4095) >> 2); + if((_maxi_read_req_fsm == 0) && (_maxi_read_start || _maxi_read_cont) && !_maxi_read_req_fifo_almost_full && (_maxi_read_global_size <= 256) && ((mask_addr_masked_60 & 4095) + (_maxi_read_global_size << 2) >= 4096)) begin + _maxi_read_cur_global_size <= 4096 - (mask_addr_masked_62 & 4095) >> 2; + _maxi_read_global_size <= _maxi_read_global_size - (4096 - (mask_addr_masked_64 & 4095) >> 2); end else if((_maxi_read_req_fsm == 0) && (_maxi_read_start || _maxi_read_cont) && !_maxi_read_req_fifo_almost_full && (_maxi_read_global_size <= 256)) begin _maxi_read_cur_global_size <= _maxi_read_global_size; _maxi_read_global_size <= 0; - end else if((_maxi_read_req_fsm == 0) && (_maxi_read_start || _maxi_read_cont) && !_maxi_read_req_fifo_almost_full && ((mask_addr_masked_36 & 4095) + 1024 >= 4096)) begin - _maxi_read_cur_global_size <= 4096 - (mask_addr_masked_38 & 4095) >> 2; - _maxi_read_global_size <= _maxi_read_global_size - (4096 - (mask_addr_masked_40 & 4095) >> 2); + end else if((_maxi_read_req_fsm == 0) && (_maxi_read_start || _maxi_read_cont) && !_maxi_read_req_fifo_almost_full && ((mask_addr_masked_66 & 4095) + 1024 >= 4096)) begin + _maxi_read_cur_global_size <= 4096 - (mask_addr_masked_68 & 4095) >> 2; + _maxi_read_global_size <= _maxi_read_global_size - (4096 - (mask_addr_masked_70 & 4095) >> 2); end else if((_maxi_read_req_fsm == 0) && (_maxi_read_start || _maxi_read_cont) && !_maxi_read_req_fifo_almost_full) begin _maxi_read_cur_global_size <= 256; _maxi_read_global_size <= _maxi_read_global_size - 256; end - if((_maxi_read_req_fsm == 1) && (maxi_arready || !maxi_arvalid)) begin - maxi_araddr <= _maxi_read_global_addr; - maxi_arlen <= _maxi_read_cur_global_size - 1; - maxi_arvalid <= 1; - end - _maxi_cond_0_1 <= 1; - if(maxi_arvalid && !maxi_arready) begin - maxi_arvalid <= maxi_arvalid; - end if((_maxi_read_req_fsm == 1) && (maxi_arready || !maxi_arvalid)) begin _maxi_read_global_addr <= _maxi_read_global_addr + (_maxi_read_cur_global_size << 2); end @@ -2030,16 +2319,16 @@ _maxi_read_local_size_buf <= _maxi_read_local_size_fifo; _maxi_read_local_blocksize_buf <= _maxi_read_local_blocksize_fifo; end - if((_maxi_read_data_fsm == 2) && maxi_rvalid) begin + if((_maxi_read_data_fsm == 2) && _maxi_rvalid_sb_0) begin _maxi_read_local_size_buf <= _maxi_read_local_size_buf - 1; end - if((_maxi_read_data_fsm == 2) && maxi_rvalid && (_maxi_read_local_size_buf <= 1)) begin + if((_maxi_read_data_fsm == 2) && _maxi_rvalid_sb_0 && (_maxi_read_local_size_buf <= 1)) begin _maxi_read_data_busy <= 0; end if((th_memcpy == 19) && _maxi_write_req_idle) begin _maxi_write_start <= 1; _maxi_write_op_sel <= 1; - _maxi_write_global_addr <= mask_addr_masked_46; + _maxi_write_global_addr <= mask_addr_masked_76; _maxi_write_global_size <= _th_memcpy_dma_size_10; _maxi_write_local_addr <= _th_memcpy_local_addr_9; _maxi_write_local_stride <= 1; @@ -2052,31 +2341,19 @@ if(_maxi_write_start && _maxi_write_req_fifo_almost_full) begin _maxi_write_start <= 1; end - if((_maxi_write_req_fsm == 0) && (_maxi_write_start || _maxi_write_cont) && !_maxi_write_req_fifo_almost_full && (_maxi_write_global_size <= 256) && ((mask_addr_masked_56 & 4095) + (_maxi_write_global_size << 2) >= 4096)) begin - _maxi_write_cur_global_size <= 4096 - (mask_addr_masked_58 & 4095) >> 2; - _maxi_write_global_size <= _maxi_write_global_size - (4096 - (mask_addr_masked_60 & 4095) >> 2); + if((_maxi_write_req_fsm == 0) && (_maxi_write_start || _maxi_write_cont) && !_maxi_write_req_fifo_almost_full && (_maxi_write_global_size <= 256) && ((mask_addr_masked_86 & 4095) + (_maxi_write_global_size << 2) >= 4096)) begin + _maxi_write_cur_global_size <= 4096 - (mask_addr_masked_88 & 4095) >> 2; + _maxi_write_global_size <= _maxi_write_global_size - (4096 - (mask_addr_masked_90 & 4095) >> 2); end else if((_maxi_write_req_fsm == 0) && (_maxi_write_start || _maxi_write_cont) && !_maxi_write_req_fifo_almost_full && (_maxi_write_global_size <= 256)) begin _maxi_write_cur_global_size <= _maxi_write_global_size; _maxi_write_global_size <= 0; - end else if((_maxi_write_req_fsm == 0) && (_maxi_write_start || _maxi_write_cont) && !_maxi_write_req_fifo_almost_full && ((mask_addr_masked_62 & 4095) + 1024 >= 4096)) begin - _maxi_write_cur_global_size <= 4096 - (mask_addr_masked_64 & 4095) >> 2; - _maxi_write_global_size <= _maxi_write_global_size - (4096 - (mask_addr_masked_66 & 4095) >> 2); + end else if((_maxi_write_req_fsm == 0) && (_maxi_write_start || _maxi_write_cont) && !_maxi_write_req_fifo_almost_full && ((mask_addr_masked_92 & 4095) + 1024 >= 4096)) begin + _maxi_write_cur_global_size <= 4096 - (mask_addr_masked_94 & 4095) >> 2; + _maxi_write_global_size <= _maxi_write_global_size - (4096 - (mask_addr_masked_96 & 4095) >> 2); end else if((_maxi_write_req_fsm == 0) && (_maxi_write_start || _maxi_write_cont) && !_maxi_write_req_fifo_almost_full) begin _maxi_write_cur_global_size <= 256; _maxi_write_global_size <= _maxi_write_global_size - 256; end - if((_maxi_write_req_fsm == 1) && !_maxi_write_req_fifo_almost_full && (_maxi_outstanding_wcount < 6) && ((_maxi_outstanding_wcount < 6) && (maxi_awready || !maxi_awvalid))) begin - maxi_awaddr <= _maxi_write_global_addr; - maxi_awlen <= _maxi_write_cur_global_size - 1; - maxi_awvalid <= 1; - end - if((_maxi_write_req_fsm == 1) && !_maxi_write_req_fifo_almost_full && (_maxi_outstanding_wcount < 6) && ((_maxi_outstanding_wcount < 6) && (maxi_awready || !maxi_awvalid)) && (_maxi_write_cur_global_size == 0)) begin - maxi_awvalid <= 0; - end - _maxi_cond_1_1 <= 1; - if(maxi_awvalid && !maxi_awready) begin - maxi_awvalid <= maxi_awvalid; - end if((_maxi_write_req_fsm == 1) && ((_maxi_write_req_fsm == 1) && !_maxi_write_req_fifo_almost_full && (maxi_awready || !maxi_awvalid) && (_maxi_outstanding_wcount < 6))) begin _maxi_write_global_addr <= _maxi_write_global_addr + (_maxi_write_cur_global_size << 2); end @@ -2097,21 +2374,10 @@ if((_maxi_write_data_fsm == 2) && (!_maxi_write_req_fifo_empty && (_maxi_write_size_buf == 0))) begin _maxi_write_size_buf <= _maxi_write_size_fifo; end - if((_maxi_write_op_sel_buf == 1) && read_burst_rvalid_78 && ((maxi_wready || !maxi_wvalid) && (_maxi_write_size_buf > 0)) && (maxi_wready || !maxi_wvalid)) begin - maxi_wdata <= read_burst_rdata_82; - maxi_wvalid <= 1; - maxi_wlast <= read_burst_rlast_79 || (_maxi_write_size_buf == 1); - maxi_wstrb <= { 4{ 1'd1 } }; - end - _maxi_cond_2_1 <= 1; - if(maxi_wvalid && !maxi_wready) begin - maxi_wvalid <= maxi_wvalid; - maxi_wlast <= maxi_wlast; - end - if((_maxi_write_data_fsm == 2) && read_burst_rvalid_78 && ((maxi_wready || !maxi_wvalid) && (_maxi_write_size_buf > 0))) begin + if((_maxi_write_data_fsm == 2) && read_burst_rvalid_108 && ((_maxi_wready_sb_0 || !_maxi_wvalid_sb_0) && (_maxi_write_size_buf > 0))) begin _maxi_write_size_buf <= _maxi_write_size_buf - 1; end - if((_maxi_write_data_fsm == 2) && ((_maxi_write_op_sel_buf == 1) && read_burst_rvalid_78 && ((maxi_wready || !maxi_wvalid) && (_maxi_write_size_buf > 0))) && read_burst_rlast_79) begin + if((_maxi_write_data_fsm == 2) && ((_maxi_write_op_sel_buf == 1) && read_burst_rvalid_108 && ((_maxi_wready_sb_0 || !_maxi_wvalid_sb_0) && (_maxi_write_size_buf > 0))) && read_burst_rlast_109) begin _maxi_write_data_busy <= 0; end end @@ -2121,7 +2387,7 @@ always @(posedge CLK) begin if(RST) begin count__maxi_read_req_fifo <= 0; - __tmp_28_1 <= 0; + __tmp_58_1 <= 0; end else begin if(_maxi_read_req_fifo_enq && !_maxi_read_req_fifo_full && (_maxi_read_req_fifo_deq && !_maxi_read_req_fifo_empty)) begin count__maxi_read_req_fifo <= count__maxi_read_req_fifo; @@ -2130,7 +2396,7 @@ end else if(_maxi_read_req_fifo_deq && !_maxi_read_req_fifo_empty) begin count__maxi_read_req_fifo <= count__maxi_read_req_fifo - 1; end - __tmp_28_1 <= _tmp_28; + __tmp_58_1 <= _tmp_58; end end @@ -2138,8 +2404,8 @@ always @(posedge CLK) begin if(RST) begin count__maxi_write_req_fifo <= 0; - __tmp_54_1 <= 0; - __tmp_74_1 <= 0; + __tmp_84_1 <= 0; + __tmp_104_1 <= 0; end else begin if(_maxi_write_req_fifo_enq && !_maxi_write_req_fifo_full && (_maxi_write_req_fifo_deq && !_maxi_write_req_fifo_empty)) begin count__maxi_write_req_fifo <= count__maxi_write_req_fifo; @@ -2148,23 +2414,41 @@ end else if(_maxi_write_req_fifo_deq && !_maxi_write_req_fifo_empty) begin count__maxi_write_req_fifo <= count__maxi_write_req_fifo - 1; end - __tmp_54_1 <= _tmp_54; - __tmp_74_1 <= _tmp_74; + __tmp_84_1 <= _tmp_84; + __tmp_104_1 <= _tmp_104; end end always @(posedge CLK) begin if(RST) begin - saxi_bvalid <= 0; - prev_awvalid_13 <= 0; - prev_arvalid_14 <= 0; - writevalid_11 <= 0; - readvalid_12 <= 0; - addr_10 <= 0; saxi_rdata <= 0; saxi_rvalid <= 0; - _saxi_cond_0_1 <= 0; + _saxi_rdata_cond_0_1 <= 0; + end else begin + if(_saxi_rdata_cond_0_1) begin + saxi_rvalid <= 0; + end + if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid)) begin + saxi_rdata <= axislite_rdata_46; + saxi_rvalid <= 1; + end + _saxi_rdata_cond_0_1 <= 1; + if(saxi_rvalid && !saxi_rready) begin + saxi_rvalid <= saxi_rvalid; + end + end + end + + + always @(posedge CLK) begin + if(RST) begin + saxi_bvalid <= 0; + prev_awvalid_43 <= 0; + prev_arvalid_44 <= 0; + writevalid_41 <= 0; + readvalid_42 <= 0; + addr_40 <= 0; _saxi_register_0 <= 0; _saxi_flag_0 <= 0; _saxi_register_1 <= 0; @@ -2182,88 +2466,77 @@ _saxi_register_7 <= 0; _saxi_flag_7 <= 0; end else begin - if(_saxi_cond_0_1) begin - saxi_rvalid <= 0; - end if(saxi_bvalid && saxi_bready) begin saxi_bvalid <= 0; end if(saxi_wvalid && saxi_wready) begin saxi_bvalid <= 1; end - prev_awvalid_13 <= saxi_awvalid; - prev_arvalid_14 <= saxi_arvalid; - writevalid_11 <= 0; - readvalid_12 <= 0; + prev_awvalid_43 <= saxi_awvalid; + prev_arvalid_44 <= saxi_arvalid; + writevalid_41 <= 0; + readvalid_42 <= 0; if(saxi_awready && saxi_awvalid && !saxi_bvalid) begin - addr_10 <= saxi_awaddr; - writevalid_11 <= 1; + addr_40 <= saxi_awaddr; + writevalid_41 <= 1; end else if(saxi_arready && saxi_arvalid) begin - addr_10 <= saxi_araddr; - readvalid_12 <= 1; - end - if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid)) begin - saxi_rdata <= axislite_rdata_16; - saxi_rvalid <= 1; - end - _saxi_cond_0_1 <= 1; - if(saxi_rvalid && !saxi_rready) begin - saxi_rvalid <= saxi_rvalid; + addr_40 <= saxi_araddr; + readvalid_42 <= 1; end - if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_17 && (axis_maskaddr_15 == 0)) begin - _saxi_register_0 <= axislite_resetval_18; + if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_47 && (axis_maskaddr_45 == 0)) begin + _saxi_register_0 <= axislite_resetval_48; _saxi_flag_0 <= 0; end - if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_17 && (axis_maskaddr_15 == 1)) begin - _saxi_register_1 <= axislite_resetval_18; + if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_47 && (axis_maskaddr_45 == 1)) begin + _saxi_register_1 <= axislite_resetval_48; _saxi_flag_1 <= 0; end - if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_17 && (axis_maskaddr_15 == 2)) begin - _saxi_register_2 <= axislite_resetval_18; + if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_47 && (axis_maskaddr_45 == 2)) begin + _saxi_register_2 <= axislite_resetval_48; _saxi_flag_2 <= 0; end - if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_17 && (axis_maskaddr_15 == 3)) begin - _saxi_register_3 <= axislite_resetval_18; + if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_47 && (axis_maskaddr_45 == 3)) begin + _saxi_register_3 <= axislite_resetval_48; _saxi_flag_3 <= 0; end - if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_17 && (axis_maskaddr_15 == 4)) begin - _saxi_register_4 <= axislite_resetval_18; + if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_47 && (axis_maskaddr_45 == 4)) begin + _saxi_register_4 <= axislite_resetval_48; _saxi_flag_4 <= 0; end - if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_17 && (axis_maskaddr_15 == 5)) begin - _saxi_register_5 <= axislite_resetval_18; + if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_47 && (axis_maskaddr_45 == 5)) begin + _saxi_register_5 <= axislite_resetval_48; _saxi_flag_5 <= 0; end - if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_17 && (axis_maskaddr_15 == 6)) begin - _saxi_register_6 <= axislite_resetval_18; + if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_47 && (axis_maskaddr_45 == 6)) begin + _saxi_register_6 <= axislite_resetval_48; _saxi_flag_6 <= 0; end - if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_17 && (axis_maskaddr_15 == 7)) begin - _saxi_register_7 <= axislite_resetval_18; + if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_47 && (axis_maskaddr_45 == 7)) begin + _saxi_register_7 <= axislite_resetval_48; _saxi_flag_7 <= 0; end - if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_15 == 0)) begin + if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_45 == 0)) begin _saxi_register_0 <= saxi_wdata; end - if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_15 == 1)) begin + if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_45 == 1)) begin _saxi_register_1 <= saxi_wdata; end - if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_15 == 2)) begin + if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_45 == 2)) begin _saxi_register_2 <= saxi_wdata; end - if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_15 == 3)) begin + if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_45 == 3)) begin _saxi_register_3 <= saxi_wdata; end - if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_15 == 4)) begin + if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_45 == 4)) begin _saxi_register_4 <= saxi_wdata; end - if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_15 == 5)) begin + if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_45 == 5)) begin _saxi_register_5 <= saxi_wdata; end - if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_15 == 6)) begin + if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_45 == 6)) begin _saxi_register_6 <= saxi_wdata; end - if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_15 == 7)) begin + if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_45 == 7)) begin _saxi_register_7 <= saxi_wdata; end if((_saxi_register_0 == 1) && (th_memcpy == 2) && 1) begin @@ -2365,17 +2638,17 @@ always @(posedge CLK) begin if(RST) begin _saxi_register_fsm <= _saxi_register_fsm_init; - axis_maskaddr_15 <= 0; + axis_maskaddr_45 <= 0; end else begin case(_saxi_register_fsm) _saxi_register_fsm_init: begin - if(readvalid_12 || writevalid_11) begin - axis_maskaddr_15 <= (addr_10 >> _saxi_shift) & _saxi_mask; + if(readvalid_42 || writevalid_41) begin + axis_maskaddr_45 <= (addr_40 >> _saxi_shift) & _saxi_mask; end - if(readvalid_12) begin + if(readvalid_42) begin _saxi_register_fsm <= _saxi_register_fsm_1; end - if(writevalid_11) begin + if(writevalid_41) begin _saxi_register_fsm <= _saxi_register_fsm_3; end end @@ -2614,7 +2887,7 @@ _maxi_read_data_fsm <= _maxi_read_data_fsm_2; end _maxi_read_data_fsm_2: begin - if(maxi_rvalid && (_maxi_read_local_size_buf <= 1)) begin + if(_maxi_rvalid_sb_0 && (_maxi_read_local_size_buf <= 1)) begin _maxi_read_data_fsm <= _maxi_read_data_fsm_init; end end @@ -2627,37 +2900,37 @@ always @(posedge CLK) begin if(RST) begin write_burst_fsm_0 <= write_burst_fsm_0_init; - write_burst_addr_41 <= 0; - write_burst_stride_42 <= 0; - write_burst_length_43 <= 0; - write_burst_done_44 <= 0; + write_burst_addr_71 <= 0; + write_burst_stride_72 <= 0; + write_burst_length_73 <= 0; + write_burst_done_74 <= 0; end else begin case(write_burst_fsm_0) write_burst_fsm_0_init: begin - write_burst_addr_41 <= _maxi_read_local_addr_buf; - write_burst_stride_42 <= _maxi_read_local_stride_buf; - write_burst_length_43 <= _maxi_read_local_size_buf; - write_burst_done_44 <= 0; + write_burst_addr_71 <= _maxi_read_local_addr_buf; + write_burst_stride_72 <= _maxi_read_local_stride_buf; + write_burst_length_73 <= _maxi_read_local_size_buf; + write_burst_done_74 <= 0; if((_maxi_read_data_fsm == 1) && (_maxi_read_op_sel_buf == 1) && (_maxi_read_local_size_buf > 0)) begin write_burst_fsm_0 <= write_burst_fsm_0_1; end end write_burst_fsm_0_1: begin - if(maxi_rvalid) begin - write_burst_addr_41 <= write_burst_addr_41 + write_burst_stride_42; - write_burst_length_43 <= write_burst_length_43 - 1; - write_burst_done_44 <= 0; + if(_maxi_rvalid_sb_0) begin + write_burst_addr_71 <= write_burst_addr_71 + write_burst_stride_72; + write_burst_length_73 <= write_burst_length_73 - 1; + write_burst_done_74 <= 0; end - if(maxi_rvalid && (write_burst_length_43 <= 1)) begin - write_burst_done_44 <= 1; + if(_maxi_rvalid_sb_0 && (write_burst_length_73 <= 1)) begin + write_burst_done_74 <= 1; end - if(maxi_rvalid && 0) begin - write_burst_done_44 <= 1; + if(_maxi_rvalid_sb_0 && 0) begin + write_burst_done_74 <= 1; end - if(maxi_rvalid && (write_burst_length_43 <= 1)) begin + if(_maxi_rvalid_sb_0 && (write_burst_length_73 <= 1)) begin write_burst_fsm_0 <= write_burst_fsm_0_init; end - if(maxi_rvalid && 0) begin + if(_maxi_rvalid_sb_0 && 0) begin write_burst_fsm_0 <= write_burst_fsm_0_init; end if(0) begin @@ -2713,7 +2986,7 @@ _maxi_write_data_fsm <= _maxi_write_data_fsm_2; end _maxi_write_data_fsm_2: begin - if((_maxi_write_op_sel_buf == 1) && read_burst_rvalid_78 && ((maxi_wready || !maxi_wvalid) && (_maxi_write_size_buf > 0)) && read_burst_rlast_79) begin + if((_maxi_write_op_sel_buf == 1) && read_burst_rvalid_108 && ((_maxi_wready_sb_0 || !_maxi_wvalid_sb_0) && (_maxi_write_size_buf > 0)) && read_burst_rlast_109) begin _maxi_write_data_fsm <= _maxi_write_data_fsm_init; end end @@ -2726,41 +2999,41 @@ always @(posedge CLK) begin if(RST) begin read_burst_fsm_1 <= read_burst_fsm_1_init; - read_burst_addr_75 <= 0; - read_burst_stride_76 <= 0; - read_burst_length_77 <= 0; - read_burst_rvalid_78 <= 0; - read_burst_rlast_79 <= 0; + read_burst_addr_105 <= 0; + read_burst_stride_106 <= 0; + read_burst_length_107 <= 0; + read_burst_rvalid_108 <= 0; + read_burst_rlast_109 <= 0; end else begin case(read_burst_fsm_1) read_burst_fsm_1_init: begin - read_burst_addr_75 <= _maxi_write_local_addr_buf; - read_burst_stride_76 <= _maxi_write_local_stride_buf; - read_burst_length_77 <= _maxi_write_size_buf; - read_burst_rvalid_78 <= 0; - read_burst_rlast_79 <= 0; + read_burst_addr_105 <= _maxi_write_local_addr_buf; + read_burst_stride_106 <= _maxi_write_local_stride_buf; + read_burst_length_107 <= _maxi_write_size_buf; + read_burst_rvalid_108 <= 0; + read_burst_rlast_109 <= 0; if((_maxi_write_data_fsm == 1) && (_maxi_write_op_sel_buf == 1) && (_maxi_write_size_buf > 0)) begin read_burst_fsm_1 <= read_burst_fsm_1_1; end end read_burst_fsm_1_1: begin - if((maxi_wready || !maxi_wvalid) && (_maxi_write_size_buf > 0) && (read_burst_length_77 > 0)) begin - read_burst_addr_75 <= read_burst_addr_75 + read_burst_stride_76; - read_burst_length_77 <= read_burst_length_77 - 1; - read_burst_rvalid_78 <= 1; + if((_maxi_wready_sb_0 || !_maxi_wvalid_sb_0) && (_maxi_write_size_buf > 0) && (read_burst_length_107 > 0)) begin + read_burst_addr_105 <= read_burst_addr_105 + read_burst_stride_106; + read_burst_length_107 <= read_burst_length_107 - 1; + read_burst_rvalid_108 <= 1; end - if((maxi_wready || !maxi_wvalid) && (_maxi_write_size_buf > 0) && (read_burst_length_77 <= 1)) begin - read_burst_rlast_79 <= 1; + if((_maxi_wready_sb_0 || !_maxi_wvalid_sb_0) && (_maxi_write_size_buf > 0) && (read_burst_length_107 <= 1)) begin + read_burst_rlast_109 <= 1; end - if(read_burst_rlast_79 && read_burst_rvalid_78 && ((maxi_wready || !maxi_wvalid) && (_maxi_write_size_buf > 0))) begin - read_burst_rvalid_78 <= 0; - read_burst_rlast_79 <= 0; + if(read_burst_rlast_109 && read_burst_rvalid_108 && ((_maxi_wready_sb_0 || !_maxi_wvalid_sb_0) && (_maxi_write_size_buf > 0))) begin + read_burst_rvalid_108 <= 0; + read_burst_rlast_109 <= 0; end if(0) begin - read_burst_rvalid_78 <= 0; - read_burst_rlast_79 <= 0; + read_burst_rvalid_108 <= 0; + read_burst_rlast_109 <= 0; end - if(read_burst_rlast_79 && read_burst_rvalid_78 && ((maxi_wready || !maxi_wvalid) && (_maxi_write_size_buf > 0))) begin + if(read_burst_rlast_109 && read_burst_rvalid_108 && ((_maxi_wready_sb_0 || !_maxi_wvalid_sb_0) && (_maxi_write_size_buf > 0))) begin read_burst_fsm_1 <= read_burst_fsm_1_init; end if(0) begin diff --git a/examples/thread_matmul/test_thread_matmul.py b/examples/thread_matmul/test_thread_matmul.py index e11f3412..dbb9d51a 100644 --- a/examples/thread_matmul/test_thread_matmul.py +++ b/examples/thread_matmul/test_thread_matmul.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_matmul.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/examples/thread_matmul/thread_matmul.py b/examples/thread_matmul/thread_matmul.py index 86326d98..fa871592 100644 --- a/examples/thread_matmul/thread_matmul.py +++ b/examples/thread_matmul/thread_matmul.py @@ -230,9 +230,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/examples/thread_matmul_ext_onchip_ram/test_thread_matmul_ext_onchip_ram.py b/examples/thread_matmul_ext_onchip_ram/test_thread_matmul_ext_onchip_ram.py index 1deb3d05..0a164b54 100644 --- a/examples/thread_matmul_ext_onchip_ram/test_thread_matmul_ext_onchip_ram.py +++ b/examples/thread_matmul_ext_onchip_ram/test_thread_matmul_ext_onchip_ram.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_matmul_ext_onchip_ram.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/examples/thread_matmul_ext_onchip_ram/thread_matmul_ext_onchip_ram.py b/examples/thread_matmul_ext_onchip_ram/thread_matmul_ext_onchip_ram.py index d3febe69..594610b6 100644 --- a/examples/thread_matmul_ext_onchip_ram/thread_matmul_ext_onchip_ram.py +++ b/examples/thread_matmul_ext_onchip_ram/thread_matmul_ext_onchip_ram.py @@ -3,6 +3,7 @@ import sys import os import numpy as np +import math # the next line can be removed after installation sys.path.insert(0, os.path.dirname(os.path.dirname( @@ -12,13 +13,23 @@ import veriloggen.thread as vthread import veriloggen.types.axi as axi -datawidth = 8 +mem_datawidth = 8 +datawidth = 16 addrwidth = 8 -matrix_size = 8 +matrix_size = 10 + +num_pack = math.ceil(datawidth / mem_datawidth) +addr_pack = math.ceil((addrwidth + math.ceil(np.log2(datawidth / mem_datawidth))) + / mem_datawidth) + +matrix_size_addr = 0 +a_offset_addr = 4 +b_offset_addr = 8 +c_offset_addr = 12 a_offset = 16 -b_offset = a_offset + matrix_size * matrix_size -c_offset = b_offset + matrix_size * matrix_size +b_offset = a_offset + matrix_size * matrix_size * num_pack +c_offset = b_offset + matrix_size * matrix_size * num_pack def mkLed(): @@ -28,7 +39,8 @@ def mkLed(): start = m.Input('start') busy = m.OutputReg('busy', initval=0) - ram = vthread.ExtRAM(m, 'ram', clk, rst, datawidth, addrwidth) + ram = vthread.ExtRAM(m, 'ram', clk, rst, mem_datawidth, + addrwidth + math.ceil(np.log2(datawidth / mem_datawidth))) def matmul(): while True: @@ -46,27 +58,31 @@ def wait(): busy.value = 1 def read_matrix_size(): - size0 = ram.read(0) - size1 = ram.read(1) - size = (size1 << 8) | size0 + size = 0 + for i in range(addr_pack): + size |= ((ram.read(matrix_size_addr + i) & ((1 << mem_datawidth) - 1)) + << (mem_datawidth * i)) return size def read_matrix_a_offset(): - offset0 = ram.read(4) & 0xff - offset1 = ram.read(5) & 0xff - offset = (offset1 << 8) | offset0 + offset = 0 + for i in range(addr_pack): + offset |= ((ram.read(a_offset_addr + i) & ((1 << mem_datawidth) - 1)) + << (mem_datawidth * i)) return offset def read_matrix_b_offset(): - offset0 = ram.read(8) & 0xff - offset1 = ram.read(9) & 0xff - offset = (offset1 << 8) | offset0 + offset = 0 + for i in range(addr_pack): + offset |= ((ram.read(b_offset_addr + i) & ((1 << mem_datawidth) - 1)) + << (mem_datawidth * i)) return offset def read_matrix_c_offset(): - offset0 = ram.read(12) & 0xff - offset1 = ram.read(13) & 0xff - offset = (offset1 << 8) | offset0 + offset = 0 + for i in range(addr_pack): + offset |= ((ram.read(c_offset_addr + i) & ((1 << mem_datawidth) - 1)) + << (mem_datawidth * i)) return offset def comp(matrix_size, a_offset, b_offset, c_offset): @@ -77,15 +93,24 @@ def comp(matrix_size, a_offset, b_offset, c_offset): for j in range(matrix_size): sum = 0 for k in range(matrix_size): - x = ram.read(a_addr + k) - y = ram.read(b_addr + k) + x = int(0, base=2) + y = 0 + for l in range(num_pack): + x |= ((ram.read(a_addr + k * num_pack + l) + & ((1 << mem_datawidth) - 1)) + << (mem_datawidth * l)) + y |= ((ram.read(b_addr + k * num_pack + l) + & ((1 << mem_datawidth) - 1)) + << (mem_datawidth * l)) sum += x * y - ram.write(c_addr + j, sum) + for l in range(num_pack): + ram.write(c_addr + j * num_pack + l, + (sum >> (mem_datawidth * l)) & (1<> 8) & 0xff) - print('# matrix_size[15:8] = %d' % v) - memory.write(awaddr, v, port=1) - - awaddr = 4 - v = (a_offset & 0xff) - print('# a_offset[7:0] = %d' % v) - memory.write(awaddr, v, port=1) - - awaddr = 5 - v = ((a_offset >> 8) & 0xff) - print('# a_offset[15:8] = %d' % v) - memory.write(awaddr, v, port=1) - - awaddr = 8 - v = (b_offset & 0xff) - print('# b_offset[7:0] = %d' % v) - memory.write(awaddr, v, port=1) - - awaddr = 9 - v = ((b_offset >> 8) & 0xff) - print('# b_offset[15:8] = %d' % v) - memory.write(awaddr, v, port=1) - - awaddr = 12 - v = (c_offset & 0xff) - print('# c_offset[7:0] = %d' % v) - memory.write(awaddr, v, port=1) - - awaddr = 13 - v = ((c_offset >> 8) & 0xff) - print('# c_offset[15:8] = %d' % v) - memory.write(awaddr, v, port=1) + for i in range(addr_pack): + awaddr = matrix_size_addr + i + v = (matrix_size >> (mem_datawidth * i)) & ((1 << mem_datawidth) - 1) + print('# matrix_size[%d:%d] = %d' % + (mem_datawidth * (i+1) - 1, mem_datawidth * i, v)) + memory.write(awaddr, v, port=1) + + for i in range(addr_pack): + awaddr = a_offset_addr + i + v = (a_offset >> (mem_datawidth * i)) & ((1 << mem_datawidth) - 1) + print('# a_offset[%d:%d] = %d' % + (mem_datawidth * (i+1) - 1, mem_datawidth * i, v)) + memory.write(awaddr, v, port=1) + + for i in range(addr_pack): + awaddr = b_offset_addr + i + v = (b_offset >> (mem_datawidth * i)) & ((1 << mem_datawidth) - 1) + print('# b_offset[%d:%d] = %d' % + (mem_datawidth * (i+1) - 1, mem_datawidth * i, v)) + memory.write(awaddr, v, port=1) + + for i in range(addr_pack): + awaddr = c_offset_addr + i + v = (c_offset >> (mem_datawidth * i)) & ((1 << mem_datawidth) - 1) + print('# c_offset[%d:%d] = %d' % + (mem_datawidth * (i+1) - 1, mem_datawidth * i, v)) + memory.write(awaddr, v, port=1) start_time = counter print('# start time = %d' % start_time) @@ -227,14 +239,19 @@ def ctrl(): all_ok = True for y in range(matrix_size): for x in range(matrix_size): - v = memory.read( - c_offset + (y * matrix_size + x) * datawidth // 8, port=1) + v = 0 + v_addr = c_offset + (y * matrix_size + x) * num_pack + for l in range(num_pack): + v |= memory.read(v_addr + l, port=1) << (mem_datawidth * l) + v |= ((memory.read(v_addr + l, port=1) + & ((1 << mem_datawidth) - 1)) + << (mem_datawidth * l)) if y == x and vthread.verilog.NotEql(v, (y + 1) * 2): all_ok = False - print("NG [%d,%d] = %d" % (y, x, v)) + print("NG [%d,%d] = %d (expected: %d)" % (y, x, v, (y + 1) * 2)) if y != x and vthread.verilog.NotEql(v, 0): all_ok = False - print("NG [%d,%d] = %d" % (y, x, v)) + print("NG [%d,%d] = %d (expected: %d)" % (y, x, v, 0)) if all_ok: print('# verify: PASSED') @@ -286,9 +303,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/examples/thread_matmul_ipxact/test_thread_matmul_ipxact.py b/examples/thread_matmul_ipxact/test_thread_matmul_ipxact.py index 15245a29..f38174c4 100644 --- a/examples/thread_matmul_ipxact/test_thread_matmul_ipxact.py +++ b/examples/thread_matmul_ipxact/test_thread_matmul_ipxact.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_matmul_ipxact.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/examples/thread_matmul_ipxact/thread_matmul_ipxact.py b/examples/thread_matmul_ipxact/thread_matmul_ipxact.py index b981ef1c..5bb97b4b 100644 --- a/examples/thread_matmul_ipxact/thread_matmul_ipxact.py +++ b/examples/thread_matmul_ipxact/thread_matmul_ipxact.py @@ -231,9 +231,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/examples/thread_matmul_narrow/test_thread_matmul_narrow.py b/examples/thread_matmul_narrow/test_thread_matmul_narrow.py index 879c0111..de157381 100644 --- a/examples/thread_matmul_narrow/test_thread_matmul_narrow.py +++ b/examples/thread_matmul_narrow/test_thread_matmul_narrow.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_matmul_narrow.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/examples/thread_matmul_narrow/thread_matmul_narrow.py b/examples/thread_matmul_narrow/thread_matmul_narrow.py index d0aede43..279dbd56 100644 --- a/examples/thread_matmul_narrow/thread_matmul_narrow.py +++ b/examples/thread_matmul_narrow/thread_matmul_narrow.py @@ -231,9 +231,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/examples/thread_matmul_wide/test_thread_matmul_wide.py b/examples/thread_matmul_wide/test_thread_matmul_wide.py index fa7600cc..b8405da8 100644 --- a/examples/thread_matmul_wide/test_thread_matmul_wide.py +++ b/examples/thread_matmul_wide/test_thread_matmul_wide.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_matmul_wide.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/examples/thread_matmul_wide/thread_matmul_wide.py b/examples/thread_matmul_wide/thread_matmul_wide.py index 77a8037d..77eb8996 100644 --- a/examples/thread_matmul_wide/thread_matmul_wide.py +++ b/examples/thread_matmul_wide/thread_matmul_wide.py @@ -232,9 +232,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/examples/thread_memcpy_ipxact_ultra96v2_pynq/test_thread_memcpy_ipxact.py b/examples/thread_memcpy_ipxact_ultra96v2_pynq/test_thread_memcpy_ipxact.py index ebeed3bd..dffbd440 100644 --- a/examples/thread_memcpy_ipxact_ultra96v2_pynq/test_thread_memcpy_ipxact.py +++ b/examples/thread_memcpy_ipxact_ultra96v2_pynq/test_thread_memcpy_ipxact.py @@ -147,6 +147,7 @@ wire [2-1:0] memory_bresp; reg memory_bvalid; wire memory_bready; + assign memory_bresp = 0; wire [32-1:0] memory_araddr; wire [8-1:0] memory_arlen; wire [3-1:0] memory_arsize; @@ -163,7 +164,6 @@ reg memory_rlast; reg memory_rvalid; wire memory_rready; - assign memory_bresp = 0; assign memory_rresp = 0; reg [32-1:0] _memory_waddr_fsm; localparam _memory_waddr_fsm_init = 0; @@ -416,127 +416,185 @@ wire [3-1:0] _saxi_awprot; reg _saxi_awvalid; wire _saxi_awready; - reg [32-1:0] _saxi_wdata; - reg [4-1:0] _saxi_wstrb; - reg _saxi_wvalid; + assign _saxi_awcache = 3; + assign _saxi_awprot = 0; + wire [32-1:0] _saxi_wdata; + wire [4-1:0] _saxi_wstrb; + wire _saxi_wvalid; wire _saxi_wready; + reg [32-1:0] __saxi_wdata_sb_0; + reg [4-1:0] __saxi_wstrb_sb_0; + reg __saxi_wvalid_sb_0; + wire __saxi_wready_sb_0; + wire [4-1:0] _sb__saxi_writedata_s_value_34; + assign _sb__saxi_writedata_s_value_34 = __saxi_wstrb_sb_0; + wire [32-1:0] _sb__saxi_writedata_s_value_35; + assign _sb__saxi_writedata_s_value_35 = __saxi_wdata_sb_0; + wire [36-1:0] _sb__saxi_writedata_s_data_36; + assign _sb__saxi_writedata_s_data_36 = { _sb__saxi_writedata_s_value_34, _sb__saxi_writedata_s_value_35 }; + wire _sb__saxi_writedata_s_valid_37; + assign _sb__saxi_writedata_s_valid_37 = __saxi_wvalid_sb_0; + wire _sb__saxi_writedata_m_ready_38; + assign _sb__saxi_writedata_m_ready_38 = _saxi_wready; + reg [36-1:0] _sb__saxi_writedata_data_39; + reg _sb__saxi_writedata_valid_40; + wire _sb__saxi_writedata_ready_41; + reg [36-1:0] _sb__saxi_writedata_tmp_data_42; + reg _sb__saxi_writedata_tmp_valid_43; + wire [36-1:0] _sb__saxi_writedata_next_data_44; + wire _sb__saxi_writedata_next_valid_45; + assign _sb__saxi_writedata_ready_41 = !_sb__saxi_writedata_tmp_valid_43; + assign _sb__saxi_writedata_next_data_44 = (_sb__saxi_writedata_tmp_valid_43)? _sb__saxi_writedata_tmp_data_42 : _sb__saxi_writedata_s_data_36; + assign _sb__saxi_writedata_next_valid_45 = _sb__saxi_writedata_tmp_valid_43 || _sb__saxi_writedata_s_valid_37; + wire [4-1:0] _sb__saxi_writedata_m_value_46; + assign _sb__saxi_writedata_m_value_46 = _sb__saxi_writedata_data_39[35:32]; + wire [32-1:0] _sb__saxi_writedata_m_value_47; + assign _sb__saxi_writedata_m_value_47 = _sb__saxi_writedata_data_39[31:0]; + assign __saxi_wready_sb_0 = _sb__saxi_writedata_ready_41; + assign _saxi_wdata = _sb__saxi_writedata_m_value_47; + assign _saxi_wstrb = _sb__saxi_writedata_m_value_46; + assign _saxi_wvalid = _sb__saxi_writedata_valid_40; wire [2-1:0] _saxi_bresp; wire _saxi_bvalid; wire _saxi_bready; + assign _saxi_bready = 1; reg [32-1:0] _saxi_araddr; wire [4-1:0] _saxi_arcache; wire [3-1:0] _saxi_arprot; reg _saxi_arvalid; wire _saxi_arready; + assign _saxi_arcache = 3; + assign _saxi_arprot = 0; wire [32-1:0] _saxi_rdata; wire [2-1:0] _saxi_rresp; wire _saxi_rvalid; wire _saxi_rready; - assign _saxi_awcache = 3; - assign _saxi_awprot = 0; - assign _saxi_bready = 1; - assign _saxi_arcache = 3; - assign _saxi_arprot = 0; + wire [32-1:0] __saxi_rdata_sb_0; + wire __saxi_rvalid_sb_0; + wire __saxi_rready_sb_0; + wire [32-1:0] _sb__saxi_readdata_s_value_48; + assign _sb__saxi_readdata_s_value_48 = _saxi_rdata; + wire [32-1:0] _sb__saxi_readdata_s_data_49; + assign _sb__saxi_readdata_s_data_49 = { _sb__saxi_readdata_s_value_48 }; + wire _sb__saxi_readdata_s_valid_50; + assign _sb__saxi_readdata_s_valid_50 = _saxi_rvalid; + wire _sb__saxi_readdata_m_ready_51; + assign _sb__saxi_readdata_m_ready_51 = __saxi_rready_sb_0; + reg [32-1:0] _sb__saxi_readdata_data_52; + reg _sb__saxi_readdata_valid_53; + wire _sb__saxi_readdata_ready_54; + reg [32-1:0] _sb__saxi_readdata_tmp_data_55; + reg _sb__saxi_readdata_tmp_valid_56; + wire [32-1:0] _sb__saxi_readdata_next_data_57; + wire _sb__saxi_readdata_next_valid_58; + assign _sb__saxi_readdata_ready_54 = !_sb__saxi_readdata_tmp_valid_56; + assign _sb__saxi_readdata_next_data_57 = (_sb__saxi_readdata_tmp_valid_56)? _sb__saxi_readdata_tmp_data_55 : _sb__saxi_readdata_s_data_49; + assign _sb__saxi_readdata_next_valid_58 = _sb__saxi_readdata_tmp_valid_56 || _sb__saxi_readdata_s_valid_50; + wire [32-1:0] _sb__saxi_readdata_m_value_59; + assign _sb__saxi_readdata_m_value_59 = _sb__saxi_readdata_data_52[31:0]; + assign __saxi_rdata_sb_0 = _sb__saxi_readdata_m_value_59; + assign __saxi_rvalid_sb_0 = _sb__saxi_readdata_valid_53; + assign _saxi_rready = _sb__saxi_readdata_ready_54; reg [3-1:0] __saxi_outstanding_wcount; wire __saxi_has_outstanding_write; assign __saxi_has_outstanding_write = (__saxi_outstanding_wcount > 0) || _saxi_awvalid; - wire [32-1:0] _tmp_34; - assign _tmp_34 = _saxi_awaddr; + wire [32-1:0] _tmp_60; + assign _tmp_60 = _saxi_awaddr; always @(*) begin - uut_saxi_awaddr = _tmp_34; + uut_saxi_awaddr = _tmp_60; end - wire [4-1:0] _tmp_35; - assign _tmp_35 = _saxi_awcache; + wire [4-1:0] _tmp_61; + assign _tmp_61 = _saxi_awcache; always @(*) begin - uut_saxi_awcache = _tmp_35; + uut_saxi_awcache = _tmp_61; end - wire [3-1:0] _tmp_36; - assign _tmp_36 = _saxi_awprot; + wire [3-1:0] _tmp_62; + assign _tmp_62 = _saxi_awprot; always @(*) begin - uut_saxi_awprot = _tmp_36; + uut_saxi_awprot = _tmp_62; end - wire _tmp_37; - assign _tmp_37 = _saxi_awvalid; + wire _tmp_63; + assign _tmp_63 = _saxi_awvalid; always @(*) begin - uut_saxi_awvalid = _tmp_37; + uut_saxi_awvalid = _tmp_63; end assign _saxi_awready = uut_saxi_awready; - wire [32-1:0] _tmp_38; - assign _tmp_38 = _saxi_wdata; + wire [32-1:0] _tmp_64; + assign _tmp_64 = _saxi_wdata; always @(*) begin - uut_saxi_wdata = _tmp_38; + uut_saxi_wdata = _tmp_64; end - wire [4-1:0] _tmp_39; - assign _tmp_39 = _saxi_wstrb; + wire [4-1:0] _tmp_65; + assign _tmp_65 = _saxi_wstrb; always @(*) begin - uut_saxi_wstrb = _tmp_39; + uut_saxi_wstrb = _tmp_65; end - wire _tmp_40; - assign _tmp_40 = _saxi_wvalid; + wire _tmp_66; + assign _tmp_66 = _saxi_wvalid; always @(*) begin - uut_saxi_wvalid = _tmp_40; + uut_saxi_wvalid = _tmp_66; end assign _saxi_wready = uut_saxi_wready; assign _saxi_bresp = uut_saxi_bresp; assign _saxi_bvalid = uut_saxi_bvalid; - wire _tmp_41; - assign _tmp_41 = _saxi_bready; + wire _tmp_67; + assign _tmp_67 = _saxi_bready; always @(*) begin - uut_saxi_bready = _tmp_41; + uut_saxi_bready = _tmp_67; end - wire [32-1:0] _tmp_42; - assign _tmp_42 = _saxi_araddr; + wire [32-1:0] _tmp_68; + assign _tmp_68 = _saxi_araddr; always @(*) begin - uut_saxi_araddr = _tmp_42; + uut_saxi_araddr = _tmp_68; end - wire [4-1:0] _tmp_43; - assign _tmp_43 = _saxi_arcache; + wire [4-1:0] _tmp_69; + assign _tmp_69 = _saxi_arcache; always @(*) begin - uut_saxi_arcache = _tmp_43; + uut_saxi_arcache = _tmp_69; end - wire [3-1:0] _tmp_44; - assign _tmp_44 = _saxi_arprot; + wire [3-1:0] _tmp_70; + assign _tmp_70 = _saxi_arprot; always @(*) begin - uut_saxi_arprot = _tmp_44; + uut_saxi_arprot = _tmp_70; end - wire _tmp_45; - assign _tmp_45 = _saxi_arvalid; + wire _tmp_71; + assign _tmp_71 = _saxi_arvalid; always @(*) begin - uut_saxi_arvalid = _tmp_45; + uut_saxi_arvalid = _tmp_71; end assign _saxi_arready = uut_saxi_arready; assign _saxi_rdata = uut_saxi_rdata; assign _saxi_rresp = uut_saxi_rresp; assign _saxi_rvalid = uut_saxi_rvalid; - wire _tmp_46; - assign _tmp_46 = _saxi_rready; + wire _tmp_72; + assign _tmp_72 = _saxi_rready; always @(*) begin - uut_saxi_rready = _tmp_46; + uut_saxi_rready = _tmp_72; end reg [32-1:0] counter; @@ -544,21 +602,21 @@ localparam th_ctrl_init = 0; reg signed [32-1:0] _th_ctrl_i_11; reg signed [32-1:0] _th_ctrl_awaddr_12; - reg __saxi_cond_0_1; - reg __saxi_cond_1_1; + reg __saxi_waddr_cond_0_1; + reg __saxi_wdata_cond_0_1; reg signed [32-1:0] _th_ctrl_src_offset_13; - reg __saxi_cond_2_1; - reg __saxi_cond_3_1; + reg __saxi_waddr_cond_1_1; + reg __saxi_wdata_cond_1_1; reg signed [32-1:0] _th_ctrl_dst_offset_14; - reg __saxi_cond_4_1; - reg __saxi_cond_5_1; + reg __saxi_waddr_cond_2_1; + reg __saxi_wdata_cond_2_1; reg signed [32-1:0] _th_ctrl_start_time_15; - reg __saxi_cond_6_1; - reg __saxi_cond_7_1; + reg __saxi_waddr_cond_3_1; + reg __saxi_wdata_cond_3_1; reg signed [32-1:0] _th_ctrl_araddr_16; - reg __saxi_cond_8_1; - reg signed [32-1:0] axim_rdata_47; - assign _saxi_rready = th_ctrl == 39; + reg __saxi_raddr_cond_0_1; + reg signed [32-1:0] axim_rdata_73; + assign __saxi_rready_sb_0 = th_ctrl == 39; reg signed [32-1:0] _th_ctrl_busy_17; reg signed [32-1:0] _th_ctrl_end_time_18; reg signed [32-1:0] _th_ctrl_time_19; @@ -605,30 +663,38 @@ __memory_rdata_fsm_cond_11_0_1 = 0; _saxi_awaddr = 0; _saxi_awvalid = 0; - _saxi_wdata = 0; - _saxi_wstrb = 0; - _saxi_wvalid = 0; + __saxi_wdata_sb_0 = 0; + __saxi_wstrb_sb_0 = 0; + __saxi_wvalid_sb_0 = 0; + _sb__saxi_writedata_data_39 = 0; + _sb__saxi_writedata_valid_40 = 0; + _sb__saxi_writedata_tmp_data_42 = 0; + _sb__saxi_writedata_tmp_valid_43 = 0; _saxi_araddr = 0; _saxi_arvalid = 0; + _sb__saxi_readdata_data_52 = 0; + _sb__saxi_readdata_valid_53 = 0; + _sb__saxi_readdata_tmp_data_55 = 0; + _sb__saxi_readdata_tmp_valid_56 = 0; __saxi_outstanding_wcount = 0; counter = 0; th_ctrl = th_ctrl_init; _th_ctrl_i_11 = 0; _th_ctrl_awaddr_12 = 0; - __saxi_cond_0_1 = 0; - __saxi_cond_1_1 = 0; + __saxi_waddr_cond_0_1 = 0; + __saxi_wdata_cond_0_1 = 0; _th_ctrl_src_offset_13 = 0; - __saxi_cond_2_1 = 0; - __saxi_cond_3_1 = 0; + __saxi_waddr_cond_1_1 = 0; + __saxi_wdata_cond_1_1 = 0; _th_ctrl_dst_offset_14 = 0; - __saxi_cond_4_1 = 0; - __saxi_cond_5_1 = 0; + __saxi_waddr_cond_2_1 = 0; + __saxi_wdata_cond_2_1 = 0; _th_ctrl_start_time_15 = 0; - __saxi_cond_6_1 = 0; - __saxi_cond_7_1 = 0; + __saxi_waddr_cond_3_1 = 0; + __saxi_wdata_cond_3_1 = 0; _th_ctrl_araddr_16 = 0; - __saxi_cond_8_1 = 0; - axim_rdata_47 = 0; + __saxi_raddr_cond_0_1 = 0; + axim_rdata_73 = 0; _th_ctrl_busy_17 = 0; _th_ctrl_end_time_18 = 0; _th_ctrl_time_19 = 0; @@ -984,130 +1050,159 @@ always @(posedge uut_CLK) begin if(uut_RST) begin - __saxi_outstanding_wcount <= 0; _saxi_awaddr <= 0; _saxi_awvalid <= 0; - __saxi_cond_0_1 <= 0; - _saxi_wdata <= 0; - _saxi_wvalid <= 0; - _saxi_wstrb <= 0; - __saxi_cond_1_1 <= 0; - __saxi_cond_2_1 <= 0; - __saxi_cond_3_1 <= 0; - __saxi_cond_4_1 <= 0; - __saxi_cond_5_1 <= 0; - __saxi_cond_6_1 <= 0; - __saxi_cond_7_1 <= 0; - _saxi_araddr <= 0; - _saxi_arvalid <= 0; - __saxi_cond_8_1 <= 0; + __saxi_waddr_cond_0_1 <= 0; + __saxi_waddr_cond_1_1 <= 0; + __saxi_waddr_cond_2_1 <= 0; + __saxi_waddr_cond_3_1 <= 0; end else begin - if(__saxi_cond_0_1) begin + if(__saxi_waddr_cond_0_1) begin _saxi_awvalid <= 0; end - if(__saxi_cond_1_1) begin - _saxi_wvalid <= 0; - end - if(__saxi_cond_2_1) begin + if(__saxi_waddr_cond_1_1) begin _saxi_awvalid <= 0; end - if(__saxi_cond_3_1) begin - _saxi_wvalid <= 0; - end - if(__saxi_cond_4_1) begin + if(__saxi_waddr_cond_2_1) begin _saxi_awvalid <= 0; end - if(__saxi_cond_5_1) begin - _saxi_wvalid <= 0; - end - if(__saxi_cond_6_1) begin + if(__saxi_waddr_cond_3_1) begin _saxi_awvalid <= 0; end - if(__saxi_cond_7_1) begin - _saxi_wvalid <= 0; - end - if(__saxi_cond_8_1) begin - _saxi_arvalid <= 0; - end - if(_saxi_awvalid && _saxi_awready && !(_saxi_bvalid && _saxi_bready) && (__saxi_outstanding_wcount < 7)) begin - __saxi_outstanding_wcount <= __saxi_outstanding_wcount + 1; - end - if(!(_saxi_awvalid && _saxi_awready) && (_saxi_bvalid && _saxi_bready) && (__saxi_outstanding_wcount > 0)) begin - __saxi_outstanding_wcount <= __saxi_outstanding_wcount - 1; - end if((th_ctrl == 6) && ((__saxi_outstanding_wcount == 0) && (_saxi_awready || !_saxi_awvalid))) begin _saxi_awaddr <= _th_ctrl_awaddr_12; _saxi_awvalid <= 1; end - __saxi_cond_0_1 <= 1; + __saxi_waddr_cond_0_1 <= 1; if(_saxi_awvalid && !_saxi_awready) begin _saxi_awvalid <= _saxi_awvalid; end - if((th_ctrl == 8) && (_saxi_wready || !_saxi_wvalid)) begin - _saxi_wdata <= 4096; - _saxi_wvalid <= 1; - _saxi_wstrb <= { 4{ 1'd1 } }; - end - __saxi_cond_1_1 <= 1; - if(_saxi_wvalid && !_saxi_wready) begin - _saxi_wvalid <= _saxi_wvalid; - end if((th_ctrl == 14) && ((__saxi_outstanding_wcount == 0) && (_saxi_awready || !_saxi_awvalid))) begin _saxi_awaddr <= _th_ctrl_awaddr_12; _saxi_awvalid <= 1; end - __saxi_cond_2_1 <= 1; + __saxi_waddr_cond_1_1 <= 1; if(_saxi_awvalid && !_saxi_awready) begin _saxi_awvalid <= _saxi_awvalid; end - if((th_ctrl == 16) && (_saxi_wready || !_saxi_wvalid)) begin - _saxi_wdata <= _th_ctrl_src_offset_13; - _saxi_wvalid <= 1; - _saxi_wstrb <= { 4{ 1'd1 } }; - end - __saxi_cond_3_1 <= 1; - if(_saxi_wvalid && !_saxi_wready) begin - _saxi_wvalid <= _saxi_wvalid; - end if((th_ctrl == 22) && ((__saxi_outstanding_wcount == 0) && (_saxi_awready || !_saxi_awvalid))) begin _saxi_awaddr <= _th_ctrl_awaddr_12; _saxi_awvalid <= 1; end - __saxi_cond_4_1 <= 1; + __saxi_waddr_cond_2_1 <= 1; if(_saxi_awvalid && !_saxi_awready) begin _saxi_awvalid <= _saxi_awvalid; end - if((th_ctrl == 24) && (_saxi_wready || !_saxi_wvalid)) begin - _saxi_wdata <= _th_ctrl_dst_offset_14; - _saxi_wvalid <= 1; - _saxi_wstrb <= { 4{ 1'd1 } }; - end - __saxi_cond_5_1 <= 1; - if(_saxi_wvalid && !_saxi_wready) begin - _saxi_wvalid <= _saxi_wvalid; - end if((th_ctrl == 30) && ((__saxi_outstanding_wcount == 0) && (_saxi_awready || !_saxi_awvalid))) begin _saxi_awaddr <= _th_ctrl_awaddr_12; _saxi_awvalid <= 1; end - __saxi_cond_6_1 <= 1; + __saxi_waddr_cond_3_1 <= 1; if(_saxi_awvalid && !_saxi_awready) begin _saxi_awvalid <= _saxi_awvalid; end - if((th_ctrl == 32) && (_saxi_wready || !_saxi_wvalid)) begin - _saxi_wdata <= 1; - _saxi_wvalid <= 1; - _saxi_wstrb <= { 4{ 1'd1 } }; + end + end + + + always @(posedge uut_CLK) begin + if(uut_RST) begin + __saxi_wdata_sb_0 <= 0; + __saxi_wvalid_sb_0 <= 0; + __saxi_wstrb_sb_0 <= 0; + __saxi_wdata_cond_0_1 <= 0; + __saxi_wdata_cond_1_1 <= 0; + __saxi_wdata_cond_2_1 <= 0; + __saxi_wdata_cond_3_1 <= 0; + end else begin + if(__saxi_wdata_cond_0_1) begin + __saxi_wvalid_sb_0 <= 0; + end + if(__saxi_wdata_cond_1_1) begin + __saxi_wvalid_sb_0 <= 0; + end + if(__saxi_wdata_cond_2_1) begin + __saxi_wvalid_sb_0 <= 0; + end + if(__saxi_wdata_cond_3_1) begin + __saxi_wvalid_sb_0 <= 0; + end + if((th_ctrl == 8) && (__saxi_wready_sb_0 || !__saxi_wvalid_sb_0)) begin + __saxi_wdata_sb_0 <= 4096; + __saxi_wvalid_sb_0 <= 1; + __saxi_wstrb_sb_0 <= { 4{ 1'd1 } }; + end + __saxi_wdata_cond_0_1 <= 1; + if(__saxi_wvalid_sb_0 && !__saxi_wready_sb_0) begin + __saxi_wvalid_sb_0 <= __saxi_wvalid_sb_0; + end + if((th_ctrl == 16) && (__saxi_wready_sb_0 || !__saxi_wvalid_sb_0)) begin + __saxi_wdata_sb_0 <= _th_ctrl_src_offset_13; + __saxi_wvalid_sb_0 <= 1; + __saxi_wstrb_sb_0 <= { 4{ 1'd1 } }; + end + __saxi_wdata_cond_1_1 <= 1; + if(__saxi_wvalid_sb_0 && !__saxi_wready_sb_0) begin + __saxi_wvalid_sb_0 <= __saxi_wvalid_sb_0; + end + if((th_ctrl == 24) && (__saxi_wready_sb_0 || !__saxi_wvalid_sb_0)) begin + __saxi_wdata_sb_0 <= _th_ctrl_dst_offset_14; + __saxi_wvalid_sb_0 <= 1; + __saxi_wstrb_sb_0 <= { 4{ 1'd1 } }; + end + __saxi_wdata_cond_2_1 <= 1; + if(__saxi_wvalid_sb_0 && !__saxi_wready_sb_0) begin + __saxi_wvalid_sb_0 <= __saxi_wvalid_sb_0; + end + if((th_ctrl == 32) && (__saxi_wready_sb_0 || !__saxi_wvalid_sb_0)) begin + __saxi_wdata_sb_0 <= 1; + __saxi_wvalid_sb_0 <= 1; + __saxi_wstrb_sb_0 <= { 4{ 1'd1 } }; + end + __saxi_wdata_cond_3_1 <= 1; + if(__saxi_wvalid_sb_0 && !__saxi_wready_sb_0) begin + __saxi_wvalid_sb_0 <= __saxi_wvalid_sb_0; + end + end + end + + + always @(posedge uut_CLK) begin + if(uut_RST) begin + _sb__saxi_writedata_data_39 <= 0; + _sb__saxi_writedata_valid_40 <= 0; + _sb__saxi_writedata_tmp_data_42 <= 0; + _sb__saxi_writedata_tmp_valid_43 <= 0; + end else begin + if(_sb__saxi_writedata_m_ready_38 || !_sb__saxi_writedata_valid_40) begin + _sb__saxi_writedata_data_39 <= _sb__saxi_writedata_next_data_44; + _sb__saxi_writedata_valid_40 <= _sb__saxi_writedata_next_valid_45; + end + if(!_sb__saxi_writedata_tmp_valid_43 && _sb__saxi_writedata_valid_40 && !_sb__saxi_writedata_m_ready_38) begin + _sb__saxi_writedata_tmp_data_42 <= _sb__saxi_writedata_s_data_36; + _sb__saxi_writedata_tmp_valid_43 <= _sb__saxi_writedata_s_valid_37; + end + if(_sb__saxi_writedata_tmp_valid_43 && _sb__saxi_writedata_m_ready_38) begin + _sb__saxi_writedata_tmp_valid_43 <= 0; end - __saxi_cond_7_1 <= 1; - if(_saxi_wvalid && !_saxi_wready) begin - _saxi_wvalid <= _saxi_wvalid; + end + end + + + always @(posedge uut_CLK) begin + if(uut_RST) begin + _saxi_araddr <= 0; + _saxi_arvalid <= 0; + __saxi_raddr_cond_0_1 <= 0; + end else begin + if(__saxi_raddr_cond_0_1) begin + _saxi_arvalid <= 0; end if((th_ctrl == 37) && (_saxi_arready || !_saxi_arvalid)) begin _saxi_araddr <= _th_ctrl_araddr_16; _saxi_arvalid <= 1; end - __saxi_cond_8_1 <= 1; + __saxi_raddr_cond_0_1 <= 1; if(_saxi_arvalid && !_saxi_arready) begin _saxi_arvalid <= _saxi_arvalid; end @@ -1115,6 +1210,42 @@ end + always @(posedge uut_CLK) begin + if(uut_RST) begin + _sb__saxi_readdata_data_52 <= 0; + _sb__saxi_readdata_valid_53 <= 0; + _sb__saxi_readdata_tmp_data_55 <= 0; + _sb__saxi_readdata_tmp_valid_56 <= 0; + end else begin + if(_sb__saxi_readdata_m_ready_51 || !_sb__saxi_readdata_valid_53) begin + _sb__saxi_readdata_data_52 <= _sb__saxi_readdata_next_data_57; + _sb__saxi_readdata_valid_53 <= _sb__saxi_readdata_next_valid_58; + end + if(!_sb__saxi_readdata_tmp_valid_56 && _sb__saxi_readdata_valid_53 && !_sb__saxi_readdata_m_ready_51) begin + _sb__saxi_readdata_tmp_data_55 <= _sb__saxi_readdata_s_data_49; + _sb__saxi_readdata_tmp_valid_56 <= _sb__saxi_readdata_s_valid_50; + end + if(_sb__saxi_readdata_tmp_valid_56 && _sb__saxi_readdata_m_ready_51) begin + _sb__saxi_readdata_tmp_valid_56 <= 0; + end + end + end + + + always @(posedge uut_CLK) begin + if(uut_RST) begin + __saxi_outstanding_wcount <= 0; + end else begin + if(_saxi_awvalid && _saxi_awready && !(_saxi_bvalid && _saxi_bready) && (__saxi_outstanding_wcount < 7)) begin + __saxi_outstanding_wcount <= __saxi_outstanding_wcount + 1; + end + if(!(_saxi_awvalid && _saxi_awready) && (_saxi_bvalid && _saxi_bready) && (__saxi_outstanding_wcount > 0)) begin + __saxi_outstanding_wcount <= __saxi_outstanding_wcount - 1; + end + end + end + + always @(posedge uut_CLK) begin if(uut_RST) begin counter <= 0; @@ -1181,7 +1312,7 @@ _th_ctrl_dst_offset_14 <= 0; _th_ctrl_start_time_15 <= 0; _th_ctrl_araddr_16 <= 0; - axim_rdata_47 <= 0; + axim_rdata_73 <= 0; _th_ctrl_busy_17 <= 0; _th_ctrl_end_time_18 <= 0; _th_ctrl_time_19 <= 0; @@ -1224,12 +1355,12 @@ end end th_ctrl_8: begin - if(_saxi_wready || !_saxi_wvalid) begin + if(__saxi_wready_sb_0 || !__saxi_wvalid_sb_0) begin th_ctrl <= th_ctrl_9; end end th_ctrl_9: begin - if(_saxi_wvalid && _saxi_wready) begin + if(__saxi_wvalid_sb_0 && __saxi_wready_sb_0) begin th_ctrl <= th_ctrl_10; end end @@ -1261,12 +1392,12 @@ end end th_ctrl_16: begin - if(_saxi_wready || !_saxi_wvalid) begin + if(__saxi_wready_sb_0 || !__saxi_wvalid_sb_0) begin th_ctrl <= th_ctrl_17; end end th_ctrl_17: begin - if(_saxi_wvalid && _saxi_wready) begin + if(__saxi_wvalid_sb_0 && __saxi_wready_sb_0) begin th_ctrl <= th_ctrl_18; end end @@ -1298,12 +1429,12 @@ end end th_ctrl_24: begin - if(_saxi_wready || !_saxi_wvalid) begin + if(__saxi_wready_sb_0 || !__saxi_wvalid_sb_0) begin th_ctrl <= th_ctrl_25; end end th_ctrl_25: begin - if(_saxi_wvalid && _saxi_wready) begin + if(__saxi_wvalid_sb_0 && __saxi_wready_sb_0) begin th_ctrl <= th_ctrl_26; end end @@ -1335,12 +1466,12 @@ end end th_ctrl_32: begin - if(_saxi_wready || !_saxi_wvalid) begin + if(__saxi_wready_sb_0 || !__saxi_wvalid_sb_0) begin th_ctrl <= th_ctrl_33; end end th_ctrl_33: begin - if(_saxi_wvalid && _saxi_wready) begin + if(__saxi_wvalid_sb_0 && __saxi_wready_sb_0) begin th_ctrl <= th_ctrl_34; end end @@ -1371,15 +1502,15 @@ end end th_ctrl_39: begin - if(_saxi_rvalid) begin - axim_rdata_47 <= _saxi_rdata; + if(__saxi_rvalid_sb_0) begin + axim_rdata_73 <= __saxi_rdata_sb_0; end - if(_saxi_rvalid) begin + if(__saxi_rvalid_sb_0) begin th_ctrl <= th_ctrl_40; end end th_ctrl_40: begin - _th_ctrl_busy_17 <= axim_rdata_47; + _th_ctrl_busy_17 <= axim_rdata_73; th_ctrl <= th_ctrl_41; end th_ctrl_41: begin @@ -1435,10 +1566,10 @@ output [2-1:0] maxi_awuser, output reg maxi_awvalid, input maxi_awready, - output reg [32-1:0] maxi_wdata, - output reg [4-1:0] maxi_wstrb, - output reg maxi_wlast, - output reg maxi_wvalid, + output [32-1:0] maxi_wdata, + output [4-1:0] maxi_wstrb, + output maxi_wlast, + output maxi_wvalid, input maxi_wready, input [2-1:0] maxi_bresp, input maxi_bvalid, @@ -1506,6 +1637,44 @@ assign maxi_awprot = 0; assign maxi_awqos = 0; assign maxi_awuser = 0; + reg [32-1:0] _maxi_wdata_sb_0; + reg [4-1:0] _maxi_wstrb_sb_0; + reg _maxi_wlast_sb_0; + reg _maxi_wvalid_sb_0; + wire _maxi_wready_sb_0; + wire _sb_maxi_writedata_s_value_0; + assign _sb_maxi_writedata_s_value_0 = _maxi_wlast_sb_0; + wire [4-1:0] _sb_maxi_writedata_s_value_1; + assign _sb_maxi_writedata_s_value_1 = _maxi_wstrb_sb_0; + wire [32-1:0] _sb_maxi_writedata_s_value_2; + assign _sb_maxi_writedata_s_value_2 = _maxi_wdata_sb_0; + wire [37-1:0] _sb_maxi_writedata_s_data_3; + assign _sb_maxi_writedata_s_data_3 = { _sb_maxi_writedata_s_value_0, _sb_maxi_writedata_s_value_1, _sb_maxi_writedata_s_value_2 }; + wire _sb_maxi_writedata_s_valid_4; + assign _sb_maxi_writedata_s_valid_4 = _maxi_wvalid_sb_0; + wire _sb_maxi_writedata_m_ready_5; + assign _sb_maxi_writedata_m_ready_5 = maxi_wready; + reg [37-1:0] _sb_maxi_writedata_data_6; + reg _sb_maxi_writedata_valid_7; + wire _sb_maxi_writedata_ready_8; + reg [37-1:0] _sb_maxi_writedata_tmp_data_9; + reg _sb_maxi_writedata_tmp_valid_10; + wire [37-1:0] _sb_maxi_writedata_next_data_11; + wire _sb_maxi_writedata_next_valid_12; + assign _sb_maxi_writedata_ready_8 = !_sb_maxi_writedata_tmp_valid_10; + assign _sb_maxi_writedata_next_data_11 = (_sb_maxi_writedata_tmp_valid_10)? _sb_maxi_writedata_tmp_data_9 : _sb_maxi_writedata_s_data_3; + assign _sb_maxi_writedata_next_valid_12 = _sb_maxi_writedata_tmp_valid_10 || _sb_maxi_writedata_s_valid_4; + wire _sb_maxi_writedata_m_value_13; + assign _sb_maxi_writedata_m_value_13 = _sb_maxi_writedata_data_6[36:36]; + wire [4-1:0] _sb_maxi_writedata_m_value_14; + assign _sb_maxi_writedata_m_value_14 = _sb_maxi_writedata_data_6[35:32]; + wire [32-1:0] _sb_maxi_writedata_m_value_15; + assign _sb_maxi_writedata_m_value_15 = _sb_maxi_writedata_data_6[31:0]; + assign _maxi_wready_sb_0 = _sb_maxi_writedata_ready_8; + assign maxi_wdata = _sb_maxi_writedata_m_value_15; + assign maxi_wstrb = _sb_maxi_writedata_m_value_14; + assign maxi_wlast = _sb_maxi_writedata_m_value_13; + assign maxi_wvalid = _sb_maxi_writedata_valid_7; assign maxi_bready = 1; assign maxi_arsize = 2; assign maxi_arburst = 1; @@ -1514,6 +1683,38 @@ assign maxi_arprot = 0; assign maxi_arqos = 0; assign maxi_aruser = 0; + wire [32-1:0] _maxi_rdata_sb_0; + wire _maxi_rlast_sb_0; + wire _maxi_rvalid_sb_0; + wire _maxi_rready_sb_0; + wire _sb_maxi_readdata_s_value_16; + assign _sb_maxi_readdata_s_value_16 = maxi_rlast; + wire [32-1:0] _sb_maxi_readdata_s_value_17; + assign _sb_maxi_readdata_s_value_17 = maxi_rdata; + wire [33-1:0] _sb_maxi_readdata_s_data_18; + assign _sb_maxi_readdata_s_data_18 = { _sb_maxi_readdata_s_value_16, _sb_maxi_readdata_s_value_17 }; + wire _sb_maxi_readdata_s_valid_19; + assign _sb_maxi_readdata_s_valid_19 = maxi_rvalid; + wire _sb_maxi_readdata_m_ready_20; + assign _sb_maxi_readdata_m_ready_20 = _maxi_rready_sb_0; + reg [33-1:0] _sb_maxi_readdata_data_21; + reg _sb_maxi_readdata_valid_22; + wire _sb_maxi_readdata_ready_23; + reg [33-1:0] _sb_maxi_readdata_tmp_data_24; + reg _sb_maxi_readdata_tmp_valid_25; + wire [33-1:0] _sb_maxi_readdata_next_data_26; + wire _sb_maxi_readdata_next_valid_27; + assign _sb_maxi_readdata_ready_23 = !_sb_maxi_readdata_tmp_valid_25; + assign _sb_maxi_readdata_next_data_26 = (_sb_maxi_readdata_tmp_valid_25)? _sb_maxi_readdata_tmp_data_24 : _sb_maxi_readdata_s_data_18; + assign _sb_maxi_readdata_next_valid_27 = _sb_maxi_readdata_tmp_valid_25 || _sb_maxi_readdata_s_valid_19; + wire _sb_maxi_readdata_m_value_28; + assign _sb_maxi_readdata_m_value_28 = _sb_maxi_readdata_data_21[32:32]; + wire [32-1:0] _sb_maxi_readdata_m_value_29; + assign _sb_maxi_readdata_m_value_29 = _sb_maxi_readdata_data_21[31:0]; + assign _maxi_rdata_sb_0 = _sb_maxi_readdata_m_value_29; + assign _maxi_rlast_sb_0 = _sb_maxi_readdata_m_value_28; + assign _maxi_rvalid_sb_0 = _sb_maxi_readdata_valid_22; + assign maxi_rready = _sb_maxi_readdata_ready_23; reg [3-1:0] _maxi_outstanding_wcount; wire _maxi_has_outstanding_write; assign _maxi_has_outstanding_write = (_maxi_outstanding_wcount > 0) || maxi_awvalid; @@ -1555,21 +1756,21 @@ wire [32-1:0] _maxi_read_local_stride_fifo; wire [33-1:0] _maxi_read_local_size_fifo; wire [32-1:0] _maxi_read_local_blocksize_fifo; - wire [8-1:0] unpack_read_req_op_sel_0; - wire [32-1:0] unpack_read_req_local_addr_1; - wire [32-1:0] unpack_read_req_local_stride_2; - wire [33-1:0] unpack_read_req_local_size_3; - wire [32-1:0] unpack_read_req_local_blocksize_4; - assign unpack_read_req_op_sel_0 = _maxi_read_req_fifo_rdata[136:129]; - assign unpack_read_req_local_addr_1 = _maxi_read_req_fifo_rdata[128:97]; - assign unpack_read_req_local_stride_2 = _maxi_read_req_fifo_rdata[96:65]; - assign unpack_read_req_local_size_3 = _maxi_read_req_fifo_rdata[64:32]; - assign unpack_read_req_local_blocksize_4 = _maxi_read_req_fifo_rdata[31:0]; - assign _maxi_read_op_sel_fifo = unpack_read_req_op_sel_0; - assign _maxi_read_local_addr_fifo = unpack_read_req_local_addr_1; - assign _maxi_read_local_stride_fifo = unpack_read_req_local_stride_2; - assign _maxi_read_local_size_fifo = unpack_read_req_local_size_3; - assign _maxi_read_local_blocksize_fifo = unpack_read_req_local_blocksize_4; + wire [8-1:0] unpack_read_req_op_sel_30; + wire [32-1:0] unpack_read_req_local_addr_31; + wire [32-1:0] unpack_read_req_local_stride_32; + wire [33-1:0] unpack_read_req_local_size_33; + wire [32-1:0] unpack_read_req_local_blocksize_34; + assign unpack_read_req_op_sel_30 = _maxi_read_req_fifo_rdata[136:129]; + assign unpack_read_req_local_addr_31 = _maxi_read_req_fifo_rdata[128:97]; + assign unpack_read_req_local_stride_32 = _maxi_read_req_fifo_rdata[96:65]; + assign unpack_read_req_local_size_33 = _maxi_read_req_fifo_rdata[64:32]; + assign unpack_read_req_local_blocksize_34 = _maxi_read_req_fifo_rdata[31:0]; + assign _maxi_read_op_sel_fifo = unpack_read_req_op_sel_30; + assign _maxi_read_local_addr_fifo = unpack_read_req_local_addr_31; + assign _maxi_read_local_stride_fifo = unpack_read_req_local_stride_32; + assign _maxi_read_local_size_fifo = unpack_read_req_local_size_33; + assign _maxi_read_local_blocksize_fifo = unpack_read_req_local_blocksize_34; reg [8-1:0] _maxi_read_op_sel_buf; reg [32-1:0] _maxi_read_local_addr_buf; reg [32-1:0] _maxi_read_local_stride_buf; @@ -1621,21 +1822,21 @@ wire [32-1:0] _maxi_write_local_stride_fifo; wire [33-1:0] _maxi_write_size_fifo; wire [32-1:0] _maxi_write_local_blocksize_fifo; - wire [8-1:0] unpack_write_req_op_sel_5; - wire [32-1:0] unpack_write_req_local_addr_6; - wire [32-1:0] unpack_write_req_local_stride_7; - wire [33-1:0] unpack_write_req_size_8; - wire [32-1:0] unpack_write_req_local_blocksize_9; - assign unpack_write_req_op_sel_5 = _maxi_write_req_fifo_rdata[136:129]; - assign unpack_write_req_local_addr_6 = _maxi_write_req_fifo_rdata[128:97]; - assign unpack_write_req_local_stride_7 = _maxi_write_req_fifo_rdata[96:65]; - assign unpack_write_req_size_8 = _maxi_write_req_fifo_rdata[64:32]; - assign unpack_write_req_local_blocksize_9 = _maxi_write_req_fifo_rdata[31:0]; - assign _maxi_write_op_sel_fifo = unpack_write_req_op_sel_5; - assign _maxi_write_local_addr_fifo = unpack_write_req_local_addr_6; - assign _maxi_write_local_stride_fifo = unpack_write_req_local_stride_7; - assign _maxi_write_size_fifo = unpack_write_req_size_8; - assign _maxi_write_local_blocksize_fifo = unpack_write_req_local_blocksize_9; + wire [8-1:0] unpack_write_req_op_sel_35; + wire [32-1:0] unpack_write_req_local_addr_36; + wire [32-1:0] unpack_write_req_local_stride_37; + wire [33-1:0] unpack_write_req_size_38; + wire [32-1:0] unpack_write_req_local_blocksize_39; + assign unpack_write_req_op_sel_35 = _maxi_write_req_fifo_rdata[136:129]; + assign unpack_write_req_local_addr_36 = _maxi_write_req_fifo_rdata[128:97]; + assign unpack_write_req_local_stride_37 = _maxi_write_req_fifo_rdata[96:65]; + assign unpack_write_req_size_38 = _maxi_write_req_fifo_rdata[64:32]; + assign unpack_write_req_local_blocksize_39 = _maxi_write_req_fifo_rdata[31:0]; + assign _maxi_write_op_sel_fifo = unpack_write_req_op_sel_35; + assign _maxi_write_local_addr_fifo = unpack_write_req_local_addr_36; + assign _maxi_write_local_stride_fifo = unpack_write_req_local_stride_37; + assign _maxi_write_size_fifo = unpack_write_req_size_38; + assign _maxi_write_local_blocksize_fifo = unpack_write_req_local_blocksize_39; reg [8-1:0] _maxi_write_op_sel_buf; reg [32-1:0] _maxi_write_local_addr_buf; reg [32-1:0] _maxi_write_local_stride_buf; @@ -1680,42 +1881,42 @@ localparam _saxi_shift = 2; reg [32-1:0] _saxi_register_fsm; localparam _saxi_register_fsm_init = 0; - reg [32-1:0] addr_10; - reg writevalid_11; - reg readvalid_12; - reg prev_awvalid_13; - reg prev_arvalid_14; - assign saxi_awready = (_saxi_register_fsm == 0) && (!writevalid_11 && !readvalid_12 && !saxi_bvalid && prev_awvalid_13); - assign saxi_arready = (_saxi_register_fsm == 0) && (!readvalid_12 && !writevalid_11 && prev_arvalid_14 && !prev_awvalid_13); - reg [_saxi_maskwidth-1:0] axis_maskaddr_15; - wire signed [32-1:0] axislite_rdata_16; - assign axislite_rdata_16 = (axis_maskaddr_15 == 0)? _saxi_register_0 : - (axis_maskaddr_15 == 1)? _saxi_register_1 : - (axis_maskaddr_15 == 2)? _saxi_register_2 : - (axis_maskaddr_15 == 3)? _saxi_register_3 : - (axis_maskaddr_15 == 4)? _saxi_register_4 : - (axis_maskaddr_15 == 5)? _saxi_register_5 : - (axis_maskaddr_15 == 6)? _saxi_register_6 : - (axis_maskaddr_15 == 7)? _saxi_register_7 : 'hx; - wire axislite_flag_17; - assign axislite_flag_17 = (axis_maskaddr_15 == 0)? _saxi_flag_0 : - (axis_maskaddr_15 == 1)? _saxi_flag_1 : - (axis_maskaddr_15 == 2)? _saxi_flag_2 : - (axis_maskaddr_15 == 3)? _saxi_flag_3 : - (axis_maskaddr_15 == 4)? _saxi_flag_4 : - (axis_maskaddr_15 == 5)? _saxi_flag_5 : - (axis_maskaddr_15 == 6)? _saxi_flag_6 : - (axis_maskaddr_15 == 7)? _saxi_flag_7 : 'hx; - wire signed [32-1:0] axislite_resetval_18; - assign axislite_resetval_18 = (axis_maskaddr_15 == 0)? _saxi_resetval_0 : - (axis_maskaddr_15 == 1)? _saxi_resetval_1 : - (axis_maskaddr_15 == 2)? _saxi_resetval_2 : - (axis_maskaddr_15 == 3)? _saxi_resetval_3 : - (axis_maskaddr_15 == 4)? _saxi_resetval_4 : - (axis_maskaddr_15 == 5)? _saxi_resetval_5 : - (axis_maskaddr_15 == 6)? _saxi_resetval_6 : - (axis_maskaddr_15 == 7)? _saxi_resetval_7 : 'hx; - reg _saxi_cond_0_1; + reg [32-1:0] addr_40; + reg writevalid_41; + reg readvalid_42; + reg prev_awvalid_43; + reg prev_arvalid_44; + assign saxi_awready = (_saxi_register_fsm == 0) && (!writevalid_41 && !readvalid_42 && !saxi_bvalid && prev_awvalid_43); + assign saxi_arready = (_saxi_register_fsm == 0) && (!readvalid_42 && !writevalid_41 && prev_arvalid_44 && !prev_awvalid_43); + reg [_saxi_maskwidth-1:0] axis_maskaddr_45; + wire signed [32-1:0] axislite_rdata_46; + assign axislite_rdata_46 = (axis_maskaddr_45 == 0)? _saxi_register_0 : + (axis_maskaddr_45 == 1)? _saxi_register_1 : + (axis_maskaddr_45 == 2)? _saxi_register_2 : + (axis_maskaddr_45 == 3)? _saxi_register_3 : + (axis_maskaddr_45 == 4)? _saxi_register_4 : + (axis_maskaddr_45 == 5)? _saxi_register_5 : + (axis_maskaddr_45 == 6)? _saxi_register_6 : + (axis_maskaddr_45 == 7)? _saxi_register_7 : 'hx; + wire axislite_flag_47; + assign axislite_flag_47 = (axis_maskaddr_45 == 0)? _saxi_flag_0 : + (axis_maskaddr_45 == 1)? _saxi_flag_1 : + (axis_maskaddr_45 == 2)? _saxi_flag_2 : + (axis_maskaddr_45 == 3)? _saxi_flag_3 : + (axis_maskaddr_45 == 4)? _saxi_flag_4 : + (axis_maskaddr_45 == 5)? _saxi_flag_5 : + (axis_maskaddr_45 == 6)? _saxi_flag_6 : + (axis_maskaddr_45 == 7)? _saxi_flag_7 : 'hx; + wire signed [32-1:0] axislite_resetval_48; + assign axislite_resetval_48 = (axis_maskaddr_45 == 0)? _saxi_resetval_0 : + (axis_maskaddr_45 == 1)? _saxi_resetval_1 : + (axis_maskaddr_45 == 2)? _saxi_resetval_2 : + (axis_maskaddr_45 == 3)? _saxi_resetval_3 : + (axis_maskaddr_45 == 4)? _saxi_resetval_4 : + (axis_maskaddr_45 == 5)? _saxi_resetval_5 : + (axis_maskaddr_45 == 6)? _saxi_resetval_6 : + (axis_maskaddr_45 == 7)? _saxi_resetval_7 : 'hx; + reg _saxi_rdata_cond_0_1; assign saxi_wready = _saxi_register_fsm == 3; reg [32-1:0] th_memcpy; localparam th_memcpy_init = 0; @@ -1730,166 +1931,286 @@ reg signed [32-1:0] _th_memcpy_dst_global_addr_8; reg signed [32-1:0] _th_memcpy_local_addr_9; reg signed [32-1:0] _th_memcpy_dma_size_10; - wire [32-1:0] mask_addr_shifted_19; - assign mask_addr_shifted_19 = _th_memcpy_src_global_addr_7 >> 2; - wire [32-1:0] mask_addr_masked_20; - assign mask_addr_masked_20 = mask_addr_shifted_19 << 2; + wire [32-1:0] mask_addr_shifted_49; + assign mask_addr_shifted_49 = _th_memcpy_src_global_addr_7 >> 2; + wire [32-1:0] mask_addr_masked_50; + assign mask_addr_masked_50 = mask_addr_shifted_49 << 2; reg [32-1:0] _maxi_read_req_fsm; localparam _maxi_read_req_fsm_init = 0; reg [33-1:0] _maxi_read_cur_global_size; reg _maxi_read_cont; - wire [8-1:0] pack_read_req_op_sel_21; - wire [32-1:0] pack_read_req_local_addr_22; - wire [32-1:0] pack_read_req_local_stride_23; - wire [33-1:0] pack_read_req_local_size_24; - wire [32-1:0] pack_read_req_local_blocksize_25; - assign pack_read_req_op_sel_21 = _maxi_read_op_sel; - assign pack_read_req_local_addr_22 = _maxi_read_local_addr; - assign pack_read_req_local_stride_23 = _maxi_read_local_stride; - assign pack_read_req_local_size_24 = _maxi_read_local_size; - assign pack_read_req_local_blocksize_25 = _maxi_read_local_blocksize; - wire [137-1:0] pack_read_req_packed_26; - assign pack_read_req_packed_26 = { pack_read_req_op_sel_21, pack_read_req_local_addr_22, pack_read_req_local_stride_23, pack_read_req_local_size_24, pack_read_req_local_blocksize_25 }; - assign _maxi_read_req_fifo_wdata = ((_maxi_read_req_fsm == 0) && _maxi_read_start && !_maxi_read_req_fifo_almost_full)? pack_read_req_packed_26 : 'hx; + wire [8-1:0] pack_read_req_op_sel_51; + wire [32-1:0] pack_read_req_local_addr_52; + wire [32-1:0] pack_read_req_local_stride_53; + wire [33-1:0] pack_read_req_local_size_54; + wire [32-1:0] pack_read_req_local_blocksize_55; + assign pack_read_req_op_sel_51 = _maxi_read_op_sel; + assign pack_read_req_local_addr_52 = _maxi_read_local_addr; + assign pack_read_req_local_stride_53 = _maxi_read_local_stride; + assign pack_read_req_local_size_54 = _maxi_read_local_size; + assign pack_read_req_local_blocksize_55 = _maxi_read_local_blocksize; + wire [137-1:0] pack_read_req_packed_56; + assign pack_read_req_packed_56 = { pack_read_req_op_sel_51, pack_read_req_local_addr_52, pack_read_req_local_stride_53, pack_read_req_local_size_54, pack_read_req_local_blocksize_55 }; + assign _maxi_read_req_fifo_wdata = ((_maxi_read_req_fsm == 0) && _maxi_read_start && !_maxi_read_req_fifo_almost_full)? pack_read_req_packed_56 : 'hx; assign _maxi_read_req_fifo_enq = ((_maxi_read_req_fsm == 0) && _maxi_read_start && !_maxi_read_req_fifo_almost_full)? (_maxi_read_req_fsm == 0) && _maxi_read_start && !_maxi_read_req_fifo_almost_full && !_maxi_read_req_fifo_almost_full : 0; - localparam _tmp_27 = 1; - wire [_tmp_27-1:0] _tmp_28; - assign _tmp_28 = !_maxi_read_req_fifo_almost_full; - reg [_tmp_27-1:0] __tmp_28_1; - wire [32-1:0] mask_addr_shifted_29; - assign mask_addr_shifted_29 = _maxi_read_global_addr >> 2; - wire [32-1:0] mask_addr_masked_30; - assign mask_addr_masked_30 = mask_addr_shifted_29 << 2; - wire [32-1:0] mask_addr_shifted_31; - assign mask_addr_shifted_31 = _maxi_read_global_addr >> 2; - wire [32-1:0] mask_addr_masked_32; - assign mask_addr_masked_32 = mask_addr_shifted_31 << 2; - wire [32-1:0] mask_addr_shifted_33; - assign mask_addr_shifted_33 = _maxi_read_global_addr >> 2; - wire [32-1:0] mask_addr_masked_34; - assign mask_addr_masked_34 = mask_addr_shifted_33 << 2; - wire [32-1:0] mask_addr_shifted_35; - assign mask_addr_shifted_35 = _maxi_read_global_addr >> 2; - wire [32-1:0] mask_addr_masked_36; - assign mask_addr_masked_36 = mask_addr_shifted_35 << 2; - wire [32-1:0] mask_addr_shifted_37; - assign mask_addr_shifted_37 = _maxi_read_global_addr >> 2; - wire [32-1:0] mask_addr_masked_38; - assign mask_addr_masked_38 = mask_addr_shifted_37 << 2; - wire [32-1:0] mask_addr_shifted_39; - assign mask_addr_shifted_39 = _maxi_read_global_addr >> 2; - wire [32-1:0] mask_addr_masked_40; - assign mask_addr_masked_40 = mask_addr_shifted_39 << 2; - reg _maxi_cond_0_1; - reg [32-1:0] _maxi_read_data_fsm; - localparam _maxi_read_data_fsm_init = 0; - assign _maxi_read_req_fifo_deq = ((_maxi_read_data_fsm == 0) && (!_maxi_read_data_busy && !_maxi_read_req_fifo_empty && (_maxi_read_op_sel_fifo == 1)) && !_maxi_read_req_fifo_empty)? 1 : 0; - reg [32-1:0] write_burst_fsm_0; - localparam write_burst_fsm_0_init = 0; - reg [10-1:0] write_burst_addr_41; - reg [10-1:0] write_burst_stride_42; - reg [33-1:0] write_burst_length_43; - reg write_burst_done_44; - assign ram_a_0_wdata = ((write_burst_fsm_0 == 1) && maxi_rvalid)? maxi_rdata : 'hx; - assign ram_a_0_wenable = ((write_burst_fsm_0 == 1) && maxi_rvalid)? 1'd1 : 0; - assign maxi_rready = _maxi_read_data_fsm == 2; - wire [32-1:0] mask_addr_shifted_45; - assign mask_addr_shifted_45 = _th_memcpy_dst_global_addr_8 >> 2; - wire [32-1:0] mask_addr_masked_46; - assign mask_addr_masked_46 = mask_addr_shifted_45 << 2; - reg [32-1:0] _maxi_write_req_fsm; - localparam _maxi_write_req_fsm_init = 0; - reg [33-1:0] _maxi_write_cur_global_size; - reg _maxi_write_cont; - wire [8-1:0] pack_write_req_op_sel_47; - wire [32-1:0] pack_write_req_local_addr_48; - wire [32-1:0] pack_write_req_local_stride_49; - wire [33-1:0] pack_write_req_size_50; - wire [32-1:0] pack_write_req_local_blocksize_51; - assign pack_write_req_op_sel_47 = _maxi_write_op_sel; - assign pack_write_req_local_addr_48 = _maxi_write_local_addr; - assign pack_write_req_local_stride_49 = _maxi_write_local_stride; - assign pack_write_req_size_50 = _maxi_write_local_size; - assign pack_write_req_local_blocksize_51 = _maxi_write_local_blocksize; - wire [137-1:0] pack_write_req_packed_52; - assign pack_write_req_packed_52 = { pack_write_req_op_sel_47, pack_write_req_local_addr_48, pack_write_req_local_stride_49, pack_write_req_size_50, pack_write_req_local_blocksize_51 }; - localparam _tmp_53 = 1; - wire [_tmp_53-1:0] _tmp_54; - assign _tmp_54 = !_maxi_write_req_fifo_almost_full; - reg [_tmp_53-1:0] __tmp_54_1; - wire [32-1:0] mask_addr_shifted_55; - assign mask_addr_shifted_55 = _maxi_write_global_addr >> 2; - wire [32-1:0] mask_addr_masked_56; - assign mask_addr_masked_56 = mask_addr_shifted_55 << 2; - wire [32-1:0] mask_addr_shifted_57; - assign mask_addr_shifted_57 = _maxi_write_global_addr >> 2; - wire [32-1:0] mask_addr_masked_58; - assign mask_addr_masked_58 = mask_addr_shifted_57 << 2; + localparam _tmp_57 = 1; + wire [_tmp_57-1:0] _tmp_58; + assign _tmp_58 = !_maxi_read_req_fifo_almost_full; + reg [_tmp_57-1:0] __tmp_58_1; wire [32-1:0] mask_addr_shifted_59; - assign mask_addr_shifted_59 = _maxi_write_global_addr >> 2; + assign mask_addr_shifted_59 = _maxi_read_global_addr >> 2; wire [32-1:0] mask_addr_masked_60; assign mask_addr_masked_60 = mask_addr_shifted_59 << 2; wire [32-1:0] mask_addr_shifted_61; - assign mask_addr_shifted_61 = _maxi_write_global_addr >> 2; + assign mask_addr_shifted_61 = _maxi_read_global_addr >> 2; wire [32-1:0] mask_addr_masked_62; assign mask_addr_masked_62 = mask_addr_shifted_61 << 2; wire [32-1:0] mask_addr_shifted_63; - assign mask_addr_shifted_63 = _maxi_write_global_addr >> 2; + assign mask_addr_shifted_63 = _maxi_read_global_addr >> 2; wire [32-1:0] mask_addr_masked_64; assign mask_addr_masked_64 = mask_addr_shifted_63 << 2; wire [32-1:0] mask_addr_shifted_65; - assign mask_addr_shifted_65 = _maxi_write_global_addr >> 2; + assign mask_addr_shifted_65 = _maxi_read_global_addr >> 2; wire [32-1:0] mask_addr_masked_66; assign mask_addr_masked_66 = mask_addr_shifted_65 << 2; - wire [8-1:0] pack_write_req_op_sel_67; - wire [32-1:0] pack_write_req_local_addr_68; - wire [32-1:0] pack_write_req_local_stride_69; - wire [33-1:0] pack_write_req_size_70; - wire [32-1:0] pack_write_req_local_blocksize_71; - assign pack_write_req_op_sel_67 = _maxi_write_op_sel; - assign pack_write_req_local_addr_68 = _maxi_write_local_addr; - assign pack_write_req_local_stride_69 = _maxi_write_local_stride; - assign pack_write_req_size_70 = _maxi_write_cur_global_size; - assign pack_write_req_local_blocksize_71 = _maxi_write_local_blocksize; - wire [137-1:0] pack_write_req_packed_72; - assign pack_write_req_packed_72 = { pack_write_req_op_sel_67, pack_write_req_local_addr_68, pack_write_req_local_stride_69, pack_write_req_size_70, pack_write_req_local_blocksize_71 }; - assign _maxi_write_req_fifo_wdata = ((_maxi_write_req_fsm == 1) && !_maxi_write_req_fifo_almost_full && (maxi_awready || !maxi_awvalid) && (_maxi_outstanding_wcount < 6))? pack_write_req_packed_72 : - ((_maxi_write_req_fsm == 0) && _maxi_write_start && !_maxi_write_req_fifo_almost_full)? pack_write_req_packed_52 : 'hx; + wire [32-1:0] mask_addr_shifted_67; + assign mask_addr_shifted_67 = _maxi_read_global_addr >> 2; + wire [32-1:0] mask_addr_masked_68; + assign mask_addr_masked_68 = mask_addr_shifted_67 << 2; + wire [32-1:0] mask_addr_shifted_69; + assign mask_addr_shifted_69 = _maxi_read_global_addr >> 2; + wire [32-1:0] mask_addr_masked_70; + assign mask_addr_masked_70 = mask_addr_shifted_69 << 2; + reg _maxi_raddr_cond_0_1; + reg [32-1:0] _maxi_read_data_fsm; + localparam _maxi_read_data_fsm_init = 0; + assign _maxi_read_req_fifo_deq = ((_maxi_read_data_fsm == 0) && (!_maxi_read_data_busy && !_maxi_read_req_fifo_empty && (_maxi_read_op_sel_fifo == 1)) && !_maxi_read_req_fifo_empty)? 1 : 0; + reg [32-1:0] write_burst_fsm_0; + localparam write_burst_fsm_0_init = 0; + reg [10-1:0] write_burst_addr_71; + reg [10-1:0] write_burst_stride_72; + reg [33-1:0] write_burst_length_73; + reg write_burst_done_74; + assign ram_a_0_wdata = ((write_burst_fsm_0 == 1) && _maxi_rvalid_sb_0)? _maxi_rdata_sb_0 : 'hx; + assign ram_a_0_wenable = ((write_burst_fsm_0 == 1) && _maxi_rvalid_sb_0)? 1'd1 : 0; + assign _maxi_rready_sb_0 = _maxi_read_data_fsm == 2; + wire [32-1:0] mask_addr_shifted_75; + assign mask_addr_shifted_75 = _th_memcpy_dst_global_addr_8 >> 2; + wire [32-1:0] mask_addr_masked_76; + assign mask_addr_masked_76 = mask_addr_shifted_75 << 2; + reg [32-1:0] _maxi_write_req_fsm; + localparam _maxi_write_req_fsm_init = 0; + reg [33-1:0] _maxi_write_cur_global_size; + reg _maxi_write_cont; + wire [8-1:0] pack_write_req_op_sel_77; + wire [32-1:0] pack_write_req_local_addr_78; + wire [32-1:0] pack_write_req_local_stride_79; + wire [33-1:0] pack_write_req_size_80; + wire [32-1:0] pack_write_req_local_blocksize_81; + assign pack_write_req_op_sel_77 = _maxi_write_op_sel; + assign pack_write_req_local_addr_78 = _maxi_write_local_addr; + assign pack_write_req_local_stride_79 = _maxi_write_local_stride; + assign pack_write_req_size_80 = _maxi_write_local_size; + assign pack_write_req_local_blocksize_81 = _maxi_write_local_blocksize; + wire [137-1:0] pack_write_req_packed_82; + assign pack_write_req_packed_82 = { pack_write_req_op_sel_77, pack_write_req_local_addr_78, pack_write_req_local_stride_79, pack_write_req_size_80, pack_write_req_local_blocksize_81 }; + localparam _tmp_83 = 1; + wire [_tmp_83-1:0] _tmp_84; + assign _tmp_84 = !_maxi_write_req_fifo_almost_full; + reg [_tmp_83-1:0] __tmp_84_1; + wire [32-1:0] mask_addr_shifted_85; + assign mask_addr_shifted_85 = _maxi_write_global_addr >> 2; + wire [32-1:0] mask_addr_masked_86; + assign mask_addr_masked_86 = mask_addr_shifted_85 << 2; + wire [32-1:0] mask_addr_shifted_87; + assign mask_addr_shifted_87 = _maxi_write_global_addr >> 2; + wire [32-1:0] mask_addr_masked_88; + assign mask_addr_masked_88 = mask_addr_shifted_87 << 2; + wire [32-1:0] mask_addr_shifted_89; + assign mask_addr_shifted_89 = _maxi_write_global_addr >> 2; + wire [32-1:0] mask_addr_masked_90; + assign mask_addr_masked_90 = mask_addr_shifted_89 << 2; + wire [32-1:0] mask_addr_shifted_91; + assign mask_addr_shifted_91 = _maxi_write_global_addr >> 2; + wire [32-1:0] mask_addr_masked_92; + assign mask_addr_masked_92 = mask_addr_shifted_91 << 2; + wire [32-1:0] mask_addr_shifted_93; + assign mask_addr_shifted_93 = _maxi_write_global_addr >> 2; + wire [32-1:0] mask_addr_masked_94; + assign mask_addr_masked_94 = mask_addr_shifted_93 << 2; + wire [32-1:0] mask_addr_shifted_95; + assign mask_addr_shifted_95 = _maxi_write_global_addr >> 2; + wire [32-1:0] mask_addr_masked_96; + assign mask_addr_masked_96 = mask_addr_shifted_95 << 2; + wire [8-1:0] pack_write_req_op_sel_97; + wire [32-1:0] pack_write_req_local_addr_98; + wire [32-1:0] pack_write_req_local_stride_99; + wire [33-1:0] pack_write_req_size_100; + wire [32-1:0] pack_write_req_local_blocksize_101; + assign pack_write_req_op_sel_97 = _maxi_write_op_sel; + assign pack_write_req_local_addr_98 = _maxi_write_local_addr; + assign pack_write_req_local_stride_99 = _maxi_write_local_stride; + assign pack_write_req_size_100 = _maxi_write_cur_global_size; + assign pack_write_req_local_blocksize_101 = _maxi_write_local_blocksize; + wire [137-1:0] pack_write_req_packed_102; + assign pack_write_req_packed_102 = { pack_write_req_op_sel_97, pack_write_req_local_addr_98, pack_write_req_local_stride_99, pack_write_req_size_100, pack_write_req_local_blocksize_101 }; + assign _maxi_write_req_fifo_wdata = ((_maxi_write_req_fsm == 1) && !_maxi_write_req_fifo_almost_full && (maxi_awready || !maxi_awvalid) && (_maxi_outstanding_wcount < 6))? pack_write_req_packed_102 : + ((_maxi_write_req_fsm == 0) && _maxi_write_start && !_maxi_write_req_fifo_almost_full)? pack_write_req_packed_82 : 'hx; assign _maxi_write_req_fifo_enq = ((_maxi_write_req_fsm == 1) && !_maxi_write_req_fifo_almost_full && (maxi_awready || !maxi_awvalid) && (_maxi_outstanding_wcount < 6))? (_maxi_write_req_fsm == 1) && !_maxi_write_req_fifo_almost_full && (maxi_awready || !maxi_awvalid) && (_maxi_outstanding_wcount < 6) && !_maxi_write_req_fifo_almost_full : ((_maxi_write_req_fsm == 0) && _maxi_write_start && !_maxi_write_req_fifo_almost_full)? (_maxi_write_req_fsm == 0) && _maxi_write_start && !_maxi_write_req_fifo_almost_full && !_maxi_write_req_fifo_almost_full : 0; - localparam _tmp_73 = 1; - wire [_tmp_73-1:0] _tmp_74; - assign _tmp_74 = !_maxi_write_req_fifo_almost_full; - reg [_tmp_73-1:0] __tmp_74_1; - reg _maxi_cond_1_1; + localparam _tmp_103 = 1; + wire [_tmp_103-1:0] _tmp_104; + assign _tmp_104 = !_maxi_write_req_fifo_almost_full; + reg [_tmp_103-1:0] __tmp_104_1; + reg _maxi_waddr_cond_0_1; reg [32-1:0] _maxi_write_data_fsm; localparam _maxi_write_data_fsm_init = 0; reg [32-1:0] read_burst_fsm_1; localparam read_burst_fsm_1_init = 0; - reg [10-1:0] read_burst_addr_75; - reg [10-1:0] read_burst_stride_76; - reg [33-1:0] read_burst_length_77; - reg read_burst_rvalid_78; - reg read_burst_rlast_79; - assign ram_a_0_addr = ((read_burst_fsm_1 == 1) && (!read_burst_rvalid_78 || (maxi_wready || !maxi_wvalid) && (_maxi_write_size_buf > 0)))? read_burst_addr_75 : - ((write_burst_fsm_0 == 1) && maxi_rvalid)? write_burst_addr_41 : 'hx; - assign ram_a_0_enable = ((read_burst_fsm_1 == 1) && (!read_burst_rvalid_78 || (maxi_wready || !maxi_wvalid) && (_maxi_write_size_buf > 0)))? 1'd1 : - ((write_burst_fsm_0 == 1) && maxi_rvalid)? 1'd1 : 0; - localparam _tmp_80 = 1; - wire [_tmp_80-1:0] _tmp_81; - assign _tmp_81 = (read_burst_fsm_1 == 1) && (!read_burst_rvalid_78 || (maxi_wready || !maxi_wvalid) && (_maxi_write_size_buf > 0)); - reg [_tmp_80-1:0] __tmp_81_1; - wire [32-1:0] read_burst_rdata_82; - assign read_burst_rdata_82 = ram_a_0_rdata; + reg [10-1:0] read_burst_addr_105; + reg [10-1:0] read_burst_stride_106; + reg [33-1:0] read_burst_length_107; + reg read_burst_rvalid_108; + reg read_burst_rlast_109; + assign ram_a_0_addr = ((read_burst_fsm_1 == 1) && (!read_burst_rvalid_108 || (_maxi_wready_sb_0 || !_maxi_wvalid_sb_0) && (_maxi_write_size_buf > 0)))? read_burst_addr_105 : + ((write_burst_fsm_0 == 1) && _maxi_rvalid_sb_0)? write_burst_addr_71 : 'hx; + assign ram_a_0_enable = ((read_burst_fsm_1 == 1) && (!read_burst_rvalid_108 || (_maxi_wready_sb_0 || !_maxi_wvalid_sb_0) && (_maxi_write_size_buf > 0)))? 1'd1 : + ((write_burst_fsm_0 == 1) && _maxi_rvalid_sb_0)? 1'd1 : 0; + localparam _tmp_110 = 1; + wire [_tmp_110-1:0] _tmp_111; + assign _tmp_111 = (read_burst_fsm_1 == 1) && (!read_burst_rvalid_108 || (_maxi_wready_sb_0 || !_maxi_wvalid_sb_0) && (_maxi_write_size_buf > 0)); + reg [_tmp_110-1:0] __tmp_111_1; + wire [32-1:0] read_burst_rdata_112; + assign read_burst_rdata_112 = ram_a_0_rdata; assign _maxi_write_req_fifo_deq = ((_maxi_write_data_fsm == 2) && (!_maxi_write_req_fifo_empty && (_maxi_write_size_buf == 0)) && !_maxi_write_req_fifo_empty)? 1 : ((_maxi_write_data_fsm == 0) && (!_maxi_write_data_busy && !_maxi_write_req_fifo_empty && (_maxi_write_op_sel_fifo == 1)) && !_maxi_write_req_fifo_empty)? 1 : 0; - reg _maxi_cond_2_1; + reg _maxi_wdata_cond_0_1; always @(posedge CLK) begin if(RST) begin - __tmp_81_1 <= 0; + __tmp_111_1 <= 0; end else begin - __tmp_81_1 <= _tmp_81; + __tmp_111_1 <= _tmp_111; + end + end + + + always @(posedge CLK) begin + if(RST) begin + maxi_awaddr <= 0; + maxi_awlen <= 0; + maxi_awvalid <= 0; + _maxi_waddr_cond_0_1 <= 0; + end else begin + if(_maxi_waddr_cond_0_1) begin + maxi_awvalid <= 0; + end + if((_maxi_write_req_fsm == 1) && !_maxi_write_req_fifo_almost_full && (_maxi_outstanding_wcount < 6) && ((_maxi_outstanding_wcount < 6) && (maxi_awready || !maxi_awvalid))) begin + maxi_awaddr <= _maxi_write_global_addr; + maxi_awlen <= _maxi_write_cur_global_size - 1; + maxi_awvalid <= 1; + end + if((_maxi_write_req_fsm == 1) && !_maxi_write_req_fifo_almost_full && (_maxi_outstanding_wcount < 6) && ((_maxi_outstanding_wcount < 6) && (maxi_awready || !maxi_awvalid)) && (_maxi_write_cur_global_size == 0)) begin + maxi_awvalid <= 0; + end + _maxi_waddr_cond_0_1 <= 1; + if(maxi_awvalid && !maxi_awready) begin + maxi_awvalid <= maxi_awvalid; + end + end + end + + + always @(posedge CLK) begin + if(RST) begin + _maxi_wdata_sb_0 <= 0; + _maxi_wvalid_sb_0 <= 0; + _maxi_wlast_sb_0 <= 0; + _maxi_wstrb_sb_0 <= 0; + _maxi_wdata_cond_0_1 <= 0; + end else begin + if(_maxi_wdata_cond_0_1) begin + _maxi_wvalid_sb_0 <= 0; + _maxi_wlast_sb_0 <= 0; + end + if((_maxi_write_op_sel_buf == 1) && read_burst_rvalid_108 && ((_maxi_wready_sb_0 || !_maxi_wvalid_sb_0) && (_maxi_write_size_buf > 0)) && (_maxi_wready_sb_0 || !_maxi_wvalid_sb_0)) begin + _maxi_wdata_sb_0 <= read_burst_rdata_112; + _maxi_wvalid_sb_0 <= 1; + _maxi_wlast_sb_0 <= read_burst_rlast_109 || (_maxi_write_size_buf == 1); + _maxi_wstrb_sb_0 <= { 4{ 1'd1 } }; + end + _maxi_wdata_cond_0_1 <= 1; + if(_maxi_wvalid_sb_0 && !_maxi_wready_sb_0) begin + _maxi_wvalid_sb_0 <= _maxi_wvalid_sb_0; + _maxi_wlast_sb_0 <= _maxi_wlast_sb_0; + end + end + end + + + always @(posedge CLK) begin + if(RST) begin + _sb_maxi_writedata_data_6 <= 0; + _sb_maxi_writedata_valid_7 <= 0; + _sb_maxi_writedata_tmp_data_9 <= 0; + _sb_maxi_writedata_tmp_valid_10 <= 0; + end else begin + if(_sb_maxi_writedata_m_ready_5 || !_sb_maxi_writedata_valid_7) begin + _sb_maxi_writedata_data_6 <= _sb_maxi_writedata_next_data_11; + _sb_maxi_writedata_valid_7 <= _sb_maxi_writedata_next_valid_12; + end + if(!_sb_maxi_writedata_tmp_valid_10 && _sb_maxi_writedata_valid_7 && !_sb_maxi_writedata_m_ready_5) begin + _sb_maxi_writedata_tmp_data_9 <= _sb_maxi_writedata_s_data_3; + _sb_maxi_writedata_tmp_valid_10 <= _sb_maxi_writedata_s_valid_4; + end + if(_sb_maxi_writedata_tmp_valid_10 && _sb_maxi_writedata_m_ready_5) begin + _sb_maxi_writedata_tmp_valid_10 <= 0; + end + end + end + + + always @(posedge CLK) begin + if(RST) begin + maxi_araddr <= 0; + maxi_arlen <= 0; + maxi_arvalid <= 0; + _maxi_raddr_cond_0_1 <= 0; + end else begin + if(_maxi_raddr_cond_0_1) begin + maxi_arvalid <= 0; + end + if((_maxi_read_req_fsm == 1) && (maxi_arready || !maxi_arvalid)) begin + maxi_araddr <= _maxi_read_global_addr; + maxi_arlen <= _maxi_read_cur_global_size - 1; + maxi_arvalid <= 1; + end + _maxi_raddr_cond_0_1 <= 1; + if(maxi_arvalid && !maxi_arready) begin + maxi_arvalid <= maxi_arvalid; + end + end + end + + + always @(posedge CLK) begin + if(RST) begin + _sb_maxi_readdata_data_21 <= 0; + _sb_maxi_readdata_valid_22 <= 0; + _sb_maxi_readdata_tmp_data_24 <= 0; + _sb_maxi_readdata_tmp_valid_25 <= 0; + end else begin + if(_sb_maxi_readdata_m_ready_20 || !_sb_maxi_readdata_valid_22) begin + _sb_maxi_readdata_data_21 <= _sb_maxi_readdata_next_data_26; + _sb_maxi_readdata_valid_22 <= _sb_maxi_readdata_next_valid_27; + end + if(!_sb_maxi_readdata_tmp_valid_25 && _sb_maxi_readdata_valid_22 && !_sb_maxi_readdata_m_ready_20) begin + _sb_maxi_readdata_tmp_data_24 <= _sb_maxi_readdata_s_data_18; + _sb_maxi_readdata_tmp_valid_25 <= _sb_maxi_readdata_s_valid_19; + end + if(_sb_maxi_readdata_tmp_valid_25 && _sb_maxi_readdata_m_ready_20) begin + _sb_maxi_readdata_tmp_valid_25 <= 0; + end end end @@ -1908,10 +2229,6 @@ _maxi_read_local_blocksize <= 0; _maxi_read_req_busy <= 0; _maxi_read_cur_global_size <= 0; - maxi_araddr <= 0; - maxi_arlen <= 0; - maxi_arvalid <= 0; - _maxi_cond_0_1 <= 0; _maxi_read_data_busy <= 0; _maxi_read_op_sel_buf <= 0; _maxi_read_local_addr_buf <= 0; @@ -1927,32 +2244,13 @@ _maxi_write_local_blocksize <= 0; _maxi_write_req_busy <= 0; _maxi_write_cur_global_size <= 0; - maxi_awaddr <= 0; - maxi_awlen <= 0; - maxi_awvalid <= 0; - _maxi_cond_1_1 <= 0; _maxi_write_data_busy <= 0; _maxi_write_op_sel_buf <= 0; _maxi_write_local_addr_buf <= 0; _maxi_write_local_stride_buf <= 0; _maxi_write_size_buf <= 0; _maxi_write_local_blocksize_buf <= 0; - maxi_wdata <= 0; - maxi_wvalid <= 0; - maxi_wlast <= 0; - maxi_wstrb <= 0; - _maxi_cond_2_1 <= 0; end else begin - if(_maxi_cond_0_1) begin - maxi_arvalid <= 0; - end - if(_maxi_cond_1_1) begin - maxi_awvalid <= 0; - end - if(_maxi_cond_2_1) begin - maxi_wvalid <= 0; - maxi_wlast <= 0; - end if(maxi_awvalid && maxi_awready && !(maxi_bvalid && maxi_bready) && (_maxi_outstanding_wcount < 7)) begin _maxi_outstanding_wcount <= _maxi_outstanding_wcount + 1; end @@ -1964,7 +2262,7 @@ if((th_memcpy == 17) && _maxi_read_req_idle) begin _maxi_read_start <= 1; _maxi_read_op_sel <= 1; - _maxi_read_global_addr <= mask_addr_masked_20; + _maxi_read_global_addr <= mask_addr_masked_50; _maxi_read_global_size <= _th_memcpy_dma_size_10; _maxi_read_local_addr <= _th_memcpy_local_addr_9; _maxi_read_local_stride <= 1; @@ -1977,28 +2275,19 @@ if(_maxi_read_start && _maxi_read_req_fifo_almost_full) begin _maxi_read_start <= 1; end - if((_maxi_read_req_fsm == 0) && (_maxi_read_start || _maxi_read_cont) && !_maxi_read_req_fifo_almost_full && (_maxi_read_global_size <= 256) && ((mask_addr_masked_30 & 4095) + (_maxi_read_global_size << 2) >= 4096)) begin - _maxi_read_cur_global_size <= 4096 - (mask_addr_masked_32 & 4095) >> 2; - _maxi_read_global_size <= _maxi_read_global_size - (4096 - (mask_addr_masked_34 & 4095) >> 2); + if((_maxi_read_req_fsm == 0) && (_maxi_read_start || _maxi_read_cont) && !_maxi_read_req_fifo_almost_full && (_maxi_read_global_size <= 256) && ((mask_addr_masked_60 & 4095) + (_maxi_read_global_size << 2) >= 4096)) begin + _maxi_read_cur_global_size <= 4096 - (mask_addr_masked_62 & 4095) >> 2; + _maxi_read_global_size <= _maxi_read_global_size - (4096 - (mask_addr_masked_64 & 4095) >> 2); end else if((_maxi_read_req_fsm == 0) && (_maxi_read_start || _maxi_read_cont) && !_maxi_read_req_fifo_almost_full && (_maxi_read_global_size <= 256)) begin _maxi_read_cur_global_size <= _maxi_read_global_size; _maxi_read_global_size <= 0; - end else if((_maxi_read_req_fsm == 0) && (_maxi_read_start || _maxi_read_cont) && !_maxi_read_req_fifo_almost_full && ((mask_addr_masked_36 & 4095) + 1024 >= 4096)) begin - _maxi_read_cur_global_size <= 4096 - (mask_addr_masked_38 & 4095) >> 2; - _maxi_read_global_size <= _maxi_read_global_size - (4096 - (mask_addr_masked_40 & 4095) >> 2); + end else if((_maxi_read_req_fsm == 0) && (_maxi_read_start || _maxi_read_cont) && !_maxi_read_req_fifo_almost_full && ((mask_addr_masked_66 & 4095) + 1024 >= 4096)) begin + _maxi_read_cur_global_size <= 4096 - (mask_addr_masked_68 & 4095) >> 2; + _maxi_read_global_size <= _maxi_read_global_size - (4096 - (mask_addr_masked_70 & 4095) >> 2); end else if((_maxi_read_req_fsm == 0) && (_maxi_read_start || _maxi_read_cont) && !_maxi_read_req_fifo_almost_full) begin _maxi_read_cur_global_size <= 256; _maxi_read_global_size <= _maxi_read_global_size - 256; end - if((_maxi_read_req_fsm == 1) && (maxi_arready || !maxi_arvalid)) begin - maxi_araddr <= _maxi_read_global_addr; - maxi_arlen <= _maxi_read_cur_global_size - 1; - maxi_arvalid <= 1; - end - _maxi_cond_0_1 <= 1; - if(maxi_arvalid && !maxi_arready) begin - maxi_arvalid <= maxi_arvalid; - end if((_maxi_read_req_fsm == 1) && (maxi_arready || !maxi_arvalid)) begin _maxi_read_global_addr <= _maxi_read_global_addr + (_maxi_read_cur_global_size << 2); end @@ -2013,16 +2302,16 @@ _maxi_read_local_size_buf <= _maxi_read_local_size_fifo; _maxi_read_local_blocksize_buf <= _maxi_read_local_blocksize_fifo; end - if((_maxi_read_data_fsm == 2) && maxi_rvalid) begin + if((_maxi_read_data_fsm == 2) && _maxi_rvalid_sb_0) begin _maxi_read_local_size_buf <= _maxi_read_local_size_buf - 1; end - if((_maxi_read_data_fsm == 2) && maxi_rvalid && (_maxi_read_local_size_buf <= 1)) begin + if((_maxi_read_data_fsm == 2) && _maxi_rvalid_sb_0 && (_maxi_read_local_size_buf <= 1)) begin _maxi_read_data_busy <= 0; end if((th_memcpy == 19) && _maxi_write_req_idle) begin _maxi_write_start <= 1; _maxi_write_op_sel <= 1; - _maxi_write_global_addr <= mask_addr_masked_46; + _maxi_write_global_addr <= mask_addr_masked_76; _maxi_write_global_size <= _th_memcpy_dma_size_10; _maxi_write_local_addr <= _th_memcpy_local_addr_9; _maxi_write_local_stride <= 1; @@ -2035,31 +2324,19 @@ if(_maxi_write_start && _maxi_write_req_fifo_almost_full) begin _maxi_write_start <= 1; end - if((_maxi_write_req_fsm == 0) && (_maxi_write_start || _maxi_write_cont) && !_maxi_write_req_fifo_almost_full && (_maxi_write_global_size <= 256) && ((mask_addr_masked_56 & 4095) + (_maxi_write_global_size << 2) >= 4096)) begin - _maxi_write_cur_global_size <= 4096 - (mask_addr_masked_58 & 4095) >> 2; - _maxi_write_global_size <= _maxi_write_global_size - (4096 - (mask_addr_masked_60 & 4095) >> 2); + if((_maxi_write_req_fsm == 0) && (_maxi_write_start || _maxi_write_cont) && !_maxi_write_req_fifo_almost_full && (_maxi_write_global_size <= 256) && ((mask_addr_masked_86 & 4095) + (_maxi_write_global_size << 2) >= 4096)) begin + _maxi_write_cur_global_size <= 4096 - (mask_addr_masked_88 & 4095) >> 2; + _maxi_write_global_size <= _maxi_write_global_size - (4096 - (mask_addr_masked_90 & 4095) >> 2); end else if((_maxi_write_req_fsm == 0) && (_maxi_write_start || _maxi_write_cont) && !_maxi_write_req_fifo_almost_full && (_maxi_write_global_size <= 256)) begin _maxi_write_cur_global_size <= _maxi_write_global_size; _maxi_write_global_size <= 0; - end else if((_maxi_write_req_fsm == 0) && (_maxi_write_start || _maxi_write_cont) && !_maxi_write_req_fifo_almost_full && ((mask_addr_masked_62 & 4095) + 1024 >= 4096)) begin - _maxi_write_cur_global_size <= 4096 - (mask_addr_masked_64 & 4095) >> 2; - _maxi_write_global_size <= _maxi_write_global_size - (4096 - (mask_addr_masked_66 & 4095) >> 2); + end else if((_maxi_write_req_fsm == 0) && (_maxi_write_start || _maxi_write_cont) && !_maxi_write_req_fifo_almost_full && ((mask_addr_masked_92 & 4095) + 1024 >= 4096)) begin + _maxi_write_cur_global_size <= 4096 - (mask_addr_masked_94 & 4095) >> 2; + _maxi_write_global_size <= _maxi_write_global_size - (4096 - (mask_addr_masked_96 & 4095) >> 2); end else if((_maxi_write_req_fsm == 0) && (_maxi_write_start || _maxi_write_cont) && !_maxi_write_req_fifo_almost_full) begin _maxi_write_cur_global_size <= 256; _maxi_write_global_size <= _maxi_write_global_size - 256; end - if((_maxi_write_req_fsm == 1) && !_maxi_write_req_fifo_almost_full && (_maxi_outstanding_wcount < 6) && ((_maxi_outstanding_wcount < 6) && (maxi_awready || !maxi_awvalid))) begin - maxi_awaddr <= _maxi_write_global_addr; - maxi_awlen <= _maxi_write_cur_global_size - 1; - maxi_awvalid <= 1; - end - if((_maxi_write_req_fsm == 1) && !_maxi_write_req_fifo_almost_full && (_maxi_outstanding_wcount < 6) && ((_maxi_outstanding_wcount < 6) && (maxi_awready || !maxi_awvalid)) && (_maxi_write_cur_global_size == 0)) begin - maxi_awvalid <= 0; - end - _maxi_cond_1_1 <= 1; - if(maxi_awvalid && !maxi_awready) begin - maxi_awvalid <= maxi_awvalid; - end if((_maxi_write_req_fsm == 1) && ((_maxi_write_req_fsm == 1) && !_maxi_write_req_fifo_almost_full && (maxi_awready || !maxi_awvalid) && (_maxi_outstanding_wcount < 6))) begin _maxi_write_global_addr <= _maxi_write_global_addr + (_maxi_write_cur_global_size << 2); end @@ -2080,21 +2357,10 @@ if((_maxi_write_data_fsm == 2) && (!_maxi_write_req_fifo_empty && (_maxi_write_size_buf == 0))) begin _maxi_write_size_buf <= _maxi_write_size_fifo; end - if((_maxi_write_op_sel_buf == 1) && read_burst_rvalid_78 && ((maxi_wready || !maxi_wvalid) && (_maxi_write_size_buf > 0)) && (maxi_wready || !maxi_wvalid)) begin - maxi_wdata <= read_burst_rdata_82; - maxi_wvalid <= 1; - maxi_wlast <= read_burst_rlast_79 || (_maxi_write_size_buf == 1); - maxi_wstrb <= { 4{ 1'd1 } }; - end - _maxi_cond_2_1 <= 1; - if(maxi_wvalid && !maxi_wready) begin - maxi_wvalid <= maxi_wvalid; - maxi_wlast <= maxi_wlast; - end - if((_maxi_write_data_fsm == 2) && read_burst_rvalid_78 && ((maxi_wready || !maxi_wvalid) && (_maxi_write_size_buf > 0))) begin + if((_maxi_write_data_fsm == 2) && read_burst_rvalid_108 && ((_maxi_wready_sb_0 || !_maxi_wvalid_sb_0) && (_maxi_write_size_buf > 0))) begin _maxi_write_size_buf <= _maxi_write_size_buf - 1; end - if((_maxi_write_data_fsm == 2) && ((_maxi_write_op_sel_buf == 1) && read_burst_rvalid_78 && ((maxi_wready || !maxi_wvalid) && (_maxi_write_size_buf > 0))) && read_burst_rlast_79) begin + if((_maxi_write_data_fsm == 2) && ((_maxi_write_op_sel_buf == 1) && read_burst_rvalid_108 && ((_maxi_wready_sb_0 || !_maxi_wvalid_sb_0) && (_maxi_write_size_buf > 0))) && read_burst_rlast_109) begin _maxi_write_data_busy <= 0; end end @@ -2104,7 +2370,7 @@ always @(posedge CLK) begin if(RST) begin count__maxi_read_req_fifo <= 0; - __tmp_28_1 <= 0; + __tmp_58_1 <= 0; end else begin if(_maxi_read_req_fifo_enq && !_maxi_read_req_fifo_full && (_maxi_read_req_fifo_deq && !_maxi_read_req_fifo_empty)) begin count__maxi_read_req_fifo <= count__maxi_read_req_fifo; @@ -2113,7 +2379,7 @@ end else if(_maxi_read_req_fifo_deq && !_maxi_read_req_fifo_empty) begin count__maxi_read_req_fifo <= count__maxi_read_req_fifo - 1; end - __tmp_28_1 <= _tmp_28; + __tmp_58_1 <= _tmp_58; end end @@ -2121,8 +2387,8 @@ always @(posedge CLK) begin if(RST) begin count__maxi_write_req_fifo <= 0; - __tmp_54_1 <= 0; - __tmp_74_1 <= 0; + __tmp_84_1 <= 0; + __tmp_104_1 <= 0; end else begin if(_maxi_write_req_fifo_enq && !_maxi_write_req_fifo_full && (_maxi_write_req_fifo_deq && !_maxi_write_req_fifo_empty)) begin count__maxi_write_req_fifo <= count__maxi_write_req_fifo; @@ -2131,23 +2397,41 @@ end else if(_maxi_write_req_fifo_deq && !_maxi_write_req_fifo_empty) begin count__maxi_write_req_fifo <= count__maxi_write_req_fifo - 1; end - __tmp_54_1 <= _tmp_54; - __tmp_74_1 <= _tmp_74; + __tmp_84_1 <= _tmp_84; + __tmp_104_1 <= _tmp_104; end end always @(posedge CLK) begin if(RST) begin - saxi_bvalid <= 0; - prev_awvalid_13 <= 0; - prev_arvalid_14 <= 0; - writevalid_11 <= 0; - readvalid_12 <= 0; - addr_10 <= 0; saxi_rdata <= 0; saxi_rvalid <= 0; - _saxi_cond_0_1 <= 0; + _saxi_rdata_cond_0_1 <= 0; + end else begin + if(_saxi_rdata_cond_0_1) begin + saxi_rvalid <= 0; + end + if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid)) begin + saxi_rdata <= axislite_rdata_46; + saxi_rvalid <= 1; + end + _saxi_rdata_cond_0_1 <= 1; + if(saxi_rvalid && !saxi_rready) begin + saxi_rvalid <= saxi_rvalid; + end + end + end + + + always @(posedge CLK) begin + if(RST) begin + saxi_bvalid <= 0; + prev_awvalid_43 <= 0; + prev_arvalid_44 <= 0; + writevalid_41 <= 0; + readvalid_42 <= 0; + addr_40 <= 0; _saxi_register_0 <= 0; _saxi_flag_0 <= 0; _saxi_register_1 <= 0; @@ -2165,88 +2449,77 @@ _saxi_register_7 <= 0; _saxi_flag_7 <= 0; end else begin - if(_saxi_cond_0_1) begin - saxi_rvalid <= 0; - end if(saxi_bvalid && saxi_bready) begin saxi_bvalid <= 0; end if(saxi_wvalid && saxi_wready) begin saxi_bvalid <= 1; end - prev_awvalid_13 <= saxi_awvalid; - prev_arvalid_14 <= saxi_arvalid; - writevalid_11 <= 0; - readvalid_12 <= 0; + prev_awvalid_43 <= saxi_awvalid; + prev_arvalid_44 <= saxi_arvalid; + writevalid_41 <= 0; + readvalid_42 <= 0; if(saxi_awready && saxi_awvalid && !saxi_bvalid) begin - addr_10 <= saxi_awaddr; - writevalid_11 <= 1; + addr_40 <= saxi_awaddr; + writevalid_41 <= 1; end else if(saxi_arready && saxi_arvalid) begin - addr_10 <= saxi_araddr; - readvalid_12 <= 1; - end - if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid)) begin - saxi_rdata <= axislite_rdata_16; - saxi_rvalid <= 1; - end - _saxi_cond_0_1 <= 1; - if(saxi_rvalid && !saxi_rready) begin - saxi_rvalid <= saxi_rvalid; + addr_40 <= saxi_araddr; + readvalid_42 <= 1; end - if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_17 && (axis_maskaddr_15 == 0)) begin - _saxi_register_0 <= axislite_resetval_18; + if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_47 && (axis_maskaddr_45 == 0)) begin + _saxi_register_0 <= axislite_resetval_48; _saxi_flag_0 <= 0; end - if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_17 && (axis_maskaddr_15 == 1)) begin - _saxi_register_1 <= axislite_resetval_18; + if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_47 && (axis_maskaddr_45 == 1)) begin + _saxi_register_1 <= axislite_resetval_48; _saxi_flag_1 <= 0; end - if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_17 && (axis_maskaddr_15 == 2)) begin - _saxi_register_2 <= axislite_resetval_18; + if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_47 && (axis_maskaddr_45 == 2)) begin + _saxi_register_2 <= axislite_resetval_48; _saxi_flag_2 <= 0; end - if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_17 && (axis_maskaddr_15 == 3)) begin - _saxi_register_3 <= axislite_resetval_18; + if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_47 && (axis_maskaddr_45 == 3)) begin + _saxi_register_3 <= axislite_resetval_48; _saxi_flag_3 <= 0; end - if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_17 && (axis_maskaddr_15 == 4)) begin - _saxi_register_4 <= axislite_resetval_18; + if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_47 && (axis_maskaddr_45 == 4)) begin + _saxi_register_4 <= axislite_resetval_48; _saxi_flag_4 <= 0; end - if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_17 && (axis_maskaddr_15 == 5)) begin - _saxi_register_5 <= axislite_resetval_18; + if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_47 && (axis_maskaddr_45 == 5)) begin + _saxi_register_5 <= axislite_resetval_48; _saxi_flag_5 <= 0; end - if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_17 && (axis_maskaddr_15 == 6)) begin - _saxi_register_6 <= axislite_resetval_18; + if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_47 && (axis_maskaddr_45 == 6)) begin + _saxi_register_6 <= axislite_resetval_48; _saxi_flag_6 <= 0; end - if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_17 && (axis_maskaddr_15 == 7)) begin - _saxi_register_7 <= axislite_resetval_18; + if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_47 && (axis_maskaddr_45 == 7)) begin + _saxi_register_7 <= axislite_resetval_48; _saxi_flag_7 <= 0; end - if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_15 == 0)) begin + if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_45 == 0)) begin _saxi_register_0 <= saxi_wdata; end - if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_15 == 1)) begin + if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_45 == 1)) begin _saxi_register_1 <= saxi_wdata; end - if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_15 == 2)) begin + if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_45 == 2)) begin _saxi_register_2 <= saxi_wdata; end - if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_15 == 3)) begin + if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_45 == 3)) begin _saxi_register_3 <= saxi_wdata; end - if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_15 == 4)) begin + if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_45 == 4)) begin _saxi_register_4 <= saxi_wdata; end - if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_15 == 5)) begin + if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_45 == 5)) begin _saxi_register_5 <= saxi_wdata; end - if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_15 == 6)) begin + if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_45 == 6)) begin _saxi_register_6 <= saxi_wdata; end - if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_15 == 7)) begin + if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_45 == 7)) begin _saxi_register_7 <= saxi_wdata; end if((_saxi_register_0 == 1) && (th_memcpy == 2) && 1) begin @@ -2348,17 +2621,17 @@ always @(posedge CLK) begin if(RST) begin _saxi_register_fsm <= _saxi_register_fsm_init; - axis_maskaddr_15 <= 0; + axis_maskaddr_45 <= 0; end else begin case(_saxi_register_fsm) _saxi_register_fsm_init: begin - if(readvalid_12 || writevalid_11) begin - axis_maskaddr_15 <= (addr_10 >> _saxi_shift) & _saxi_mask; + if(readvalid_42 || writevalid_41) begin + axis_maskaddr_45 <= (addr_40 >> _saxi_shift) & _saxi_mask; end - if(readvalid_12) begin + if(readvalid_42) begin _saxi_register_fsm <= _saxi_register_fsm_1; end - if(writevalid_11) begin + if(writevalid_41) begin _saxi_register_fsm <= _saxi_register_fsm_3; end end @@ -2597,7 +2870,7 @@ _maxi_read_data_fsm <= _maxi_read_data_fsm_2; end _maxi_read_data_fsm_2: begin - if(maxi_rvalid && (_maxi_read_local_size_buf <= 1)) begin + if(_maxi_rvalid_sb_0 && (_maxi_read_local_size_buf <= 1)) begin _maxi_read_data_fsm <= _maxi_read_data_fsm_init; end end @@ -2610,37 +2883,37 @@ always @(posedge CLK) begin if(RST) begin write_burst_fsm_0 <= write_burst_fsm_0_init; - write_burst_addr_41 <= 0; - write_burst_stride_42 <= 0; - write_burst_length_43 <= 0; - write_burst_done_44 <= 0; + write_burst_addr_71 <= 0; + write_burst_stride_72 <= 0; + write_burst_length_73 <= 0; + write_burst_done_74 <= 0; end else begin case(write_burst_fsm_0) write_burst_fsm_0_init: begin - write_burst_addr_41 <= _maxi_read_local_addr_buf; - write_burst_stride_42 <= _maxi_read_local_stride_buf; - write_burst_length_43 <= _maxi_read_local_size_buf; - write_burst_done_44 <= 0; + write_burst_addr_71 <= _maxi_read_local_addr_buf; + write_burst_stride_72 <= _maxi_read_local_stride_buf; + write_burst_length_73 <= _maxi_read_local_size_buf; + write_burst_done_74 <= 0; if((_maxi_read_data_fsm == 1) && (_maxi_read_op_sel_buf == 1) && (_maxi_read_local_size_buf > 0)) begin write_burst_fsm_0 <= write_burst_fsm_0_1; end end write_burst_fsm_0_1: begin - if(maxi_rvalid) begin - write_burst_addr_41 <= write_burst_addr_41 + write_burst_stride_42; - write_burst_length_43 <= write_burst_length_43 - 1; - write_burst_done_44 <= 0; + if(_maxi_rvalid_sb_0) begin + write_burst_addr_71 <= write_burst_addr_71 + write_burst_stride_72; + write_burst_length_73 <= write_burst_length_73 - 1; + write_burst_done_74 <= 0; end - if(maxi_rvalid && (write_burst_length_43 <= 1)) begin - write_burst_done_44 <= 1; + if(_maxi_rvalid_sb_0 && (write_burst_length_73 <= 1)) begin + write_burst_done_74 <= 1; end - if(maxi_rvalid && 0) begin - write_burst_done_44 <= 1; + if(_maxi_rvalid_sb_0 && 0) begin + write_burst_done_74 <= 1; end - if(maxi_rvalid && (write_burst_length_43 <= 1)) begin + if(_maxi_rvalid_sb_0 && (write_burst_length_73 <= 1)) begin write_burst_fsm_0 <= write_burst_fsm_0_init; end - if(maxi_rvalid && 0) begin + if(_maxi_rvalid_sb_0 && 0) begin write_burst_fsm_0 <= write_burst_fsm_0_init; end if(0) begin @@ -2696,7 +2969,7 @@ _maxi_write_data_fsm <= _maxi_write_data_fsm_2; end _maxi_write_data_fsm_2: begin - if((_maxi_write_op_sel_buf == 1) && read_burst_rvalid_78 && ((maxi_wready || !maxi_wvalid) && (_maxi_write_size_buf > 0)) && read_burst_rlast_79) begin + if((_maxi_write_op_sel_buf == 1) && read_burst_rvalid_108 && ((_maxi_wready_sb_0 || !_maxi_wvalid_sb_0) && (_maxi_write_size_buf > 0)) && read_burst_rlast_109) begin _maxi_write_data_fsm <= _maxi_write_data_fsm_init; end end @@ -2709,41 +2982,41 @@ always @(posedge CLK) begin if(RST) begin read_burst_fsm_1 <= read_burst_fsm_1_init; - read_burst_addr_75 <= 0; - read_burst_stride_76 <= 0; - read_burst_length_77 <= 0; - read_burst_rvalid_78 <= 0; - read_burst_rlast_79 <= 0; + read_burst_addr_105 <= 0; + read_burst_stride_106 <= 0; + read_burst_length_107 <= 0; + read_burst_rvalid_108 <= 0; + read_burst_rlast_109 <= 0; end else begin case(read_burst_fsm_1) read_burst_fsm_1_init: begin - read_burst_addr_75 <= _maxi_write_local_addr_buf; - read_burst_stride_76 <= _maxi_write_local_stride_buf; - read_burst_length_77 <= _maxi_write_size_buf; - read_burst_rvalid_78 <= 0; - read_burst_rlast_79 <= 0; + read_burst_addr_105 <= _maxi_write_local_addr_buf; + read_burst_stride_106 <= _maxi_write_local_stride_buf; + read_burst_length_107 <= _maxi_write_size_buf; + read_burst_rvalid_108 <= 0; + read_burst_rlast_109 <= 0; if((_maxi_write_data_fsm == 1) && (_maxi_write_op_sel_buf == 1) && (_maxi_write_size_buf > 0)) begin read_burst_fsm_1 <= read_burst_fsm_1_1; end end read_burst_fsm_1_1: begin - if((maxi_wready || !maxi_wvalid) && (_maxi_write_size_buf > 0) && (read_burst_length_77 > 0)) begin - read_burst_addr_75 <= read_burst_addr_75 + read_burst_stride_76; - read_burst_length_77 <= read_burst_length_77 - 1; - read_burst_rvalid_78 <= 1; + if((_maxi_wready_sb_0 || !_maxi_wvalid_sb_0) && (_maxi_write_size_buf > 0) && (read_burst_length_107 > 0)) begin + read_burst_addr_105 <= read_burst_addr_105 + read_burst_stride_106; + read_burst_length_107 <= read_burst_length_107 - 1; + read_burst_rvalid_108 <= 1; end - if((maxi_wready || !maxi_wvalid) && (_maxi_write_size_buf > 0) && (read_burst_length_77 <= 1)) begin - read_burst_rlast_79 <= 1; + if((_maxi_wready_sb_0 || !_maxi_wvalid_sb_0) && (_maxi_write_size_buf > 0) && (read_burst_length_107 <= 1)) begin + read_burst_rlast_109 <= 1; end - if(read_burst_rlast_79 && read_burst_rvalid_78 && ((maxi_wready || !maxi_wvalid) && (_maxi_write_size_buf > 0))) begin - read_burst_rvalid_78 <= 0; - read_burst_rlast_79 <= 0; + if(read_burst_rlast_109 && read_burst_rvalid_108 && ((_maxi_wready_sb_0 || !_maxi_wvalid_sb_0) && (_maxi_write_size_buf > 0))) begin + read_burst_rvalid_108 <= 0; + read_burst_rlast_109 <= 0; end if(0) begin - read_burst_rvalid_78 <= 0; - read_burst_rlast_79 <= 0; + read_burst_rvalid_108 <= 0; + read_burst_rlast_109 <= 0; end - if(read_burst_rlast_79 && read_burst_rvalid_78 && ((maxi_wready || !maxi_wvalid) && (_maxi_write_size_buf > 0))) begin + if(read_burst_rlast_109 && read_burst_rvalid_108 && ((_maxi_wready_sb_0 || !_maxi_wvalid_sb_0) && (_maxi_write_size_buf > 0))) begin read_burst_fsm_1 <= read_burst_fsm_1_init; end if(0) begin diff --git a/examples/thread_memcpy_ipxact_ultra96v2_pynq/ultra96v2_pynq/run_on_pynq.py b/examples/thread_memcpy_ipxact_ultra96v2_pynq/ultra96v2_pynq/run_on_pynq.py index 76733e58..c3162d21 100644 --- a/examples/thread_memcpy_ipxact_ultra96v2_pynq/ultra96v2_pynq/run_on_pynq.py +++ b/examples/thread_memcpy_ipxact_ultra96v2_pynq/ultra96v2_pynq/run_on_pynq.py @@ -80,4 +80,3 @@ diff_sum = np.sum(expected - b) print(diff_sum) - diff --git a/examples/thread_multithread_top_nexys4/thread_multithread_top.py b/examples/thread_multithread_top_nexys4/thread_multithread_top.py index 9d0c7fac..6a4aaba0 100644 --- a/examples/thread_multithread_top_nexys4/thread_multithread_top.py +++ b/examples/thread_multithread_top_nexys4/thread_multithread_top.py @@ -167,6 +167,7 @@ def test(): return m + if __name__ == '__main__': test = mkTest() verilog = test.to_verilog('tmp.v') diff --git a/examples/thread_uart_top_nexys4/test_thread_uart_top.py b/examples/thread_uart_top_nexys4/test_thread_uart_top.py index 04d2b7f4..8b480d05 100644 --- a/examples/thread_uart_top_nexys4/test_thread_uart_top.py +++ b/examples/thread_uart_top_nexys4/test_thread_uart_top.py @@ -12,5 +12,5 @@ def test(request): rslt = thread_uart_top.run(filename=None, simtype=simtype) - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/examples/thread_uart_top_nexys4/thread_uart_top.py b/examples/thread_uart_top_nexys4/thread_uart_top.py index 90adcbc2..e2a556c7 100644 --- a/examples/thread_uart_top_nexys4/thread_uart_top.py +++ b/examples/thread_uart_top_nexys4/thread_uart_top.py @@ -142,9 +142,7 @@ def run(filename='tmp.v', simtype='iverilog'): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run() - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/examples/thread_verilog_submodule_ipxact/test_thread_verilog_submodule_ipxact.py b/examples/thread_verilog_submodule_ipxact/test_thread_verilog_submodule_ipxact.py index 6b41b127..3bea9909 100644 --- a/examples/thread_verilog_submodule_ipxact/test_thread_verilog_submodule_ipxact.py +++ b/examples/thread_verilog_submodule_ipxact/test_thread_verilog_submodule_ipxact.py @@ -149,6 +149,7 @@ wire [2-1:0] memory_bresp; reg memory_bvalid; wire memory_bready; + assign memory_bresp = 0; wire [32-1:0] memory_araddr; wire [8-1:0] memory_arlen; wire [3-1:0] memory_arsize; @@ -165,7 +166,6 @@ reg memory_rlast; reg memory_rvalid; wire memory_rready; - assign memory_bresp = 0; assign memory_rresp = 0; reg [32-1:0] _memory_waddr_fsm; localparam _memory_waddr_fsm_init = 0; @@ -418,127 +418,185 @@ wire [3-1:0] _saxi_awprot; reg _saxi_awvalid; wire _saxi_awready; - reg [32-1:0] _saxi_wdata; - reg [4-1:0] _saxi_wstrb; - reg _saxi_wvalid; + assign _saxi_awcache = 3; + assign _saxi_awprot = 0; + wire [32-1:0] _saxi_wdata; + wire [4-1:0] _saxi_wstrb; + wire _saxi_wvalid; wire _saxi_wready; + reg [32-1:0] __saxi_wdata_sb_0; + reg [4-1:0] __saxi_wstrb_sb_0; + reg __saxi_wvalid_sb_0; + wire __saxi_wready_sb_0; + wire [4-1:0] _sb__saxi_writedata_s_value_34; + assign _sb__saxi_writedata_s_value_34 = __saxi_wstrb_sb_0; + wire [32-1:0] _sb__saxi_writedata_s_value_35; + assign _sb__saxi_writedata_s_value_35 = __saxi_wdata_sb_0; + wire [36-1:0] _sb__saxi_writedata_s_data_36; + assign _sb__saxi_writedata_s_data_36 = { _sb__saxi_writedata_s_value_34, _sb__saxi_writedata_s_value_35 }; + wire _sb__saxi_writedata_s_valid_37; + assign _sb__saxi_writedata_s_valid_37 = __saxi_wvalid_sb_0; + wire _sb__saxi_writedata_m_ready_38; + assign _sb__saxi_writedata_m_ready_38 = _saxi_wready; + reg [36-1:0] _sb__saxi_writedata_data_39; + reg _sb__saxi_writedata_valid_40; + wire _sb__saxi_writedata_ready_41; + reg [36-1:0] _sb__saxi_writedata_tmp_data_42; + reg _sb__saxi_writedata_tmp_valid_43; + wire [36-1:0] _sb__saxi_writedata_next_data_44; + wire _sb__saxi_writedata_next_valid_45; + assign _sb__saxi_writedata_ready_41 = !_sb__saxi_writedata_tmp_valid_43; + assign _sb__saxi_writedata_next_data_44 = (_sb__saxi_writedata_tmp_valid_43)? _sb__saxi_writedata_tmp_data_42 : _sb__saxi_writedata_s_data_36; + assign _sb__saxi_writedata_next_valid_45 = _sb__saxi_writedata_tmp_valid_43 || _sb__saxi_writedata_s_valid_37; + wire [4-1:0] _sb__saxi_writedata_m_value_46; + assign _sb__saxi_writedata_m_value_46 = _sb__saxi_writedata_data_39[35:32]; + wire [32-1:0] _sb__saxi_writedata_m_value_47; + assign _sb__saxi_writedata_m_value_47 = _sb__saxi_writedata_data_39[31:0]; + assign __saxi_wready_sb_0 = _sb__saxi_writedata_ready_41; + assign _saxi_wdata = _sb__saxi_writedata_m_value_47; + assign _saxi_wstrb = _sb__saxi_writedata_m_value_46; + assign _saxi_wvalid = _sb__saxi_writedata_valid_40; wire [2-1:0] _saxi_bresp; wire _saxi_bvalid; wire _saxi_bready; + assign _saxi_bready = 1; reg [32-1:0] _saxi_araddr; wire [4-1:0] _saxi_arcache; wire [3-1:0] _saxi_arprot; reg _saxi_arvalid; wire _saxi_arready; + assign _saxi_arcache = 3; + assign _saxi_arprot = 0; wire [32-1:0] _saxi_rdata; wire [2-1:0] _saxi_rresp; wire _saxi_rvalid; wire _saxi_rready; - assign _saxi_awcache = 3; - assign _saxi_awprot = 0; - assign _saxi_bready = 1; - assign _saxi_arcache = 3; - assign _saxi_arprot = 0; + wire [32-1:0] __saxi_rdata_sb_0; + wire __saxi_rvalid_sb_0; + wire __saxi_rready_sb_0; + wire [32-1:0] _sb__saxi_readdata_s_value_48; + assign _sb__saxi_readdata_s_value_48 = _saxi_rdata; + wire [32-1:0] _sb__saxi_readdata_s_data_49; + assign _sb__saxi_readdata_s_data_49 = { _sb__saxi_readdata_s_value_48 }; + wire _sb__saxi_readdata_s_valid_50; + assign _sb__saxi_readdata_s_valid_50 = _saxi_rvalid; + wire _sb__saxi_readdata_m_ready_51; + assign _sb__saxi_readdata_m_ready_51 = __saxi_rready_sb_0; + reg [32-1:0] _sb__saxi_readdata_data_52; + reg _sb__saxi_readdata_valid_53; + wire _sb__saxi_readdata_ready_54; + reg [32-1:0] _sb__saxi_readdata_tmp_data_55; + reg _sb__saxi_readdata_tmp_valid_56; + wire [32-1:0] _sb__saxi_readdata_next_data_57; + wire _sb__saxi_readdata_next_valid_58; + assign _sb__saxi_readdata_ready_54 = !_sb__saxi_readdata_tmp_valid_56; + assign _sb__saxi_readdata_next_data_57 = (_sb__saxi_readdata_tmp_valid_56)? _sb__saxi_readdata_tmp_data_55 : _sb__saxi_readdata_s_data_49; + assign _sb__saxi_readdata_next_valid_58 = _sb__saxi_readdata_tmp_valid_56 || _sb__saxi_readdata_s_valid_50; + wire [32-1:0] _sb__saxi_readdata_m_value_59; + assign _sb__saxi_readdata_m_value_59 = _sb__saxi_readdata_data_52[31:0]; + assign __saxi_rdata_sb_0 = _sb__saxi_readdata_m_value_59; + assign __saxi_rvalid_sb_0 = _sb__saxi_readdata_valid_53; + assign _saxi_rready = _sb__saxi_readdata_ready_54; reg [3-1:0] __saxi_outstanding_wcount; wire __saxi_has_outstanding_write; assign __saxi_has_outstanding_write = (__saxi_outstanding_wcount > 0) || _saxi_awvalid; - wire [32-1:0] _tmp_34; - assign _tmp_34 = _saxi_awaddr; + wire [32-1:0] _tmp_60; + assign _tmp_60 = _saxi_awaddr; always @(*) begin - uut_saxi_awaddr = _tmp_34; + uut_saxi_awaddr = _tmp_60; end - wire [4-1:0] _tmp_35; - assign _tmp_35 = _saxi_awcache; + wire [4-1:0] _tmp_61; + assign _tmp_61 = _saxi_awcache; always @(*) begin - uut_saxi_awcache = _tmp_35; + uut_saxi_awcache = _tmp_61; end - wire [3-1:0] _tmp_36; - assign _tmp_36 = _saxi_awprot; + wire [3-1:0] _tmp_62; + assign _tmp_62 = _saxi_awprot; always @(*) begin - uut_saxi_awprot = _tmp_36; + uut_saxi_awprot = _tmp_62; end - wire _tmp_37; - assign _tmp_37 = _saxi_awvalid; + wire _tmp_63; + assign _tmp_63 = _saxi_awvalid; always @(*) begin - uut_saxi_awvalid = _tmp_37; + uut_saxi_awvalid = _tmp_63; end assign _saxi_awready = uut_saxi_awready; - wire [32-1:0] _tmp_38; - assign _tmp_38 = _saxi_wdata; + wire [32-1:0] _tmp_64; + assign _tmp_64 = _saxi_wdata; always @(*) begin - uut_saxi_wdata = _tmp_38; + uut_saxi_wdata = _tmp_64; end - wire [4-1:0] _tmp_39; - assign _tmp_39 = _saxi_wstrb; + wire [4-1:0] _tmp_65; + assign _tmp_65 = _saxi_wstrb; always @(*) begin - uut_saxi_wstrb = _tmp_39; + uut_saxi_wstrb = _tmp_65; end - wire _tmp_40; - assign _tmp_40 = _saxi_wvalid; + wire _tmp_66; + assign _tmp_66 = _saxi_wvalid; always @(*) begin - uut_saxi_wvalid = _tmp_40; + uut_saxi_wvalid = _tmp_66; end assign _saxi_wready = uut_saxi_wready; assign _saxi_bresp = uut_saxi_bresp; assign _saxi_bvalid = uut_saxi_bvalid; - wire _tmp_41; - assign _tmp_41 = _saxi_bready; + wire _tmp_67; + assign _tmp_67 = _saxi_bready; always @(*) begin - uut_saxi_bready = _tmp_41; + uut_saxi_bready = _tmp_67; end - wire [32-1:0] _tmp_42; - assign _tmp_42 = _saxi_araddr; + wire [32-1:0] _tmp_68; + assign _tmp_68 = _saxi_araddr; always @(*) begin - uut_saxi_araddr = _tmp_42; + uut_saxi_araddr = _tmp_68; end - wire [4-1:0] _tmp_43; - assign _tmp_43 = _saxi_arcache; + wire [4-1:0] _tmp_69; + assign _tmp_69 = _saxi_arcache; always @(*) begin - uut_saxi_arcache = _tmp_43; + uut_saxi_arcache = _tmp_69; end - wire [3-1:0] _tmp_44; - assign _tmp_44 = _saxi_arprot; + wire [3-1:0] _tmp_70; + assign _tmp_70 = _saxi_arprot; always @(*) begin - uut_saxi_arprot = _tmp_44; + uut_saxi_arprot = _tmp_70; end - wire _tmp_45; - assign _tmp_45 = _saxi_arvalid; + wire _tmp_71; + assign _tmp_71 = _saxi_arvalid; always @(*) begin - uut_saxi_arvalid = _tmp_45; + uut_saxi_arvalid = _tmp_71; end assign _saxi_arready = uut_saxi_arready; assign _saxi_rdata = uut_saxi_rdata; assign _saxi_rresp = uut_saxi_rresp; assign _saxi_rvalid = uut_saxi_rvalid; - wire _tmp_46; - assign _tmp_46 = _saxi_rready; + wire _tmp_72; + assign _tmp_72 = _saxi_rready; always @(*) begin - uut_saxi_rready = _tmp_46; + uut_saxi_rready = _tmp_72; end reg [32-1:0] counter; @@ -546,21 +604,21 @@ localparam th_ctrl_init = 0; reg signed [32-1:0] _th_ctrl_i_12; reg signed [32-1:0] _th_ctrl_awaddr_13; - reg __saxi_cond_0_1; - reg __saxi_cond_1_1; + reg __saxi_waddr_cond_0_1; + reg __saxi_wdata_cond_0_1; reg signed [32-1:0] _th_ctrl_src_offset_14; - reg __saxi_cond_2_1; - reg __saxi_cond_3_1; + reg __saxi_waddr_cond_1_1; + reg __saxi_wdata_cond_1_1; reg signed [32-1:0] _th_ctrl_dst_offset_15; - reg __saxi_cond_4_1; - reg __saxi_cond_5_1; + reg __saxi_waddr_cond_2_1; + reg __saxi_wdata_cond_2_1; reg signed [32-1:0] _th_ctrl_start_time_16; - reg __saxi_cond_6_1; - reg __saxi_cond_7_1; + reg __saxi_waddr_cond_3_1; + reg __saxi_wdata_cond_3_1; reg signed [32-1:0] _th_ctrl_araddr_17; - reg __saxi_cond_8_1; - reg signed [32-1:0] axim_rdata_47; - assign _saxi_rready = th_ctrl == 39; + reg __saxi_raddr_cond_0_1; + reg signed [32-1:0] axim_rdata_73; + assign __saxi_rready_sb_0 = th_ctrl == 39; reg signed [32-1:0] _th_ctrl_busy_18; reg signed [32-1:0] _th_ctrl_end_time_19; reg signed [32-1:0] _th_ctrl_time_20; @@ -607,30 +665,38 @@ __memory_rdata_fsm_cond_11_0_1 = 0; _saxi_awaddr = 0; _saxi_awvalid = 0; - _saxi_wdata = 0; - _saxi_wstrb = 0; - _saxi_wvalid = 0; + __saxi_wdata_sb_0 = 0; + __saxi_wstrb_sb_0 = 0; + __saxi_wvalid_sb_0 = 0; + _sb__saxi_writedata_data_39 = 0; + _sb__saxi_writedata_valid_40 = 0; + _sb__saxi_writedata_tmp_data_42 = 0; + _sb__saxi_writedata_tmp_valid_43 = 0; _saxi_araddr = 0; _saxi_arvalid = 0; + _sb__saxi_readdata_data_52 = 0; + _sb__saxi_readdata_valid_53 = 0; + _sb__saxi_readdata_tmp_data_55 = 0; + _sb__saxi_readdata_tmp_valid_56 = 0; __saxi_outstanding_wcount = 0; counter = 0; th_ctrl = th_ctrl_init; _th_ctrl_i_12 = 0; _th_ctrl_awaddr_13 = 0; - __saxi_cond_0_1 = 0; - __saxi_cond_1_1 = 0; + __saxi_waddr_cond_0_1 = 0; + __saxi_wdata_cond_0_1 = 0; _th_ctrl_src_offset_14 = 0; - __saxi_cond_2_1 = 0; - __saxi_cond_3_1 = 0; + __saxi_waddr_cond_1_1 = 0; + __saxi_wdata_cond_1_1 = 0; _th_ctrl_dst_offset_15 = 0; - __saxi_cond_4_1 = 0; - __saxi_cond_5_1 = 0; + __saxi_waddr_cond_2_1 = 0; + __saxi_wdata_cond_2_1 = 0; _th_ctrl_start_time_16 = 0; - __saxi_cond_6_1 = 0; - __saxi_cond_7_1 = 0; + __saxi_waddr_cond_3_1 = 0; + __saxi_wdata_cond_3_1 = 0; _th_ctrl_araddr_17 = 0; - __saxi_cond_8_1 = 0; - axim_rdata_47 = 0; + __saxi_raddr_cond_0_1 = 0; + axim_rdata_73 = 0; _th_ctrl_busy_18 = 0; _th_ctrl_end_time_19 = 0; _th_ctrl_time_20 = 0; @@ -986,130 +1052,159 @@ always @(posedge uut_CLK) begin if(uut_RST) begin - __saxi_outstanding_wcount <= 0; _saxi_awaddr <= 0; _saxi_awvalid <= 0; - __saxi_cond_0_1 <= 0; - _saxi_wdata <= 0; - _saxi_wvalid <= 0; - _saxi_wstrb <= 0; - __saxi_cond_1_1 <= 0; - __saxi_cond_2_1 <= 0; - __saxi_cond_3_1 <= 0; - __saxi_cond_4_1 <= 0; - __saxi_cond_5_1 <= 0; - __saxi_cond_6_1 <= 0; - __saxi_cond_7_1 <= 0; - _saxi_araddr <= 0; - _saxi_arvalid <= 0; - __saxi_cond_8_1 <= 0; + __saxi_waddr_cond_0_1 <= 0; + __saxi_waddr_cond_1_1 <= 0; + __saxi_waddr_cond_2_1 <= 0; + __saxi_waddr_cond_3_1 <= 0; end else begin - if(__saxi_cond_0_1) begin + if(__saxi_waddr_cond_0_1) begin _saxi_awvalid <= 0; end - if(__saxi_cond_1_1) begin - _saxi_wvalid <= 0; - end - if(__saxi_cond_2_1) begin + if(__saxi_waddr_cond_1_1) begin _saxi_awvalid <= 0; end - if(__saxi_cond_3_1) begin - _saxi_wvalid <= 0; - end - if(__saxi_cond_4_1) begin + if(__saxi_waddr_cond_2_1) begin _saxi_awvalid <= 0; end - if(__saxi_cond_5_1) begin - _saxi_wvalid <= 0; - end - if(__saxi_cond_6_1) begin + if(__saxi_waddr_cond_3_1) begin _saxi_awvalid <= 0; end - if(__saxi_cond_7_1) begin - _saxi_wvalid <= 0; - end - if(__saxi_cond_8_1) begin - _saxi_arvalid <= 0; - end - if(_saxi_awvalid && _saxi_awready && !(_saxi_bvalid && _saxi_bready) && (__saxi_outstanding_wcount < 7)) begin - __saxi_outstanding_wcount <= __saxi_outstanding_wcount + 1; - end - if(!(_saxi_awvalid && _saxi_awready) && (_saxi_bvalid && _saxi_bready) && (__saxi_outstanding_wcount > 0)) begin - __saxi_outstanding_wcount <= __saxi_outstanding_wcount - 1; - end if((th_ctrl == 6) && ((__saxi_outstanding_wcount == 0) && (_saxi_awready || !_saxi_awvalid))) begin _saxi_awaddr <= _th_ctrl_awaddr_13; _saxi_awvalid <= 1; end - __saxi_cond_0_1 <= 1; + __saxi_waddr_cond_0_1 <= 1; if(_saxi_awvalid && !_saxi_awready) begin _saxi_awvalid <= _saxi_awvalid; end - if((th_ctrl == 8) && (_saxi_wready || !_saxi_wvalid)) begin - _saxi_wdata <= 4096; - _saxi_wvalid <= 1; - _saxi_wstrb <= { 4{ 1'd1 } }; - end - __saxi_cond_1_1 <= 1; - if(_saxi_wvalid && !_saxi_wready) begin - _saxi_wvalid <= _saxi_wvalid; - end if((th_ctrl == 14) && ((__saxi_outstanding_wcount == 0) && (_saxi_awready || !_saxi_awvalid))) begin _saxi_awaddr <= _th_ctrl_awaddr_13; _saxi_awvalid <= 1; end - __saxi_cond_2_1 <= 1; + __saxi_waddr_cond_1_1 <= 1; if(_saxi_awvalid && !_saxi_awready) begin _saxi_awvalid <= _saxi_awvalid; end - if((th_ctrl == 16) && (_saxi_wready || !_saxi_wvalid)) begin - _saxi_wdata <= _th_ctrl_src_offset_14; - _saxi_wvalid <= 1; - _saxi_wstrb <= { 4{ 1'd1 } }; - end - __saxi_cond_3_1 <= 1; - if(_saxi_wvalid && !_saxi_wready) begin - _saxi_wvalid <= _saxi_wvalid; - end if((th_ctrl == 22) && ((__saxi_outstanding_wcount == 0) && (_saxi_awready || !_saxi_awvalid))) begin _saxi_awaddr <= _th_ctrl_awaddr_13; _saxi_awvalid <= 1; end - __saxi_cond_4_1 <= 1; + __saxi_waddr_cond_2_1 <= 1; if(_saxi_awvalid && !_saxi_awready) begin _saxi_awvalid <= _saxi_awvalid; end - if((th_ctrl == 24) && (_saxi_wready || !_saxi_wvalid)) begin - _saxi_wdata <= _th_ctrl_dst_offset_15; - _saxi_wvalid <= 1; - _saxi_wstrb <= { 4{ 1'd1 } }; - end - __saxi_cond_5_1 <= 1; - if(_saxi_wvalid && !_saxi_wready) begin - _saxi_wvalid <= _saxi_wvalid; - end if((th_ctrl == 30) && ((__saxi_outstanding_wcount == 0) && (_saxi_awready || !_saxi_awvalid))) begin _saxi_awaddr <= _th_ctrl_awaddr_13; _saxi_awvalid <= 1; end - __saxi_cond_6_1 <= 1; + __saxi_waddr_cond_3_1 <= 1; if(_saxi_awvalid && !_saxi_awready) begin _saxi_awvalid <= _saxi_awvalid; end - if((th_ctrl == 32) && (_saxi_wready || !_saxi_wvalid)) begin - _saxi_wdata <= 1; - _saxi_wvalid <= 1; - _saxi_wstrb <= { 4{ 1'd1 } }; + end + end + + + always @(posedge uut_CLK) begin + if(uut_RST) begin + __saxi_wdata_sb_0 <= 0; + __saxi_wvalid_sb_0 <= 0; + __saxi_wstrb_sb_0 <= 0; + __saxi_wdata_cond_0_1 <= 0; + __saxi_wdata_cond_1_1 <= 0; + __saxi_wdata_cond_2_1 <= 0; + __saxi_wdata_cond_3_1 <= 0; + end else begin + if(__saxi_wdata_cond_0_1) begin + __saxi_wvalid_sb_0 <= 0; + end + if(__saxi_wdata_cond_1_1) begin + __saxi_wvalid_sb_0 <= 0; + end + if(__saxi_wdata_cond_2_1) begin + __saxi_wvalid_sb_0 <= 0; + end + if(__saxi_wdata_cond_3_1) begin + __saxi_wvalid_sb_0 <= 0; + end + if((th_ctrl == 8) && (__saxi_wready_sb_0 || !__saxi_wvalid_sb_0)) begin + __saxi_wdata_sb_0 <= 4096; + __saxi_wvalid_sb_0 <= 1; + __saxi_wstrb_sb_0 <= { 4{ 1'd1 } }; + end + __saxi_wdata_cond_0_1 <= 1; + if(__saxi_wvalid_sb_0 && !__saxi_wready_sb_0) begin + __saxi_wvalid_sb_0 <= __saxi_wvalid_sb_0; + end + if((th_ctrl == 16) && (__saxi_wready_sb_0 || !__saxi_wvalid_sb_0)) begin + __saxi_wdata_sb_0 <= _th_ctrl_src_offset_14; + __saxi_wvalid_sb_0 <= 1; + __saxi_wstrb_sb_0 <= { 4{ 1'd1 } }; + end + __saxi_wdata_cond_1_1 <= 1; + if(__saxi_wvalid_sb_0 && !__saxi_wready_sb_0) begin + __saxi_wvalid_sb_0 <= __saxi_wvalid_sb_0; end - __saxi_cond_7_1 <= 1; - if(_saxi_wvalid && !_saxi_wready) begin - _saxi_wvalid <= _saxi_wvalid; + if((th_ctrl == 24) && (__saxi_wready_sb_0 || !__saxi_wvalid_sb_0)) begin + __saxi_wdata_sb_0 <= _th_ctrl_dst_offset_15; + __saxi_wvalid_sb_0 <= 1; + __saxi_wstrb_sb_0 <= { 4{ 1'd1 } }; + end + __saxi_wdata_cond_2_1 <= 1; + if(__saxi_wvalid_sb_0 && !__saxi_wready_sb_0) begin + __saxi_wvalid_sb_0 <= __saxi_wvalid_sb_0; + end + if((th_ctrl == 32) && (__saxi_wready_sb_0 || !__saxi_wvalid_sb_0)) begin + __saxi_wdata_sb_0 <= 1; + __saxi_wvalid_sb_0 <= 1; + __saxi_wstrb_sb_0 <= { 4{ 1'd1 } }; + end + __saxi_wdata_cond_3_1 <= 1; + if(__saxi_wvalid_sb_0 && !__saxi_wready_sb_0) begin + __saxi_wvalid_sb_0 <= __saxi_wvalid_sb_0; + end + end + end + + + always @(posedge uut_CLK) begin + if(uut_RST) begin + _sb__saxi_writedata_data_39 <= 0; + _sb__saxi_writedata_valid_40 <= 0; + _sb__saxi_writedata_tmp_data_42 <= 0; + _sb__saxi_writedata_tmp_valid_43 <= 0; + end else begin + if(_sb__saxi_writedata_m_ready_38 || !_sb__saxi_writedata_valid_40) begin + _sb__saxi_writedata_data_39 <= _sb__saxi_writedata_next_data_44; + _sb__saxi_writedata_valid_40 <= _sb__saxi_writedata_next_valid_45; + end + if(!_sb__saxi_writedata_tmp_valid_43 && _sb__saxi_writedata_valid_40 && !_sb__saxi_writedata_m_ready_38) begin + _sb__saxi_writedata_tmp_data_42 <= _sb__saxi_writedata_s_data_36; + _sb__saxi_writedata_tmp_valid_43 <= _sb__saxi_writedata_s_valid_37; + end + if(_sb__saxi_writedata_tmp_valid_43 && _sb__saxi_writedata_m_ready_38) begin + _sb__saxi_writedata_tmp_valid_43 <= 0; + end + end + end + + + always @(posedge uut_CLK) begin + if(uut_RST) begin + _saxi_araddr <= 0; + _saxi_arvalid <= 0; + __saxi_raddr_cond_0_1 <= 0; + end else begin + if(__saxi_raddr_cond_0_1) begin + _saxi_arvalid <= 0; end if((th_ctrl == 37) && (_saxi_arready || !_saxi_arvalid)) begin _saxi_araddr <= _th_ctrl_araddr_17; _saxi_arvalid <= 1; end - __saxi_cond_8_1 <= 1; + __saxi_raddr_cond_0_1 <= 1; if(_saxi_arvalid && !_saxi_arready) begin _saxi_arvalid <= _saxi_arvalid; end @@ -1117,6 +1212,42 @@ end + always @(posedge uut_CLK) begin + if(uut_RST) begin + _sb__saxi_readdata_data_52 <= 0; + _sb__saxi_readdata_valid_53 <= 0; + _sb__saxi_readdata_tmp_data_55 <= 0; + _sb__saxi_readdata_tmp_valid_56 <= 0; + end else begin + if(_sb__saxi_readdata_m_ready_51 || !_sb__saxi_readdata_valid_53) begin + _sb__saxi_readdata_data_52 <= _sb__saxi_readdata_next_data_57; + _sb__saxi_readdata_valid_53 <= _sb__saxi_readdata_next_valid_58; + end + if(!_sb__saxi_readdata_tmp_valid_56 && _sb__saxi_readdata_valid_53 && !_sb__saxi_readdata_m_ready_51) begin + _sb__saxi_readdata_tmp_data_55 <= _sb__saxi_readdata_s_data_49; + _sb__saxi_readdata_tmp_valid_56 <= _sb__saxi_readdata_s_valid_50; + end + if(_sb__saxi_readdata_tmp_valid_56 && _sb__saxi_readdata_m_ready_51) begin + _sb__saxi_readdata_tmp_valid_56 <= 0; + end + end + end + + + always @(posedge uut_CLK) begin + if(uut_RST) begin + __saxi_outstanding_wcount <= 0; + end else begin + if(_saxi_awvalid && _saxi_awready && !(_saxi_bvalid && _saxi_bready) && (__saxi_outstanding_wcount < 7)) begin + __saxi_outstanding_wcount <= __saxi_outstanding_wcount + 1; + end + if(!(_saxi_awvalid && _saxi_awready) && (_saxi_bvalid && _saxi_bready) && (__saxi_outstanding_wcount > 0)) begin + __saxi_outstanding_wcount <= __saxi_outstanding_wcount - 1; + end + end + end + + always @(posedge uut_CLK) begin if(uut_RST) begin counter <= 0; @@ -1183,7 +1314,7 @@ _th_ctrl_dst_offset_15 <= 0; _th_ctrl_start_time_16 <= 0; _th_ctrl_araddr_17 <= 0; - axim_rdata_47 <= 0; + axim_rdata_73 <= 0; _th_ctrl_busy_18 <= 0; _th_ctrl_end_time_19 <= 0; _th_ctrl_time_20 <= 0; @@ -1226,12 +1357,12 @@ end end th_ctrl_8: begin - if(_saxi_wready || !_saxi_wvalid) begin + if(__saxi_wready_sb_0 || !__saxi_wvalid_sb_0) begin th_ctrl <= th_ctrl_9; end end th_ctrl_9: begin - if(_saxi_wvalid && _saxi_wready) begin + if(__saxi_wvalid_sb_0 && __saxi_wready_sb_0) begin th_ctrl <= th_ctrl_10; end end @@ -1263,12 +1394,12 @@ end end th_ctrl_16: begin - if(_saxi_wready || !_saxi_wvalid) begin + if(__saxi_wready_sb_0 || !__saxi_wvalid_sb_0) begin th_ctrl <= th_ctrl_17; end end th_ctrl_17: begin - if(_saxi_wvalid && _saxi_wready) begin + if(__saxi_wvalid_sb_0 && __saxi_wready_sb_0) begin th_ctrl <= th_ctrl_18; end end @@ -1300,12 +1431,12 @@ end end th_ctrl_24: begin - if(_saxi_wready || !_saxi_wvalid) begin + if(__saxi_wready_sb_0 || !__saxi_wvalid_sb_0) begin th_ctrl <= th_ctrl_25; end end th_ctrl_25: begin - if(_saxi_wvalid && _saxi_wready) begin + if(__saxi_wvalid_sb_0 && __saxi_wready_sb_0) begin th_ctrl <= th_ctrl_26; end end @@ -1337,12 +1468,12 @@ end end th_ctrl_32: begin - if(_saxi_wready || !_saxi_wvalid) begin + if(__saxi_wready_sb_0 || !__saxi_wvalid_sb_0) begin th_ctrl <= th_ctrl_33; end end th_ctrl_33: begin - if(_saxi_wvalid && _saxi_wready) begin + if(__saxi_wvalid_sb_0 && __saxi_wready_sb_0) begin th_ctrl <= th_ctrl_34; end end @@ -1373,15 +1504,15 @@ end end th_ctrl_39: begin - if(_saxi_rvalid) begin - axim_rdata_47 <= _saxi_rdata; + if(__saxi_rvalid_sb_0) begin + axim_rdata_73 <= __saxi_rdata_sb_0; end - if(_saxi_rvalid) begin + if(__saxi_rvalid_sb_0) begin th_ctrl <= th_ctrl_40; end end th_ctrl_40: begin - _th_ctrl_busy_18 <= axim_rdata_47; + _th_ctrl_busy_18 <= axim_rdata_73; th_ctrl <= th_ctrl_41; end th_ctrl_41: begin @@ -1438,10 +1569,10 @@ output [2-1:0] maxi_awuser, output reg maxi_awvalid, input maxi_awready, - output reg [32-1:0] maxi_wdata, - output reg [4-1:0] maxi_wstrb, - output reg maxi_wlast, - output reg maxi_wvalid, + output [32-1:0] maxi_wdata, + output [4-1:0] maxi_wstrb, + output maxi_wlast, + output maxi_wvalid, input maxi_wready, input [2-1:0] maxi_bresp, input maxi_bvalid, @@ -1519,6 +1650,44 @@ assign maxi_awprot = 0; assign maxi_awqos = 0; assign maxi_awuser = 0; + reg [32-1:0] _maxi_wdata_sb_0; + reg [4-1:0] _maxi_wstrb_sb_0; + reg _maxi_wlast_sb_0; + reg _maxi_wvalid_sb_0; + wire _maxi_wready_sb_0; + wire _sb_maxi_writedata_s_value_0; + assign _sb_maxi_writedata_s_value_0 = _maxi_wlast_sb_0; + wire [4-1:0] _sb_maxi_writedata_s_value_1; + assign _sb_maxi_writedata_s_value_1 = _maxi_wstrb_sb_0; + wire [32-1:0] _sb_maxi_writedata_s_value_2; + assign _sb_maxi_writedata_s_value_2 = _maxi_wdata_sb_0; + wire [37-1:0] _sb_maxi_writedata_s_data_3; + assign _sb_maxi_writedata_s_data_3 = { _sb_maxi_writedata_s_value_0, _sb_maxi_writedata_s_value_1, _sb_maxi_writedata_s_value_2 }; + wire _sb_maxi_writedata_s_valid_4; + assign _sb_maxi_writedata_s_valid_4 = _maxi_wvalid_sb_0; + wire _sb_maxi_writedata_m_ready_5; + assign _sb_maxi_writedata_m_ready_5 = maxi_wready; + reg [37-1:0] _sb_maxi_writedata_data_6; + reg _sb_maxi_writedata_valid_7; + wire _sb_maxi_writedata_ready_8; + reg [37-1:0] _sb_maxi_writedata_tmp_data_9; + reg _sb_maxi_writedata_tmp_valid_10; + wire [37-1:0] _sb_maxi_writedata_next_data_11; + wire _sb_maxi_writedata_next_valid_12; + assign _sb_maxi_writedata_ready_8 = !_sb_maxi_writedata_tmp_valid_10; + assign _sb_maxi_writedata_next_data_11 = (_sb_maxi_writedata_tmp_valid_10)? _sb_maxi_writedata_tmp_data_9 : _sb_maxi_writedata_s_data_3; + assign _sb_maxi_writedata_next_valid_12 = _sb_maxi_writedata_tmp_valid_10 || _sb_maxi_writedata_s_valid_4; + wire _sb_maxi_writedata_m_value_13; + assign _sb_maxi_writedata_m_value_13 = _sb_maxi_writedata_data_6[36:36]; + wire [4-1:0] _sb_maxi_writedata_m_value_14; + assign _sb_maxi_writedata_m_value_14 = _sb_maxi_writedata_data_6[35:32]; + wire [32-1:0] _sb_maxi_writedata_m_value_15; + assign _sb_maxi_writedata_m_value_15 = _sb_maxi_writedata_data_6[31:0]; + assign _maxi_wready_sb_0 = _sb_maxi_writedata_ready_8; + assign maxi_wdata = _sb_maxi_writedata_m_value_15; + assign maxi_wstrb = _sb_maxi_writedata_m_value_14; + assign maxi_wlast = _sb_maxi_writedata_m_value_13; + assign maxi_wvalid = _sb_maxi_writedata_valid_7; assign maxi_bready = 1; assign maxi_arsize = 2; assign maxi_arburst = 1; @@ -1527,6 +1696,38 @@ assign maxi_arprot = 0; assign maxi_arqos = 0; assign maxi_aruser = 0; + wire [32-1:0] _maxi_rdata_sb_0; + wire _maxi_rlast_sb_0; + wire _maxi_rvalid_sb_0; + wire _maxi_rready_sb_0; + wire _sb_maxi_readdata_s_value_16; + assign _sb_maxi_readdata_s_value_16 = maxi_rlast; + wire [32-1:0] _sb_maxi_readdata_s_value_17; + assign _sb_maxi_readdata_s_value_17 = maxi_rdata; + wire [33-1:0] _sb_maxi_readdata_s_data_18; + assign _sb_maxi_readdata_s_data_18 = { _sb_maxi_readdata_s_value_16, _sb_maxi_readdata_s_value_17 }; + wire _sb_maxi_readdata_s_valid_19; + assign _sb_maxi_readdata_s_valid_19 = maxi_rvalid; + wire _sb_maxi_readdata_m_ready_20; + assign _sb_maxi_readdata_m_ready_20 = _maxi_rready_sb_0; + reg [33-1:0] _sb_maxi_readdata_data_21; + reg _sb_maxi_readdata_valid_22; + wire _sb_maxi_readdata_ready_23; + reg [33-1:0] _sb_maxi_readdata_tmp_data_24; + reg _sb_maxi_readdata_tmp_valid_25; + wire [33-1:0] _sb_maxi_readdata_next_data_26; + wire _sb_maxi_readdata_next_valid_27; + assign _sb_maxi_readdata_ready_23 = !_sb_maxi_readdata_tmp_valid_25; + assign _sb_maxi_readdata_next_data_26 = (_sb_maxi_readdata_tmp_valid_25)? _sb_maxi_readdata_tmp_data_24 : _sb_maxi_readdata_s_data_18; + assign _sb_maxi_readdata_next_valid_27 = _sb_maxi_readdata_tmp_valid_25 || _sb_maxi_readdata_s_valid_19; + wire _sb_maxi_readdata_m_value_28; + assign _sb_maxi_readdata_m_value_28 = _sb_maxi_readdata_data_21[32:32]; + wire [32-1:0] _sb_maxi_readdata_m_value_29; + assign _sb_maxi_readdata_m_value_29 = _sb_maxi_readdata_data_21[31:0]; + assign _maxi_rdata_sb_0 = _sb_maxi_readdata_m_value_29; + assign _maxi_rlast_sb_0 = _sb_maxi_readdata_m_value_28; + assign _maxi_rvalid_sb_0 = _sb_maxi_readdata_valid_22; + assign maxi_rready = _sb_maxi_readdata_ready_23; reg [3-1:0] _maxi_outstanding_wcount; wire _maxi_has_outstanding_write; assign _maxi_has_outstanding_write = (_maxi_outstanding_wcount > 0) || maxi_awvalid; @@ -1568,21 +1769,21 @@ wire [32-1:0] _maxi_read_local_stride_fifo; wire [33-1:0] _maxi_read_local_size_fifo; wire [32-1:0] _maxi_read_local_blocksize_fifo; - wire [8-1:0] unpack_read_req_op_sel_0; - wire [32-1:0] unpack_read_req_local_addr_1; - wire [32-1:0] unpack_read_req_local_stride_2; - wire [33-1:0] unpack_read_req_local_size_3; - wire [32-1:0] unpack_read_req_local_blocksize_4; - assign unpack_read_req_op_sel_0 = _maxi_read_req_fifo_rdata[136:129]; - assign unpack_read_req_local_addr_1 = _maxi_read_req_fifo_rdata[128:97]; - assign unpack_read_req_local_stride_2 = _maxi_read_req_fifo_rdata[96:65]; - assign unpack_read_req_local_size_3 = _maxi_read_req_fifo_rdata[64:32]; - assign unpack_read_req_local_blocksize_4 = _maxi_read_req_fifo_rdata[31:0]; - assign _maxi_read_op_sel_fifo = unpack_read_req_op_sel_0; - assign _maxi_read_local_addr_fifo = unpack_read_req_local_addr_1; - assign _maxi_read_local_stride_fifo = unpack_read_req_local_stride_2; - assign _maxi_read_local_size_fifo = unpack_read_req_local_size_3; - assign _maxi_read_local_blocksize_fifo = unpack_read_req_local_blocksize_4; + wire [8-1:0] unpack_read_req_op_sel_30; + wire [32-1:0] unpack_read_req_local_addr_31; + wire [32-1:0] unpack_read_req_local_stride_32; + wire [33-1:0] unpack_read_req_local_size_33; + wire [32-1:0] unpack_read_req_local_blocksize_34; + assign unpack_read_req_op_sel_30 = _maxi_read_req_fifo_rdata[136:129]; + assign unpack_read_req_local_addr_31 = _maxi_read_req_fifo_rdata[128:97]; + assign unpack_read_req_local_stride_32 = _maxi_read_req_fifo_rdata[96:65]; + assign unpack_read_req_local_size_33 = _maxi_read_req_fifo_rdata[64:32]; + assign unpack_read_req_local_blocksize_34 = _maxi_read_req_fifo_rdata[31:0]; + assign _maxi_read_op_sel_fifo = unpack_read_req_op_sel_30; + assign _maxi_read_local_addr_fifo = unpack_read_req_local_addr_31; + assign _maxi_read_local_stride_fifo = unpack_read_req_local_stride_32; + assign _maxi_read_local_size_fifo = unpack_read_req_local_size_33; + assign _maxi_read_local_blocksize_fifo = unpack_read_req_local_blocksize_34; reg [8-1:0] _maxi_read_op_sel_buf; reg [32-1:0] _maxi_read_local_addr_buf; reg [32-1:0] _maxi_read_local_stride_buf; @@ -1634,21 +1835,21 @@ wire [32-1:0] _maxi_write_local_stride_fifo; wire [33-1:0] _maxi_write_size_fifo; wire [32-1:0] _maxi_write_local_blocksize_fifo; - wire [8-1:0] unpack_write_req_op_sel_5; - wire [32-1:0] unpack_write_req_local_addr_6; - wire [32-1:0] unpack_write_req_local_stride_7; - wire [33-1:0] unpack_write_req_size_8; - wire [32-1:0] unpack_write_req_local_blocksize_9; - assign unpack_write_req_op_sel_5 = _maxi_write_req_fifo_rdata[136:129]; - assign unpack_write_req_local_addr_6 = _maxi_write_req_fifo_rdata[128:97]; - assign unpack_write_req_local_stride_7 = _maxi_write_req_fifo_rdata[96:65]; - assign unpack_write_req_size_8 = _maxi_write_req_fifo_rdata[64:32]; - assign unpack_write_req_local_blocksize_9 = _maxi_write_req_fifo_rdata[31:0]; - assign _maxi_write_op_sel_fifo = unpack_write_req_op_sel_5; - assign _maxi_write_local_addr_fifo = unpack_write_req_local_addr_6; - assign _maxi_write_local_stride_fifo = unpack_write_req_local_stride_7; - assign _maxi_write_size_fifo = unpack_write_req_size_8; - assign _maxi_write_local_blocksize_fifo = unpack_write_req_local_blocksize_9; + wire [8-1:0] unpack_write_req_op_sel_35; + wire [32-1:0] unpack_write_req_local_addr_36; + wire [32-1:0] unpack_write_req_local_stride_37; + wire [33-1:0] unpack_write_req_size_38; + wire [32-1:0] unpack_write_req_local_blocksize_39; + assign unpack_write_req_op_sel_35 = _maxi_write_req_fifo_rdata[136:129]; + assign unpack_write_req_local_addr_36 = _maxi_write_req_fifo_rdata[128:97]; + assign unpack_write_req_local_stride_37 = _maxi_write_req_fifo_rdata[96:65]; + assign unpack_write_req_size_38 = _maxi_write_req_fifo_rdata[64:32]; + assign unpack_write_req_local_blocksize_39 = _maxi_write_req_fifo_rdata[31:0]; + assign _maxi_write_op_sel_fifo = unpack_write_req_op_sel_35; + assign _maxi_write_local_addr_fifo = unpack_write_req_local_addr_36; + assign _maxi_write_local_stride_fifo = unpack_write_req_local_stride_37; + assign _maxi_write_size_fifo = unpack_write_req_size_38; + assign _maxi_write_local_blocksize_fifo = unpack_write_req_local_blocksize_39; reg [8-1:0] _maxi_write_op_sel_buf; reg [32-1:0] _maxi_write_local_addr_buf; reg [32-1:0] _maxi_write_local_stride_buf; @@ -1693,42 +1894,42 @@ localparam _saxi_shift = 2; reg [32-1:0] _saxi_register_fsm; localparam _saxi_register_fsm_init = 0; - reg [32-1:0] addr_10; - reg writevalid_11; - reg readvalid_12; - reg prev_awvalid_13; - reg prev_arvalid_14; - assign saxi_awready = (_saxi_register_fsm == 0) && (!writevalid_11 && !readvalid_12 && !saxi_bvalid && prev_awvalid_13); - assign saxi_arready = (_saxi_register_fsm == 0) && (!readvalid_12 && !writevalid_11 && prev_arvalid_14 && !prev_awvalid_13); - reg [_saxi_maskwidth-1:0] axis_maskaddr_15; - wire signed [32-1:0] axislite_rdata_16; - assign axislite_rdata_16 = (axis_maskaddr_15 == 0)? _saxi_register_0 : - (axis_maskaddr_15 == 1)? _saxi_register_1 : - (axis_maskaddr_15 == 2)? _saxi_register_2 : - (axis_maskaddr_15 == 3)? _saxi_register_3 : - (axis_maskaddr_15 == 4)? _saxi_register_4 : - (axis_maskaddr_15 == 5)? _saxi_register_5 : - (axis_maskaddr_15 == 6)? _saxi_register_6 : - (axis_maskaddr_15 == 7)? _saxi_register_7 : 'hx; - wire axislite_flag_17; - assign axislite_flag_17 = (axis_maskaddr_15 == 0)? _saxi_flag_0 : - (axis_maskaddr_15 == 1)? _saxi_flag_1 : - (axis_maskaddr_15 == 2)? _saxi_flag_2 : - (axis_maskaddr_15 == 3)? _saxi_flag_3 : - (axis_maskaddr_15 == 4)? _saxi_flag_4 : - (axis_maskaddr_15 == 5)? _saxi_flag_5 : - (axis_maskaddr_15 == 6)? _saxi_flag_6 : - (axis_maskaddr_15 == 7)? _saxi_flag_7 : 'hx; - wire signed [32-1:0] axislite_resetval_18; - assign axislite_resetval_18 = (axis_maskaddr_15 == 0)? _saxi_resetval_0 : - (axis_maskaddr_15 == 1)? _saxi_resetval_1 : - (axis_maskaddr_15 == 2)? _saxi_resetval_2 : - (axis_maskaddr_15 == 3)? _saxi_resetval_3 : - (axis_maskaddr_15 == 4)? _saxi_resetval_4 : - (axis_maskaddr_15 == 5)? _saxi_resetval_5 : - (axis_maskaddr_15 == 6)? _saxi_resetval_6 : - (axis_maskaddr_15 == 7)? _saxi_resetval_7 : 'hx; - reg _saxi_cond_0_1; + reg [32-1:0] addr_40; + reg writevalid_41; + reg readvalid_42; + reg prev_awvalid_43; + reg prev_arvalid_44; + assign saxi_awready = (_saxi_register_fsm == 0) && (!writevalid_41 && !readvalid_42 && !saxi_bvalid && prev_awvalid_43); + assign saxi_arready = (_saxi_register_fsm == 0) && (!readvalid_42 && !writevalid_41 && prev_arvalid_44 && !prev_awvalid_43); + reg [_saxi_maskwidth-1:0] axis_maskaddr_45; + wire signed [32-1:0] axislite_rdata_46; + assign axislite_rdata_46 = (axis_maskaddr_45 == 0)? _saxi_register_0 : + (axis_maskaddr_45 == 1)? _saxi_register_1 : + (axis_maskaddr_45 == 2)? _saxi_register_2 : + (axis_maskaddr_45 == 3)? _saxi_register_3 : + (axis_maskaddr_45 == 4)? _saxi_register_4 : + (axis_maskaddr_45 == 5)? _saxi_register_5 : + (axis_maskaddr_45 == 6)? _saxi_register_6 : + (axis_maskaddr_45 == 7)? _saxi_register_7 : 'hx; + wire axislite_flag_47; + assign axislite_flag_47 = (axis_maskaddr_45 == 0)? _saxi_flag_0 : + (axis_maskaddr_45 == 1)? _saxi_flag_1 : + (axis_maskaddr_45 == 2)? _saxi_flag_2 : + (axis_maskaddr_45 == 3)? _saxi_flag_3 : + (axis_maskaddr_45 == 4)? _saxi_flag_4 : + (axis_maskaddr_45 == 5)? _saxi_flag_5 : + (axis_maskaddr_45 == 6)? _saxi_flag_6 : + (axis_maskaddr_45 == 7)? _saxi_flag_7 : 'hx; + wire signed [32-1:0] axislite_resetval_48; + assign axislite_resetval_48 = (axis_maskaddr_45 == 0)? _saxi_resetval_0 : + (axis_maskaddr_45 == 1)? _saxi_resetval_1 : + (axis_maskaddr_45 == 2)? _saxi_resetval_2 : + (axis_maskaddr_45 == 3)? _saxi_resetval_3 : + (axis_maskaddr_45 == 4)? _saxi_resetval_4 : + (axis_maskaddr_45 == 5)? _saxi_resetval_5 : + (axis_maskaddr_45 == 6)? _saxi_resetval_6 : + (axis_maskaddr_45 == 7)? _saxi_resetval_7 : 'hx; + reg _saxi_rdata_cond_0_1; assign saxi_wready = _saxi_register_fsm == 3; reg start; wire busy; @@ -1776,167 +1977,287 @@ reg signed [32-1:0] _th_memcpy_dst_global_addr_8; reg signed [32-1:0] _th_memcpy_local_addr_9; reg signed [32-1:0] _th_memcpy_dma_size_10; - wire [32-1:0] mask_addr_shifted_19; - assign mask_addr_shifted_19 = _th_memcpy_src_global_addr_7 >> 2; - wire [32-1:0] mask_addr_masked_20; - assign mask_addr_masked_20 = mask_addr_shifted_19 << 2; + wire [32-1:0] mask_addr_shifted_49; + assign mask_addr_shifted_49 = _th_memcpy_src_global_addr_7 >> 2; + wire [32-1:0] mask_addr_masked_50; + assign mask_addr_masked_50 = mask_addr_shifted_49 << 2; reg [32-1:0] _maxi_read_req_fsm; localparam _maxi_read_req_fsm_init = 0; reg [33-1:0] _maxi_read_cur_global_size; reg _maxi_read_cont; - wire [8-1:0] pack_read_req_op_sel_21; - wire [32-1:0] pack_read_req_local_addr_22; - wire [32-1:0] pack_read_req_local_stride_23; - wire [33-1:0] pack_read_req_local_size_24; - wire [32-1:0] pack_read_req_local_blocksize_25; - assign pack_read_req_op_sel_21 = _maxi_read_op_sel; - assign pack_read_req_local_addr_22 = _maxi_read_local_addr; - assign pack_read_req_local_stride_23 = _maxi_read_local_stride; - assign pack_read_req_local_size_24 = _maxi_read_local_size; - assign pack_read_req_local_blocksize_25 = _maxi_read_local_blocksize; - wire [137-1:0] pack_read_req_packed_26; - assign pack_read_req_packed_26 = { pack_read_req_op_sel_21, pack_read_req_local_addr_22, pack_read_req_local_stride_23, pack_read_req_local_size_24, pack_read_req_local_blocksize_25 }; - assign _maxi_read_req_fifo_wdata = ((_maxi_read_req_fsm == 0) && _maxi_read_start && !_maxi_read_req_fifo_almost_full)? pack_read_req_packed_26 : 'hx; + wire [8-1:0] pack_read_req_op_sel_51; + wire [32-1:0] pack_read_req_local_addr_52; + wire [32-1:0] pack_read_req_local_stride_53; + wire [33-1:0] pack_read_req_local_size_54; + wire [32-1:0] pack_read_req_local_blocksize_55; + assign pack_read_req_op_sel_51 = _maxi_read_op_sel; + assign pack_read_req_local_addr_52 = _maxi_read_local_addr; + assign pack_read_req_local_stride_53 = _maxi_read_local_stride; + assign pack_read_req_local_size_54 = _maxi_read_local_size; + assign pack_read_req_local_blocksize_55 = _maxi_read_local_blocksize; + wire [137-1:0] pack_read_req_packed_56; + assign pack_read_req_packed_56 = { pack_read_req_op_sel_51, pack_read_req_local_addr_52, pack_read_req_local_stride_53, pack_read_req_local_size_54, pack_read_req_local_blocksize_55 }; + assign _maxi_read_req_fifo_wdata = ((_maxi_read_req_fsm == 0) && _maxi_read_start && !_maxi_read_req_fifo_almost_full)? pack_read_req_packed_56 : 'hx; assign _maxi_read_req_fifo_enq = ((_maxi_read_req_fsm == 0) && _maxi_read_start && !_maxi_read_req_fifo_almost_full)? (_maxi_read_req_fsm == 0) && _maxi_read_start && !_maxi_read_req_fifo_almost_full && !_maxi_read_req_fifo_almost_full : 0; - localparam _tmp_27 = 1; - wire [_tmp_27-1:0] _tmp_28; - assign _tmp_28 = !_maxi_read_req_fifo_almost_full; - reg [_tmp_27-1:0] __tmp_28_1; - wire [32-1:0] mask_addr_shifted_29; - assign mask_addr_shifted_29 = _maxi_read_global_addr >> 2; - wire [32-1:0] mask_addr_masked_30; - assign mask_addr_masked_30 = mask_addr_shifted_29 << 2; - wire [32-1:0] mask_addr_shifted_31; - assign mask_addr_shifted_31 = _maxi_read_global_addr >> 2; - wire [32-1:0] mask_addr_masked_32; - assign mask_addr_masked_32 = mask_addr_shifted_31 << 2; - wire [32-1:0] mask_addr_shifted_33; - assign mask_addr_shifted_33 = _maxi_read_global_addr >> 2; - wire [32-1:0] mask_addr_masked_34; - assign mask_addr_masked_34 = mask_addr_shifted_33 << 2; - wire [32-1:0] mask_addr_shifted_35; - assign mask_addr_shifted_35 = _maxi_read_global_addr >> 2; - wire [32-1:0] mask_addr_masked_36; - assign mask_addr_masked_36 = mask_addr_shifted_35 << 2; - wire [32-1:0] mask_addr_shifted_37; - assign mask_addr_shifted_37 = _maxi_read_global_addr >> 2; - wire [32-1:0] mask_addr_masked_38; - assign mask_addr_masked_38 = mask_addr_shifted_37 << 2; - wire [32-1:0] mask_addr_shifted_39; - assign mask_addr_shifted_39 = _maxi_read_global_addr >> 2; - wire [32-1:0] mask_addr_masked_40; - assign mask_addr_masked_40 = mask_addr_shifted_39 << 2; - reg _maxi_cond_0_1; - reg [32-1:0] _maxi_read_data_fsm; - localparam _maxi_read_data_fsm_init = 0; - assign _maxi_read_req_fifo_deq = ((_maxi_read_data_fsm == 0) && (!_maxi_read_data_busy && !_maxi_read_req_fifo_empty && (_maxi_read_op_sel_fifo == 1)) && !_maxi_read_req_fifo_empty)? 1 : 0; - reg [32-1:0] write_burst_fsm_0; - localparam write_burst_fsm_0_init = 0; - reg [10-1:0] write_burst_addr_41; - reg [10-1:0] write_burst_stride_42; - reg [33-1:0] write_burst_length_43; - reg write_burst_done_44; - assign ram_a_0_wdata = ((write_burst_fsm_0 == 1) && maxi_rvalid)? maxi_rdata : 'hx; - assign ram_a_0_wenable = ((write_burst_fsm_0 == 1) && maxi_rvalid)? 1'd1 : 0; - assign maxi_rready = _maxi_read_data_fsm == 2; - reg signed [32-1:0] _th_memcpy_v_11; - wire [32-1:0] mask_addr_shifted_45; - assign mask_addr_shifted_45 = _th_memcpy_dst_global_addr_8 >> 2; - wire [32-1:0] mask_addr_masked_46; - assign mask_addr_masked_46 = mask_addr_shifted_45 << 2; - reg [32-1:0] _maxi_write_req_fsm; - localparam _maxi_write_req_fsm_init = 0; - reg [33-1:0] _maxi_write_cur_global_size; - reg _maxi_write_cont; - wire [8-1:0] pack_write_req_op_sel_47; - wire [32-1:0] pack_write_req_local_addr_48; - wire [32-1:0] pack_write_req_local_stride_49; - wire [33-1:0] pack_write_req_size_50; - wire [32-1:0] pack_write_req_local_blocksize_51; - assign pack_write_req_op_sel_47 = _maxi_write_op_sel; - assign pack_write_req_local_addr_48 = _maxi_write_local_addr; - assign pack_write_req_local_stride_49 = _maxi_write_local_stride; - assign pack_write_req_size_50 = _maxi_write_local_size; - assign pack_write_req_local_blocksize_51 = _maxi_write_local_blocksize; - wire [137-1:0] pack_write_req_packed_52; - assign pack_write_req_packed_52 = { pack_write_req_op_sel_47, pack_write_req_local_addr_48, pack_write_req_local_stride_49, pack_write_req_size_50, pack_write_req_local_blocksize_51 }; - localparam _tmp_53 = 1; - wire [_tmp_53-1:0] _tmp_54; - assign _tmp_54 = !_maxi_write_req_fifo_almost_full; - reg [_tmp_53-1:0] __tmp_54_1; - wire [32-1:0] mask_addr_shifted_55; - assign mask_addr_shifted_55 = _maxi_write_global_addr >> 2; - wire [32-1:0] mask_addr_masked_56; - assign mask_addr_masked_56 = mask_addr_shifted_55 << 2; - wire [32-1:0] mask_addr_shifted_57; - assign mask_addr_shifted_57 = _maxi_write_global_addr >> 2; - wire [32-1:0] mask_addr_masked_58; - assign mask_addr_masked_58 = mask_addr_shifted_57 << 2; + localparam _tmp_57 = 1; + wire [_tmp_57-1:0] _tmp_58; + assign _tmp_58 = !_maxi_read_req_fifo_almost_full; + reg [_tmp_57-1:0] __tmp_58_1; wire [32-1:0] mask_addr_shifted_59; - assign mask_addr_shifted_59 = _maxi_write_global_addr >> 2; + assign mask_addr_shifted_59 = _maxi_read_global_addr >> 2; wire [32-1:0] mask_addr_masked_60; assign mask_addr_masked_60 = mask_addr_shifted_59 << 2; wire [32-1:0] mask_addr_shifted_61; - assign mask_addr_shifted_61 = _maxi_write_global_addr >> 2; + assign mask_addr_shifted_61 = _maxi_read_global_addr >> 2; wire [32-1:0] mask_addr_masked_62; assign mask_addr_masked_62 = mask_addr_shifted_61 << 2; wire [32-1:0] mask_addr_shifted_63; - assign mask_addr_shifted_63 = _maxi_write_global_addr >> 2; + assign mask_addr_shifted_63 = _maxi_read_global_addr >> 2; wire [32-1:0] mask_addr_masked_64; assign mask_addr_masked_64 = mask_addr_shifted_63 << 2; wire [32-1:0] mask_addr_shifted_65; - assign mask_addr_shifted_65 = _maxi_write_global_addr >> 2; + assign mask_addr_shifted_65 = _maxi_read_global_addr >> 2; wire [32-1:0] mask_addr_masked_66; assign mask_addr_masked_66 = mask_addr_shifted_65 << 2; - wire [8-1:0] pack_write_req_op_sel_67; - wire [32-1:0] pack_write_req_local_addr_68; - wire [32-1:0] pack_write_req_local_stride_69; - wire [33-1:0] pack_write_req_size_70; - wire [32-1:0] pack_write_req_local_blocksize_71; - assign pack_write_req_op_sel_67 = _maxi_write_op_sel; - assign pack_write_req_local_addr_68 = _maxi_write_local_addr; - assign pack_write_req_local_stride_69 = _maxi_write_local_stride; - assign pack_write_req_size_70 = _maxi_write_cur_global_size; - assign pack_write_req_local_blocksize_71 = _maxi_write_local_blocksize; - wire [137-1:0] pack_write_req_packed_72; - assign pack_write_req_packed_72 = { pack_write_req_op_sel_67, pack_write_req_local_addr_68, pack_write_req_local_stride_69, pack_write_req_size_70, pack_write_req_local_blocksize_71 }; - assign _maxi_write_req_fifo_wdata = ((_maxi_write_req_fsm == 1) && !_maxi_write_req_fifo_almost_full && (maxi_awready || !maxi_awvalid) && (_maxi_outstanding_wcount < 6))? pack_write_req_packed_72 : - ((_maxi_write_req_fsm == 0) && _maxi_write_start && !_maxi_write_req_fifo_almost_full)? pack_write_req_packed_52 : 'hx; + wire [32-1:0] mask_addr_shifted_67; + assign mask_addr_shifted_67 = _maxi_read_global_addr >> 2; + wire [32-1:0] mask_addr_masked_68; + assign mask_addr_masked_68 = mask_addr_shifted_67 << 2; + wire [32-1:0] mask_addr_shifted_69; + assign mask_addr_shifted_69 = _maxi_read_global_addr >> 2; + wire [32-1:0] mask_addr_masked_70; + assign mask_addr_masked_70 = mask_addr_shifted_69 << 2; + reg _maxi_raddr_cond_0_1; + reg [32-1:0] _maxi_read_data_fsm; + localparam _maxi_read_data_fsm_init = 0; + assign _maxi_read_req_fifo_deq = ((_maxi_read_data_fsm == 0) && (!_maxi_read_data_busy && !_maxi_read_req_fifo_empty && (_maxi_read_op_sel_fifo == 1)) && !_maxi_read_req_fifo_empty)? 1 : 0; + reg [32-1:0] write_burst_fsm_0; + localparam write_burst_fsm_0_init = 0; + reg [10-1:0] write_burst_addr_71; + reg [10-1:0] write_burst_stride_72; + reg [33-1:0] write_burst_length_73; + reg write_burst_done_74; + assign ram_a_0_wdata = ((write_burst_fsm_0 == 1) && _maxi_rvalid_sb_0)? _maxi_rdata_sb_0 : 'hx; + assign ram_a_0_wenable = ((write_burst_fsm_0 == 1) && _maxi_rvalid_sb_0)? 1'd1 : 0; + assign _maxi_rready_sb_0 = _maxi_read_data_fsm == 2; + reg signed [32-1:0] _th_memcpy_v_11; + wire [32-1:0] mask_addr_shifted_75; + assign mask_addr_shifted_75 = _th_memcpy_dst_global_addr_8 >> 2; + wire [32-1:0] mask_addr_masked_76; + assign mask_addr_masked_76 = mask_addr_shifted_75 << 2; + reg [32-1:0] _maxi_write_req_fsm; + localparam _maxi_write_req_fsm_init = 0; + reg [33-1:0] _maxi_write_cur_global_size; + reg _maxi_write_cont; + wire [8-1:0] pack_write_req_op_sel_77; + wire [32-1:0] pack_write_req_local_addr_78; + wire [32-1:0] pack_write_req_local_stride_79; + wire [33-1:0] pack_write_req_size_80; + wire [32-1:0] pack_write_req_local_blocksize_81; + assign pack_write_req_op_sel_77 = _maxi_write_op_sel; + assign pack_write_req_local_addr_78 = _maxi_write_local_addr; + assign pack_write_req_local_stride_79 = _maxi_write_local_stride; + assign pack_write_req_size_80 = _maxi_write_local_size; + assign pack_write_req_local_blocksize_81 = _maxi_write_local_blocksize; + wire [137-1:0] pack_write_req_packed_82; + assign pack_write_req_packed_82 = { pack_write_req_op_sel_77, pack_write_req_local_addr_78, pack_write_req_local_stride_79, pack_write_req_size_80, pack_write_req_local_blocksize_81 }; + localparam _tmp_83 = 1; + wire [_tmp_83-1:0] _tmp_84; + assign _tmp_84 = !_maxi_write_req_fifo_almost_full; + reg [_tmp_83-1:0] __tmp_84_1; + wire [32-1:0] mask_addr_shifted_85; + assign mask_addr_shifted_85 = _maxi_write_global_addr >> 2; + wire [32-1:0] mask_addr_masked_86; + assign mask_addr_masked_86 = mask_addr_shifted_85 << 2; + wire [32-1:0] mask_addr_shifted_87; + assign mask_addr_shifted_87 = _maxi_write_global_addr >> 2; + wire [32-1:0] mask_addr_masked_88; + assign mask_addr_masked_88 = mask_addr_shifted_87 << 2; + wire [32-1:0] mask_addr_shifted_89; + assign mask_addr_shifted_89 = _maxi_write_global_addr >> 2; + wire [32-1:0] mask_addr_masked_90; + assign mask_addr_masked_90 = mask_addr_shifted_89 << 2; + wire [32-1:0] mask_addr_shifted_91; + assign mask_addr_shifted_91 = _maxi_write_global_addr >> 2; + wire [32-1:0] mask_addr_masked_92; + assign mask_addr_masked_92 = mask_addr_shifted_91 << 2; + wire [32-1:0] mask_addr_shifted_93; + assign mask_addr_shifted_93 = _maxi_write_global_addr >> 2; + wire [32-1:0] mask_addr_masked_94; + assign mask_addr_masked_94 = mask_addr_shifted_93 << 2; + wire [32-1:0] mask_addr_shifted_95; + assign mask_addr_shifted_95 = _maxi_write_global_addr >> 2; + wire [32-1:0] mask_addr_masked_96; + assign mask_addr_masked_96 = mask_addr_shifted_95 << 2; + wire [8-1:0] pack_write_req_op_sel_97; + wire [32-1:0] pack_write_req_local_addr_98; + wire [32-1:0] pack_write_req_local_stride_99; + wire [33-1:0] pack_write_req_size_100; + wire [32-1:0] pack_write_req_local_blocksize_101; + assign pack_write_req_op_sel_97 = _maxi_write_op_sel; + assign pack_write_req_local_addr_98 = _maxi_write_local_addr; + assign pack_write_req_local_stride_99 = _maxi_write_local_stride; + assign pack_write_req_size_100 = _maxi_write_cur_global_size; + assign pack_write_req_local_blocksize_101 = _maxi_write_local_blocksize; + wire [137-1:0] pack_write_req_packed_102; + assign pack_write_req_packed_102 = { pack_write_req_op_sel_97, pack_write_req_local_addr_98, pack_write_req_local_stride_99, pack_write_req_size_100, pack_write_req_local_blocksize_101 }; + assign _maxi_write_req_fifo_wdata = ((_maxi_write_req_fsm == 1) && !_maxi_write_req_fifo_almost_full && (maxi_awready || !maxi_awvalid) && (_maxi_outstanding_wcount < 6))? pack_write_req_packed_102 : + ((_maxi_write_req_fsm == 0) && _maxi_write_start && !_maxi_write_req_fifo_almost_full)? pack_write_req_packed_82 : 'hx; assign _maxi_write_req_fifo_enq = ((_maxi_write_req_fsm == 1) && !_maxi_write_req_fifo_almost_full && (maxi_awready || !maxi_awvalid) && (_maxi_outstanding_wcount < 6))? (_maxi_write_req_fsm == 1) && !_maxi_write_req_fifo_almost_full && (maxi_awready || !maxi_awvalid) && (_maxi_outstanding_wcount < 6) && !_maxi_write_req_fifo_almost_full : ((_maxi_write_req_fsm == 0) && _maxi_write_start && !_maxi_write_req_fifo_almost_full)? (_maxi_write_req_fsm == 0) && _maxi_write_start && !_maxi_write_req_fifo_almost_full && !_maxi_write_req_fifo_almost_full : 0; - localparam _tmp_73 = 1; - wire [_tmp_73-1:0] _tmp_74; - assign _tmp_74 = !_maxi_write_req_fifo_almost_full; - reg [_tmp_73-1:0] __tmp_74_1; - reg _maxi_cond_1_1; + localparam _tmp_103 = 1; + wire [_tmp_103-1:0] _tmp_104; + assign _tmp_104 = !_maxi_write_req_fifo_almost_full; + reg [_tmp_103-1:0] __tmp_104_1; + reg _maxi_waddr_cond_0_1; reg [32-1:0] _maxi_write_data_fsm; localparam _maxi_write_data_fsm_init = 0; reg [32-1:0] read_burst_fsm_1; localparam read_burst_fsm_1_init = 0; - reg [10-1:0] read_burst_addr_75; - reg [10-1:0] read_burst_stride_76; - reg [33-1:0] read_burst_length_77; - reg read_burst_rvalid_78; - reg read_burst_rlast_79; - assign ram_a_0_addr = ((read_burst_fsm_1 == 1) && (!read_burst_rvalid_78 || (maxi_wready || !maxi_wvalid) && (_maxi_write_size_buf > 0)))? read_burst_addr_75 : - ((write_burst_fsm_0 == 1) && maxi_rvalid)? write_burst_addr_41 : 'hx; - assign ram_a_0_enable = ((read_burst_fsm_1 == 1) && (!read_burst_rvalid_78 || (maxi_wready || !maxi_wvalid) && (_maxi_write_size_buf > 0)))? 1'd1 : - ((write_burst_fsm_0 == 1) && maxi_rvalid)? 1'd1 : 0; - localparam _tmp_80 = 1; - wire [_tmp_80-1:0] _tmp_81; - assign _tmp_81 = (read_burst_fsm_1 == 1) && (!read_burst_rvalid_78 || (maxi_wready || !maxi_wvalid) && (_maxi_write_size_buf > 0)); - reg [_tmp_80-1:0] __tmp_81_1; - wire [32-1:0] read_burst_rdata_82; - assign read_burst_rdata_82 = ram_a_0_rdata; + reg [10-1:0] read_burst_addr_105; + reg [10-1:0] read_burst_stride_106; + reg [33-1:0] read_burst_length_107; + reg read_burst_rvalid_108; + reg read_burst_rlast_109; + assign ram_a_0_addr = ((read_burst_fsm_1 == 1) && (!read_burst_rvalid_108 || (_maxi_wready_sb_0 || !_maxi_wvalid_sb_0) && (_maxi_write_size_buf > 0)))? read_burst_addr_105 : + ((write_burst_fsm_0 == 1) && _maxi_rvalid_sb_0)? write_burst_addr_71 : 'hx; + assign ram_a_0_enable = ((read_burst_fsm_1 == 1) && (!read_burst_rvalid_108 || (_maxi_wready_sb_0 || !_maxi_wvalid_sb_0) && (_maxi_write_size_buf > 0)))? 1'd1 : + ((write_burst_fsm_0 == 1) && _maxi_rvalid_sb_0)? 1'd1 : 0; + localparam _tmp_110 = 1; + wire [_tmp_110-1:0] _tmp_111; + assign _tmp_111 = (read_burst_fsm_1 == 1) && (!read_burst_rvalid_108 || (_maxi_wready_sb_0 || !_maxi_wvalid_sb_0) && (_maxi_write_size_buf > 0)); + reg [_tmp_110-1:0] __tmp_111_1; + wire [32-1:0] read_burst_rdata_112; + assign read_burst_rdata_112 = ram_a_0_rdata; assign _maxi_write_req_fifo_deq = ((_maxi_write_data_fsm == 2) && (!_maxi_write_req_fifo_empty && (_maxi_write_size_buf == 0)) && !_maxi_write_req_fifo_empty)? 1 : ((_maxi_write_data_fsm == 0) && (!_maxi_write_data_busy && !_maxi_write_req_fifo_empty && (_maxi_write_op_sel_fifo == 1)) && !_maxi_write_req_fifo_empty)? 1 : 0; - reg _maxi_cond_2_1; + reg _maxi_wdata_cond_0_1; always @(posedge CLK) begin if(RST) begin - __tmp_81_1 <= 0; + __tmp_111_1 <= 0; end else begin - __tmp_81_1 <= _tmp_81; + __tmp_111_1 <= _tmp_111; + end + end + + + always @(posedge CLK) begin + if(RST) begin + maxi_awaddr <= 0; + maxi_awlen <= 0; + maxi_awvalid <= 0; + _maxi_waddr_cond_0_1 <= 0; + end else begin + if(_maxi_waddr_cond_0_1) begin + maxi_awvalid <= 0; + end + if((_maxi_write_req_fsm == 1) && !_maxi_write_req_fifo_almost_full && (_maxi_outstanding_wcount < 6) && ((_maxi_outstanding_wcount < 6) && (maxi_awready || !maxi_awvalid))) begin + maxi_awaddr <= _maxi_write_global_addr; + maxi_awlen <= _maxi_write_cur_global_size - 1; + maxi_awvalid <= 1; + end + if((_maxi_write_req_fsm == 1) && !_maxi_write_req_fifo_almost_full && (_maxi_outstanding_wcount < 6) && ((_maxi_outstanding_wcount < 6) && (maxi_awready || !maxi_awvalid)) && (_maxi_write_cur_global_size == 0)) begin + maxi_awvalid <= 0; + end + _maxi_waddr_cond_0_1 <= 1; + if(maxi_awvalid && !maxi_awready) begin + maxi_awvalid <= maxi_awvalid; + end + end + end + + + always @(posedge CLK) begin + if(RST) begin + _maxi_wdata_sb_0 <= 0; + _maxi_wvalid_sb_0 <= 0; + _maxi_wlast_sb_0 <= 0; + _maxi_wstrb_sb_0 <= 0; + _maxi_wdata_cond_0_1 <= 0; + end else begin + if(_maxi_wdata_cond_0_1) begin + _maxi_wvalid_sb_0 <= 0; + _maxi_wlast_sb_0 <= 0; + end + if((_maxi_write_op_sel_buf == 1) && read_burst_rvalid_108 && ((_maxi_wready_sb_0 || !_maxi_wvalid_sb_0) && (_maxi_write_size_buf > 0)) && (_maxi_wready_sb_0 || !_maxi_wvalid_sb_0)) begin + _maxi_wdata_sb_0 <= read_burst_rdata_112; + _maxi_wvalid_sb_0 <= 1; + _maxi_wlast_sb_0 <= read_burst_rlast_109 || (_maxi_write_size_buf == 1); + _maxi_wstrb_sb_0 <= { 4{ 1'd1 } }; + end + _maxi_wdata_cond_0_1 <= 1; + if(_maxi_wvalid_sb_0 && !_maxi_wready_sb_0) begin + _maxi_wvalid_sb_0 <= _maxi_wvalid_sb_0; + _maxi_wlast_sb_0 <= _maxi_wlast_sb_0; + end + end + end + + + always @(posedge CLK) begin + if(RST) begin + _sb_maxi_writedata_data_6 <= 0; + _sb_maxi_writedata_valid_7 <= 0; + _sb_maxi_writedata_tmp_data_9 <= 0; + _sb_maxi_writedata_tmp_valid_10 <= 0; + end else begin + if(_sb_maxi_writedata_m_ready_5 || !_sb_maxi_writedata_valid_7) begin + _sb_maxi_writedata_data_6 <= _sb_maxi_writedata_next_data_11; + _sb_maxi_writedata_valid_7 <= _sb_maxi_writedata_next_valid_12; + end + if(!_sb_maxi_writedata_tmp_valid_10 && _sb_maxi_writedata_valid_7 && !_sb_maxi_writedata_m_ready_5) begin + _sb_maxi_writedata_tmp_data_9 <= _sb_maxi_writedata_s_data_3; + _sb_maxi_writedata_tmp_valid_10 <= _sb_maxi_writedata_s_valid_4; + end + if(_sb_maxi_writedata_tmp_valid_10 && _sb_maxi_writedata_m_ready_5) begin + _sb_maxi_writedata_tmp_valid_10 <= 0; + end + end + end + + + always @(posedge CLK) begin + if(RST) begin + maxi_araddr <= 0; + maxi_arlen <= 0; + maxi_arvalid <= 0; + _maxi_raddr_cond_0_1 <= 0; + end else begin + if(_maxi_raddr_cond_0_1) begin + maxi_arvalid <= 0; + end + if((_maxi_read_req_fsm == 1) && (maxi_arready || !maxi_arvalid)) begin + maxi_araddr <= _maxi_read_global_addr; + maxi_arlen <= _maxi_read_cur_global_size - 1; + maxi_arvalid <= 1; + end + _maxi_raddr_cond_0_1 <= 1; + if(maxi_arvalid && !maxi_arready) begin + maxi_arvalid <= maxi_arvalid; + end + end + end + + + always @(posedge CLK) begin + if(RST) begin + _sb_maxi_readdata_data_21 <= 0; + _sb_maxi_readdata_valid_22 <= 0; + _sb_maxi_readdata_tmp_data_24 <= 0; + _sb_maxi_readdata_tmp_valid_25 <= 0; + end else begin + if(_sb_maxi_readdata_m_ready_20 || !_sb_maxi_readdata_valid_22) begin + _sb_maxi_readdata_data_21 <= _sb_maxi_readdata_next_data_26; + _sb_maxi_readdata_valid_22 <= _sb_maxi_readdata_next_valid_27; + end + if(!_sb_maxi_readdata_tmp_valid_25 && _sb_maxi_readdata_valid_22 && !_sb_maxi_readdata_m_ready_20) begin + _sb_maxi_readdata_tmp_data_24 <= _sb_maxi_readdata_s_data_18; + _sb_maxi_readdata_tmp_valid_25 <= _sb_maxi_readdata_s_valid_19; + end + if(_sb_maxi_readdata_tmp_valid_25 && _sb_maxi_readdata_m_ready_20) begin + _sb_maxi_readdata_tmp_valid_25 <= 0; + end end end @@ -1955,10 +2276,6 @@ _maxi_read_local_blocksize <= 0; _maxi_read_req_busy <= 0; _maxi_read_cur_global_size <= 0; - maxi_araddr <= 0; - maxi_arlen <= 0; - maxi_arvalid <= 0; - _maxi_cond_0_1 <= 0; _maxi_read_data_busy <= 0; _maxi_read_op_sel_buf <= 0; _maxi_read_local_addr_buf <= 0; @@ -1974,32 +2291,13 @@ _maxi_write_local_blocksize <= 0; _maxi_write_req_busy <= 0; _maxi_write_cur_global_size <= 0; - maxi_awaddr <= 0; - maxi_awlen <= 0; - maxi_awvalid <= 0; - _maxi_cond_1_1 <= 0; _maxi_write_data_busy <= 0; _maxi_write_op_sel_buf <= 0; _maxi_write_local_addr_buf <= 0; _maxi_write_local_stride_buf <= 0; _maxi_write_size_buf <= 0; _maxi_write_local_blocksize_buf <= 0; - maxi_wdata <= 0; - maxi_wvalid <= 0; - maxi_wlast <= 0; - maxi_wstrb <= 0; - _maxi_cond_2_1 <= 0; end else begin - if(_maxi_cond_0_1) begin - maxi_arvalid <= 0; - end - if(_maxi_cond_1_1) begin - maxi_awvalid <= 0; - end - if(_maxi_cond_2_1) begin - maxi_wvalid <= 0; - maxi_wlast <= 0; - end if(maxi_awvalid && maxi_awready && !(maxi_bvalid && maxi_bready) && (_maxi_outstanding_wcount < 7)) begin _maxi_outstanding_wcount <= _maxi_outstanding_wcount + 1; end @@ -2011,7 +2309,7 @@ if((th_memcpy == 17) && _maxi_read_req_idle) begin _maxi_read_start <= 1; _maxi_read_op_sel <= 1; - _maxi_read_global_addr <= mask_addr_masked_20; + _maxi_read_global_addr <= mask_addr_masked_50; _maxi_read_global_size <= _th_memcpy_dma_size_10; _maxi_read_local_addr <= _th_memcpy_local_addr_9; _maxi_read_local_stride <= 1; @@ -2024,28 +2322,19 @@ if(_maxi_read_start && _maxi_read_req_fifo_almost_full) begin _maxi_read_start <= 1; end - if((_maxi_read_req_fsm == 0) && (_maxi_read_start || _maxi_read_cont) && !_maxi_read_req_fifo_almost_full && (_maxi_read_global_size <= 256) && ((mask_addr_masked_30 & 4095) + (_maxi_read_global_size << 2) >= 4096)) begin - _maxi_read_cur_global_size <= 4096 - (mask_addr_masked_32 & 4095) >> 2; - _maxi_read_global_size <= _maxi_read_global_size - (4096 - (mask_addr_masked_34 & 4095) >> 2); + if((_maxi_read_req_fsm == 0) && (_maxi_read_start || _maxi_read_cont) && !_maxi_read_req_fifo_almost_full && (_maxi_read_global_size <= 256) && ((mask_addr_masked_60 & 4095) + (_maxi_read_global_size << 2) >= 4096)) begin + _maxi_read_cur_global_size <= 4096 - (mask_addr_masked_62 & 4095) >> 2; + _maxi_read_global_size <= _maxi_read_global_size - (4096 - (mask_addr_masked_64 & 4095) >> 2); end else if((_maxi_read_req_fsm == 0) && (_maxi_read_start || _maxi_read_cont) && !_maxi_read_req_fifo_almost_full && (_maxi_read_global_size <= 256)) begin _maxi_read_cur_global_size <= _maxi_read_global_size; _maxi_read_global_size <= 0; - end else if((_maxi_read_req_fsm == 0) && (_maxi_read_start || _maxi_read_cont) && !_maxi_read_req_fifo_almost_full && ((mask_addr_masked_36 & 4095) + 1024 >= 4096)) begin - _maxi_read_cur_global_size <= 4096 - (mask_addr_masked_38 & 4095) >> 2; - _maxi_read_global_size <= _maxi_read_global_size - (4096 - (mask_addr_masked_40 & 4095) >> 2); + end else if((_maxi_read_req_fsm == 0) && (_maxi_read_start || _maxi_read_cont) && !_maxi_read_req_fifo_almost_full && ((mask_addr_masked_66 & 4095) + 1024 >= 4096)) begin + _maxi_read_cur_global_size <= 4096 - (mask_addr_masked_68 & 4095) >> 2; + _maxi_read_global_size <= _maxi_read_global_size - (4096 - (mask_addr_masked_70 & 4095) >> 2); end else if((_maxi_read_req_fsm == 0) && (_maxi_read_start || _maxi_read_cont) && !_maxi_read_req_fifo_almost_full) begin _maxi_read_cur_global_size <= 256; _maxi_read_global_size <= _maxi_read_global_size - 256; end - if((_maxi_read_req_fsm == 1) && (maxi_arready || !maxi_arvalid)) begin - maxi_araddr <= _maxi_read_global_addr; - maxi_arlen <= _maxi_read_cur_global_size - 1; - maxi_arvalid <= 1; - end - _maxi_cond_0_1 <= 1; - if(maxi_arvalid && !maxi_arready) begin - maxi_arvalid <= maxi_arvalid; - end if((_maxi_read_req_fsm == 1) && (maxi_arready || !maxi_arvalid)) begin _maxi_read_global_addr <= _maxi_read_global_addr + (_maxi_read_cur_global_size << 2); end @@ -2060,16 +2349,16 @@ _maxi_read_local_size_buf <= _maxi_read_local_size_fifo; _maxi_read_local_blocksize_buf <= _maxi_read_local_blocksize_fifo; end - if((_maxi_read_data_fsm == 2) && maxi_rvalid) begin + if((_maxi_read_data_fsm == 2) && _maxi_rvalid_sb_0) begin _maxi_read_local_size_buf <= _maxi_read_local_size_buf - 1; end - if((_maxi_read_data_fsm == 2) && maxi_rvalid && (_maxi_read_local_size_buf <= 1)) begin + if((_maxi_read_data_fsm == 2) && _maxi_rvalid_sb_0 && (_maxi_read_local_size_buf <= 1)) begin _maxi_read_data_busy <= 0; end if((th_memcpy == 25) && _maxi_write_req_idle) begin _maxi_write_start <= 1; _maxi_write_op_sel <= 1; - _maxi_write_global_addr <= mask_addr_masked_46; + _maxi_write_global_addr <= mask_addr_masked_76; _maxi_write_global_size <= _th_memcpy_dma_size_10; _maxi_write_local_addr <= _th_memcpy_local_addr_9; _maxi_write_local_stride <= 1; @@ -2082,31 +2371,19 @@ if(_maxi_write_start && _maxi_write_req_fifo_almost_full) begin _maxi_write_start <= 1; end - if((_maxi_write_req_fsm == 0) && (_maxi_write_start || _maxi_write_cont) && !_maxi_write_req_fifo_almost_full && (_maxi_write_global_size <= 256) && ((mask_addr_masked_56 & 4095) + (_maxi_write_global_size << 2) >= 4096)) begin - _maxi_write_cur_global_size <= 4096 - (mask_addr_masked_58 & 4095) >> 2; - _maxi_write_global_size <= _maxi_write_global_size - (4096 - (mask_addr_masked_60 & 4095) >> 2); + if((_maxi_write_req_fsm == 0) && (_maxi_write_start || _maxi_write_cont) && !_maxi_write_req_fifo_almost_full && (_maxi_write_global_size <= 256) && ((mask_addr_masked_86 & 4095) + (_maxi_write_global_size << 2) >= 4096)) begin + _maxi_write_cur_global_size <= 4096 - (mask_addr_masked_88 & 4095) >> 2; + _maxi_write_global_size <= _maxi_write_global_size - (4096 - (mask_addr_masked_90 & 4095) >> 2); end else if((_maxi_write_req_fsm == 0) && (_maxi_write_start || _maxi_write_cont) && !_maxi_write_req_fifo_almost_full && (_maxi_write_global_size <= 256)) begin _maxi_write_cur_global_size <= _maxi_write_global_size; _maxi_write_global_size <= 0; - end else if((_maxi_write_req_fsm == 0) && (_maxi_write_start || _maxi_write_cont) && !_maxi_write_req_fifo_almost_full && ((mask_addr_masked_62 & 4095) + 1024 >= 4096)) begin - _maxi_write_cur_global_size <= 4096 - (mask_addr_masked_64 & 4095) >> 2; - _maxi_write_global_size <= _maxi_write_global_size - (4096 - (mask_addr_masked_66 & 4095) >> 2); + end else if((_maxi_write_req_fsm == 0) && (_maxi_write_start || _maxi_write_cont) && !_maxi_write_req_fifo_almost_full && ((mask_addr_masked_92 & 4095) + 1024 >= 4096)) begin + _maxi_write_cur_global_size <= 4096 - (mask_addr_masked_94 & 4095) >> 2; + _maxi_write_global_size <= _maxi_write_global_size - (4096 - (mask_addr_masked_96 & 4095) >> 2); end else if((_maxi_write_req_fsm == 0) && (_maxi_write_start || _maxi_write_cont) && !_maxi_write_req_fifo_almost_full) begin _maxi_write_cur_global_size <= 256; _maxi_write_global_size <= _maxi_write_global_size - 256; end - if((_maxi_write_req_fsm == 1) && !_maxi_write_req_fifo_almost_full && (_maxi_outstanding_wcount < 6) && ((_maxi_outstanding_wcount < 6) && (maxi_awready || !maxi_awvalid))) begin - maxi_awaddr <= _maxi_write_global_addr; - maxi_awlen <= _maxi_write_cur_global_size - 1; - maxi_awvalid <= 1; - end - if((_maxi_write_req_fsm == 1) && !_maxi_write_req_fifo_almost_full && (_maxi_outstanding_wcount < 6) && ((_maxi_outstanding_wcount < 6) && (maxi_awready || !maxi_awvalid)) && (_maxi_write_cur_global_size == 0)) begin - maxi_awvalid <= 0; - end - _maxi_cond_1_1 <= 1; - if(maxi_awvalid && !maxi_awready) begin - maxi_awvalid <= maxi_awvalid; - end if((_maxi_write_req_fsm == 1) && ((_maxi_write_req_fsm == 1) && !_maxi_write_req_fifo_almost_full && (maxi_awready || !maxi_awvalid) && (_maxi_outstanding_wcount < 6))) begin _maxi_write_global_addr <= _maxi_write_global_addr + (_maxi_write_cur_global_size << 2); end @@ -2127,21 +2404,10 @@ if((_maxi_write_data_fsm == 2) && (!_maxi_write_req_fifo_empty && (_maxi_write_size_buf == 0))) begin _maxi_write_size_buf <= _maxi_write_size_fifo; end - if((_maxi_write_op_sel_buf == 1) && read_burst_rvalid_78 && ((maxi_wready || !maxi_wvalid) && (_maxi_write_size_buf > 0)) && (maxi_wready || !maxi_wvalid)) begin - maxi_wdata <= read_burst_rdata_82; - maxi_wvalid <= 1; - maxi_wlast <= read_burst_rlast_79 || (_maxi_write_size_buf == 1); - maxi_wstrb <= { 4{ 1'd1 } }; - end - _maxi_cond_2_1 <= 1; - if(maxi_wvalid && !maxi_wready) begin - maxi_wvalid <= maxi_wvalid; - maxi_wlast <= maxi_wlast; - end - if((_maxi_write_data_fsm == 2) && read_burst_rvalid_78 && ((maxi_wready || !maxi_wvalid) && (_maxi_write_size_buf > 0))) begin + if((_maxi_write_data_fsm == 2) && read_burst_rvalid_108 && ((_maxi_wready_sb_0 || !_maxi_wvalid_sb_0) && (_maxi_write_size_buf > 0))) begin _maxi_write_size_buf <= _maxi_write_size_buf - 1; end - if((_maxi_write_data_fsm == 2) && ((_maxi_write_op_sel_buf == 1) && read_burst_rvalid_78 && ((maxi_wready || !maxi_wvalid) && (_maxi_write_size_buf > 0))) && read_burst_rlast_79) begin + if((_maxi_write_data_fsm == 2) && ((_maxi_write_op_sel_buf == 1) && read_burst_rvalid_108 && ((_maxi_wready_sb_0 || !_maxi_wvalid_sb_0) && (_maxi_write_size_buf > 0))) && read_burst_rlast_109) begin _maxi_write_data_busy <= 0; end end @@ -2151,7 +2417,7 @@ always @(posedge CLK) begin if(RST) begin count__maxi_read_req_fifo <= 0; - __tmp_28_1 <= 0; + __tmp_58_1 <= 0; end else begin if(_maxi_read_req_fifo_enq && !_maxi_read_req_fifo_full && (_maxi_read_req_fifo_deq && !_maxi_read_req_fifo_empty)) begin count__maxi_read_req_fifo <= count__maxi_read_req_fifo; @@ -2160,7 +2426,7 @@ end else if(_maxi_read_req_fifo_deq && !_maxi_read_req_fifo_empty) begin count__maxi_read_req_fifo <= count__maxi_read_req_fifo - 1; end - __tmp_28_1 <= _tmp_28; + __tmp_58_1 <= _tmp_58; end end @@ -2168,8 +2434,8 @@ always @(posedge CLK) begin if(RST) begin count__maxi_write_req_fifo <= 0; - __tmp_54_1 <= 0; - __tmp_74_1 <= 0; + __tmp_84_1 <= 0; + __tmp_104_1 <= 0; end else begin if(_maxi_write_req_fifo_enq && !_maxi_write_req_fifo_full && (_maxi_write_req_fifo_deq && !_maxi_write_req_fifo_empty)) begin count__maxi_write_req_fifo <= count__maxi_write_req_fifo; @@ -2178,23 +2444,41 @@ end else if(_maxi_write_req_fifo_deq && !_maxi_write_req_fifo_empty) begin count__maxi_write_req_fifo <= count__maxi_write_req_fifo - 1; end - __tmp_54_1 <= _tmp_54; - __tmp_74_1 <= _tmp_74; + __tmp_84_1 <= _tmp_84; + __tmp_104_1 <= _tmp_104; end end always @(posedge CLK) begin if(RST) begin - saxi_bvalid <= 0; - prev_awvalid_13 <= 0; - prev_arvalid_14 <= 0; - writevalid_11 <= 0; - readvalid_12 <= 0; - addr_10 <= 0; saxi_rdata <= 0; saxi_rvalid <= 0; - _saxi_cond_0_1 <= 0; + _saxi_rdata_cond_0_1 <= 0; + end else begin + if(_saxi_rdata_cond_0_1) begin + saxi_rvalid <= 0; + end + if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid)) begin + saxi_rdata <= axislite_rdata_46; + saxi_rvalid <= 1; + end + _saxi_rdata_cond_0_1 <= 1; + if(saxi_rvalid && !saxi_rready) begin + saxi_rvalid <= saxi_rvalid; + end + end + end + + + always @(posedge CLK) begin + if(RST) begin + saxi_bvalid <= 0; + prev_awvalid_43 <= 0; + prev_arvalid_44 <= 0; + writevalid_41 <= 0; + readvalid_42 <= 0; + addr_40 <= 0; _saxi_register_0 <= 0; _saxi_flag_0 <= 0; _saxi_register_1 <= 0; @@ -2212,88 +2496,77 @@ _saxi_register_7 <= 0; _saxi_flag_7 <= 0; end else begin - if(_saxi_cond_0_1) begin - saxi_rvalid <= 0; - end if(saxi_bvalid && saxi_bready) begin saxi_bvalid <= 0; end if(saxi_wvalid && saxi_wready) begin saxi_bvalid <= 1; end - prev_awvalid_13 <= saxi_awvalid; - prev_arvalid_14 <= saxi_arvalid; - writevalid_11 <= 0; - readvalid_12 <= 0; + prev_awvalid_43 <= saxi_awvalid; + prev_arvalid_44 <= saxi_arvalid; + writevalid_41 <= 0; + readvalid_42 <= 0; if(saxi_awready && saxi_awvalid && !saxi_bvalid) begin - addr_10 <= saxi_awaddr; - writevalid_11 <= 1; + addr_40 <= saxi_awaddr; + writevalid_41 <= 1; end else if(saxi_arready && saxi_arvalid) begin - addr_10 <= saxi_araddr; - readvalid_12 <= 1; - end - if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid)) begin - saxi_rdata <= axislite_rdata_16; - saxi_rvalid <= 1; - end - _saxi_cond_0_1 <= 1; - if(saxi_rvalid && !saxi_rready) begin - saxi_rvalid <= saxi_rvalid; + addr_40 <= saxi_araddr; + readvalid_42 <= 1; end - if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_17 && (axis_maskaddr_15 == 0)) begin - _saxi_register_0 <= axislite_resetval_18; + if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_47 && (axis_maskaddr_45 == 0)) begin + _saxi_register_0 <= axislite_resetval_48; _saxi_flag_0 <= 0; end - if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_17 && (axis_maskaddr_15 == 1)) begin - _saxi_register_1 <= axislite_resetval_18; + if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_47 && (axis_maskaddr_45 == 1)) begin + _saxi_register_1 <= axislite_resetval_48; _saxi_flag_1 <= 0; end - if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_17 && (axis_maskaddr_15 == 2)) begin - _saxi_register_2 <= axislite_resetval_18; + if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_47 && (axis_maskaddr_45 == 2)) begin + _saxi_register_2 <= axislite_resetval_48; _saxi_flag_2 <= 0; end - if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_17 && (axis_maskaddr_15 == 3)) begin - _saxi_register_3 <= axislite_resetval_18; + if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_47 && (axis_maskaddr_45 == 3)) begin + _saxi_register_3 <= axislite_resetval_48; _saxi_flag_3 <= 0; end - if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_17 && (axis_maskaddr_15 == 4)) begin - _saxi_register_4 <= axislite_resetval_18; + if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_47 && (axis_maskaddr_45 == 4)) begin + _saxi_register_4 <= axislite_resetval_48; _saxi_flag_4 <= 0; end - if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_17 && (axis_maskaddr_15 == 5)) begin - _saxi_register_5 <= axislite_resetval_18; + if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_47 && (axis_maskaddr_45 == 5)) begin + _saxi_register_5 <= axislite_resetval_48; _saxi_flag_5 <= 0; end - if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_17 && (axis_maskaddr_15 == 6)) begin - _saxi_register_6 <= axislite_resetval_18; + if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_47 && (axis_maskaddr_45 == 6)) begin + _saxi_register_6 <= axislite_resetval_48; _saxi_flag_6 <= 0; end - if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_17 && (axis_maskaddr_15 == 7)) begin - _saxi_register_7 <= axislite_resetval_18; + if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_47 && (axis_maskaddr_45 == 7)) begin + _saxi_register_7 <= axislite_resetval_48; _saxi_flag_7 <= 0; end - if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_15 == 0)) begin + if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_45 == 0)) begin _saxi_register_0 <= saxi_wdata; end - if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_15 == 1)) begin + if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_45 == 1)) begin _saxi_register_1 <= saxi_wdata; end - if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_15 == 2)) begin + if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_45 == 2)) begin _saxi_register_2 <= saxi_wdata; end - if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_15 == 3)) begin + if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_45 == 3)) begin _saxi_register_3 <= saxi_wdata; end - if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_15 == 4)) begin + if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_45 == 4)) begin _saxi_register_4 <= saxi_wdata; end - if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_15 == 5)) begin + if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_45 == 5)) begin _saxi_register_5 <= saxi_wdata; end - if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_15 == 6)) begin + if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_45 == 6)) begin _saxi_register_6 <= saxi_wdata; end - if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_15 == 7)) begin + if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_45 == 7)) begin _saxi_register_7 <= saxi_wdata; end if((_saxi_register_0 == 1) && (th_memcpy == 2) && 1) begin @@ -2395,17 +2668,17 @@ always @(posedge CLK) begin if(RST) begin _saxi_register_fsm <= _saxi_register_fsm_init; - axis_maskaddr_15 <= 0; + axis_maskaddr_45 <= 0; end else begin case(_saxi_register_fsm) _saxi_register_fsm_init: begin - if(readvalid_12 || writevalid_11) begin - axis_maskaddr_15 <= (addr_10 >> _saxi_shift) & _saxi_mask; + if(readvalid_42 || writevalid_41) begin + axis_maskaddr_45 <= (addr_40 >> _saxi_shift) & _saxi_mask; end - if(readvalid_12) begin + if(readvalid_42) begin _saxi_register_fsm <= _saxi_register_fsm_1; end - if(writevalid_11) begin + if(writevalid_41) begin _saxi_register_fsm <= _saxi_register_fsm_3; end end @@ -2679,7 +2952,7 @@ _maxi_read_data_fsm <= _maxi_read_data_fsm_2; end _maxi_read_data_fsm_2: begin - if(maxi_rvalid && (_maxi_read_local_size_buf <= 1)) begin + if(_maxi_rvalid_sb_0 && (_maxi_read_local_size_buf <= 1)) begin _maxi_read_data_fsm <= _maxi_read_data_fsm_init; end end @@ -2692,37 +2965,37 @@ always @(posedge CLK) begin if(RST) begin write_burst_fsm_0 <= write_burst_fsm_0_init; - write_burst_addr_41 <= 0; - write_burst_stride_42 <= 0; - write_burst_length_43 <= 0; - write_burst_done_44 <= 0; + write_burst_addr_71 <= 0; + write_burst_stride_72 <= 0; + write_burst_length_73 <= 0; + write_burst_done_74 <= 0; end else begin case(write_burst_fsm_0) write_burst_fsm_0_init: begin - write_burst_addr_41 <= _maxi_read_local_addr_buf; - write_burst_stride_42 <= _maxi_read_local_stride_buf; - write_burst_length_43 <= _maxi_read_local_size_buf; - write_burst_done_44 <= 0; + write_burst_addr_71 <= _maxi_read_local_addr_buf; + write_burst_stride_72 <= _maxi_read_local_stride_buf; + write_burst_length_73 <= _maxi_read_local_size_buf; + write_burst_done_74 <= 0; if((_maxi_read_data_fsm == 1) && (_maxi_read_op_sel_buf == 1) && (_maxi_read_local_size_buf > 0)) begin write_burst_fsm_0 <= write_burst_fsm_0_1; end end write_burst_fsm_0_1: begin - if(maxi_rvalid) begin - write_burst_addr_41 <= write_burst_addr_41 + write_burst_stride_42; - write_burst_length_43 <= write_burst_length_43 - 1; - write_burst_done_44 <= 0; + if(_maxi_rvalid_sb_0) begin + write_burst_addr_71 <= write_burst_addr_71 + write_burst_stride_72; + write_burst_length_73 <= write_burst_length_73 - 1; + write_burst_done_74 <= 0; end - if(maxi_rvalid && (write_burst_length_43 <= 1)) begin - write_burst_done_44 <= 1; + if(_maxi_rvalid_sb_0 && (write_burst_length_73 <= 1)) begin + write_burst_done_74 <= 1; end - if(maxi_rvalid && 0) begin - write_burst_done_44 <= 1; + if(_maxi_rvalid_sb_0 && 0) begin + write_burst_done_74 <= 1; end - if(maxi_rvalid && (write_burst_length_43 <= 1)) begin + if(_maxi_rvalid_sb_0 && (write_burst_length_73 <= 1)) begin write_burst_fsm_0 <= write_burst_fsm_0_init; end - if(maxi_rvalid && 0) begin + if(_maxi_rvalid_sb_0 && 0) begin write_burst_fsm_0 <= write_burst_fsm_0_init; end if(0) begin @@ -2778,7 +3051,7 @@ _maxi_write_data_fsm <= _maxi_write_data_fsm_2; end _maxi_write_data_fsm_2: begin - if((_maxi_write_op_sel_buf == 1) && read_burst_rvalid_78 && ((maxi_wready || !maxi_wvalid) && (_maxi_write_size_buf > 0)) && read_burst_rlast_79) begin + if((_maxi_write_op_sel_buf == 1) && read_burst_rvalid_108 && ((_maxi_wready_sb_0 || !_maxi_wvalid_sb_0) && (_maxi_write_size_buf > 0)) && read_burst_rlast_109) begin _maxi_write_data_fsm <= _maxi_write_data_fsm_init; end end @@ -2791,41 +3064,41 @@ always @(posedge CLK) begin if(RST) begin read_burst_fsm_1 <= read_burst_fsm_1_init; - read_burst_addr_75 <= 0; - read_burst_stride_76 <= 0; - read_burst_length_77 <= 0; - read_burst_rvalid_78 <= 0; - read_burst_rlast_79 <= 0; + read_burst_addr_105 <= 0; + read_burst_stride_106 <= 0; + read_burst_length_107 <= 0; + read_burst_rvalid_108 <= 0; + read_burst_rlast_109 <= 0; end else begin case(read_burst_fsm_1) read_burst_fsm_1_init: begin - read_burst_addr_75 <= _maxi_write_local_addr_buf; - read_burst_stride_76 <= _maxi_write_local_stride_buf; - read_burst_length_77 <= _maxi_write_size_buf; - read_burst_rvalid_78 <= 0; - read_burst_rlast_79 <= 0; + read_burst_addr_105 <= _maxi_write_local_addr_buf; + read_burst_stride_106 <= _maxi_write_local_stride_buf; + read_burst_length_107 <= _maxi_write_size_buf; + read_burst_rvalid_108 <= 0; + read_burst_rlast_109 <= 0; if((_maxi_write_data_fsm == 1) && (_maxi_write_op_sel_buf == 1) && (_maxi_write_size_buf > 0)) begin read_burst_fsm_1 <= read_burst_fsm_1_1; end end read_burst_fsm_1_1: begin - if((maxi_wready || !maxi_wvalid) && (_maxi_write_size_buf > 0) && (read_burst_length_77 > 0)) begin - read_burst_addr_75 <= read_burst_addr_75 + read_burst_stride_76; - read_burst_length_77 <= read_burst_length_77 - 1; - read_burst_rvalid_78 <= 1; + if((_maxi_wready_sb_0 || !_maxi_wvalid_sb_0) && (_maxi_write_size_buf > 0) && (read_burst_length_107 > 0)) begin + read_burst_addr_105 <= read_burst_addr_105 + read_burst_stride_106; + read_burst_length_107 <= read_burst_length_107 - 1; + read_burst_rvalid_108 <= 1; end - if((maxi_wready || !maxi_wvalid) && (_maxi_write_size_buf > 0) && (read_burst_length_77 <= 1)) begin - read_burst_rlast_79 <= 1; + if((_maxi_wready_sb_0 || !_maxi_wvalid_sb_0) && (_maxi_write_size_buf > 0) && (read_burst_length_107 <= 1)) begin + read_burst_rlast_109 <= 1; end - if(read_burst_rlast_79 && read_burst_rvalid_78 && ((maxi_wready || !maxi_wvalid) && (_maxi_write_size_buf > 0))) begin - read_burst_rvalid_78 <= 0; - read_burst_rlast_79 <= 0; + if(read_burst_rlast_109 && read_burst_rvalid_108 && ((_maxi_wready_sb_0 || !_maxi_wvalid_sb_0) && (_maxi_write_size_buf > 0))) begin + read_burst_rvalid_108 <= 0; + read_burst_rlast_109 <= 0; end if(0) begin - read_burst_rvalid_78 <= 0; - read_burst_rlast_79 <= 0; + read_burst_rvalid_108 <= 0; + read_burst_rlast_109 <= 0; end - if(read_burst_rlast_79 && read_burst_rvalid_78 && ((maxi_wready || !maxi_wvalid) && (_maxi_write_size_buf > 0))) begin + if(read_burst_rlast_109 && read_burst_rvalid_108 && ((_maxi_wready_sb_0 || !_maxi_wvalid_sb_0) && (_maxi_write_size_buf > 0))) begin read_burst_fsm_1 <= read_burst_fsm_1_init; end if(0) begin diff --git a/examples/uart/test_uart.py b/examples/uart/test_uart.py index 11bfca19..4688cea8 100644 --- a/examples/uart/test_uart.py +++ b/examples/uart/test_uart.py @@ -540,6 +540,7 @@ endmodule """ + def test(): veriloggen.reset() test_module = uart.mkTest() diff --git a/examples_obsolete/dataflow_example/dataflow_example.py b/examples_obsolete/dataflow_example/dataflow_example.py index 5a1e519c..0cdcd4ad 100644 --- a/examples_obsolete/dataflow_example/dataflow_example.py +++ b/examples_obsolete/dataflow_example/dataflow_example.py @@ -9,6 +9,7 @@ from veriloggen import * import veriloggen.dataflow as dataflow + def mkMain(): # input variiable x = dataflow.Variable('xdata', valid='xvalid', ready='xready') @@ -22,9 +23,10 @@ def mkMain(): df = dataflow.Dataflow(z) m = df.to_module('main') - + return m + def mkTest(numports=8): m = Module('test') @@ -40,27 +42,27 @@ def mkTest(numports=8): xdata = ports['xdata'] xvalid = ports['xvalid'] xready = ports['xready'] - + ydata = ports['ydata'] yvalid = ports['yvalid'] yready = ports['yready'] - + zdata = ports['zdata'] zvalid = ports['zvalid'] zready = ports['zready'] - + uut = m.Instance(main, 'uut', params=m.connect_params(main), ports=m.connect_ports(main)) reset_done = m.Reg('reset_done', initval=0) reset_stmt = [] - reset_stmt.append( reset_done(0) ) - reset_stmt.append( xdata(0) ) - reset_stmt.append( xvalid(0) ) - reset_stmt.append( ydata(0) ) - reset_stmt.append( yvalid(0) ) - reset_stmt.append( zready(0) ) + reset_stmt.append(reset_done(0)) + reset_stmt.append(xdata(0)) + reset_stmt.append(xvalid(0)) + reset_stmt.append(ydata(0)) + reset_stmt.append(yvalid(0)) + reset_stmt.append(zready(0)) vcd_name = os.path.splitext(os.path.basename(__file__))[0] + '.vcd' simulation.setup_waveform(m, uut, dumpfile=vcd_name) @@ -68,7 +70,7 @@ def mkTest(numports=8): init = simulation.setup_reset(m, rst, reset_stmt, period=100) nclk = simulation.next_clock - + init.add( Delay(1000), reset_done(1), @@ -80,57 +82,54 @@ def mkTest(numports=8): def send(name, data, valid, ready, step=1, waitnum=10): fsm = FSM(m, name + 'fsm', clk, rst) count = m.TmpReg(32, initval=0) - + fsm.add(valid(0)) fsm.goto_next(cond=reset_done) for _ in range(waitnum): fsm.goto_next() - + fsm.add(valid(1)) fsm.goto_next() - + fsm.add(data(data + step), cond=ready) fsm.add(count.inc(), cond=ready) - fsm.goto_next(cond=AndList(count==5, ready)) - + fsm.goto_next(cond=AndList(count == 5, ready)) + fsm.add(valid(0)) for _ in range(waitnum): fsm.goto_next() fsm.add(valid(1)) - + fsm.add(data(data + step), cond=ready) fsm.add(count.inc(), cond=ready) - fsm.goto_next(cond=AndList(count==10, ready)) - + fsm.goto_next(cond=AndList(count == 10, ready)) + fsm.add(valid(0)) - + fsm.make_always() - def receive(name, data, valid, ready, waitnum=10): fsm = FSM(m, name + 'fsm', clk, rst) - + fsm.add(ready(0)) fsm.goto_next(cond=reset_done) fsm.goto_next() - - yinit= fsm.current + + yinit = fsm.current fsm.add(ready(1), cond=valid) fsm.goto_next(cond=valid) for i in range(waitnum): fsm.add(ready(0)) fsm.goto_next() - + fsm.goto(yinit) - + fsm.make_always() - send('x', xdata, xvalid, xready, step=1, waitnum=10) send('y', ydata, yvalid, yready, step=2, waitnum=20) receive('z', zdata, zvalid, zready, waitnum=5) - - + m.Always(Posedge(clk))( If(reset_done)( If(AndList(xvalid, xready))( @@ -144,10 +143,10 @@ def receive(name, data, valid, ready, waitnum=10): ) ) ) - + return m - + if __name__ == '__main__': test = mkTest() verilog = test.to_verilog('tmp.v') @@ -155,10 +154,10 @@ def receive(name, data, valid, ready, waitnum=10): # run simulator (Icarus Verilog) sim = simulation.Simulator(test) - rslt = sim.run() # display=False + rslt = sim.run() # display=False #rslt = sim.run(display=True) print(rslt) # launch waveform viewer (GTKwave) - #sim.view_waveform() # background=False - #sim.view_waveform(background=True) + # sim.view_waveform() # background=False + # sim.view_waveform(background=True) diff --git a/examples_obsolete/dataflow_example/test_dataflow_example.py b/examples_obsolete/dataflow_example/test_dataflow_example.py index cb16f284..cd29a9ac 100644 --- a/examples_obsolete/dataflow_example/test_dataflow_example.py +++ b/examples_obsolete/dataflow_example/test_dataflow_example.py @@ -549,6 +549,8 @@ endmodule """ + + def test(): veriloggen.reset() test_module = dataflow_example.mkTest() diff --git a/examples_obsolete/dataflow_fft4/test_dataflow_fft4.py b/examples_obsolete/dataflow_fft4/test_dataflow_fft4.py index 3e01cf7a..6b4c041f 100644 --- a/examples_obsolete/dataflow_fft4/test_dataflow_fft4.py +++ b/examples_obsolete/dataflow_fft4/test_dataflow_fft4.py @@ -3998,6 +3998,8 @@ endmodule """ + + def test(): veriloggen.reset() test_module = dataflow_fft4.mkTest() diff --git a/examples_obsolete/dataflow_fftN/dataflow_fftN.py b/examples_obsolete/dataflow_fftN/dataflow_fftN.py index ffe8f6eb..a76f889d 100644 --- a/examples_obsolete/dataflow_fftN/dataflow_fftN.py +++ b/examples_obsolete/dataflow_fftN/dataflow_fftN.py @@ -59,7 +59,7 @@ def radix2(x, y, c): r1 = complex_mult(d1, c) return r0, r1 -#------------------------------------------------------------------------------- +# ------------------------------------------------------------------------------- def gen_weight(n): @@ -131,7 +131,7 @@ def fft(din, n): weight = gen_weight(n) return fft_weight(din, n, weight) -#------------------------------------------------------------------------------- +# ------------------------------------------------------------------------------- def mkFFT(n, datawidth=16, point=8): @@ -165,7 +165,7 @@ def mkFFT(n, datawidth=16, point=8): return m -#------------------------------------------------------------------------------- +# ------------------------------------------------------------------------------- def mkTest(n=8, datawidth=16, point=8): diff --git a/examples_obsolete/dataflow_fftN/test_dataflow_fftN.py b/examples_obsolete/dataflow_fftN/test_dataflow_fftN.py index 432abdd3..58f29a1a 100644 --- a/examples_obsolete/dataflow_fftN/test_dataflow_fftN.py +++ b/examples_obsolete/dataflow_fftN/test_dataflow_fftN.py @@ -13182,6 +13182,8 @@ endmodule """ + + def test(): veriloggen.reset() test_module = dataflow_fftN.mkTest() diff --git a/examples_obsolete/dataflow_movavg/test_dataflow_movavg.py b/examples_obsolete/dataflow_movavg/test_dataflow_movavg.py index 3ab7cf98..fb1506e6 100644 --- a/examples_obsolete/dataflow_movavg/test_dataflow_movavg.py +++ b/examples_obsolete/dataflow_movavg/test_dataflow_movavg.py @@ -459,6 +459,8 @@ endmodule """ + + def test(): veriloggen.reset() test_module = dataflow_movavg.mkTest() diff --git a/examples_obsolete/dataflow_movmin/test_dataflow_movmin.py b/examples_obsolete/dataflow_movmin/test_dataflow_movmin.py index 0349812e..543b7e01 100644 --- a/examples_obsolete/dataflow_movmin/test_dataflow_movmin.py +++ b/examples_obsolete/dataflow_movmin/test_dataflow_movmin.py @@ -760,6 +760,7 @@ """ + def test(): veriloggen.reset() test_module = dataflow_movmin.mkTest() diff --git a/examples_obsolete/dataflow_radix2/test_dataflow_radix2.py b/examples_obsolete/dataflow_radix2/test_dataflow_radix2.py index 5ebd87f1..fde980b3 100644 --- a/examples_obsolete/dataflow_radix2/test_dataflow_radix2.py +++ b/examples_obsolete/dataflow_radix2/test_dataflow_radix2.py @@ -1051,6 +1051,7 @@ """ + def test(): veriloggen.reset() test_module = dataflow_radix2.mkTest() diff --git a/examples_obsolete/dataflow_sort/test_dataflow_sort.py b/examples_obsolete/dataflow_sort/test_dataflow_sort.py index 9e7804f0..8dc01c76 100644 --- a/examples_obsolete/dataflow_sort/test_dataflow_sort.py +++ b/examples_obsolete/dataflow_sort/test_dataflow_sort.py @@ -4542,6 +4542,7 @@ """ + def test(): veriloggen.reset() test_module = dataflow_sort.mkTest() diff --git a/hello_led.py b/hello_led.py index e4a255f9..87922e91 100644 --- a/hello_led.py +++ b/hello_led.py @@ -54,6 +54,7 @@ def mkTest(): return m + if __name__ == '__main__': test = mkTest() verilog = test.to_verilog(filename='tmp.v') diff --git a/tests/core/_class/_class.py b/tests/core/_class/_class.py index f827c7c3..88b4959e 100644 --- a/tests/core/_class/_class.py +++ b/tests/core/_class/_class.py @@ -4,10 +4,12 @@ import os # the next line can be removed after installation -sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))) +sys.path.insert(0, os.path.dirname(os.path.dirname( + os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))) from veriloggen import * + class Led(Module): def __init__(self, name='blinkled'): Module.__init__(self, name) @@ -27,7 +29,7 @@ def __init__(self, name='blinkled'): self.count(self.count + 1) ) )) - + self.Always(Posedge(self.clk))( If(self.rst)( self.led(0) @@ -36,7 +38,8 @@ def __init__(self, name='blinkled'): self.led(self.led + 1) ) )) - + + if __name__ == '__main__': led = Led() verilog = led.to_verilog() diff --git a/tests/core/_class/test__class.py b/tests/core/_class/test__class.py index 8d67c1a2..18c79cd1 100644 --- a/tests/core/_class/test__class.py +++ b/tests/core/_class/test__class.py @@ -37,6 +37,7 @@ endmodule """ + def test(): veriloggen.reset() test_module = _class.Led() diff --git a/tests/core/_elif/_elif.py b/tests/core/_elif/_elif.py index 78a5e6ce..007cf666 100644 --- a/tests/core/_elif/_elif.py +++ b/tests/core/_elif/_elif.py @@ -4,10 +4,12 @@ import os # the next line can be removed after installation -sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))) +sys.path.insert(0, os.path.dirname(os.path.dirname( + os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))) from veriloggen import * + def mkLed(): m = Module('blinkled') width = m.Parameter('WIDTH', 8) @@ -34,18 +36,19 @@ def mkLed(): count(count + 5) ) )) - + m.Always(Posedge(clk))( If(rst)( - led( 0 ) + led(0) ).Else( If(count == 1023)( - led( led + 1 ) + led(led + 1) ) )) return m + if __name__ == '__main__': led = mkLed() verilog = led.to_verilog() diff --git a/tests/core/_elif/test__elif.py b/tests/core/_elif/test__elif.py index 20a10c5d..13833e27 100644 --- a/tests/core/_elif/test__elif.py +++ b/tests/core/_elif/test__elif.py @@ -45,6 +45,7 @@ endmodule """ + def test(): veriloggen.reset() test_module = _elif.mkLed() diff --git a/tests/core/_for/_for.py b/tests/core/_for/_for.py index a798960a..276b03b8 100644 --- a/tests/core/_for/_for.py +++ b/tests/core/_for/_for.py @@ -4,10 +4,12 @@ import os # the next line can be removed after installation -sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))) +sys.path.insert(0, os.path.dirname(os.path.dirname( + os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))) from veriloggen import * + def mkLed(): m = Module('blinkled') width = m.Parameter('WIDTH', 8) @@ -17,7 +19,7 @@ def mkLed(): count = m.Reg('count', 32) i = m.Integer('i') - + m.Always(Posedge(clk))( If(rst)( count(0), @@ -25,9 +27,9 @@ def mkLed(): ).Else( If(count == 1023)( count(0), - led[0](led[width-1]), - For(i(1), i> width-1))) ) - ) + led(Or((led << 1), (led >> width - 1)))) ) + ) return m + if __name__ == '__main__': led = mkLed() verilog = led.to_verilog() diff --git a/tests/core/shift/test_shift.py b/tests/core/shift/test_shift.py index c1609bf3..3cc0d9d4 100644 --- a/tests/core/shift/test_shift.py +++ b/tests/core/shift/test_shift.py @@ -39,6 +39,7 @@ endmodule """ + def test_led(): test_module = shift.mkLed() code = test_module.to_verilog() diff --git a/tests/core/singed/signed.py b/tests/core/singed/signed.py index bb30fd01..4313fb79 100644 --- a/tests/core/singed/signed.py +++ b/tests/core/singed/signed.py @@ -4,10 +4,12 @@ import os # the next line can be removed after installation -sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))) +sys.path.insert(0, os.path.dirname(os.path.dirname( + os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))) from veriloggen import * + def mkLed(): m = Module('blinkled') width = m.Parameter('WIDTH', 8) @@ -27,18 +29,19 @@ def mkLed(): count(count + 1) ) )) - + m.Always(Posedge(clk))( If(rst)( - led( Int(0b00000001, width=8, base=2) ) + led(Int(0b00000001, width=8, base=2)) ).Else( If(count == 1023)( - led( led + 1 ) + led(led + 1) ) )) return m + if __name__ == '__main__': led = mkLed() verilog = led.to_verilog() diff --git a/tests/core/singed/test_signed.py b/tests/core/singed/test_signed.py index bef2d492..3bf97c69 100644 --- a/tests/core/singed/test_signed.py +++ b/tests/core/singed/test_signed.py @@ -42,6 +42,7 @@ endmodule """ + def test(): veriloggen.reset() test_module = signed.mkLed() diff --git a/tests/core/stub_/_class/stub__class.py b/tests/core/stub_/_class/stub__class.py index efe2ba47..08bb8079 100644 --- a/tests/core/stub_/_class/stub__class.py +++ b/tests/core/stub_/_class/stub__class.py @@ -5,29 +5,33 @@ import collections # the next line can be removed after installation -sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) +sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname( + os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) from veriloggen import * + def mkLed(): m = StubModule('blinkled') return m + def mkTop(): m = Module('top') width = m.Parameter('WIDTH', 8) clk = m.Input('CLK') rst = m.Input('RST') led = m.Output('LED', width) - - params = ( width, ) - ports = ( clk, rst, led ) - + + params = (width, ) + ports = (clk, rst, led) + # Passing a StubModule m.Instance(mkLed(), 'inst_blinkled', params, ports) return m + if __name__ == '__main__': top = mkTop() verilog = top.to_verilog() diff --git a/tests/core/stub_/_class/test_stub__class.py b/tests/core/stub_/_class/test_stub__class.py index f1e77958..bb400fc4 100644 --- a/tests/core/stub_/_class/test_stub__class.py +++ b/tests/core/stub_/_class/test_stub__class.py @@ -26,6 +26,7 @@ endmodule """ + def test(): veriloggen.reset() test_module = stub__class.mkTop() diff --git a/tests/core/stub_/str/stub_str.py b/tests/core/stub_/str/stub_str.py index 14e61efd..11a52993 100644 --- a/tests/core/stub_/str/stub_str.py +++ b/tests/core/stub_/str/stub_str.py @@ -5,13 +5,11 @@ import collections # the next line can be removed after installation -sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) +sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname( + os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) from veriloggen import * -def mkLed(): - m = StubModule('blinkled') - return m def mkTop(): m = Module('top') @@ -19,15 +17,16 @@ def mkTop(): clk = m.Input('CLK') rst = m.Input('RST') led = m.Output('LED', width) - - params = ( width, ) - ports = ( clk, rst, led ) - + + params = (width,) + ports = (clk, rst, led) + # StubModule is automatically created inside m.Instance('blinkled', 'inst_blinkled', params, ports) return m + if __name__ == '__main__': top = mkTop() verilog = top.to_verilog() diff --git a/tests/core/stub_/str/test_stub_str.py b/tests/core/stub_/str/test_stub_str.py index 781ce46d..48fc2877 100644 --- a/tests/core/stub_/str/test_stub_str.py +++ b/tests/core/stub_/str/test_stub_str.py @@ -26,6 +26,7 @@ endmodule """ + def test(): veriloggen.reset() test_module = stub_str.mkTop() diff --git a/tests/extension/thread_/stream_reduce_iteration_interval/Makefile b/tests/core/stub_/str_multiple/Makefile similarity index 100% rename from tests/extension/thread_/stream_reduce_iteration_interval/Makefile rename to tests/core/stub_/str_multiple/Makefile diff --git a/tests/core/stub_/str_multiple/stub_str_multiple.py b/tests/core/stub_/str_multiple/stub_str_multiple.py new file mode 100644 index 00000000..96d8930c --- /dev/null +++ b/tests/core/stub_/str_multiple/stub_str_multiple.py @@ -0,0 +1,36 @@ +from __future__ import absolute_import +from __future__ import print_function +import sys +import os +import collections + +# the next line can be removed after installation +sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname( + os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) + +from veriloggen import * + + +def mkTop(): + m = Module('top') + width = m.Parameter('WIDTH', 8) + clk = m.Input('CLK') + rst = m.Input('RST') + led0 = m.Output('LED0', width) + led1 = m.Output('LED1', width) + + params0 = (width,) + ports0 = (clk, rst, led0) + m.Instance('blinkled', 'inst_blinkled0', params0, ports0) + + params1 = (width,) + ports1 = (clk, rst, led1) + m.Instance('blinkled', 'inst_blinkled1', params0, ports1) + + return m + + +if __name__ == '__main__': + top = mkTop() + verilog = top.to_verilog() + print(verilog) diff --git a/tests/core/stub_/str_multiple/test_stub_str_multiple.py b/tests/core/stub_/str_multiple/test_stub_str_multiple.py new file mode 100644 index 00000000..7f11a338 --- /dev/null +++ b/tests/core/stub_/str_multiple/test_stub_str_multiple.py @@ -0,0 +1,60 @@ +from __future__ import absolute_import +from __future__ import print_function +import veriloggen +import stub_str_multiple + + +expected_verilog = """ +module top # +( + parameter WIDTH = 8 +) +( + input CLK, + input RST, + output [WIDTH-1:0] LED0, + output [WIDTH-1:0] LED1 +); + + + blinkled + #( + WIDTH + ) + inst_blinkled0 + ( + CLK, + RST, + LED0 + ); + + + blinkled + #( + WIDTH + ) + inst_blinkled1 + ( + CLK, + RST, + LED1 + ); + + +endmodule +""" + + +def test(): + veriloggen.reset() + test_module = stub_str_multiple.mkTop() + code = test_module.to_verilog() + + from pyverilog.vparser.parser import VerilogParser + from pyverilog.ast_code_generator.codegen import ASTCodeGenerator + parser = VerilogParser() + expected_ast = parser.parse(expected_verilog) + codegen = ASTCodeGenerator() + expected_code = codegen.visit(expected_ast) + + assert(expected_code == code) diff --git a/tests/core/stub_/withcode/stub_withcode.py b/tests/core/stub_/withcode/stub_withcode.py index d6213098..6a07f676 100644 --- a/tests/core/stub_/withcode/stub_withcode.py +++ b/tests/core/stub_/withcode/stub_withcode.py @@ -5,7 +5,8 @@ import collections # the next line can be removed after installation -sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) +sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname( + os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) from veriloggen import * @@ -52,25 +53,28 @@ """ + def mkLed(): m = StubModule('blinkled', code=stubcode) return m + def mkTop(): m = Module('top') width = m.Parameter('WIDTH', 8) clk = m.Input('CLK') rst = m.Input('RST') led = m.Output('LED', width) - - params = ( width, ) - ports = ( clk, rst, led ) - + + params = (width, ) + ports = (clk, rst, led) + # Passing a StubModule m.Instance(mkLed(), 'inst_blinkled', params, ports) return m + if __name__ == '__main__': top = mkTop() verilog = top.to_verilog() diff --git a/tests/core/stub_/withcode/test_stub_withcode.py b/tests/core/stub_/withcode/test_stub_withcode.py index d02eceda..51a88e3f 100644 --- a/tests/core/stub_/withcode/test_stub_withcode.py +++ b/tests/core/stub_/withcode/test_stub_withcode.py @@ -62,6 +62,7 @@ endmodule """ + def test(): veriloggen.reset() test_module = stub_withcode.mkTop() diff --git a/tests/core/stub_/withcode_multiple/Makefile b/tests/core/stub_/withcode_multiple/Makefile new file mode 100644 index 00000000..d1ef91af --- /dev/null +++ b/tests/core/stub_/withcode_multiple/Makefile @@ -0,0 +1,29 @@ +TARGET=$(shell ls *.py | grep -v test | grep -v parsetab.py) +ARGS= + +PYTHON=python3 +#PYTHON=python +#OPT=-m pdb +#OPT=-m cProfile -s time +#OPT=-m cProfile -o profile.rslt + +.PHONY: all +all: test + +.PHONY: run +run: + $(PYTHON) $(OPT) $(TARGET) $(ARGS) + +.PHONY: test +test: + $(PYTHON) -m pytest -vv + +.PHONY: check +check: + $(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v + iverilog -tnull -Wall tmp.v + rm -f tmp.v + +.PHONY: clean +clean: + rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v *.vcd diff --git a/tests/core/stub_/withcode_multiple/stub_withcode_multiple.py b/tests/core/stub_/withcode_multiple/stub_withcode_multiple.py new file mode 100644 index 00000000..9d0b51d3 --- /dev/null +++ b/tests/core/stub_/withcode_multiple/stub_withcode_multiple.py @@ -0,0 +1,84 @@ +from __future__ import absolute_import +from __future__ import print_function +import sys +import os +import collections + +# the next line can be removed after installation +sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname( + os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) + +from veriloggen import * + +stubcode = """\ + + +module blinkled # +( + parameter WIDTH = 8 +) +( + input CLK, + input RST, + output reg [WIDTH-1:0] LED +); + + reg [32-1:0] count; + + always @(posedge CLK) begin + if(RST) begin + count <= 0; + end else begin + if(count == 1023) begin + count <= 0; + end else begin + count <= count + 1; + end + end + end + + + always @(posedge CLK) begin + if(RST) begin + LED <= 0; + end else begin + if(count == 1023) begin + LED <= LED + 1; + end + end + end + + +endmodule + +""" + + +def mkLed(): + m = StubModule('blinkled', code=stubcode) + return m + + +def mkTop(): + m = Module('top') + width = m.Parameter('WIDTH', 8) + clk = m.Input('CLK') + rst = m.Input('RST') + led0 = m.Output('LED0', width) + led1 = m.Output('LED1', width) + + params0 = (width,) + ports0 = (clk, rst, led0) + m.Instance(mkLed(), 'inst_blinkled0', params0, ports0) + + params1 = (width,) + ports1 = (clk, rst, led1) + m.Instance(mkLed(), 'inst_blinkled1', params1, ports1) + + return m + + +if __name__ == '__main__': + top = mkTop() + verilog = top.to_verilog() + print(verilog) diff --git a/tests/core/stub_/withcode_multiple/test_stub_withcode_multiple.py b/tests/core/stub_/withcode_multiple/test_stub_withcode_multiple.py new file mode 100644 index 00000000..2f449c73 --- /dev/null +++ b/tests/core/stub_/withcode_multiple/test_stub_withcode_multiple.py @@ -0,0 +1,99 @@ +from __future__ import absolute_import +from __future__ import print_function +import veriloggen +import stub_withcode_multiple + +expected_verilog = """ +module top # +( + parameter WIDTH = 8 +) +( + input CLK, + input RST, + output [WIDTH-1:0] LED0, + output [WIDTH-1:0] LED1 +); + + + blinkled + #( + WIDTH + ) + inst_blinkled0 + ( + CLK, + RST, + LED0 + ); + + + blinkled + #( + WIDTH + ) + inst_blinkled1 + ( + CLK, + RST, + LED1 + ); + + +endmodule + + + +module blinkled # +( + parameter WIDTH = 8 +) +( + input CLK, + input RST, + output reg [WIDTH-1:0] LED +); + + reg [32-1:0] count; + + always @(posedge CLK) begin + if(RST) begin + count <= 0; + end else begin + if(count == 1023) begin + count <= 0; + end else begin + count <= count + 1; + end + end + end + + + always @(posedge CLK) begin + if(RST) begin + LED <= 0; + end else begin + if(count == 1023) begin + LED <= LED + 1; + end + end + end + + +endmodule +""" + + +def test(): + veriloggen.reset() + test_module = stub_withcode_multiple.mkTop() + code = test_module.to_verilog() + + from pyverilog.vparser.parser import VerilogParser + from pyverilog.ast_code_generator.codegen import ASTCodeGenerator + parser = VerilogParser() + expected_ast = parser.parse(expected_verilog) + codegen = ASTCodeGenerator() + expected_code = codegen.visit(expected_ast) + + assert(expected_code == code) diff --git a/tests/core/submodule_/get/submodule_get.py b/tests/core/submodule_/get/submodule_get.py index e939f971..dc16bf38 100644 --- a/tests/core/submodule_/get/submodule_get.py +++ b/tests/core/submodule_/get/submodule_get.py @@ -100,6 +100,7 @@ def mkTest(): return m + if __name__ == '__main__': test = mkTest() verilog = test.to_verilog(filename='tmp.v') diff --git a/tests/core/submodule_/named_args/submodule_named_args.py b/tests/core/submodule_/named_args/submodule_named_args.py index beb0c0f0..ecd58a78 100644 --- a/tests/core/submodule_/named_args/submodule_named_args.py +++ b/tests/core/submodule_/named_args/submodule_named_args.py @@ -64,6 +64,7 @@ def mkTop(): return m + if __name__ == '__main__': top = mkTop() verilog = top.to_verilog('tmp.v') diff --git a/tests/core/submodule_/named_args/test_submodule_named_args.py b/tests/core/submodule_/named_args/test_submodule_named_args.py index 59d6d45e..2f193316 100644 --- a/tests/core/submodule_/named_args/test_submodule_named_args.py +++ b/tests/core/submodule_/named_args/test_submodule_named_args.py @@ -89,6 +89,7 @@ endmodule """ + def test(): test_module = submodule_named_args.mkTop() code = test_module.to_verilog() diff --git a/tests/core/submodule_/nonamed_args/submodule_nonamed_args.py b/tests/core/submodule_/nonamed_args/submodule_nonamed_args.py index 61a0af98..c0fe56bb 100644 --- a/tests/core/submodule_/nonamed_args/submodule_nonamed_args.py +++ b/tests/core/submodule_/nonamed_args/submodule_nonamed_args.py @@ -64,6 +64,7 @@ def mkTop(): return m + if __name__ == '__main__': top = mkTop() verilog = top.to_verilog('tmp.v') diff --git a/tests/core/submodule_/nonamed_args/test_submodule_nonamed_args.py b/tests/core/submodule_/nonamed_args/test_submodule_nonamed_args.py index 0e7d2480..d739fda3 100644 --- a/tests/core/submodule_/nonamed_args/test_submodule_nonamed_args.py +++ b/tests/core/submodule_/nonamed_args/test_submodule_nonamed_args.py @@ -89,6 +89,7 @@ endmodule """ + def test(): test_module = submodule_nonamed_args.mkTop() code = test_module.to_verilog() diff --git a/tests/core/submodule_/prefix/submodule_prefix.py b/tests/core/submodule_/prefix/submodule_prefix.py index b1abad6c..738ad0bd 100644 --- a/tests/core/submodule_/prefix/submodule_prefix.py +++ b/tests/core/submodule_/prefix/submodule_prefix.py @@ -64,6 +64,7 @@ def mkTop(): return m + if __name__ == '__main__': top = mkTop() verilog = top.to_verilog('tmp.v') diff --git a/tests/core/submodule_/prefix/test_submodule_prefix.py b/tests/core/submodule_/prefix/test_submodule_prefix.py index 51331d91..325f270c 100644 --- a/tests/core/submodule_/prefix/test_submodule_prefix.py +++ b/tests/core/submodule_/prefix/test_submodule_prefix.py @@ -89,6 +89,7 @@ endmodule """ + def test(): test_module = submodule_prefix.mkTop() code = test_module.to_verilog() diff --git a/tests/core/submodule_/read_verilog/submodule_read_verilog.py b/tests/core/submodule_/read_verilog/submodule_read_verilog.py index 2669cb10..61935cc3 100644 --- a/tests/core/submodule_/read_verilog/submodule_read_verilog.py +++ b/tests/core/submodule_/read_verilog/submodule_read_verilog.py @@ -71,6 +71,7 @@ def mkTop(): return m + if __name__ == '__main__': top = mkTop() verilog = top.to_verilog('tmp.v') diff --git a/tests/core/submodule_/read_verilog_nested/submodule_read_verilog_nested.py b/tests/core/submodule_/read_verilog_nested/submodule_read_verilog_nested.py index 22487376..6c3bd178 100644 --- a/tests/core/submodule_/read_verilog_nested/submodule_read_verilog_nested.py +++ b/tests/core/submodule_/read_verilog_nested/submodule_read_verilog_nested.py @@ -107,6 +107,7 @@ def mkTop(): return m + if __name__ == '__main__': top = mkTop() verilog = top.to_verilog('tmp.v') diff --git a/tests/core/submodule_/regex/submodule_regex.py b/tests/core/submodule_/regex/submodule_regex.py index ed9a24a6..95d2da0f 100644 --- a/tests/core/submodule_/regex/submodule_regex.py +++ b/tests/core/submodule_/regex/submodule_regex.py @@ -64,6 +64,7 @@ def mkTop(): return m + if __name__ == '__main__': top = mkTop() verilog = top.to_verilog('tmp.v') diff --git a/tests/core/submodule_/regex/test_submodule_regex.py b/tests/core/submodule_/regex/test_submodule_regex.py index 404740f0..34b92bec 100644 --- a/tests/core/submodule_/regex/test_submodule_regex.py +++ b/tests/core/submodule_/regex/test_submodule_regex.py @@ -89,6 +89,7 @@ endmodule """ + def test(): test_module = submodule_regex.mkTop() code = test_module.to_verilog() diff --git a/tests/core/submodule_/sim/submodule_sim.py b/tests/core/submodule_/sim/submodule_sim.py index 604f1a28..6332eb04 100644 --- a/tests/core/submodule_/sim/submodule_sim.py +++ b/tests/core/submodule_/sim/submodule_sim.py @@ -92,6 +92,7 @@ def mkTest(): return m + if __name__ == '__main__': test = mkTest() verilog = test.to_verilog(filename='tmp.v') diff --git a/tests/core/systemtask/systemtask.py b/tests/core/systemtask/systemtask.py index 97030e40..be398b99 100644 --- a/tests/core/systemtask/systemtask.py +++ b/tests/core/systemtask/systemtask.py @@ -4,10 +4,12 @@ import os # the next line can be removed after installation -sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))) +sys.path.insert(0, os.path.dirname(os.path.dirname( + os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))) from veriloggen import * + def mkLed(): m = Module('blinkled') width = m.Parameter('WIDTH', 8) @@ -26,7 +28,7 @@ def mkLed(): count(count + 1) ) )) - + m.Always(Posedge(clk))( If(rst)( led(0) @@ -37,9 +39,10 @@ def mkLed(): SingleStatement(SystemTask('display', 'led:%x', led)) ) )) - + return m + if __name__ == '__main__': led = mkLed() verilog = led.to_verilog() diff --git a/tests/core/systemtask/test_systemtask.py b/tests/core/systemtask/test_systemtask.py index b28994ec..3955662c 100644 --- a/tests/core/systemtask/test_systemtask.py +++ b/tests/core/systemtask/test_systemtask.py @@ -38,6 +38,7 @@ endmodule """ + def test_led(): test_module = systemtask.mkLed() code = test_module.to_verilog() diff --git a/tests/core/tmpvar/test_tmpvar.py b/tests/core/tmpvar/test_tmpvar.py index 8c216e20..5e2b5740 100644 --- a/tests/core/tmpvar/test_tmpvar.py +++ b/tests/core/tmpvar/test_tmpvar.py @@ -43,6 +43,7 @@ endmodule """ + def test(): veriloggen.reset() test_module = tmpvar.mkLed() diff --git a/tests/core/tmpvar/tmpvar.py b/tests/core/tmpvar/tmpvar.py index a6e2f73e..92410792 100644 --- a/tests/core/tmpvar/tmpvar.py +++ b/tests/core/tmpvar/tmpvar.py @@ -4,10 +4,12 @@ import os # the next line can be removed after installation -sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))) +sys.path.insert(0, os.path.dirname(os.path.dirname( + os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))) from veriloggen import * + def mkLed(): m = Module('blinkled') width = m.Parameter('WIDTH', 8) @@ -30,7 +32,7 @@ def mkLed(): count(count + 1) ) )) - + m.Always(Posedge(clk))( If(rst)( led(0) @@ -39,9 +41,10 @@ def mkLed(): led(led + 1) ) )) - + return m + if __name__ == '__main__': led = mkLed() verilog = led.to_verilog() diff --git a/tests/extension/fsm_/as_module/test_fsm_as_module.py b/tests/extension/fsm_/as_module/test_fsm_as_module.py index 24ef230d..a771ee46 100644 --- a/tests/extension/fsm_/as_module/test_fsm_as_module.py +++ b/tests/extension/fsm_/as_module/test_fsm_as_module.py @@ -119,6 +119,7 @@ endmodule """ + def test(): veriloggen.reset() test_module = fsm_as_module.mkLed() diff --git a/tests/extension/fsm_/as_module_delayed/test_fsm_as_module_delayed.py b/tests/extension/fsm_/as_module_delayed/test_fsm_as_module_delayed.py index 02a8288d..3a7709fa 100644 --- a/tests/extension/fsm_/as_module_delayed/test_fsm_as_module_delayed.py +++ b/tests/extension/fsm_/as_module_delayed/test_fsm_as_module_delayed.py @@ -215,6 +215,7 @@ endmodule """ + def test(): veriloggen.reset() test_module = fsm_as_module_delayed.mkTest() diff --git a/tests/extension/fsm_/branch/fsm_branch.py b/tests/extension/fsm_/branch/fsm_branch.py index ce287438..dd42a4ca 100644 --- a/tests/extension/fsm_/branch/fsm_branch.py +++ b/tests/extension/fsm_/branch/fsm_branch.py @@ -4,10 +4,12 @@ import os # the next line can be removed after installation -sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) +sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname( + os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) from veriloggen import * + class SeqIfElse(object): def __init__(self, condition, true_statements, false_statements=()): self.condition = condition @@ -16,35 +18,37 @@ def __init__(self, condition, true_statements, false_statements=()): def __len__(self): return len(self.true_statements) + len(self.true_statements) - + + def add_if_else(fsm, ifelse): # future index index_else = fsm.current + len(ifelse.true_statements) + 1 index_merge = fsm.current + len(ifelse.true_statements) + len(ifelse.false_statements) + 1 index_true = fsm.current + 1 if ifelse.true_statements else index_merge - - fsm.goto( dst=index_true, cond=ifelse.condition, else_dst=index_else ) + + fsm.goto(dst=index_true, cond=ifelse.condition, else_dst=index_else) fsm.inc() # then for i, s in enumerate(ifelse.true_statements): if i < len(ifelse.true_statements) - 1: - fsm( *s ) + fsm(*s) fsm.goto_next() else: - fsm( *s ) + fsm(*s) fsm.goto(index_merge) fsm.inc() # else for i, s in enumerate(ifelse.false_statements): if i < len(ifelse.false_statements) - 1: - fsm( *s ) + fsm(*s) fsm.goto_next() else: - fsm( *s ) + fsm(*s) fsm.goto_next() + def mkLed(): m = Module('blinkled') width = m.Parameter('WIDTH', 8) @@ -57,25 +61,26 @@ def mkLed(): # get the initial index (= 0) init = fsm.current - fsm( count(count + 1) ) + fsm(count(count + 1)) fsm.goto_next() # if-then-else statements condition = count < 1024 - true_statements = [ [ count(count + 2) ], - [ count(count + 3) ] ] - false_statements = [ [ led(led + 1) ], - [ led(led + 2) ] ] + true_statements = [[count(count + 2)], + [count(count + 3)]] + false_statements = [[led(led + 1)], + [led(led + 2)]] ifelse = SeqIfElse(condition, true_statements, false_statements) add_if_else(fsm, ifelse) - + # go to first fsm.goto(init) - + fsm.make_always() - + return m + if __name__ == '__main__': led = mkLed() verilog = led.to_verilog() diff --git a/tests/extension/fsm_/branch/test_fsm_branch.py b/tests/extension/fsm_/branch/test_fsm_branch.py index d2fa2c7a..161925c6 100644 --- a/tests/extension/fsm_/branch/test_fsm_branch.py +++ b/tests/extension/fsm_/branch/test_fsm_branch.py @@ -67,6 +67,7 @@ endmodule """ + def test(): veriloggen.reset() test_module = fsm_branch.mkLed() diff --git a/tests/extension/fsm_/countup_if_then/fsm_countup_if_then.py b/tests/extension/fsm_/countup_if_then/fsm_countup_if_then.py index c01bed8d..6f4eb8ab 100644 --- a/tests/extension/fsm_/countup_if_then/fsm_countup_if_then.py +++ b/tests/extension/fsm_/countup_if_then/fsm_countup_if_then.py @@ -4,10 +4,12 @@ import os # the next line can be removed after installation -sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) +sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname( + os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) from veriloggen import * + def mkLed(): m = Module('blinkled') interval = m.Parameter('INTERVAL', 16) @@ -23,17 +25,17 @@ def mkLed(): fsm( Systask('display', 'LED:%d count:%d', led, count) ) - - fsm.If(count=1024-1)( + seq.If(count >= 1024 - 1)( count(0) ) - seq.If(count>=1024-1)( + seq.If(count >= 1024 - 1)( led.inc() ) - - #seq.make_always() + + # seq.make_always() # make_alway() is called when to_veirlog() is called. #m.add_hook(seq.make_always, args=(), kwargs={}) # In the current implementation, make_always() is always and # automatically called with no registration. - + return m + if __name__ == '__main__': led = mkLed() # to_verilog() method is immuatable. diff --git a/tests/extension/seq_/hook/test_seq_hook.py b/tests/extension/seq_/hook/test_seq_hook.py index a85c9413..814b0ce7 100644 --- a/tests/extension/seq_/hook/test_seq_hook.py +++ b/tests/extension/seq_/hook/test_seq_hook.py @@ -35,6 +35,7 @@ endmodule """ + def test(): veriloggen.reset() test_module = seq_hook.mkLed() diff --git a/tests/extension/seq_/hook_nested/seq_hook_nested.py b/tests/extension/seq_/hook_nested/seq_hook_nested.py index 8de5e2af..a5ac090e 100644 --- a/tests/extension/seq_/hook_nested/seq_hook_nested.py +++ b/tests/extension/seq_/hook_nested/seq_hook_nested.py @@ -4,10 +4,12 @@ import os # the next line can be removed after installation -sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) +sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname( + os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) from veriloggen import * + def mkLed(): m = Module('blinkled') width = m.Parameter('WIDTH', 8) @@ -15,25 +17,26 @@ def mkLed(): rst = m.Input('RST') led = m.OutputReg('LED', width, initval=0) count = m.Reg('count', 32, initval=0) - + seq = Seq(m, 'seq', clk, rst) - seq. If(count<1024-1)( + seq. If(count < 1024 - 1)( count.inc() ) - seq.If(count>=1024-1)( + seq.If(count >= 1024 - 1)( count(0) ) - seq.If(count>=1024-1)( + seq.If(count >= 1024 - 1)( led.inc() ) - - #seq.make_always() + + # seq.make_always() # make_alway() is called when to_veirlog() is called. m.add_hook(seq.make_always, args=(), kwargs={}) - + return m + def mkTop(): m = Module('top') led = mkLed() @@ -44,6 +47,7 @@ def mkTop(): connect_same_name(*ports.values())) return m + if __name__ == '__main__': top = mkTop() # to_verilog() method is immuatable. diff --git a/tests/extension/seq_/hook_nested/test_seq_hook_nested.py b/tests/extension/seq_/hook_nested/test_seq_hook_nested.py index 334f4927..fe826a4d 100644 --- a/tests/extension/seq_/hook_nested/test_seq_hook_nested.py +++ b/tests/extension/seq_/hook_nested/test_seq_hook_nested.py @@ -57,6 +57,7 @@ endmodule """ + def test(): veriloggen.reset() test_module = seq_hook_nested.mkTop() diff --git a/tests/extension/seq_/prev_op/test_seq_prev_op.py b/tests/extension/seq_/prev_op/test_seq_prev_op.py index dca6badc..49ca74f1 100644 --- a/tests/extension/seq_/prev_op/test_seq_prev_op.py +++ b/tests/extension/seq_/prev_op/test_seq_prev_op.py @@ -216,6 +216,7 @@ endmodule """ + def test(): veriloggen.reset() test_module = seq_prev_op.mkTest() diff --git a/tests/extension/seq_/tmpseq/seq_tmpseq.py b/tests/extension/seq_/tmpseq/seq_tmpseq.py index 8d8f099c..e7fceb08 100644 --- a/tests/extension/seq_/tmpseq/seq_tmpseq.py +++ b/tests/extension/seq_/tmpseq/seq_tmpseq.py @@ -4,21 +4,23 @@ import os # the next line can be removed after installation -sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) +sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname( + os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) from veriloggen import * + def mkLed(): m = Module('blinkled') interval = m.Parameter('INTERVAL', 16) clk = m.Input('CLK') rst = m.Input('RST') led = m.OutputReg('LED', 8, initval=0) - + count = m.TmpReg(32, initval=0) seq = TmpSeq(m, clk, rst) - - seq.If(count tmp.v + iverilog -tnull -Wall tmp.v + rm -f tmp.v + +.PHONY: clean +clean: + rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v *.vcd diff --git a/tests/extension/thread_/axi_dma_sb_depth/test_thread_axi_dma_sb_depth.py b/tests/extension/thread_/axi_dma_sb_depth/test_thread_axi_dma_sb_depth.py new file mode 100644 index 00000000..bca9b09b --- /dev/null +++ b/tests/extension/thread_/axi_dma_sb_depth/test_thread_axi_dma_sb_depth.py @@ -0,0 +1,18 @@ +from __future__ import absolute_import +from __future__ import print_function + +import os +import veriloggen +import thread_axi_dma_sb_depth + + +def test(request): + veriloggen.reset() + + simtype = request.config.getoption('--sim') + + rslt = thread_axi_dma_sb_depth.run(filename=None, simtype=simtype, + outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') + + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] + assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/axi_dma_sb_depth/thread_axi_dma_sb_depth.py b/tests/extension/thread_/axi_dma_sb_depth/thread_axi_dma_sb_depth.py new file mode 100644 index 00000000..36d8db93 --- /dev/null +++ b/tests/extension/thread_/axi_dma_sb_depth/thread_axi_dma_sb_depth.py @@ -0,0 +1,155 @@ +from __future__ import absolute_import +from __future__ import print_function +import sys +import os + +# the next line can be removed after installation +sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname( + os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) + +from veriloggen import * +import veriloggen.thread as vthread +import veriloggen.types.axi as axi + + +def mkLed(): + m = Module('blinkled') + clk = m.Input('CLK') + rst = m.Input('RST') + + datawidth = 32 + addrwidth = 10 + myaxi = vthread.AXIM(m, 'myaxi', clk, rst, datawidth, + sb_depth=3) + myram0 = vthread.RAM(m, 'myram0', clk, rst, datawidth, addrwidth) + myram1 = vthread.RAM(m, 'myram1', clk, rst, datawidth, addrwidth) + + all_ok = m.TmpReg(initval=0, prefix='all_ok') + wdata = m.TmpReg(width=datawidth, initval=0, prefix='wdata') + rdata = m.TmpReg(width=datawidth, initval=0, prefix='rdata') + rexpected = m.TmpReg(width=datawidth, initval=0, prefix='rexpected') + + def blink(size): + all_ok.value = True + + for i in range(4): + print('# iter %d start' % i) + # Test for 4KB boundary check + offset = i * 1024 * 16 + (myaxi.boundary_size - (datawidth // 8) * 3) + body(size, offset) + print('# iter %d end' % i) + + if all_ok: + print('# verify: PASSED') + else: + print('# verify: FAILED') + + vthread.finish() + + def body(size, offset): + # write + for i in range(size): + wdata.value = i + 0x1000 + myram0.write(i, wdata) + + laddr = 0 + gaddr = offset + myaxi.dma_write(myram0, laddr, gaddr, size) + print('dma_write: [%d] -> [%d]' % (laddr, gaddr)) + + # write + for i in range(size): + wdata.value = i + 0x4000 + myram1.write(i, wdata) + + laddr = 0 + gaddr = (size + size) * 4 + offset + myaxi.dma_write(myram1, laddr, gaddr, size) + print('dma_write: [%d] -> [%d]' % (laddr, gaddr)) + + # read + laddr = 0 + gaddr = offset + myaxi.dma_read(myram1, laddr, gaddr, size) + print('dma_read: [%d] <- [%d]' % (laddr, gaddr)) + + for i in range(size): + rdata.value = myram1.read(i) + rexpected.value = i + 0x1000 + if vthread.verilog.NotEql(rdata, rexpected): + print('rdata[%d] = %d (expected %d)' % (i, rdata, rexpected)) + all_ok.value = False + + # read + laddr = 0 + gaddr = (size + size) * 4 + offset + myaxi.dma_read(myram0, laddr, gaddr, size) + print('dma_read: [%d] <- [%d]' % (laddr, gaddr)) + + for i in range(size): + rdata.value = myram0.read(i) + rexpected.value = i + 0x4000 + if vthread.verilog.NotEql(rdata, rexpected): + print('rdata[%d] = %d (expected %d)' % (i, rdata, rexpected)) + all_ok.value = False + + th = vthread.Thread(m, 'th_blink', clk, rst, blink) + fsm = th.start(16) + + return m + + +def mkTest(memimg_name=None): + m = Module('test') + + # target instance + led = mkLed() + + # copy paras and ports + params = m.copy_params(led) + ports = m.copy_sim_ports(led) + + clk = ports['CLK'] + rst = ports['RST'] + + memory = axi.AxiMemoryModel(m, 'memory', clk, rst, memimg_name=memimg_name) + memory.connect(ports, 'myaxi') + + uut = m.Instance(led, 'uut', + params=m.connect_params(led), + ports=m.connect_ports(led)) + + # vcd_name = os.path.splitext(os.path.basename(__file__))[0] + '.vcd' + # simulation.setup_waveform(m, uut, dumpfile=vcd_name) + simulation.setup_clock(m, clk, hperiod=5) + init = simulation.setup_reset(m, rst, m.make_reset(), period=100) + + init.add( + Delay(1000000), + Systask('finish'), + ) + + return m + + +def run(filename='tmp.v', simtype='iverilog', outputfile=None): + + if outputfile is None: + outputfile = os.path.splitext(os.path.basename(__file__))[0] + '.out' + + memimg_name = 'memimg_' + outputfile + + test = mkTest(memimg_name=memimg_name) + + if filename is not None: + test.to_verilog(filename) + + sim = simulation.Simulator(test, sim=simtype) + rslt = sim.run(outputfile=outputfile) + + return rslt + + +if __name__ == '__main__': + rslt = run(filename='tmp.v') + print(rslt) diff --git a/tests/extension/thread_/axi_dma_stride/test_thread_axi_dma_stride.py b/tests/extension/thread_/axi_dma_stride/test_thread_axi_dma_stride.py index 7fbf74ef..d5876d90 100644 --- a/tests/extension/thread_/axi_dma_stride/test_thread_axi_dma_stride.py +++ b/tests/extension/thread_/axi_dma_stride/test_thread_axi_dma_stride.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_axi_dma_stride.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/axi_dma_stride/thread_axi_dma_stride.py b/tests/extension/thread_/axi_dma_stride/thread_axi_dma_stride.py index 5bc835a3..1c42c282 100644 --- a/tests/extension/thread_/axi_dma_stride/thread_axi_dma_stride.py +++ b/tests/extension/thread_/axi_dma_stride/thread_axi_dma_stride.py @@ -165,9 +165,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/axi_dma_wide/test_thread_axi_dma_wide.py b/tests/extension/thread_/axi_dma_wide/test_thread_axi_dma_wide.py index cafe69b6..93d32c4a 100644 --- a/tests/extension/thread_/axi_dma_wide/test_thread_axi_dma_wide.py +++ b/tests/extension/thread_/axi_dma_wide/test_thread_axi_dma_wide.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_axi_dma_wide.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/axi_dma_wide/thread_axi_dma_wide.py b/tests/extension/thread_/axi_dma_wide/thread_axi_dma_wide.py index c50229e0..eeb01e02 100644 --- a/tests/extension/thread_/axi_dma_wide/thread_axi_dma_wide.py +++ b/tests/extension/thread_/axi_dma_wide/thread_axi_dma_wide.py @@ -146,9 +146,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/axi_dma_wide_unaligned/test_thread_axi_dma_wide_unaligned.py b/tests/extension/thread_/axi_dma_wide_unaligned/test_thread_axi_dma_wide_unaligned.py index 041289ac..831c7355 100644 --- a/tests/extension/thread_/axi_dma_wide_unaligned/test_thread_axi_dma_wide_unaligned.py +++ b/tests/extension/thread_/axi_dma_wide_unaligned/test_thread_axi_dma_wide_unaligned.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_axi_dma_wide_unaligned.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/axi_dma_wide_unaligned/thread_axi_dma_wide_unaligned.py b/tests/extension/thread_/axi_dma_wide_unaligned/thread_axi_dma_wide_unaligned.py index b0c1bdb2..939079bf 100644 --- a/tests/extension/thread_/axi_dma_wide_unaligned/thread_axi_dma_wide_unaligned.py +++ b/tests/extension/thread_/axi_dma_wide_unaligned/thread_axi_dma_wide_unaligned.py @@ -147,9 +147,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/axi_read_write/test_thread_axi_read_write.py b/tests/extension/thread_/axi_read_write/test_thread_axi_read_write.py index b58c1649..1d62bebc 100644 --- a/tests/extension/thread_/axi_read_write/test_thread_axi_read_write.py +++ b/tests/extension/thread_/axi_read_write/test_thread_axi_read_write.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_axi_read_write.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/axi_read_write/thread_axi_read_write.py b/tests/extension/thread_/axi_read_write/thread_axi_read_write.py index 9ce76bce..940e2a3f 100644 --- a/tests/extension/thread_/axi_read_write/thread_axi_read_write.py +++ b/tests/extension/thread_/axi_read_write/thread_axi_read_write.py @@ -127,9 +127,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/axi_slave/test_thread_axi_slave.py b/tests/extension/thread_/axi_slave/test_thread_axi_slave.py index 96e3eddd..b2afdc27 100644 --- a/tests/extension/thread_/axi_slave/test_thread_axi_slave.py +++ b/tests/extension/thread_/axi_slave/test_thread_axi_slave.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_axi_slave.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/axi_slave/thread_axi_slave.py b/tests/extension/thread_/axi_slave/thread_axi_slave.py index d8d7d7ec..00faa8b7 100644 --- a/tests/extension/thread_/axi_slave/thread_axi_slave.py +++ b/tests/extension/thread_/axi_slave/thread_axi_slave.py @@ -140,9 +140,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/axi_slave_lite/test_thread_axi_slave_lite.py b/tests/extension/thread_/axi_slave_lite/test_thread_axi_slave_lite.py index ddb48188..72ba24dc 100644 --- a/tests/extension/thread_/axi_slave_lite/test_thread_axi_slave_lite.py +++ b/tests/extension/thread_/axi_slave_lite/test_thread_axi_slave_lite.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_axi_slave_lite.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/axi_slave_lite/thread_axi_slave_lite.py b/tests/extension/thread_/axi_slave_lite/thread_axi_slave_lite.py index 8846d924..1bda522d 100644 --- a/tests/extension/thread_/axi_slave_lite/thread_axi_slave_lite.py +++ b/tests/extension/thread_/axi_slave_lite/thread_axi_slave_lite.py @@ -140,9 +140,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/axi_stream/test_thread_axi_stream.py b/tests/extension/thread_/axi_stream/test_thread_axi_stream.py index 27460941..61b693ed 100644 --- a/tests/extension/thread_/axi_stream/test_thread_axi_stream.py +++ b/tests/extension/thread_/axi_stream/test_thread_axi_stream.py @@ -189,7 +189,7 @@ (axis_maskaddr_13 == 1)? _saxi_resetval_1 : (axis_maskaddr_13 == 2)? _saxi_resetval_2 : (axis_maskaddr_13 == 3)? _saxi_resetval_3 : 'hx; - reg _saxi_cond_0_1; + reg _saxi_rdata_cond_0_1; assign saxi_wready = _saxi_register_fsm == 3; reg [32-1:0] th_comp; localparam th_comp_init = 0; @@ -235,7 +235,6 @@ always @(posedge CLK) begin if(RST) begin - _axi_b_write_data_busy <= 0; axi_b_tdata <= 0; axi_b_tvalid <= 0; axi_b_tlast <= 0; @@ -245,9 +244,6 @@ axi_b_tvalid <= 0; axi_b_tlast <= 0; end - if((th_comp == 12) && _axi_b_write_idle) begin - _axi_b_write_data_busy <= 1; - end if((th_comp == 13) && (axi_b_tready || !axi_b_tvalid)) begin axi_b_tdata <= _th_comp_b_4; axi_b_tvalid <= 1; @@ -258,6 +254,17 @@ axi_b_tvalid <= axi_b_tvalid; axi_b_tlast <= axi_b_tlast; end + end + end + + + always @(posedge CLK) begin + if(RST) begin + _axi_b_write_data_busy <= 0; + end else begin + if((th_comp == 12) && _axi_b_write_idle) begin + _axi_b_write_data_busy <= 1; + end if((th_comp == 13) && (axi_b_tready || !axi_b_tvalid)) begin _axi_b_write_data_busy <= 0; end @@ -280,6 +287,27 @@ end + always @(posedge CLK) begin + if(RST) begin + saxi_rdata <= 0; + saxi_rvalid <= 0; + _saxi_rdata_cond_0_1 <= 0; + end else begin + if(_saxi_rdata_cond_0_1) begin + saxi_rvalid <= 0; + end + if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid)) begin + saxi_rdata <= axislite_rdata_14; + saxi_rvalid <= 1; + end + _saxi_rdata_cond_0_1 <= 1; + if(saxi_rvalid && !saxi_rready) begin + saxi_rvalid <= saxi_rvalid; + end + end + end + + always @(posedge CLK) begin if(RST) begin saxi_bvalid <= 0; @@ -288,9 +316,6 @@ writevalid_9 <= 0; readvalid_10 <= 0; addr_8 <= 0; - saxi_rdata <= 0; - saxi_rvalid <= 0; - _saxi_cond_0_1 <= 0; _saxi_register_0 <= 0; _saxi_flag_0 <= 0; _saxi_register_1 <= 0; @@ -300,9 +325,6 @@ _saxi_register_3 <= 0; _saxi_flag_3 <= 0; end else begin - if(_saxi_cond_0_1) begin - saxi_rvalid <= 0; - end if(saxi_bvalid && saxi_bready) begin saxi_bvalid <= 0; end @@ -320,14 +342,6 @@ addr_8 <= saxi_araddr; readvalid_10 <= 1; end - if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid)) begin - saxi_rdata <= axislite_rdata_14; - saxi_rvalid <= 1; - end - _saxi_cond_0_1 <= 1; - if(saxi_rvalid && !saxi_rready) begin - saxi_rvalid <= saxi_rvalid; - end if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_15 && (axis_maskaddr_13 == 0)) begin _saxi_register_0 <= axislite_resetval_16; _saxi_flag_0 <= 0; diff --git a/tests/extension/thread_/axi_stream_with_master/test_thread_axi_stream_with_master.py b/tests/extension/thread_/axi_stream_with_master/test_thread_axi_stream_with_master.py index eb90b182..97b2c175 100644 --- a/tests/extension/thread_/axi_stream_with_master/test_thread_axi_stream_with_master.py +++ b/tests/extension/thread_/axi_stream_with_master/test_thread_axi_stream_with_master.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_axi_stream_with_master.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/axi_stream_with_master/thread_axi_stream_with_master.py b/tests/extension/thread_/axi_stream_with_master/thread_axi_stream_with_master.py index ad82beed..e1c26161 100644 --- a/tests/extension/thread_/axi_stream_with_master/thread_axi_stream_with_master.py +++ b/tests/extension/thread_/axi_stream_with_master/thread_axi_stream_with_master.py @@ -142,9 +142,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/axi_stream_with_master_fifo/test_thread_axi_stream_with_master_fifo.py b/tests/extension/thread_/axi_stream_with_master_fifo/test_thread_axi_stream_with_master_fifo.py index 69a9f048..6400fb78 100644 --- a/tests/extension/thread_/axi_stream_with_master_fifo/test_thread_axi_stream_with_master_fifo.py +++ b/tests/extension/thread_/axi_stream_with_master_fifo/test_thread_axi_stream_with_master_fifo.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_axi_stream_with_master_fifo.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/axi_stream_with_master_fifo/thread_axi_stream_with_master_fifo.py b/tests/extension/thread_/axi_stream_with_master_fifo/thread_axi_stream_with_master_fifo.py index f62a6061..43ab41e8 100644 --- a/tests/extension/thread_/axi_stream_with_master_fifo/thread_axi_stream_with_master_fifo.py +++ b/tests/extension/thread_/axi_stream_with_master_fifo/thread_axi_stream_with_master_fifo.py @@ -158,9 +158,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/axi_stream_with_master_fifo_narrow/test_thread_axi_stream_with_master_fifo_narrow.py b/tests/extension/thread_/axi_stream_with_master_fifo_narrow/test_thread_axi_stream_with_master_fifo_narrow.py index 785379ff..73671fb9 100644 --- a/tests/extension/thread_/axi_stream_with_master_fifo_narrow/test_thread_axi_stream_with_master_fifo_narrow.py +++ b/tests/extension/thread_/axi_stream_with_master_fifo_narrow/test_thread_axi_stream_with_master_fifo_narrow.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_axi_stream_with_master_fifo_narrow.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/axi_stream_with_master_fifo_narrow/thread_axi_stream_with_master_fifo_narrow.py b/tests/extension/thread_/axi_stream_with_master_fifo_narrow/thread_axi_stream_with_master_fifo_narrow.py index 5f153284..dbdf1861 100644 --- a/tests/extension/thread_/axi_stream_with_master_fifo_narrow/thread_axi_stream_with_master_fifo_narrow.py +++ b/tests/extension/thread_/axi_stream_with_master_fifo_narrow/thread_axi_stream_with_master_fifo_narrow.py @@ -64,7 +64,8 @@ def body(size, offset): for i in range(size): wdata.value = 0 for j in range(word_datawidth // datawidth): - wdata.value = (i + 0x1000 * j) << (word_datawidth - datawidth) | (wdata.value >> datawidth) + wdata.value = (i + 0x1000 * j) << (word_datawidth - + datawidth) | (wdata.value >> datawidth) myram.write(i, wdata) laddr = 0 @@ -151,9 +152,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/axi_stream_with_master_fifo_wide/test_thread_axi_stream_with_master_fifo_wide.py b/tests/extension/thread_/axi_stream_with_master_fifo_wide/test_thread_axi_stream_with_master_fifo_wide.py index 3a83ed40..912bff54 100644 --- a/tests/extension/thread_/axi_stream_with_master_fifo_wide/test_thread_axi_stream_with_master_fifo_wide.py +++ b/tests/extension/thread_/axi_stream_with_master_fifo_wide/test_thread_axi_stream_with_master_fifo_wide.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_axi_stream_with_master_fifo_wide.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/axi_stream_with_master_fifo_wide/thread_axi_stream_with_master_fifo_wide.py b/tests/extension/thread_/axi_stream_with_master_fifo_wide/thread_axi_stream_with_master_fifo_wide.py index 7ed1573b..15b71e30 100644 --- a/tests/extension/thread_/axi_stream_with_master_fifo_wide/thread_axi_stream_with_master_fifo_wide.py +++ b/tests/extension/thread_/axi_stream_with_master_fifo_wide/thread_axi_stream_with_master_fifo_wide.py @@ -151,9 +151,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/axi_stream_with_master_ram/test_thread_axi_stream_with_master_ram.py b/tests/extension/thread_/axi_stream_with_master_ram/test_thread_axi_stream_with_master_ram.py index c3786670..93b9fcc1 100644 --- a/tests/extension/thread_/axi_stream_with_master_ram/test_thread_axi_stream_with_master_ram.py +++ b/tests/extension/thread_/axi_stream_with_master_ram/test_thread_axi_stream_with_master_ram.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_axi_stream_with_master_ram.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/axi_stream_with_master_ram/thread_axi_stream_with_master_ram.py b/tests/extension/thread_/axi_stream_with_master_ram/thread_axi_stream_with_master_ram.py index cca9b777..43f84ccb 100644 --- a/tests/extension/thread_/axi_stream_with_master_ram/thread_axi_stream_with_master_ram.py +++ b/tests/extension/thread_/axi_stream_with_master_ram/thread_axi_stream_with_master_ram.py @@ -147,9 +147,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/axi_stream_with_master_ram_narrow/test_thread_axi_stream_with_master_ram_narrow.py b/tests/extension/thread_/axi_stream_with_master_ram_narrow/test_thread_axi_stream_with_master_ram_narrow.py index a825a2d0..4bd3a901 100644 --- a/tests/extension/thread_/axi_stream_with_master_ram_narrow/test_thread_axi_stream_with_master_ram_narrow.py +++ b/tests/extension/thread_/axi_stream_with_master_ram_narrow/test_thread_axi_stream_with_master_ram_narrow.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_axi_stream_with_master_ram_narrow.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/axi_stream_with_master_ram_narrow/thread_axi_stream_with_master_ram_narrow.py b/tests/extension/thread_/axi_stream_with_master_ram_narrow/thread_axi_stream_with_master_ram_narrow.py index 8b97027a..6ed75180 100644 --- a/tests/extension/thread_/axi_stream_with_master_ram_narrow/thread_axi_stream_with_master_ram_narrow.py +++ b/tests/extension/thread_/axi_stream_with_master_ram_narrow/thread_axi_stream_with_master_ram_narrow.py @@ -62,7 +62,8 @@ def body(size, offset): for i in range(size): wdata.value = 0 for j in range(word_datawidth // datawidth): - wdata.value = (i + 0x1000 * j) << (word_datawidth - datawidth) | (wdata.value >> datawidth) + wdata.value = (i + 0x1000 * j) << (word_datawidth - + datawidth) | (wdata.value >> datawidth) myram.write(i, wdata) laddr = 0 @@ -149,9 +150,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/axi_stream_with_master_ram_wide/test_thread_axi_stream_with_master_ram_wide.py b/tests/extension/thread_/axi_stream_with_master_ram_wide/test_thread_axi_stream_with_master_ram_wide.py index 6691c259..c836260d 100644 --- a/tests/extension/thread_/axi_stream_with_master_ram_wide/test_thread_axi_stream_with_master_ram_wide.py +++ b/tests/extension/thread_/axi_stream_with_master_ram_wide/test_thread_axi_stream_with_master_ram_wide.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_axi_stream_with_master_ram_wide.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/axi_stream_with_master_ram_wide/thread_axi_stream_with_master_ram_wide.py b/tests/extension/thread_/axi_stream_with_master_ram_wide/thread_axi_stream_with_master_ram_wide.py index 6241a373..a5e3cf6f 100644 --- a/tests/extension/thread_/axi_stream_with_master_ram_wide/thread_axi_stream_with_master_ram_wide.py +++ b/tests/extension/thread_/axi_stream_with_master_ram_wide/thread_axi_stream_with_master_ram_wide.py @@ -151,9 +151,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/ext_fifo/test_thread_ext_fifo.py b/tests/extension/thread_/ext_fifo/test_thread_ext_fifo.py index 9e3392fe..d078e677 100644 --- a/tests/extension/thread_/ext_fifo/test_thread_ext_fifo.py +++ b/tests/extension/thread_/ext_fifo/test_thread_ext_fifo.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_ext_fifo.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/ext_fifo/thread_ext_fifo.py b/tests/extension/thread_/ext_fifo/thread_ext_fifo.py index 0df38bed..1aa7c11a 100644 --- a/tests/extension/thread_/ext_fifo/thread_ext_fifo.py +++ b/tests/extension/thread_/ext_fifo/thread_ext_fifo.py @@ -96,9 +96,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/ext_ram/test_thread_ext_ram.py b/tests/extension/thread_/ext_ram/test_thread_ext_ram.py index 1fe544c7..dd308571 100644 --- a/tests/extension/thread_/ext_ram/test_thread_ext_ram.py +++ b/tests/extension/thread_/ext_ram/test_thread_ext_ram.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_ext_ram.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/ext_ram/thread_ext_ram.py b/tests/extension/thread_/ext_ram/thread_ext_ram.py index e06b2655..f97c8e6c 100644 --- a/tests/extension/thread_/ext_ram/thread_ext_ram.py +++ b/tests/extension/thread_/ext_ram/thread_ext_ram.py @@ -104,9 +104,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/fifo/test_thread_fifo.py b/tests/extension/thread_/fifo/test_thread_fifo.py index 376a30d0..7a367a4a 100644 --- a/tests/extension/thread_/fifo/test_thread_fifo.py +++ b/tests/extension/thread_/fifo/test_thread_fifo.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_fifo.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/fifo/thread_fifo.py b/tests/extension/thread_/fifo/thread_fifo.py index 2d2836d8..4abac135 100644 --- a/tests/extension/thread_/fifo/thread_fifo.py +++ b/tests/extension/thread_/fifo/thread_fifo.py @@ -89,9 +89,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/fifo_multithread/test_thread_fifo_multithread.py b/tests/extension/thread_/fifo_multithread/test_thread_fifo_multithread.py index cb58957e..23f53e94 100644 --- a/tests/extension/thread_/fifo_multithread/test_thread_fifo_multithread.py +++ b/tests/extension/thread_/fifo_multithread/test_thread_fifo_multithread.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_fifo_multithread.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/fifo_multithread/thread_fifo_multithread.py b/tests/extension/thread_/fifo_multithread/thread_fifo_multithread.py index 1c15a97c..13cae542 100644 --- a/tests/extension/thread_/fifo_multithread/thread_fifo_multithread.py +++ b/tests/extension/thread_/fifo_multithread/thread_fifo_multithread.py @@ -124,9 +124,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/fifo_tmp_name/test_thread_fifo_tmp_name.py b/tests/extension/thread_/fifo_tmp_name/test_thread_fifo_tmp_name.py index 9a67e6c8..2f5d01af 100644 --- a/tests/extension/thread_/fifo_tmp_name/test_thread_fifo_tmp_name.py +++ b/tests/extension/thread_/fifo_tmp_name/test_thread_fifo_tmp_name.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_fifo_tmp_name.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/fifo_tmp_name/thread_fifo_tmp_name.py b/tests/extension/thread_/fifo_tmp_name/thread_fifo_tmp_name.py index 18909d04..40ae7fb7 100644 --- a/tests/extension/thread_/fifo_tmp_name/thread_fifo_tmp_name.py +++ b/tests/extension/thread_/fifo_tmp_name/thread_fifo_tmp_name.py @@ -19,7 +19,7 @@ def mkLed(): datawidth = 32 addrwidth = 4 myfifo = vthread.FIFO(m, 'myfifo', clk, rst, datawidth, addrwidth, - itype='TmpWire', otype='TmpWire') + itype='TmpWire', otype='TmpWire') def blink(times): for i in range(times): @@ -90,9 +90,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/fifo_try/test_thread_fifo_try.py b/tests/extension/thread_/fifo_try/test_thread_fifo_try.py index 49826669..0ef4a6ce 100644 --- a/tests/extension/thread_/fifo_try/test_thread_fifo_try.py +++ b/tests/extension/thread_/fifo_try/test_thread_fifo_try.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_fifo_try.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/fifo_try/thread_fifo_try.py b/tests/extension/thread_/fifo_try/thread_fifo_try.py index 151e5fd2..7286f175 100644 --- a/tests/extension/thread_/fifo_try/thread_fifo_try.py +++ b/tests/extension/thread_/fifo_try/thread_fifo_try.py @@ -96,9 +96,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/fixed_fifo/test_thread_fixed_fifo.py b/tests/extension/thread_/fixed_fifo/test_thread_fixed_fifo.py index 83ad2b03..5b279654 100644 --- a/tests/extension/thread_/fixed_fifo/test_thread_fixed_fifo.py +++ b/tests/extension/thread_/fixed_fifo/test_thread_fixed_fifo.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_fixed_fifo.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/fixed_fifo/thread_fixed_fifo.py b/tests/extension/thread_/fixed_fifo/thread_fixed_fifo.py index dfeb9be8..0027ef0d 100644 --- a/tests/extension/thread_/fixed_fifo/thread_fixed_fifo.py +++ b/tests/extension/thread_/fixed_fifo/thread_fixed_fifo.py @@ -90,9 +90,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/fixed_fifo_try/test_thread_fixed_fifo_try.py b/tests/extension/thread_/fixed_fifo_try/test_thread_fixed_fifo_try.py index 0625d18f..6e851c8c 100644 --- a/tests/extension/thread_/fixed_fifo_try/test_thread_fixed_fifo_try.py +++ b/tests/extension/thread_/fixed_fifo_try/test_thread_fixed_fifo_try.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_fixed_fifo_try.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/fixed_fifo_try/thread_fixed_fifo_try.py b/tests/extension/thread_/fixed_fifo_try/thread_fixed_fifo_try.py index bb33cb7a..5b2e6778 100644 --- a/tests/extension/thread_/fixed_fifo_try/thread_fixed_fifo_try.py +++ b/tests/extension/thread_/fixed_fifo_try/thread_fixed_fifo_try.py @@ -97,9 +97,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/fixed_ram/test_thread_fixed_ram.py b/tests/extension/thread_/fixed_ram/test_thread_fixed_ram.py index 0340a2b6..23c51676 100644 --- a/tests/extension/thread_/fixed_ram/test_thread_fixed_ram.py +++ b/tests/extension/thread_/fixed_ram/test_thread_fixed_ram.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_fixed_ram.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/fixed_ram/thread_fixed_ram.py b/tests/extension/thread_/fixed_ram/thread_fixed_ram.py index f03c35e6..147d9d31 100644 --- a/tests/extension/thread_/fixed_ram/thread_fixed_ram.py +++ b/tests/extension/thread_/fixed_ram/thread_fixed_ram.py @@ -101,9 +101,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/fixed_ram_initvals/test_thread_fixed_ram_initvals.py b/tests/extension/thread_/fixed_ram_initvals/test_thread_fixed_ram_initvals.py index 478920b0..ba1d259c 100644 --- a/tests/extension/thread_/fixed_ram_initvals/test_thread_fixed_ram_initvals.py +++ b/tests/extension/thread_/fixed_ram_initvals/test_thread_fixed_ram_initvals.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_fixed_ram_initvals.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/fixed_ram_initvals/thread_fixed_ram_initvals.py b/tests/extension/thread_/fixed_ram_initvals/thread_fixed_ram_initvals.py index 5fe20cf0..050512f4 100644 --- a/tests/extension/thread_/fixed_ram_initvals/thread_fixed_ram_initvals.py +++ b/tests/extension/thread_/fixed_ram_initvals/thread_fixed_ram_initvals.py @@ -116,9 +116,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/ipxact_axi/test_thread_ipxact_axi.py b/tests/extension/thread_/ipxact_axi/test_thread_ipxact_axi.py index 18c818b2..1ed6d314 100644 --- a/tests/extension/thread_/ipxact_axi/test_thread_ipxact_axi.py +++ b/tests/extension/thread_/ipxact_axi/test_thread_ipxact_axi.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_ipxact_axi.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/ipxact_axi/thread_ipxact_axi.py b/tests/extension/thread_/ipxact_axi/thread_ipxact_axi.py index 081c6c5c..54848c01 100644 --- a/tests/extension/thread_/ipxact_axi/thread_ipxact_axi.py +++ b/tests/extension/thread_/ipxact_axi/thread_ipxact_axi.py @@ -195,9 +195,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/ipxact_axi_active_low_reset/test_thread_ipxact_axi_active_low_reset.py b/tests/extension/thread_/ipxact_axi_active_low_reset/test_thread_ipxact_axi_active_low_reset.py index 2e106717..c3253bd4 100644 --- a/tests/extension/thread_/ipxact_axi_active_low_reset/test_thread_ipxact_axi_active_low_reset.py +++ b/tests/extension/thread_/ipxact_axi_active_low_reset/test_thread_ipxact_axi_active_low_reset.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_ipxact_axi_active_low_reset.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/ipxact_axi_active_low_reset/thread_ipxact_axi_active_low_reset.py b/tests/extension/thread_/ipxact_axi_active_low_reset/thread_ipxact_axi_active_low_reset.py index 46ebac65..eec22a8a 100644 --- a/tests/extension/thread_/ipxact_axi_active_low_reset/thread_ipxact_axi_active_low_reset.py +++ b/tests/extension/thread_/ipxact_axi_active_low_reset/thread_ipxact_axi_active_low_reset.py @@ -207,9 +207,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/memorymodel/test_thread_memorymodel.py b/tests/extension/thread_/memorymodel/test_thread_memorymodel.py index aa6be36b..98cd8d1d 100644 --- a/tests/extension/thread_/memorymodel/test_thread_memorymodel.py +++ b/tests/extension/thread_/memorymodel/test_thread_memorymodel.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_memorymodel.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/memorymodel/thread_memorymodel.py b/tests/extension/thread_/memorymodel/thread_memorymodel.py index 53bff1ef..4e1cbb00 100644 --- a/tests/extension/thread_/memorymodel/thread_memorymodel.py +++ b/tests/extension/thread_/memorymodel/thread_memorymodel.py @@ -181,9 +181,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/memorymodel_fast/test_thread_memorymodel_fast.py b/tests/extension/thread_/memorymodel_fast/test_thread_memorymodel_fast.py index 07b87d67..e0014561 100644 --- a/tests/extension/thread_/memorymodel_fast/test_thread_memorymodel_fast.py +++ b/tests/extension/thread_/memorymodel_fast/test_thread_memorymodel_fast.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_memorymodel_fast.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/memorymodel_fast/thread_memorymodel_fast.py b/tests/extension/thread_/memorymodel_fast/thread_memorymodel_fast.py index 08f644dd..208d6de3 100644 --- a/tests/extension/thread_/memorymodel_fast/thread_memorymodel_fast.py +++ b/tests/extension/thread_/memorymodel_fast/thread_memorymodel_fast.py @@ -186,9 +186,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/memorymodel_readwrite/test_thread_memorymodel_readwrite.py b/tests/extension/thread_/memorymodel_readwrite/test_thread_memorymodel_readwrite.py index 10a7fa8b..f7662ce7 100644 --- a/tests/extension/thread_/memorymodel_readwrite/test_thread_memorymodel_readwrite.py +++ b/tests/extension/thread_/memorymodel_readwrite/test_thread_memorymodel_readwrite.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_memorymodel_readwrite.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/memorymodel_readwrite/thread_memorymodel_readwrite.py b/tests/extension/thread_/memorymodel_readwrite/thread_memorymodel_readwrite.py index b90b92c4..6374e30c 100644 --- a/tests/extension/thread_/memorymodel_readwrite/thread_memorymodel_readwrite.py +++ b/tests/extension/thread_/memorymodel_readwrite/thread_memorymodel_readwrite.py @@ -185,9 +185,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/memorymodel_readwrite_narrow/test_thread_memorymodel_readwrite_narrow.py b/tests/extension/thread_/memorymodel_readwrite_narrow/test_thread_memorymodel_readwrite_narrow.py index 59409f15..3d62102f 100644 --- a/tests/extension/thread_/memorymodel_readwrite_narrow/test_thread_memorymodel_readwrite_narrow.py +++ b/tests/extension/thread_/memorymodel_readwrite_narrow/test_thread_memorymodel_readwrite_narrow.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_memorymodel_readwrite_narrow.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/memorymodel_readwrite_narrow/thread_memorymodel_readwrite_narrow.py b/tests/extension/thread_/memorymodel_readwrite_narrow/thread_memorymodel_readwrite_narrow.py index 7d42fecb..05531145 100644 --- a/tests/extension/thread_/memorymodel_readwrite_narrow/thread_memorymodel_readwrite_narrow.py +++ b/tests/extension/thread_/memorymodel_readwrite_narrow/thread_memorymodel_readwrite_narrow.py @@ -189,9 +189,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/memorymodel_set_memory/test_thread_memorymodel_set_memory.py b/tests/extension/thread_/memorymodel_set_memory/test_thread_memorymodel_set_memory.py index 46dcb71d..7a7df1a0 100644 --- a/tests/extension/thread_/memorymodel_set_memory/test_thread_memorymodel_set_memory.py +++ b/tests/extension/thread_/memorymodel_set_memory/test_thread_memorymodel_set_memory.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_memorymodel_set_memory.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/memorymodel_set_memory/thread_memorymodel_set_memory.py b/tests/extension/thread_/memorymodel_set_memory/thread_memorymodel_set_memory.py index 3de7fdd4..c27fe4bc 100644 --- a/tests/extension/thread_/memorymodel_set_memory/thread_memorymodel_set_memory.py +++ b/tests/extension/thread_/memorymodel_set_memory/thread_memorymodel_set_memory.py @@ -174,9 +174,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/memorymodel_set_memory_narrow/test_thread_memorymodel_set_memory_narrow.py b/tests/extension/thread_/memorymodel_set_memory_narrow/test_thread_memorymodel_set_memory_narrow.py index 9bf49beb..26805e1f 100644 --- a/tests/extension/thread_/memorymodel_set_memory_narrow/test_thread_memorymodel_set_memory_narrow.py +++ b/tests/extension/thread_/memorymodel_set_memory_narrow/test_thread_memorymodel_set_memory_narrow.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_memorymodel_set_memory_narrow.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/memorymodel_set_memory_narrow/thread_memorymodel_set_memory_narrow.py b/tests/extension/thread_/memorymodel_set_memory_narrow/thread_memorymodel_set_memory_narrow.py index 797a274f..7829172b 100644 --- a/tests/extension/thread_/memorymodel_set_memory_narrow/thread_memorymodel_set_memory_narrow.py +++ b/tests/extension/thread_/memorymodel_set_memory_narrow/thread_memorymodel_set_memory_narrow.py @@ -179,9 +179,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/multibank_nested_ram_dma/test_thread_multibank_nested_ram_dma.py b/tests/extension/thread_/multibank_nested_ram_dma/test_thread_multibank_nested_ram_dma.py index 9f71f437..521cc04a 100644 --- a/tests/extension/thread_/multibank_nested_ram_dma/test_thread_multibank_nested_ram_dma.py +++ b/tests/extension/thread_/multibank_nested_ram_dma/test_thread_multibank_nested_ram_dma.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_multibank_nested_ram_dma.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/multibank_nested_ram_dma/thread_multibank_nested_ram_dma.py b/tests/extension/thread_/multibank_nested_ram_dma/thread_multibank_nested_ram_dma.py index f4d172e4..0351db22 100644 --- a/tests/extension/thread_/multibank_nested_ram_dma/thread_multibank_nested_ram_dma.py +++ b/tests/extension/thread_/multibank_nested_ram_dma/thread_multibank_nested_ram_dma.py @@ -164,9 +164,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/multibank_nested_ram_dma_block/test_thread_multibank_nested_ram_dma_block.py b/tests/extension/thread_/multibank_nested_ram_dma_block/test_thread_multibank_nested_ram_dma_block.py index 0e46b98d..8469a1f1 100644 --- a/tests/extension/thread_/multibank_nested_ram_dma_block/test_thread_multibank_nested_ram_dma_block.py +++ b/tests/extension/thread_/multibank_nested_ram_dma_block/test_thread_multibank_nested_ram_dma_block.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_multibank_nested_ram_dma_block.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/multibank_nested_ram_dma_block/thread_multibank_nested_ram_dma_block.py b/tests/extension/thread_/multibank_nested_ram_dma_block/thread_multibank_nested_ram_dma_block.py index 9f72bc3d..d775cd4e 100644 --- a/tests/extension/thread_/multibank_nested_ram_dma_block/thread_multibank_nested_ram_dma_block.py +++ b/tests/extension/thread_/multibank_nested_ram_dma_block/thread_multibank_nested_ram_dma_block.py @@ -209,9 +209,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/multibank_nested_ram_dma_block_non_poweroftwo/test_thread_multibank_nested_ram_dma_block_non_poweroftwo.py b/tests/extension/thread_/multibank_nested_ram_dma_block_non_poweroftwo/test_thread_multibank_nested_ram_dma_block_non_poweroftwo.py index 6f1e0888..cd4d0e33 100644 --- a/tests/extension/thread_/multibank_nested_ram_dma_block_non_poweroftwo/test_thread_multibank_nested_ram_dma_block_non_poweroftwo.py +++ b/tests/extension/thread_/multibank_nested_ram_dma_block_non_poweroftwo/test_thread_multibank_nested_ram_dma_block_non_poweroftwo.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_multibank_nested_ram_dma_block_non_poweroftwo.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/multibank_nested_ram_dma_block_non_poweroftwo/thread_multibank_nested_ram_dma_block_non_poweroftwo.py b/tests/extension/thread_/multibank_nested_ram_dma_block_non_poweroftwo/thread_multibank_nested_ram_dma_block_non_poweroftwo.py index dc2fdb8a..e98dcdd4 100644 --- a/tests/extension/thread_/multibank_nested_ram_dma_block_non_poweroftwo/thread_multibank_nested_ram_dma_block_non_poweroftwo.py +++ b/tests/extension/thread_/multibank_nested_ram_dma_block_non_poweroftwo/thread_multibank_nested_ram_dma_block_non_poweroftwo.py @@ -209,9 +209,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/multibank_ram/test_thread_multibank_ram.py b/tests/extension/thread_/multibank_ram/test_thread_multibank_ram.py index fa514cb3..629074a5 100644 --- a/tests/extension/thread_/multibank_ram/test_thread_multibank_ram.py +++ b/tests/extension/thread_/multibank_ram/test_thread_multibank_ram.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_multibank_ram.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/multibank_ram/thread_multibank_ram.py b/tests/extension/thread_/multibank_ram/thread_multibank_ram.py index 8d59d163..cfaa2ff7 100644 --- a/tests/extension/thread_/multibank_ram/thread_multibank_ram.py +++ b/tests/extension/thread_/multibank_ram/thread_multibank_ram.py @@ -102,9 +102,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/multibank_ram_bank/test_thread_multibank_ram_bank.py b/tests/extension/thread_/multibank_ram_bank/test_thread_multibank_ram_bank.py index f45a787a..5aee471f 100644 --- a/tests/extension/thread_/multibank_ram_bank/test_thread_multibank_ram_bank.py +++ b/tests/extension/thread_/multibank_ram_bank/test_thread_multibank_ram_bank.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_multibank_ram_bank.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/multibank_ram_bank/thread_multibank_ram_bank.py b/tests/extension/thread_/multibank_ram_bank/thread_multibank_ram_bank.py index 3320d993..18296b37 100644 --- a/tests/extension/thread_/multibank_ram_bank/thread_multibank_ram_bank.py +++ b/tests/extension/thread_/multibank_ram_bank/thread_multibank_ram_bank.py @@ -107,9 +107,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/multibank_ram_dma/test_thread_multibank_ram_dma.py b/tests/extension/thread_/multibank_ram_dma/test_thread_multibank_ram_dma.py index 21fa20f4..72858d06 100644 --- a/tests/extension/thread_/multibank_ram_dma/test_thread_multibank_ram_dma.py +++ b/tests/extension/thread_/multibank_ram_dma/test_thread_multibank_ram_dma.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_axi_dma.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/multibank_ram_dma/thread_multibank_ram_dma.py b/tests/extension/thread_/multibank_ram_dma/thread_multibank_ram_dma.py index 301dbda8..cf7ea49e 100644 --- a/tests/extension/thread_/multibank_ram_dma/thread_multibank_ram_dma.py +++ b/tests/extension/thread_/multibank_ram_dma/thread_multibank_ram_dma.py @@ -148,9 +148,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/multibank_ram_dma_bank/test_thread_multibank_ram_dma_bank.py b/tests/extension/thread_/multibank_ram_dma_bank/test_thread_multibank_ram_dma_bank.py index fb366633..104311ac 100644 --- a/tests/extension/thread_/multibank_ram_dma_bank/test_thread_multibank_ram_dma_bank.py +++ b/tests/extension/thread_/multibank_ram_dma_bank/test_thread_multibank_ram_dma_bank.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_multibank_ram_dma_bank.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/multibank_ram_dma_bank/thread_multibank_ram_dma_bank.py b/tests/extension/thread_/multibank_ram_dma_bank/thread_multibank_ram_dma_bank.py index fa600afe..7592b4af 100644 --- a/tests/extension/thread_/multibank_ram_dma_bank/thread_multibank_ram_dma_bank.py +++ b/tests/extension/thread_/multibank_ram_dma_bank/thread_multibank_ram_dma_bank.py @@ -150,9 +150,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/multibank_ram_dma_bcast/test_thread_multibank_ram_dma_bcast.py b/tests/extension/thread_/multibank_ram_dma_bcast/test_thread_multibank_ram_dma_bcast.py index 3a76689a..c1cdbb8a 100644 --- a/tests/extension/thread_/multibank_ram_dma_bcast/test_thread_multibank_ram_dma_bcast.py +++ b/tests/extension/thread_/multibank_ram_dma_bcast/test_thread_multibank_ram_dma_bcast.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_multibank_ram_dma_bcast.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/multibank_ram_dma_bcast/thread_multibank_ram_dma_bcast.py b/tests/extension/thread_/multibank_ram_dma_bcast/thread_multibank_ram_dma_bcast.py index fb97278a..65049711 100644 --- a/tests/extension/thread_/multibank_ram_dma_bcast/thread_multibank_ram_dma_bcast.py +++ b/tests/extension/thread_/multibank_ram_dma_bcast/thread_multibank_ram_dma_bcast.py @@ -151,9 +151,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/multibank_ram_dma_block/test_thread_multibank_ram_dma_block.py b/tests/extension/thread_/multibank_ram_dma_block/test_thread_multibank_ram_dma_block.py index a123630c..aef2c0ba 100644 --- a/tests/extension/thread_/multibank_ram_dma_block/test_thread_multibank_ram_dma_block.py +++ b/tests/extension/thread_/multibank_ram_dma_block/test_thread_multibank_ram_dma_block.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_multibank_ram_dma_block.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/multibank_ram_dma_block/thread_multibank_ram_dma_block.py b/tests/extension/thread_/multibank_ram_dma_block/thread_multibank_ram_dma_block.py index a9af10e3..e5cda9cc 100644 --- a/tests/extension/thread_/multibank_ram_dma_block/thread_multibank_ram_dma_block.py +++ b/tests/extension/thread_/multibank_ram_dma_block/thread_multibank_ram_dma_block.py @@ -210,9 +210,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/multibank_ram_dma_block_non_poweroftwo/test_thread_multibank_ram_dma_block_non_poweroftwo.py b/tests/extension/thread_/multibank_ram_dma_block_non_poweroftwo/test_thread_multibank_ram_dma_block_non_poweroftwo.py index bf15727b..5f11c60d 100644 --- a/tests/extension/thread_/multibank_ram_dma_block_non_poweroftwo/test_thread_multibank_ram_dma_block_non_poweroftwo.py +++ b/tests/extension/thread_/multibank_ram_dma_block_non_poweroftwo/test_thread_multibank_ram_dma_block_non_poweroftwo.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_multibank_ram_dma_block_non_poweroftwo.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/multibank_ram_dma_block_non_poweroftwo/thread_multibank_ram_dma_block_non_poweroftwo.py b/tests/extension/thread_/multibank_ram_dma_block_non_poweroftwo/thread_multibank_ram_dma_block_non_poweroftwo.py index b0e55031..b6ae4cb9 100644 --- a/tests/extension/thread_/multibank_ram_dma_block_non_poweroftwo/thread_multibank_ram_dma_block_non_poweroftwo.py +++ b/tests/extension/thread_/multibank_ram_dma_block_non_poweroftwo/thread_multibank_ram_dma_block_non_poweroftwo.py @@ -210,9 +210,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/multibank_ram_dma_narrow/test_thread_multibank_ram_dma_narrow.py b/tests/extension/thread_/multibank_ram_dma_narrow/test_thread_multibank_ram_dma_narrow.py index d5ca05e1..fd32f280 100644 --- a/tests/extension/thread_/multibank_ram_dma_narrow/test_thread_multibank_ram_dma_narrow.py +++ b/tests/extension/thread_/multibank_ram_dma_narrow/test_thread_multibank_ram_dma_narrow.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_multibank_ram_dma_narrow.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/multibank_ram_dma_narrow/thread_multibank_ram_dma_narrow.py b/tests/extension/thread_/multibank_ram_dma_narrow/thread_multibank_ram_dma_narrow.py index 3be0ffe3..a3c93d3d 100644 --- a/tests/extension/thread_/multibank_ram_dma_narrow/thread_multibank_ram_dma_narrow.py +++ b/tests/extension/thread_/multibank_ram_dma_narrow/thread_multibank_ram_dma_narrow.py @@ -161,9 +161,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/multibank_ram_dma_packed/test_thread_multibank_ram_dma_packed.py b/tests/extension/thread_/multibank_ram_dma_packed/test_thread_multibank_ram_dma_packed.py index f98a10f4..b252dbf1 100644 --- a/tests/extension/thread_/multibank_ram_dma_packed/test_thread_multibank_ram_dma_packed.py +++ b/tests/extension/thread_/multibank_ram_dma_packed/test_thread_multibank_ram_dma_packed.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_multibank_ram_dma_packed.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/multibank_ram_dma_packed/thread_multibank_ram_dma_packed.py b/tests/extension/thread_/multibank_ram_dma_packed/thread_multibank_ram_dma_packed.py index 668ee6b8..c1d8baa0 100644 --- a/tests/extension/thread_/multibank_ram_dma_packed/thread_multibank_ram_dma_packed.py +++ b/tests/extension/thread_/multibank_ram_dma_packed/thread_multibank_ram_dma_packed.py @@ -162,9 +162,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/multibank_ram_dma_packed_long/test_thread_multibank_ram_dma_packed_long.py b/tests/extension/thread_/multibank_ram_dma_packed_long/test_thread_multibank_ram_dma_packed_long.py index 40cadb06..b8890105 100644 --- a/tests/extension/thread_/multibank_ram_dma_packed_long/test_thread_multibank_ram_dma_packed_long.py +++ b/tests/extension/thread_/multibank_ram_dma_packed_long/test_thread_multibank_ram_dma_packed_long.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_multibank_ram_dma_packed_long.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/multibank_ram_dma_packed_long/thread_multibank_ram_dma_packed_long.py b/tests/extension/thread_/multibank_ram_dma_packed_long/thread_multibank_ram_dma_packed_long.py index 4bf9a882..f975ce8a 100644 --- a/tests/extension/thread_/multibank_ram_dma_packed_long/thread_multibank_ram_dma_packed_long.py +++ b/tests/extension/thread_/multibank_ram_dma_packed_long/thread_multibank_ram_dma_packed_long.py @@ -158,9 +158,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/multibank_ram_dma_packed_narrow/test_thread_multibank_ram_dma_packed_narrow.py b/tests/extension/thread_/multibank_ram_dma_packed_narrow/test_thread_multibank_ram_dma_packed_narrow.py index 7b67c7d6..1f746c2b 100644 --- a/tests/extension/thread_/multibank_ram_dma_packed_narrow/test_thread_multibank_ram_dma_packed_narrow.py +++ b/tests/extension/thread_/multibank_ram_dma_packed_narrow/test_thread_multibank_ram_dma_packed_narrow.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_multibank_ram_dma_packed_narrow.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/multibank_ram_dma_packed_narrow/thread_multibank_ram_dma_packed_narrow.py b/tests/extension/thread_/multibank_ram_dma_packed_narrow/thread_multibank_ram_dma_packed_narrow.py index 869435b5..e3616cdd 100644 --- a/tests/extension/thread_/multibank_ram_dma_packed_narrow/thread_multibank_ram_dma_packed_narrow.py +++ b/tests/extension/thread_/multibank_ram_dma_packed_narrow/thread_multibank_ram_dma_packed_narrow.py @@ -162,9 +162,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/multibank_ram_dma_packed_wide/test_thread_multibank_ram_dma_packed_wide.py b/tests/extension/thread_/multibank_ram_dma_packed_wide/test_thread_multibank_ram_dma_packed_wide.py index f9a4d94e..c0dae5c3 100644 --- a/tests/extension/thread_/multibank_ram_dma_packed_wide/test_thread_multibank_ram_dma_packed_wide.py +++ b/tests/extension/thread_/multibank_ram_dma_packed_wide/test_thread_multibank_ram_dma_packed_wide.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_multibank_ram_dma_packed_wide.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/multibank_ram_dma_packed_wide/thread_multibank_ram_dma_packed_wide.py b/tests/extension/thread_/multibank_ram_dma_packed_wide/thread_multibank_ram_dma_packed_wide.py index 8524bc3c..a0d53a36 100644 --- a/tests/extension/thread_/multibank_ram_dma_packed_wide/thread_multibank_ram_dma_packed_wide.py +++ b/tests/extension/thread_/multibank_ram_dma_packed_wide/thread_multibank_ram_dma_packed_wide.py @@ -160,9 +160,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/multibank_ram_dma_wide/test_thread_multibank_ram_dma_wide.py b/tests/extension/thread_/multibank_ram_dma_wide/test_thread_multibank_ram_dma_wide.py index 8b6a50de..f0aecf76 100644 --- a/tests/extension/thread_/multibank_ram_dma_wide/test_thread_multibank_ram_dma_wide.py +++ b/tests/extension/thread_/multibank_ram_dma_wide/test_thread_multibank_ram_dma_wide.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_multibank_ram_dma_wide.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/multibank_ram_dma_wide/thread_multibank_ram_dma_wide.py b/tests/extension/thread_/multibank_ram_dma_wide/thread_multibank_ram_dma_wide.py index 51fc5da5..0334524e 100644 --- a/tests/extension/thread_/multibank_ram_dma_wide/thread_multibank_ram_dma_wide.py +++ b/tests/extension/thread_/multibank_ram_dma_wide/thread_multibank_ram_dma_wide.py @@ -149,9 +149,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/multibank_ram_rtl_connect/test_thread_multibank_ram_rtl_connect.py b/tests/extension/thread_/multibank_ram_rtl_connect/test_thread_multibank_ram_rtl_connect.py index daf504f3..a7fcefa4 100644 --- a/tests/extension/thread_/multibank_ram_rtl_connect/test_thread_multibank_ram_rtl_connect.py +++ b/tests/extension/thread_/multibank_ram_rtl_connect/test_thread_multibank_ram_rtl_connect.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_multibank_ram_rtl_connect.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/multibank_ram_rtl_connect/thread_multibank_ram_rtl_connect.py b/tests/extension/thread_/multibank_ram_rtl_connect/thread_multibank_ram_rtl_connect.py index b6418eda..74aaba15 100644 --- a/tests/extension/thread_/multibank_ram_rtl_connect/thread_multibank_ram_rtl_connect.py +++ b/tests/extension/thread_/multibank_ram_rtl_connect/thread_multibank_ram_rtl_connect.py @@ -74,7 +74,7 @@ def mkLed(): fsm.Delay(2)( sum.add(rdata), Display('rdata = %d', rdata), - If(NotEql(rdata,i))(all_ok(0)), + If(NotEql(rdata, i))(all_ok(0)), i.inc(), ) fsm.If(addr == read_size - 2).goto_next() @@ -155,9 +155,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/multibank_ram_style/test_thread_multibank_ram_style.py b/tests/extension/thread_/multibank_ram_style/test_thread_multibank_ram_style.py index 456bfd57..677d448d 100644 --- a/tests/extension/thread_/multibank_ram_style/test_thread_multibank_ram_style.py +++ b/tests/extension/thread_/multibank_ram_style/test_thread_multibank_ram_style.py @@ -520,7 +520,7 @@ def test(request): rslt = thread_multibank_ram_style.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') veriloggen.reset() diff --git a/tests/extension/thread_/multibank_ram_style/thread_multibank_ram_style.py b/tests/extension/thread_/multibank_ram_style/thread_multibank_ram_style.py index 1c6cb684..591346fe 100644 --- a/tests/extension/thread_/multibank_ram_style/thread_multibank_ram_style.py +++ b/tests/extension/thread_/multibank_ram_style/thread_multibank_ram_style.py @@ -99,9 +99,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/multiport_memorymodel/test_thread_multiport_memorymodel.py b/tests/extension/thread_/multiport_memorymodel/test_thread_multiport_memorymodel.py index c188e133..8635b70d 100644 --- a/tests/extension/thread_/multiport_memorymodel/test_thread_multiport_memorymodel.py +++ b/tests/extension/thread_/multiport_memorymodel/test_thread_multiport_memorymodel.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_multiport_memorymodel.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/multiport_memorymodel/thread_multiport_memorymodel.py b/tests/extension/thread_/multiport_memorymodel/thread_multiport_memorymodel.py index 3b519060..66150607 100644 --- a/tests/extension/thread_/multiport_memorymodel/thread_multiport_memorymodel.py +++ b/tests/extension/thread_/multiport_memorymodel/thread_multiport_memorymodel.py @@ -205,9 +205,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/multiport_memorymodel_split_read_write/test_thread_multiport_memorymodel_split_read_write.py b/tests/extension/thread_/multiport_memorymodel_split_read_write/test_thread_multiport_memorymodel_split_read_write.py index 30a324c5..131793fa 100644 --- a/tests/extension/thread_/multiport_memorymodel_split_read_write/test_thread_multiport_memorymodel_split_read_write.py +++ b/tests/extension/thread_/multiport_memorymodel_split_read_write/test_thread_multiport_memorymodel_split_read_write.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_multiport_memorymodel_split_read_write.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/multiport_memorymodel_split_read_write/thread_multiport_memorymodel_split_read_write.py b/tests/extension/thread_/multiport_memorymodel_split_read_write/thread_multiport_memorymodel_split_read_write.py index f323db74..4f9f013d 100644 --- a/tests/extension/thread_/multiport_memorymodel_split_read_write/thread_multiport_memorymodel_split_read_write.py +++ b/tests/extension/thread_/multiport_memorymodel_split_read_write/thread_multiport_memorymodel_split_read_write.py @@ -226,9 +226,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/mutex_ram/test_thread_mutex_ram.py b/tests/extension/thread_/mutex_ram/test_thread_mutex_ram.py index 8d8c38a0..43ac9c20 100644 --- a/tests/extension/thread_/mutex_ram/test_thread_mutex_ram.py +++ b/tests/extension/thread_/mutex_ram/test_thread_mutex_ram.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_mutex_ram.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/mutex_ram/thread_mutex_ram.py b/tests/extension/thread_/mutex_ram/thread_mutex_ram.py index 18cc743e..60302517 100644 --- a/tests/extension/thread_/mutex_ram/thread_mutex_ram.py +++ b/tests/extension/thread_/mutex_ram/thread_mutex_ram.py @@ -116,9 +116,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/print_fstrings/Makefile b/tests/extension/thread_/print_fstrings/Makefile new file mode 100644 index 00000000..40674948 --- /dev/null +++ b/tests/extension/thread_/print_fstrings/Makefile @@ -0,0 +1,29 @@ +TARGET=$(shell ls *.py | grep -v test | grep -v parsetab.py) +ARGS= + +PYTHON=python3 +#PYTHON=python +#OPT=-m pdb +#OPT=-m cProfile -s time +#OPT=-m cProfile -o profile.rslt + +.PHONY: all +all: test + +.PHONY: run +run: + $(PYTHON) $(OPT) $(TARGET) $(ARGS) + +.PHONY: test +test: + $(PYTHON) -m pytest -vv + +.PHONY: check +check: + $(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v + iverilog -tnull -Wall tmp.v + rm -f tmp.v + +.PHONY: clean +clean: + rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v *.vcd \ No newline at end of file diff --git a/tests/extension/thread_/print_fstrings/test_thread_print_fstrings.py b/tests/extension/thread_/print_fstrings/test_thread_print_fstrings.py new file mode 100644 index 00000000..d96721f4 --- /dev/null +++ b/tests/extension/thread_/print_fstrings/test_thread_print_fstrings.py @@ -0,0 +1,148 @@ +from __future__ import absolute_import +from __future__ import print_function +import veriloggen +import thread_print_fstrings + +expected_verilog = """ +module test +( + +); + + reg CLK; + reg RST; + wire [8-1:0] LED; + + blinkled + uut + ( + .CLK(CLK), + .RST(RST), + .LED(LED) + ); + + + initial begin + CLK = 0; + forever begin + #5 CLK = !CLK; + end + end + + + initial begin + RST = 0; + #100; + RST = 1; + #100; + RST = 0; + #50000; + $finish; + end + + +endmodule + + + +module blinkled +( + input CLK, + input RST, + output reg [8-1:0] LED +); + + reg [10-1:0] CNT; + reg [32-1:0] th_blink; + localparam th_blink_init = 0; + localparam th_blink_1 = 1; + localparam th_blink_2 = 2; + localparam th_blink_3 = 3; + localparam th_blink_4 = 4; + localparam th_blink_5 = 5; + localparam th_blink_6 = 6; + localparam th_blink_7 = 7; + localparam th_blink_8 = 8; + localparam th_blink_9 = 9; + localparam th_blink_10 = 10; + localparam th_blink_11 = 11; + + always @(posedge CLK) begin + if(RST) begin + th_blink <= th_blink_init; + LED <= 0; + CNT <= 0; + end else begin + case(th_blink) + th_blink_init: begin + th_blink <= th_blink_1; + end + th_blink_1: begin + $display("Hello, world!"); + th_blink <= th_blink_2; + end + th_blink_2: begin + if(1) begin + th_blink <= th_blink_3; + end else begin + th_blink <= th_blink_11; + end + end + th_blink_3: begin + LED <= LED + 1; + th_blink <= th_blink_4; + end + th_blink_4: begin + CNT <= CNT + 3; + th_blink <= th_blink_5; + end + th_blink_5: begin + if(LED % 70 == 0) begin + th_blink <= th_blink_6; + end else begin + th_blink <= th_blink_10; + end + end + th_blink_6: begin + $display(""); + th_blink <= th_blink_7; + end + th_blink_7: begin + $display("led = %0d (%b)", LED, LED); + th_blink <= th_blink_8; + end + th_blink_8: begin + $display("cnt = %0d (%b)", CNT, CNT); + th_blink <= th_blink_9; + end + th_blink_9: begin + $display("cnt + led = %d", (CNT + LED)); + th_blink <= th_blink_10; + end + th_blink_10: begin + th_blink <= th_blink_2; + end + endcase + end + end + + +endmodule +""" + + +def test(): + veriloggen.reset() + test_module = thread_print_fstrings.mkTest() + code = test_module.to_verilog() + + from pyverilog.vparser.parser import VerilogParser + from pyverilog.ast_code_generator.codegen import ASTCodeGenerator + parser = VerilogParser() + expected_ast = parser.parse(expected_verilog) + codegen = ASTCodeGenerator() + expected_code = codegen.visit(expected_ast) + + assert(expected_code == code) + +test() diff --git a/tests/extension/thread_/print_fstrings/thread_print_fstrings.py b/tests/extension/thread_/print_fstrings/thread_print_fstrings.py new file mode 100644 index 00000000..86427a15 --- /dev/null +++ b/tests/extension/thread_/print_fstrings/thread_print_fstrings.py @@ -0,0 +1,75 @@ +from __future__ import absolute_import +from __future__ import print_function +import sys +import os + +# the next line can be removed after installation +sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname( + os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) + +from veriloggen import * +import veriloggen.thread as vthread + + +def mkLed(): + m = Module('blinkled') + clk = m.Input('CLK') + rst = m.Input('RST') + led = m.OutputReg('LED', 8, initval=0) + cnt = m.Reg('CNT', 10, initval=0) + + def blink(): + print('Hello, world!') + while True: + led.value += 1 + cnt.value += 3 + if led.value % 70 == 0: + print() + print('led = %0d (%b)' % (led, led)) + print(f'{cnt = :0d} ({cnt:b})') + print(f'cnt + led = {cnt + led}') + + th = vthread.Thread(m, 'th_blink', clk, rst, blink) + fsm = th.start() + + return m + + +def mkTest(): + m = Module('test') + + # target instance + led = mkLed() + + # copy paras and ports + params = m.copy_params(led) + ports = m.copy_sim_ports(led) + + clk = ports['CLK'] + rst = ports['RST'] + + uut = m.Instance(led, 'uut', + params=m.connect_params(led), + ports=m.connect_ports(led)) + + # vcd_name = os.path.splitext(os.path.basename(__file__))[0] + '.vcd' + # simulation.setup_waveform(m, uut, dumpfile=vcd_name) + simulation.setup_clock(m, clk, hperiod=5) + init = simulation.setup_reset(m, rst, m.make_reset(), period=100) + + init.add( + Delay(50000), + Systask('finish'), + ) + + return m + + +if __name__ == '__main__': + test = mkTest() + verilog = test.to_verilog('tmp.v') + print(verilog) + + sim = simulation.Simulator(test) + rslt = sim.run() + print(rslt) diff --git a/tests/extension/thread_/ram/test_thread_ram.py b/tests/extension/thread_/ram/test_thread_ram.py index 6f6407a8..de2abe22 100644 --- a/tests/extension/thread_/ram/test_thread_ram.py +++ b/tests/extension/thread_/ram/test_thread_ram.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_ram.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/ram/thread_ram.py b/tests/extension/thread_/ram/thread_ram.py index 281c0836..f13f2cf5 100644 --- a/tests/extension/thread_/ram/thread_ram.py +++ b/tests/extension/thread_/ram/thread_ram.py @@ -98,9 +98,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/ram_copy/test_thread_ram_copy.py b/tests/extension/thread_/ram_copy/test_thread_ram_copy.py index dba534a9..54ff3f71 100644 --- a/tests/extension/thread_/ram_copy/test_thread_ram_copy.py +++ b/tests/extension/thread_/ram_copy/test_thread_ram_copy.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_ram_copy.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/ram_copy/thread_ram_copy.py b/tests/extension/thread_/ram_copy/thread_ram_copy.py index 1587b6ca..7a4f3c54 100644 --- a/tests/extension/thread_/ram_copy/thread_ram_copy.py +++ b/tests/extension/thread_/ram_copy/thread_ram_copy.py @@ -102,9 +102,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/ram_copy_pattern/test_thread_ram_copy_pattern.py b/tests/extension/thread_/ram_copy_pattern/test_thread_ram_copy_pattern.py index a802db54..56cfa4c7 100644 --- a/tests/extension/thread_/ram_copy_pattern/test_thread_ram_copy_pattern.py +++ b/tests/extension/thread_/ram_copy_pattern/test_thread_ram_copy_pattern.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_ram_copy_pattern.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/ram_copy_pattern/thread_ram_copy_pattern.py b/tests/extension/thread_/ram_copy_pattern/thread_ram_copy_pattern.py index c388db81..5456b763 100644 --- a/tests/extension/thread_/ram_copy_pattern/thread_ram_copy_pattern.py +++ b/tests/extension/thread_/ram_copy_pattern/thread_ram_copy_pattern.py @@ -104,9 +104,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/ram_initvals/test_thread_ram_initvals.py b/tests/extension/thread_/ram_initvals/test_thread_ram_initvals.py index ad611bc2..887360e0 100644 --- a/tests/extension/thread_/ram_initvals/test_thread_ram_initvals.py +++ b/tests/extension/thread_/ram_initvals/test_thread_ram_initvals.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_ram_initvals.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/ram_initvals/thread_ram_initvals.py b/tests/extension/thread_/ram_initvals/thread_ram_initvals.py index ea40eb88..47095905 100644 --- a/tests/extension/thread_/ram_initvals/thread_ram_initvals.py +++ b/tests/extension/thread_/ram_initvals/thread_ram_initvals.py @@ -106,9 +106,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/ram_initvals_nocheck/test_thread_ram_initvals_nocheck.py b/tests/extension/thread_/ram_initvals_nocheck/test_thread_ram_initvals_nocheck.py index 96da2b18..829abf00 100644 --- a/tests/extension/thread_/ram_initvals_nocheck/test_thread_ram_initvals_nocheck.py +++ b/tests/extension/thread_/ram_initvals_nocheck/test_thread_ram_initvals_nocheck.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_ram_initvals_nocheck.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/ram_initvals_nocheck/thread_ram_initvals_nocheck.py b/tests/extension/thread_/ram_initvals_nocheck/thread_ram_initvals_nocheck.py index 353e4f12..fd15d708 100644 --- a/tests/extension/thread_/ram_initvals_nocheck/thread_ram_initvals_nocheck.py +++ b/tests/extension/thread_/ram_initvals_nocheck/thread_ram_initvals_nocheck.py @@ -107,9 +107,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/ram_own_mutex/test_thread_ram_own_mutex.py b/tests/extension/thread_/ram_own_mutex/test_thread_ram_own_mutex.py index 25be2cff..e9ec9803 100644 --- a/tests/extension/thread_/ram_own_mutex/test_thread_ram_own_mutex.py +++ b/tests/extension/thread_/ram_own_mutex/test_thread_ram_own_mutex.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_ram_own_mutex.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/ram_own_mutex/thread_ram_own_mutex.py b/tests/extension/thread_/ram_own_mutex/thread_ram_own_mutex.py index edc9a62f..43b489fe 100644 --- a/tests/extension/thread_/ram_own_mutex/thread_ram_own_mutex.py +++ b/tests/extension/thread_/ram_own_mutex/thread_ram_own_mutex.py @@ -114,9 +114,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/ram_rtl/test_thread_ram_rtl.py b/tests/extension/thread_/ram_rtl/test_thread_ram_rtl.py index ad4e745f..5119bb10 100644 --- a/tests/extension/thread_/ram_rtl/test_thread_ram_rtl.py +++ b/tests/extension/thread_/ram_rtl/test_thread_ram_rtl.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_ram_rtl.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/ram_rtl/thread_ram_rtl.py b/tests/extension/thread_/ram_rtl/thread_ram_rtl.py index ec3bfd43..75c504fa 100644 --- a/tests/extension/thread_/ram_rtl/thread_ram_rtl.py +++ b/tests/extension/thread_/ram_rtl/thread_ram_rtl.py @@ -146,9 +146,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/ram_rtl_connect/test_thread_ram_rtl_connect.py b/tests/extension/thread_/ram_rtl_connect/test_thread_ram_rtl_connect.py index 709ce492..e776b890 100644 --- a/tests/extension/thread_/ram_rtl_connect/test_thread_ram_rtl_connect.py +++ b/tests/extension/thread_/ram_rtl_connect/test_thread_ram_rtl_connect.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_ram_rtl_connect.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/ram_rtl_connect/thread_ram_rtl_connect.py b/tests/extension/thread_/ram_rtl_connect/thread_ram_rtl_connect.py index 5a8b51d5..f96c6ca8 100644 --- a/tests/extension/thread_/ram_rtl_connect/thread_ram_rtl_connect.py +++ b/tests/extension/thread_/ram_rtl_connect/thread_ram_rtl_connect.py @@ -150,9 +150,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/ram_style/test_thread_ram_style.py b/tests/extension/thread_/ram_style/test_thread_ram_style.py index 617ee08b..c5ca5777 100644 --- a/tests/extension/thread_/ram_style/test_thread_ram_style.py +++ b/tests/extension/thread_/ram_style/test_thread_ram_style.py @@ -309,7 +309,7 @@ def test(request): rslt = thread_ram_style.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') veriloggen.reset() diff --git a/tests/extension/thread_/ram_style/thread_ram_style.py b/tests/extension/thread_/ram_style/thread_ram_style.py index ae51994a..9616c9fa 100644 --- a/tests/extension/thread_/ram_style/thread_ram_style.py +++ b/tests/extension/thread_/ram_style/thread_ram_style.py @@ -99,9 +99,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/ram_tmp_name/test_thread_ram_tmp_name.py b/tests/extension/thread_/ram_tmp_name/test_thread_ram_tmp_name.py index e7a2f1a6..309c3563 100644 --- a/tests/extension/thread_/ram_tmp_name/test_thread_ram_tmp_name.py +++ b/tests/extension/thread_/ram_tmp_name/test_thread_ram_tmp_name.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_ram_tmp_name.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/ram_tmp_name/thread_ram_tmp_name.py b/tests/extension/thread_/ram_tmp_name/thread_ram_tmp_name.py index ed15b53a..46f3fb39 100644 --- a/tests/extension/thread_/ram_tmp_name/thread_ram_tmp_name.py +++ b/tests/extension/thread_/ram_tmp_name/thread_ram_tmp_name.py @@ -99,9 +99,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream/test_thread_stream.py b/tests/extension/thread_/stream/test_thread_stream.py index d81dba2a..42283a71 100644 --- a/tests/extension/thread_/stream/test_thread_stream.py +++ b/tests/extension/thread_/stream/test_thread_stream.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream/thread_stream.py b/tests/extension/thread_/stream/thread_stream.py index 83a26be4..59c65baa 100644 --- a/tests/extension/thread_/stream/thread_stream.py +++ b/tests/extension/thread_/stream/thread_stream.py @@ -132,9 +132,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_add_n/test_thread_stream_add_n.py b/tests/extension/thread_/stream_add_n/test_thread_stream_add_n.py index 2c0b534a..2dbbc354 100644 --- a/tests/extension/thread_/stream_add_n/test_thread_stream_add_n.py +++ b/tests/extension/thread_/stream_add_n/test_thread_stream_add_n.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_add_n.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_add_n/thread_stream_add_n.py b/tests/extension/thread_/stream_add_n/thread_stream_add_n.py index d9836538..6c2eddcb 100644 --- a/tests/extension/thread_/stream_add_n/thread_stream_add_n.py +++ b/tests/extension/thread_/stream_add_n/thread_stream_add_n.py @@ -132,9 +132,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_alias/test_thread_stream_alias.py b/tests/extension/thread_/stream_alias/test_thread_stream_alias.py index 60193ae4..46f57ba4 100644 --- a/tests/extension/thread_/stream_alias/test_thread_stream_alias.py +++ b/tests/extension/thread_/stream_alias/test_thread_stream_alias.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_alias.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_alias/thread_stream_alias.py b/tests/extension/thread_/stream_alias/thread_stream_alias.py index 77d0ce85..40ff3002 100644 --- a/tests/extension/thread_/stream_alias/thread_stream_alias.py +++ b/tests/extension/thread_/stream_alias/thread_stream_alias.py @@ -142,9 +142,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_alias_implicit/test_thread_stream_alias_implicit.py b/tests/extension/thread_/stream_alias_implicit/test_thread_stream_alias_implicit.py index 5e08a985..ef4d5b27 100644 --- a/tests/extension/thread_/stream_alias_implicit/test_thread_stream_alias_implicit.py +++ b/tests/extension/thread_/stream_alias_implicit/test_thread_stream_alias_implicit.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_alias_implicit.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_alias_implicit/thread_stream_alias_implicit.py b/tests/extension/thread_/stream_alias_implicit/thread_stream_alias_implicit.py index 2b605499..c9661b23 100644 --- a/tests/extension/thread_/stream_alias_implicit/thread_stream_alias_implicit.py +++ b/tests/extension/thread_/stream_alias_implicit/thread_stream_alias_implicit.py @@ -142,9 +142,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_axi_stream/test_thread_stream_axi_stream.py b/tests/extension/thread_/stream_axi_stream/test_thread_stream_axi_stream.py index b91ef885..89380a66 100644 --- a/tests/extension/thread_/stream_axi_stream/test_thread_stream_axi_stream.py +++ b/tests/extension/thread_/stream_axi_stream/test_thread_stream_axi_stream.py @@ -238,7 +238,7 @@ (axis_maskaddr_17 == 1)? _saxi_resetval_1 : (axis_maskaddr_17 == 2)? _saxi_resetval_2 : (axis_maskaddr_17 == 3)? _saxi_resetval_3 : 'hx; - reg _saxi_cond_0_1; + reg _saxi_rdata_cond_0_1; assign saxi_wready = _saxi_register_fsm == 3; wire [10-1:0] ram_a_0_addr; wire [32-1:0] ram_a_0_rdata; @@ -657,11 +657,6 @@ always @(posedge CLK) begin if(RST) begin - _axi_c_write_data_busy <= 0; - _axi_c_write_op_sel_buf <= 0; - _axi_c_write_local_addr_buf <= 0; - _axi_c_write_local_stride_buf <= 0; - _axi_c_write_size_buf <= 0; axi_c_tdata <= 0; axi_c_tvalid <= 0; axi_c_tlast <= 0; @@ -671,13 +666,6 @@ axi_c_tvalid <= 0; axi_c_tlast <= 0; end - if((_axi_c_write_data_fsm == 0) && (!_axi_c_write_data_busy && !_axi_c_write_req_fifo_empty && (_axi_c_write_op_sel_fifo == 1))) begin - _axi_c_write_data_busy <= 1; - _axi_c_write_op_sel_buf <= _axi_c_write_op_sel_fifo; - _axi_c_write_local_addr_buf <= _axi_c_write_local_addr_fifo; - _axi_c_write_local_stride_buf <= _axi_c_write_local_stride_fifo; - _axi_c_write_size_buf <= _axi_c_write_size_fifo; - end if((_axi_c_write_op_sel_buf == 1) && read_burst_rvalid_86 && (axi_c_tready || !axi_c_tvalid) && (axi_c_tready || !axi_c_tvalid)) begin axi_c_tdata <= read_burst_rdata_90; axi_c_tvalid <= 1; @@ -688,6 +676,25 @@ axi_c_tvalid <= axi_c_tvalid; axi_c_tlast <= axi_c_tlast; end + end + end + + + always @(posedge CLK) begin + if(RST) begin + _axi_c_write_data_busy <= 0; + _axi_c_write_op_sel_buf <= 0; + _axi_c_write_local_addr_buf <= 0; + _axi_c_write_local_stride_buf <= 0; + _axi_c_write_size_buf <= 0; + end else begin + if((_axi_c_write_data_fsm == 0) && (!_axi_c_write_data_busy && !_axi_c_write_req_fifo_empty && (_axi_c_write_op_sel_fifo == 1))) begin + _axi_c_write_data_busy <= 1; + _axi_c_write_op_sel_buf <= _axi_c_write_op_sel_fifo; + _axi_c_write_local_addr_buf <= _axi_c_write_local_addr_fifo; + _axi_c_write_local_stride_buf <= _axi_c_write_local_stride_fifo; + _axi_c_write_size_buf <= _axi_c_write_size_fifo; + end if((_axi_c_write_data_fsm == 2) && ((_axi_c_write_op_sel_buf == 1) && read_burst_rvalid_86 && (axi_c_tready || !axi_c_tvalid))) begin _axi_c_write_size_buf <= _axi_c_write_size_buf - 1; end @@ -715,6 +722,27 @@ end + always @(posedge CLK) begin + if(RST) begin + saxi_rdata <= 0; + saxi_rvalid <= 0; + _saxi_rdata_cond_0_1 <= 0; + end else begin + if(_saxi_rdata_cond_0_1) begin + saxi_rvalid <= 0; + end + if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid)) begin + saxi_rdata <= axislite_rdata_18; + saxi_rvalid <= 1; + end + _saxi_rdata_cond_0_1 <= 1; + if(saxi_rvalid && !saxi_rready) begin + saxi_rvalid <= saxi_rvalid; + end + end + end + + always @(posedge CLK) begin if(RST) begin saxi_bvalid <= 0; @@ -723,9 +751,6 @@ writevalid_13 <= 0; readvalid_14 <= 0; addr_12 <= 0; - saxi_rdata <= 0; - saxi_rvalid <= 0; - _saxi_cond_0_1 <= 0; _saxi_register_0 <= 0; _saxi_flag_0 <= 0; _saxi_register_1 <= 0; @@ -735,9 +760,6 @@ _saxi_register_3 <= 0; _saxi_flag_3 <= 0; end else begin - if(_saxi_cond_0_1) begin - saxi_rvalid <= 0; - end if(saxi_bvalid && saxi_bready) begin saxi_bvalid <= 0; end @@ -755,14 +777,6 @@ addr_12 <= saxi_araddr; readvalid_14 <= 1; end - if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid)) begin - saxi_rdata <= axislite_rdata_18; - saxi_rvalid <= 1; - end - _saxi_cond_0_1 <= 1; - if(saxi_rvalid && !saxi_rready) begin - saxi_rvalid <= saxi_rvalid; - end if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_19 && (axis_maskaddr_17 == 0)) begin _saxi_register_0 <= axislite_resetval_20; _saxi_flag_0 <= 0; diff --git a/tests/extension/thread_/stream_axi_stream_async/test_thread_stream_axi_stream_async.py b/tests/extension/thread_/stream_axi_stream_async/test_thread_stream_axi_stream_async.py index ddeb2b00..ca846857 100644 --- a/tests/extension/thread_/stream_axi_stream_async/test_thread_stream_axi_stream_async.py +++ b/tests/extension/thread_/stream_axi_stream_async/test_thread_stream_axi_stream_async.py @@ -238,7 +238,7 @@ (axis_maskaddr_17 == 1)? _saxi_resetval_1 : (axis_maskaddr_17 == 2)? _saxi_resetval_2 : (axis_maskaddr_17 == 3)? _saxi_resetval_3 : 'hx; - reg _saxi_cond_0_1; + reg _saxi_rdata_cond_0_1; assign saxi_wready = _saxi_register_fsm == 3; wire [10-1:0] ram_a_0_addr; wire [32-1:0] ram_a_0_rdata; @@ -657,11 +657,6 @@ always @(posedge CLK) begin if(RST) begin - _axi_c_write_data_busy <= 0; - _axi_c_write_op_sel_buf <= 0; - _axi_c_write_local_addr_buf <= 0; - _axi_c_write_local_stride_buf <= 0; - _axi_c_write_size_buf <= 0; axi_c_tdata <= 0; axi_c_tvalid <= 0; axi_c_tlast <= 0; @@ -671,13 +666,6 @@ axi_c_tvalid <= 0; axi_c_tlast <= 0; end - if((_axi_c_write_data_fsm == 0) && (!_axi_c_write_data_busy && !_axi_c_write_req_fifo_empty && (_axi_c_write_op_sel_fifo == 1))) begin - _axi_c_write_data_busy <= 1; - _axi_c_write_op_sel_buf <= _axi_c_write_op_sel_fifo; - _axi_c_write_local_addr_buf <= _axi_c_write_local_addr_fifo; - _axi_c_write_local_stride_buf <= _axi_c_write_local_stride_fifo; - _axi_c_write_size_buf <= _axi_c_write_size_fifo; - end if((_axi_c_write_op_sel_buf == 1) && read_burst_rvalid_86 && (axi_c_tready || !axi_c_tvalid) && (axi_c_tready || !axi_c_tvalid)) begin axi_c_tdata <= read_burst_rdata_90; axi_c_tvalid <= 1; @@ -688,6 +676,25 @@ axi_c_tvalid <= axi_c_tvalid; axi_c_tlast <= axi_c_tlast; end + end + end + + + always @(posedge CLK) begin + if(RST) begin + _axi_c_write_data_busy <= 0; + _axi_c_write_op_sel_buf <= 0; + _axi_c_write_local_addr_buf <= 0; + _axi_c_write_local_stride_buf <= 0; + _axi_c_write_size_buf <= 0; + end else begin + if((_axi_c_write_data_fsm == 0) && (!_axi_c_write_data_busy && !_axi_c_write_req_fifo_empty && (_axi_c_write_op_sel_fifo == 1))) begin + _axi_c_write_data_busy <= 1; + _axi_c_write_op_sel_buf <= _axi_c_write_op_sel_fifo; + _axi_c_write_local_addr_buf <= _axi_c_write_local_addr_fifo; + _axi_c_write_local_stride_buf <= _axi_c_write_local_stride_fifo; + _axi_c_write_size_buf <= _axi_c_write_size_fifo; + end if((_axi_c_write_data_fsm == 2) && ((_axi_c_write_op_sel_buf == 1) && read_burst_rvalid_86 && (axi_c_tready || !axi_c_tvalid))) begin _axi_c_write_size_buf <= _axi_c_write_size_buf - 1; end @@ -715,6 +722,27 @@ end + always @(posedge CLK) begin + if(RST) begin + saxi_rdata <= 0; + saxi_rvalid <= 0; + _saxi_rdata_cond_0_1 <= 0; + end else begin + if(_saxi_rdata_cond_0_1) begin + saxi_rvalid <= 0; + end + if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid)) begin + saxi_rdata <= axislite_rdata_18; + saxi_rvalid <= 1; + end + _saxi_rdata_cond_0_1 <= 1; + if(saxi_rvalid && !saxi_rready) begin + saxi_rvalid <= saxi_rvalid; + end + end + end + + always @(posedge CLK) begin if(RST) begin saxi_bvalid <= 0; @@ -723,9 +751,6 @@ writevalid_13 <= 0; readvalid_14 <= 0; addr_12 <= 0; - saxi_rdata <= 0; - saxi_rvalid <= 0; - _saxi_cond_0_1 <= 0; _saxi_register_0 <= 0; _saxi_flag_0 <= 0; _saxi_register_1 <= 0; @@ -735,9 +760,6 @@ _saxi_register_3 <= 0; _saxi_flag_3 <= 0; end else begin - if(_saxi_cond_0_1) begin - saxi_rvalid <= 0; - end if(saxi_bvalid && saxi_bready) begin saxi_bvalid <= 0; end @@ -755,14 +777,6 @@ addr_12 <= saxi_araddr; readvalid_14 <= 1; end - if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid)) begin - saxi_rdata <= axislite_rdata_18; - saxi_rvalid <= 1; - end - _saxi_cond_0_1 <= 1; - if(saxi_rvalid && !saxi_rready) begin - saxi_rvalid <= saxi_rvalid; - end if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_19 && (axis_maskaddr_17 == 0)) begin _saxi_register_0 <= axislite_resetval_20; _saxi_flag_0 <= 0; diff --git a/tests/extension/thread_/stream_cast/test_thread_stream_cast.py b/tests/extension/thread_/stream_cast/test_thread_stream_cast.py index 6ea6229d..b70f207d 100644 --- a/tests/extension/thread_/stream_cast/test_thread_stream_cast.py +++ b/tests/extension/thread_/stream_cast/test_thread_stream_cast.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_cast.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_cast/thread_stream_cast.py b/tests/extension/thread_/stream_cast/thread_stream_cast.py index 378a91a2..0cca076b 100644 --- a/tests/extension/thread_/stream_cast/thread_stream_cast.py +++ b/tests/extension/thread_/stream_cast/thread_stream_cast.py @@ -133,9 +133,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_conv1d/test_thread_stream_conv1d.py b/tests/extension/thread_/stream_conv1d/test_thread_stream_conv1d.py index dc2437ad..862458b6 100644 --- a/tests/extension/thread_/stream_conv1d/test_thread_stream_conv1d.py +++ b/tests/extension/thread_/stream_conv1d/test_thread_stream_conv1d.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_conv1d.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_conv1d/thread_stream_conv1d.py b/tests/extension/thread_/stream_conv1d/thread_stream_conv1d.py index 8566e7f7..c6987a75 100644 --- a/tests/extension/thread_/stream_conv1d/thread_stream_conv1d.py +++ b/tests/extension/thread_/stream_conv1d/thread_stream_conv1d.py @@ -144,9 +144,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_counter/test_thread_stream_counter.py b/tests/extension/thread_/stream_counter/test_thread_stream_counter.py index 03c39653..fc36877c 100644 --- a/tests/extension/thread_/stream_counter/test_thread_stream_counter.py +++ b/tests/extension/thread_/stream_counter/test_thread_stream_counter.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_counter.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_counter/thread_stream_counter.py b/tests/extension/thread_/stream_counter/thread_stream_counter.py index 725be7bc..e6207a40 100644 --- a/tests/extension/thread_/stream_counter/thread_stream_counter.py +++ b/tests/extension/thread_/stream_counter/thread_stream_counter.py @@ -143,9 +143,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_counter_enable/test_thread_stream_counter_enable.py b/tests/extension/thread_/stream_counter_enable/test_thread_stream_counter_enable.py index 79b220a7..5c1cff3a 100644 --- a/tests/extension/thread_/stream_counter_enable/test_thread_stream_counter_enable.py +++ b/tests/extension/thread_/stream_counter_enable/test_thread_stream_counter_enable.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_counter_enable.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_counter_enable/thread_stream_counter_enable.py b/tests/extension/thread_/stream_counter_enable/thread_stream_counter_enable.py index beb4ab9e..3e4556a4 100644 --- a/tests/extension/thread_/stream_counter_enable/thread_stream_counter_enable.py +++ b/tests/extension/thread_/stream_counter_enable/thread_stream_counter_enable.py @@ -147,9 +147,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_counter_initval_variable/test_thread_stream_counter_initval_variable.py b/tests/extension/thread_/stream_counter_initval_variable/test_thread_stream_counter_initval_variable.py index 0cf2e05e..e8c7b6c7 100644 --- a/tests/extension/thread_/stream_counter_initval_variable/test_thread_stream_counter_initval_variable.py +++ b/tests/extension/thread_/stream_counter_initval_variable/test_thread_stream_counter_initval_variable.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_counter_initval_variable.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_counter_initval_variable/thread_stream_counter_initval_variable.py b/tests/extension/thread_/stream_counter_initval_variable/thread_stream_counter_initval_variable.py index 61a252df..ec6e97ac 100644 --- a/tests/extension/thread_/stream_counter_initval_variable/thread_stream_counter_initval_variable.py +++ b/tests/extension/thread_/stream_counter_initval_variable/thread_stream_counter_initval_variable.py @@ -45,7 +45,7 @@ def comp_stream(size, offset): strm.join() def comp_sequential(size, offset): - cnt_size= 8 + cnt_size = 8 cnt_initval = 4 cnt = cnt_initval for i in range(size): @@ -139,9 +139,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_counter_initval_variable_offset/test_thread_stream_counter_initval_variable_offset.py b/tests/extension/thread_/stream_counter_initval_variable_offset/test_thread_stream_counter_initval_variable_offset.py index a306f0f8..150e66fb 100644 --- a/tests/extension/thread_/stream_counter_initval_variable_offset/test_thread_stream_counter_initval_variable_offset.py +++ b/tests/extension/thread_/stream_counter_initval_variable_offset/test_thread_stream_counter_initval_variable_offset.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_counter_initval_variable_offset.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_counter_initval_variable_offset/thread_stream_counter_initval_variable_offset.py b/tests/extension/thread_/stream_counter_initval_variable_offset/thread_stream_counter_initval_variable_offset.py index ee46df88..479782a4 100644 --- a/tests/extension/thread_/stream_counter_initval_variable_offset/thread_stream_counter_initval_variable_offset.py +++ b/tests/extension/thread_/stream_counter_initval_variable_offset/thread_stream_counter_initval_variable_offset.py @@ -48,7 +48,7 @@ def comp_stream(size, offset): strm.join() def comp_sequential(size, offset): - cnt_size= 8 + cnt_size = 8 cnt_initval = 4 cnt_offset = 3 cnt = cnt_initval @@ -143,9 +143,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_counter_offset/test_thread_stream_counter_offset.py b/tests/extension/thread_/stream_counter_offset/test_thread_stream_counter_offset.py index e6bcaa13..cd6aba61 100644 --- a/tests/extension/thread_/stream_counter_offset/test_thread_stream_counter_offset.py +++ b/tests/extension/thread_/stream_counter_offset/test_thread_stream_counter_offset.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_counter_offset.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_counter_offset/thread_stream_counter_offset.py b/tests/extension/thread_/stream_counter_offset/thread_stream_counter_offset.py index 16d989b4..de273be4 100644 --- a/tests/extension/thread_/stream_counter_offset/thread_stream_counter_offset.py +++ b/tests/extension/thread_/stream_counter_offset/thread_stream_counter_offset.py @@ -135,9 +135,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_counter_stall/test_thread_stream_counter_stall.py b/tests/extension/thread_/stream_counter_stall/test_thread_stream_counter_stall.py index 88affb0a..013f52ef 100644 --- a/tests/extension/thread_/stream_counter_stall/test_thread_stream_counter_stall.py +++ b/tests/extension/thread_/stream_counter_stall/test_thread_stream_counter_stall.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_counter_stall.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_counter_stall/thread_stream_counter_stall.py b/tests/extension/thread_/stream_counter_stall/thread_stream_counter_stall.py index 8ae402e1..fd24cba4 100644 --- a/tests/extension/thread_/stream_counter_stall/thread_stream_counter_stall.py +++ b/tests/extension/thread_/stream_counter_stall/thread_stream_counter_stall.py @@ -153,9 +153,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_countervalid/test_thread_stream_countervalid.py b/tests/extension/thread_/stream_countervalid/test_thread_stream_countervalid.py index 5c6f18e9..1e3ea205 100644 --- a/tests/extension/thread_/stream_countervalid/test_thread_stream_countervalid.py +++ b/tests/extension/thread_/stream_countervalid/test_thread_stream_countervalid.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_countervalid.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_countervalid/thread_stream_countervalid.py b/tests/extension/thread_/stream_countervalid/thread_stream_countervalid.py index db1252a2..229fe8b6 100644 --- a/tests/extension/thread_/stream_countervalid/thread_stream_countervalid.py +++ b/tests/extension/thread_/stream_countervalid/thread_stream_countervalid.py @@ -140,9 +140,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_custom_counter/test_thread_stream_custom_counter.py b/tests/extension/thread_/stream_custom_counter/test_thread_stream_custom_counter.py index dd3eb1a8..7a225d4a 100644 --- a/tests/extension/thread_/stream_custom_counter/test_thread_stream_custom_counter.py +++ b/tests/extension/thread_/stream_custom_counter/test_thread_stream_custom_counter.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_custom_counter.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_custom_counter/thread_stream_custom_counter.py b/tests/extension/thread_/stream_custom_counter/thread_stream_custom_counter.py index 84046a7d..7095d6f4 100644 --- a/tests/extension/thread_/stream_custom_counter/thread_stream_custom_counter.py +++ b/tests/extension/thread_/stream_custom_counter/thread_stream_custom_counter.py @@ -163,9 +163,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_div/test_thread_stream_div.py b/tests/extension/thread_/stream_div/test_thread_stream_div.py index 071e895d..1449f647 100644 --- a/tests/extension/thread_/stream_div/test_thread_stream_div.py +++ b/tests/extension/thread_/stream_div/test_thread_stream_div.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_div.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_div/thread_stream_div.py b/tests/extension/thread_/stream_div/thread_stream_div.py index 0c930c34..1f808e43 100644 --- a/tests/extension/thread_/stream_div/thread_stream_div.py +++ b/tests/extension/thread_/stream_div/thread_stream_div.py @@ -137,9 +137,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_div_multicycle/test_thread_stream_div_multicycle.py b/tests/extension/thread_/stream_div_multicycle/test_thread_stream_div_multicycle.py index 572e7707..c746fb79 100644 --- a/tests/extension/thread_/stream_div_multicycle/test_thread_stream_div_multicycle.py +++ b/tests/extension/thread_/stream_div_multicycle/test_thread_stream_div_multicycle.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_div_multicycle.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_div_multicycle/thread_stream_div_multicycle.py b/tests/extension/thread_/stream_div_multicycle/thread_stream_div_multicycle.py index 384c708d..3c592df7 100644 --- a/tests/extension/thread_/stream_div_multicycle/thread_stream_div_multicycle.py +++ b/tests/extension/thread_/stream_div_multicycle/thread_stream_div_multicycle.py @@ -140,9 +140,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_dump/test_thread_stream_dump.py b/tests/extension/thread_/stream_dump/test_thread_stream_dump.py index 3dad01cd..32573c34 100644 --- a/tests/extension/thread_/stream_dump/test_thread_stream_dump.py +++ b/tests/extension/thread_/stream_dump/test_thread_stream_dump.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_dump.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_dump/thread_stream_dump.py b/tests/extension/thread_/stream_dump/thread_stream_dump.py index a219d01e..35366679 100644 --- a/tests/extension/thread_/stream_dump/thread_stream_dump.py +++ b/tests/extension/thread_/stream_dump/thread_stream_dump.py @@ -133,9 +133,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_dump_mask/test_thread_stream_dump_mask.py b/tests/extension/thread_/stream_dump_mask/test_thread_stream_dump_mask.py index 77213ea7..29e25001 100644 --- a/tests/extension/thread_/stream_dump_mask/test_thread_stream_dump_mask.py +++ b/tests/extension/thread_/stream_dump_mask/test_thread_stream_dump_mask.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_dump_mask.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_dump_mask/thread_stream_dump_mask.py b/tests/extension/thread_/stream_dump_mask/thread_stream_dump_mask.py index a1a79456..0e5fc31a 100644 --- a/tests/extension/thread_/stream_dump_mask/thread_stream_dump_mask.py +++ b/tests/extension/thread_/stream_dump_mask/thread_stream_dump_mask.py @@ -133,9 +133,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_dump_selective/test_thread_stream_dump_selective.py b/tests/extension/thread_/stream_dump_selective/test_thread_stream_dump_selective.py index 48bec4c5..7a428ed2 100644 --- a/tests/extension/thread_/stream_dump_selective/test_thread_stream_dump_selective.py +++ b/tests/extension/thread_/stream_dump_selective/test_thread_stream_dump_selective.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_dump_selective.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_dump_selective/thread_stream_dump_selective.py b/tests/extension/thread_/stream_dump_selective/thread_stream_dump_selective.py index b0842f2b..dc21af06 100644 --- a/tests/extension/thread_/stream_dump_selective/thread_stream_dump_selective.py +++ b/tests/extension/thread_/stream_dump_selective/thread_stream_dump_selective.py @@ -134,9 +134,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_dump_unused/test_thread_stream_dump_unused.py b/tests/extension/thread_/stream_dump_unused/test_thread_stream_dump_unused.py index c4a041c8..42f309c9 100644 --- a/tests/extension/thread_/stream_dump_unused/test_thread_stream_dump_unused.py +++ b/tests/extension/thread_/stream_dump_unused/test_thread_stream_dump_unused.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_dump_unused.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_dump_unused/thread_stream_dump_unused.py b/tests/extension/thread_/stream_dump_unused/thread_stream_dump_unused.py index d15ac2f7..f19353f4 100644 --- a/tests/extension/thread_/stream_dump_unused/thread_stream_dump_unused.py +++ b/tests/extension/thread_/stream_dump_unused/thread_stream_dump_unused.py @@ -133,9 +133,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_empty/test_thread_stream_empty.py b/tests/extension/thread_/stream_empty/test_thread_stream_empty.py index 00cca4c1..1bc821e9 100644 --- a/tests/extension/thread_/stream_empty/test_thread_stream_empty.py +++ b/tests/extension/thread_/stream_empty/test_thread_stream_empty.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_empty.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_empty/thread_stream_empty.py b/tests/extension/thread_/stream_empty/thread_stream_empty.py index 9bb61d70..e01c5fde 100644 --- a/tests/extension/thread_/stream_empty/thread_stream_empty.py +++ b/tests/extension/thread_/stream_empty/thread_stream_empty.py @@ -138,9 +138,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_extern/test_thread_stream_extern.py b/tests/extension/thread_/stream_extern/test_thread_stream_extern.py index 46affff1..ab37619e 100644 --- a/tests/extension/thread_/stream_extern/test_thread_stream_extern.py +++ b/tests/extension/thread_/stream_extern/test_thread_stream_extern.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_extern.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_extern/thread_stream_extern.py b/tests/extension/thread_/stream_extern/thread_stream_extern.py index 1c6fd446..3cdd92c2 100644 --- a/tests/extension/thread_/stream_extern/thread_stream_extern.py +++ b/tests/extension/thread_/stream_extern/thread_stream_extern.py @@ -142,9 +142,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_fifo/test_thread_stream_fifo.py b/tests/extension/thread_/stream_fifo/test_thread_stream_fifo.py index 47b6d115..0d728a7a 100644 --- a/tests/extension/thread_/stream_fifo/test_thread_stream_fifo.py +++ b/tests/extension/thread_/stream_fifo/test_thread_stream_fifo.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_fifo.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_fifo/thread_stream_fifo.py b/tests/extension/thread_/stream_fifo/thread_stream_fifo.py index 8737bea0..05f4d980 100644 --- a/tests/extension/thread_/stream_fifo/thread_stream_fifo.py +++ b/tests/extension/thread_/stream_fifo/thread_stream_fifo.py @@ -164,9 +164,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_fifo_dump/test_thread_stream_fifo_dump.py b/tests/extension/thread_/stream_fifo_dump/test_thread_stream_fifo_dump.py index c6b26b13..88524fe2 100644 --- a/tests/extension/thread_/stream_fifo_dump/test_thread_stream_fifo_dump.py +++ b/tests/extension/thread_/stream_fifo_dump/test_thread_stream_fifo_dump.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_fifo_dump.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_fifo_dump/thread_stream_fifo_dump.py b/tests/extension/thread_/stream_fifo_dump/thread_stream_fifo_dump.py index 2eb33d28..181506d8 100644 --- a/tests/extension/thread_/stream_fifo_dump/thread_stream_fifo_dump.py +++ b/tests/extension/thread_/stream_fifo_dump/thread_stream_fifo_dump.py @@ -167,9 +167,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_fifo_multistream/test_thread_stream_fifo_multistream.py b/tests/extension/thread_/stream_fifo_multistream/test_thread_stream_fifo_multistream.py index 16851ed3..e140d1bb 100644 --- a/tests/extension/thread_/stream_fifo_multistream/test_thread_stream_fifo_multistream.py +++ b/tests/extension/thread_/stream_fifo_multistream/test_thread_stream_fifo_multistream.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_fifo_multistream.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_fifo_multistream/thread_stream_fifo_multistream.py b/tests/extension/thread_/stream_fifo_multistream/thread_stream_fifo_multistream.py index 632a2335..793a7c80 100644 --- a/tests/extension/thread_/stream_fifo_multistream/thread_stream_fifo_multistream.py +++ b/tests/extension/thread_/stream_fifo_multistream/thread_stream_fifo_multistream.py @@ -185,9 +185,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_fifo_narrow/test_thread_stream_fifo_narrow.py b/tests/extension/thread_/stream_fifo_narrow/test_thread_stream_fifo_narrow.py index 6bae48ed..2eeb728a 100644 --- a/tests/extension/thread_/stream_fifo_narrow/test_thread_stream_fifo_narrow.py +++ b/tests/extension/thread_/stream_fifo_narrow/test_thread_stream_fifo_narrow.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_fifo_narrow.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_fifo_narrow/thread_stream_fifo_narrow.py b/tests/extension/thread_/stream_fifo_narrow/thread_stream_fifo_narrow.py index e594b48e..cd76db78 100644 --- a/tests/extension/thread_/stream_fifo_narrow/thread_stream_fifo_narrow.py +++ b/tests/extension/thread_/stream_fifo_narrow/thread_stream_fifo_narrow.py @@ -176,9 +176,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_fifo_wide/test_thread_stream_fifo_wide.py b/tests/extension/thread_/stream_fifo_wide/test_thread_stream_fifo_wide.py index e5aaef7a..91c00008 100644 --- a/tests/extension/thread_/stream_fifo_wide/test_thread_stream_fifo_wide.py +++ b/tests/extension/thread_/stream_fifo_wide/test_thread_stream_fifo_wide.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_fifo_wide.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_fifo_wide/thread_stream_fifo_wide.py b/tests/extension/thread_/stream_fifo_wide/thread_stream_fifo_wide.py index 09ea9bfa..e0f8794c 100644 --- a/tests/extension/thread_/stream_fifo_wide/thread_stream_fifo_wide.py +++ b/tests/extension/thread_/stream_fifo_wide/thread_stream_fifo_wide.py @@ -178,9 +178,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_fixed/test_thread_stream_fixed.py b/tests/extension/thread_/stream_fixed/test_thread_stream_fixed.py index 3528f757..184835e1 100644 --- a/tests/extension/thread_/stream_fixed/test_thread_stream_fixed.py +++ b/tests/extension/thread_/stream_fixed/test_thread_stream_fixed.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_fixed.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_fixed/thread_stream_fixed.py b/tests/extension/thread_/stream_fixed/thread_stream_fixed.py index 57680a03..61d1f4da 100644 --- a/tests/extension/thread_/stream_fixed/thread_stream_fixed.py +++ b/tests/extension/thread_/stream_fixed/thread_stream_fixed.py @@ -138,9 +138,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_fixed_different_point/test_thread_stream_fixed_different_point.py b/tests/extension/thread_/stream_fixed_different_point/test_thread_stream_fixed_different_point.py index 3ecbb4f8..54519fc1 100644 --- a/tests/extension/thread_/stream_fixed_different_point/test_thread_stream_fixed_different_point.py +++ b/tests/extension/thread_/stream_fixed_different_point/test_thread_stream_fixed_different_point.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_fixed_different_point.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_fixed_different_point/thread_stream_fixed_different_point.py b/tests/extension/thread_/stream_fixed_different_point/thread_stream_fixed_different_point.py index 0e12eaa5..fe4899c1 100644 --- a/tests/extension/thread_/stream_fixed_different_point/thread_stream_fixed_different_point.py +++ b/tests/extension/thread_/stream_fixed_different_point/thread_stream_fixed_different_point.py @@ -138,9 +138,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_fixed_neg_point/test_thread_stream_fixed_neg_point.py b/tests/extension/thread_/stream_fixed_neg_point/test_thread_stream_fixed_neg_point.py index b7893cdd..dcb1ab92 100644 --- a/tests/extension/thread_/stream_fixed_neg_point/test_thread_stream_fixed_neg_point.py +++ b/tests/extension/thread_/stream_fixed_neg_point/test_thread_stream_fixed_neg_point.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_fixed_neg_point.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_fixed_neg_point/thread_stream_fixed_neg_point.py b/tests/extension/thread_/stream_fixed_neg_point/thread_stream_fixed_neg_point.py index 639f6ba4..d36436d5 100644 --- a/tests/extension/thread_/stream_fixed_neg_point/thread_stream_fixed_neg_point.py +++ b/tests/extension/thread_/stream_fixed_neg_point/thread_stream_fixed_neg_point.py @@ -138,9 +138,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_fsm_as_module/test_thread_stream_fsm_as_module.py b/tests/extension/thread_/stream_fsm_as_module/test_thread_stream_fsm_as_module.py index f776cc3d..5f9ed169 100644 --- a/tests/extension/thread_/stream_fsm_as_module/test_thread_stream_fsm_as_module.py +++ b/tests/extension/thread_/stream_fsm_as_module/test_thread_stream_fsm_as_module.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_fsm_as_module.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_fsm_as_module/thread_stream_fsm_as_module.py b/tests/extension/thread_/stream_fsm_as_module/thread_stream_fsm_as_module.py index 27f85997..6a87caba 100644 --- a/tests/extension/thread_/stream_fsm_as_module/thread_stream_fsm_as_module.py +++ b/tests/extension/thread_/stream_fsm_as_module/thread_stream_fsm_as_module.py @@ -130,9 +130,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_generator/test_thread_stream_generator.py b/tests/extension/thread_/stream_generator/test_thread_stream_generator.py index 34134742..e99f9aae 100644 --- a/tests/extension/thread_/stream_generator/test_thread_stream_generator.py +++ b/tests/extension/thread_/stream_generator/test_thread_stream_generator.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_generator.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_generator/thread_stream_generator.py b/tests/extension/thread_/stream_generator/thread_stream_generator.py index ed798c34..c3849122 100644 --- a/tests/extension/thread_/stream_generator/thread_stream_generator.py +++ b/tests/extension/thread_/stream_generator/thread_stream_generator.py @@ -144,9 +144,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_generator_multicase/test_thread_stream_generator_multicase.py b/tests/extension/thread_/stream_generator_multicase/test_thread_stream_generator_multicase.py index 953338bd..85c78133 100644 --- a/tests/extension/thread_/stream_generator_multicase/test_thread_stream_generator_multicase.py +++ b/tests/extension/thread_/stream_generator_multicase/test_thread_stream_generator_multicase.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_generator_multicase.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_generator_multicase/thread_stream_generator_multicase.py b/tests/extension/thread_/stream_generator_multicase/thread_stream_generator_multicase.py index c2c0ef60..f81eaf0e 100644 --- a/tests/extension/thread_/stream_generator_multicase/thread_stream_generator_multicase.py +++ b/tests/extension/thread_/stream_generator_multicase/thread_stream_generator_multicase.py @@ -160,9 +160,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_generator_multicase_multicall/test_thread_stream_generator_multicase_multicall.py b/tests/extension/thread_/stream_generator_multicase_multicall/test_thread_stream_generator_multicase_multicall.py index 8c05f6ea..312f8a08 100644 --- a/tests/extension/thread_/stream_generator_multicase_multicall/test_thread_stream_generator_multicase_multicall.py +++ b/tests/extension/thread_/stream_generator_multicase_multicall/test_thread_stream_generator_multicase_multicall.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_generator_multicase_multicall.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_generator_multicase_multicall/thread_stream_generator_multicase_multicall.py b/tests/extension/thread_/stream_generator_multicase_multicall/thread_stream_generator_multicase_multicall.py index 7b9820d9..b960554a 100644 --- a/tests/extension/thread_/stream_generator_multicase_multicall/thread_stream_generator_multicase_multicall.py +++ b/tests/extension/thread_/stream_generator_multicase_multicall/thread_stream_generator_multicase_multicall.py @@ -183,9 +183,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_generator_multidim/test_thread_stream_generator_multidim.py b/tests/extension/thread_/stream_generator_multidim/test_thread_stream_generator_multidim.py index 1494d454..ad291987 100644 --- a/tests/extension/thread_/stream_generator_multidim/test_thread_stream_generator_multidim.py +++ b/tests/extension/thread_/stream_generator_multidim/test_thread_stream_generator_multidim.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_generator_multidim.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_generator_multidim/thread_stream_generator_multidim.py b/tests/extension/thread_/stream_generator_multidim/thread_stream_generator_multidim.py index 6b921517..eb9e385d 100644 --- a/tests/extension/thread_/stream_generator_multidim/thread_stream_generator_multidim.py +++ b/tests/extension/thread_/stream_generator_multidim/thread_stream_generator_multidim.py @@ -161,9 +161,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_graph_ringbuffer_multi/test_thread_stream_graph_ringbuffer_multi.py b/tests/extension/thread_/stream_graph_ringbuffer_multi/test_thread_stream_graph_ringbuffer_multi.py index 5c8cb35a..e38e6212 100644 --- a/tests/extension/thread_/stream_graph_ringbuffer_multi/test_thread_stream_graph_ringbuffer_multi.py +++ b/tests/extension/thread_/stream_graph_ringbuffer_multi/test_thread_stream_graph_ringbuffer_multi.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_graph_ringbuffer_multi.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_graph_ringbuffer_multi/thread_stream_graph_ringbuffer_multi.py b/tests/extension/thread_/stream_graph_ringbuffer_multi/thread_stream_graph_ringbuffer_multi.py index 9cacec92..b090a1f8 100644 --- a/tests/extension/thread_/stream_graph_ringbuffer_multi/thread_stream_graph_ringbuffer_multi.py +++ b/tests/extension/thread_/stream_graph_ringbuffer_multi/thread_stream_graph_ringbuffer_multi.py @@ -157,9 +157,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_graph_scratchpad_multi/test_thread_stream_graph_scratchpad_multi.py b/tests/extension/thread_/stream_graph_scratchpad_multi/test_thread_stream_graph_scratchpad_multi.py index dfeea271..3f3131f1 100644 --- a/tests/extension/thread_/stream_graph_scratchpad_multi/test_thread_stream_graph_scratchpad_multi.py +++ b/tests/extension/thread_/stream_graph_scratchpad_multi/test_thread_stream_graph_scratchpad_multi.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_graph_scratchpad_multi.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_graph_scratchpad_multi/thread_stream_graph_scratchpad_multi.py b/tests/extension/thread_/stream_graph_scratchpad_multi/thread_stream_graph_scratchpad_multi.py index bfc4869e..ccde15be 100644 --- a/tests/extension/thread_/stream_graph_scratchpad_multi/thread_stream_graph_scratchpad_multi.py +++ b/tests/extension/thread_/stream_graph_scratchpad_multi/thread_stream_graph_scratchpad_multi.py @@ -160,9 +160,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_graph_substream/test_thread_stream_graph_substream.py b/tests/extension/thread_/stream_graph_substream/test_thread_stream_graph_substream.py index 2640b707..cff92e24 100644 --- a/tests/extension/thread_/stream_graph_substream/test_thread_stream_graph_substream.py +++ b/tests/extension/thread_/stream_graph_substream/test_thread_stream_graph_substream.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_graph_substream.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_graph_substream/thread_stream_graph_substream.py b/tests/extension/thread_/stream_graph_substream/thread_stream_graph_substream.py index d1055728..5334804c 100644 --- a/tests/extension/thread_/stream_graph_substream/thread_stream_graph_substream.py +++ b/tests/extension/thread_/stream_graph_substream/thread_stream_graph_substream.py @@ -241,9 +241,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_infinite/test_thread_stream_infinite.py b/tests/extension/thread_/stream_infinite/test_thread_stream_infinite.py index a5210569..aacff71d 100644 --- a/tests/extension/thread_/stream_infinite/test_thread_stream_infinite.py +++ b/tests/extension/thread_/stream_infinite/test_thread_stream_infinite.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_infinite.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_infinite/thread_stream_infinite.py b/tests/extension/thread_/stream_infinite/thread_stream_infinite.py index 21d3eadb..29638e5a 100644 --- a/tests/extension/thread_/stream_infinite/thread_stream_infinite.py +++ b/tests/extension/thread_/stream_infinite/thread_stream_infinite.py @@ -140,9 +140,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_len1/test_thread_stream_len1.py b/tests/extension/thread_/stream_len1/test_thread_stream_len1.py index e4f69341..6ed75afd 100644 --- a/tests/extension/thread_/stream_len1/test_thread_stream_len1.py +++ b/tests/extension/thread_/stream_len1/test_thread_stream_len1.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_len1.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_len1/thread_stream_len1.py b/tests/extension/thread_/stream_len1/thread_stream_len1.py index e0e4400d..ba04a1fb 100644 --- a/tests/extension/thread_/stream_len1/thread_stream_len1.py +++ b/tests/extension/thread_/stream_len1/thread_stream_len1.py @@ -130,9 +130,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_len1_multicall/test_thread_stream_len1_multicall.py b/tests/extension/thread_/stream_len1_multicall/test_thread_stream_len1_multicall.py index 0c7eb77b..dcc80e07 100644 --- a/tests/extension/thread_/stream_len1_multicall/test_thread_stream_len1_multicall.py +++ b/tests/extension/thread_/stream_len1_multicall/test_thread_stream_len1_multicall.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_len1_multicall.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_len1_multicall/thread_stream_len1_multicall.py b/tests/extension/thread_/stream_len1_multicall/thread_stream_len1_multicall.py index 0c722cfb..4c4a9664 100644 --- a/tests/extension/thread_/stream_len1_multicall/thread_stream_len1_multicall.py +++ b/tests/extension/thread_/stream_len1_multicall/thread_stream_len1_multicall.py @@ -151,9 +151,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_linebuffer2d/test_thread_stream_linebuffer2d.py b/tests/extension/thread_/stream_linebuffer2d/test_thread_stream_linebuffer2d.py index bf6f3b07..ef27b9a2 100644 --- a/tests/extension/thread_/stream_linebuffer2d/test_thread_stream_linebuffer2d.py +++ b/tests/extension/thread_/stream_linebuffer2d/test_thread_stream_linebuffer2d.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_linebuffer2d.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_linebuffer2d/thread_stream_linebuffer2d.py b/tests/extension/thread_/stream_linebuffer2d/thread_stream_linebuffer2d.py index 8def952f..df55d507 100644 --- a/tests/extension/thread_/stream_linebuffer2d/thread_stream_linebuffer2d.py +++ b/tests/extension/thread_/stream_linebuffer2d/thread_stream_linebuffer2d.py @@ -180,9 +180,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_linebuffer2d_2/test_thread_stream_linebuffer2d_2.py b/tests/extension/thread_/stream_linebuffer2d_2/test_thread_stream_linebuffer2d_2.py index f9e668e5..fcf45094 100644 --- a/tests/extension/thread_/stream_linebuffer2d_2/test_thread_stream_linebuffer2d_2.py +++ b/tests/extension/thread_/stream_linebuffer2d_2/test_thread_stream_linebuffer2d_2.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_linebuffer2d_2.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_linebuffer2d_2/thread_stream_linebuffer2d_2.py b/tests/extension/thread_/stream_linebuffer2d_2/thread_stream_linebuffer2d_2.py index b8b06ebb..acc3943d 100644 --- a/tests/extension/thread_/stream_linebuffer2d_2/thread_stream_linebuffer2d_2.py +++ b/tests/extension/thread_/stream_linebuffer2d_2/thread_stream_linebuffer2d_2.py @@ -224,9 +224,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_linebuffer2d_2_stall/test_thread_stream_linebuffer2d_2_stall.py b/tests/extension/thread_/stream_linebuffer2d_2_stall/test_thread_stream_linebuffer2d_2_stall.py index 5658baa4..7a22889d 100644 --- a/tests/extension/thread_/stream_linebuffer2d_2_stall/test_thread_stream_linebuffer2d_2_stall.py +++ b/tests/extension/thread_/stream_linebuffer2d_2_stall/test_thread_stream_linebuffer2d_2_stall.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_linebuffer2d_2_stall.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_linebuffer2d_2_stall/thread_stream_linebuffer2d_2_stall.py b/tests/extension/thread_/stream_linebuffer2d_2_stall/thread_stream_linebuffer2d_2_stall.py index b5db7f91..ff1f78f1 100644 --- a/tests/extension/thread_/stream_linebuffer2d_2_stall/thread_stream_linebuffer2d_2_stall.py +++ b/tests/extension/thread_/stream_linebuffer2d_2_stall/thread_stream_linebuffer2d_2_stall.py @@ -234,9 +234,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_linebuffer2d_stall/test_thread_stream_linebuffer2d_stall.py b/tests/extension/thread_/stream_linebuffer2d_stall/test_thread_stream_linebuffer2d_stall.py index abbeb510..54552cae 100644 --- a/tests/extension/thread_/stream_linebuffer2d_stall/test_thread_stream_linebuffer2d_stall.py +++ b/tests/extension/thread_/stream_linebuffer2d_stall/test_thread_stream_linebuffer2d_stall.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_linebuffer2d_stall.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_linebuffer2d_stall/thread_stream_linebuffer2d_stall.py b/tests/extension/thread_/stream_linebuffer2d_stall/thread_stream_linebuffer2d_stall.py index e83bf274..781aeb29 100644 --- a/tests/extension/thread_/stream_linebuffer2d_stall/thread_stream_linebuffer2d_stall.py +++ b/tests/extension/thread_/stream_linebuffer2d_stall/thread_stream_linebuffer2d_stall.py @@ -190,9 +190,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_linebuffer3d/test_thread_stream_linebuffer3d.py b/tests/extension/thread_/stream_linebuffer3d/test_thread_stream_linebuffer3d.py index 987098f3..7d3cb46f 100644 --- a/tests/extension/thread_/stream_linebuffer3d/test_thread_stream_linebuffer3d.py +++ b/tests/extension/thread_/stream_linebuffer3d/test_thread_stream_linebuffer3d.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_linebuffer3d.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_linebuffer3d/thread_stream_linebuffer3d.py b/tests/extension/thread_/stream_linebuffer3d/thread_stream_linebuffer3d.py index a6df1472..0e609904 100644 --- a/tests/extension/thread_/stream_linebuffer3d/thread_stream_linebuffer3d.py +++ b/tests/extension/thread_/stream_linebuffer3d/thread_stream_linebuffer3d.py @@ -187,9 +187,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_linebuffer3d_stall/test_thread_stream_linebuffer3d_stall.py b/tests/extension/thread_/stream_linebuffer3d_stall/test_thread_stream_linebuffer3d_stall.py index d68a83d7..cd2fac20 100644 --- a/tests/extension/thread_/stream_linebuffer3d_stall/test_thread_stream_linebuffer3d_stall.py +++ b/tests/extension/thread_/stream_linebuffer3d_stall/test_thread_stream_linebuffer3d_stall.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_linebuffer3d_stall.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_linebuffer3d_stall/thread_stream_linebuffer3d_stall.py b/tests/extension/thread_/stream_linebuffer3d_stall/thread_stream_linebuffer3d_stall.py index 401f01e8..5c356b7c 100644 --- a/tests/extension/thread_/stream_linebuffer3d_stall/thread_stream_linebuffer3d_stall.py +++ b/tests/extension/thread_/stream_linebuffer3d_stall/thread_stream_linebuffer3d_stall.py @@ -197,9 +197,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_mod/test_thread_stream_mod.py b/tests/extension/thread_/stream_mod/test_thread_stream_mod.py index b89b3c5d..6d227100 100644 --- a/tests/extension/thread_/stream_mod/test_thread_stream_mod.py +++ b/tests/extension/thread_/stream_mod/test_thread_stream_mod.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_mod.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_mod/thread_stream_mod.py b/tests/extension/thread_/stream_mod/thread_stream_mod.py index da5a4181..c1c112d8 100644 --- a/tests/extension/thread_/stream_mod/thread_stream_mod.py +++ b/tests/extension/thread_/stream_mod/thread_stream_mod.py @@ -137,9 +137,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_mul/test_thread_stream_mul.py b/tests/extension/thread_/stream_mul/test_thread_stream_mul.py index 88302bde..cdd3db24 100644 --- a/tests/extension/thread_/stream_mul/test_thread_stream_mul.py +++ b/tests/extension/thread_/stream_mul/test_thread_stream_mul.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_mul.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_mul/thread_stream_mul.py b/tests/extension/thread_/stream_mul/thread_stream_mul.py index c1c366ca..4f4e3d92 100644 --- a/tests/extension/thread_/stream_mul/thread_stream_mul.py +++ b/tests/extension/thread_/stream_mul/thread_stream_mul.py @@ -135,9 +135,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_mul_semi_signed/test_thread_stream_mul_semi_signed.py b/tests/extension/thread_/stream_mul_semi_signed/test_thread_stream_mul_semi_signed.py index 9de38317..5087c96c 100644 --- a/tests/extension/thread_/stream_mul_semi_signed/test_thread_stream_mul_semi_signed.py +++ b/tests/extension/thread_/stream_mul_semi_signed/test_thread_stream_mul_semi_signed.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_mul_semi_signed.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_mul_semi_signed/thread_stream_mul_semi_signed.py b/tests/extension/thread_/stream_mul_semi_signed/thread_stream_mul_semi_signed.py index f63a1f5c..c995afa0 100644 --- a/tests/extension/thread_/stream_mul_semi_signed/thread_stream_mul_semi_signed.py +++ b/tests/extension/thread_/stream_mul_semi_signed/thread_stream_mul_semi_signed.py @@ -144,9 +144,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_muladd/test_thread_stream_muladd.py b/tests/extension/thread_/stream_muladd/test_thread_stream_muladd.py index 07b257f5..32b2fa95 100644 --- a/tests/extension/thread_/stream_muladd/test_thread_stream_muladd.py +++ b/tests/extension/thread_/stream_muladd/test_thread_stream_muladd.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_muladd.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_muladd/thread_stream_muladd.py b/tests/extension/thread_/stream_muladd/thread_stream_muladd.py index e7dba933..d4fb28ec 100644 --- a/tests/extension/thread_/stream_muladd/thread_stream_muladd.py +++ b/tests/extension/thread_/stream_muladd/thread_stream_muladd.py @@ -130,9 +130,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_multibank/test_thread_stream_multibank.py b/tests/extension/thread_/stream_multibank/test_thread_stream_multibank.py index cd249956..774c9af1 100644 --- a/tests/extension/thread_/stream_multibank/test_thread_stream_multibank.py +++ b/tests/extension/thread_/stream_multibank/test_thread_stream_multibank.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_multibank.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_multibank/thread_stream_multibank.py b/tests/extension/thread_/stream_multibank/thread_stream_multibank.py index 40b805f9..193e3199 100644 --- a/tests/extension/thread_/stream_multibank/thread_stream_multibank.py +++ b/tests/extension/thread_/stream_multibank/thread_stream_multibank.py @@ -143,9 +143,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_multibank_nested/test_thread_stream_multibank_nested.py b/tests/extension/thread_/stream_multibank_nested/test_thread_stream_multibank_nested.py index de56598c..68f9a106 100644 --- a/tests/extension/thread_/stream_multibank_nested/test_thread_stream_multibank_nested.py +++ b/tests/extension/thread_/stream_multibank_nested/test_thread_stream_multibank_nested.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_multibank_nested.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_multibank_nested/thread_stream_multibank_nested.py b/tests/extension/thread_/stream_multibank_nested/thread_stream_multibank_nested.py index 3fb0641f..ac81fd02 100644 --- a/tests/extension/thread_/stream_multibank_nested/thread_stream_multibank_nested.py +++ b/tests/extension/thread_/stream_multibank_nested/thread_stream_multibank_nested.py @@ -149,9 +149,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_multicall/test_thread_stream_multicall.py b/tests/extension/thread_/stream_multicall/test_thread_stream_multicall.py index 5c9ee86d..8fbc4243 100644 --- a/tests/extension/thread_/stream_multicall/test_thread_stream_multicall.py +++ b/tests/extension/thread_/stream_multicall/test_thread_stream_multicall.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_multicall.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_multicall/thread_stream_multicall.py b/tests/extension/thread_/stream_multicall/thread_stream_multicall.py index a35d27f2..5de56e08 100644 --- a/tests/extension/thread_/stream_multicall/thread_stream_multicall.py +++ b/tests/extension/thread_/stream_multicall/thread_stream_multicall.py @@ -142,9 +142,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_multidim/test_thread_stream_multidim.py b/tests/extension/thread_/stream_multidim/test_thread_stream_multidim.py index b90035dc..32f51385 100644 --- a/tests/extension/thread_/stream_multidim/test_thread_stream_multidim.py +++ b/tests/extension/thread_/stream_multidim/test_thread_stream_multidim.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_multidim.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_multidim/thread_stream_multidim.py b/tests/extension/thread_/stream_multidim/thread_stream_multidim.py index 99de042d..d86fbc78 100644 --- a/tests/extension/thread_/stream_multidim/thread_stream_multidim.py +++ b/tests/extension/thread_/stream_multidim/thread_stream_multidim.py @@ -137,9 +137,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_multipattern/test_thread_stream_multipattern.py b/tests/extension/thread_/stream_multipattern/test_thread_stream_multipattern.py index f8ef0d17..d45cb8d0 100644 --- a/tests/extension/thread_/stream_multipattern/test_thread_stream_multipattern.py +++ b/tests/extension/thread_/stream_multipattern/test_thread_stream_multipattern.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_multipattern.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_multipattern/thread_stream_multipattern.py b/tests/extension/thread_/stream_multipattern/thread_stream_multipattern.py index 2b230913..03cd3b4c 100644 --- a/tests/extension/thread_/stream_multipattern/thread_stream_multipattern.py +++ b/tests/extension/thread_/stream_multipattern/thread_stream_multipattern.py @@ -163,9 +163,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_multipattern_stall/test_thread_stream_multipattern_stall.py b/tests/extension/thread_/stream_multipattern_stall/test_thread_stream_multipattern_stall.py index f2b482a3..532da4a2 100644 --- a/tests/extension/thread_/stream_multipattern_stall/test_thread_stream_multipattern_stall.py +++ b/tests/extension/thread_/stream_multipattern_stall/test_thread_stream_multipattern_stall.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_multipattern_stall.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_multipattern_stall/thread_stream_multipattern_stall.py b/tests/extension/thread_/stream_multipattern_stall/thread_stream_multipattern_stall.py index 12b46a13..5389da7e 100644 --- a/tests/extension/thread_/stream_multipattern_stall/thread_stream_multipattern_stall.py +++ b/tests/extension/thread_/stream_multipattern_stall/thread_stream_multipattern_stall.py @@ -173,9 +173,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_narrow/test_thread_stream_narrow.py b/tests/extension/thread_/stream_narrow/test_thread_stream_narrow.py index 14da8650..701a832c 100644 --- a/tests/extension/thread_/stream_narrow/test_thread_stream_narrow.py +++ b/tests/extension/thread_/stream_narrow/test_thread_stream_narrow.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_narrow.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_narrow/thread_stream_narrow.py b/tests/extension/thread_/stream_narrow/thread_stream_narrow.py index fd5e1d80..50f28c3d 100644 --- a/tests/extension/thread_/stream_narrow/thread_stream_narrow.py +++ b/tests/extension/thread_/stream_narrow/thread_stream_narrow.py @@ -143,9 +143,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_no_sink_size/test_thread_stream_no_sink_size.py b/tests/extension/thread_/stream_no_sink_size/test_thread_stream_no_sink_size.py index d185e243..cfc96132 100644 --- a/tests/extension/thread_/stream_no_sink_size/test_thread_stream_no_sink_size.py +++ b/tests/extension/thread_/stream_no_sink_size/test_thread_stream_no_sink_size.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_no_sink_size.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_no_sink_size/thread_stream_no_sink_size.py b/tests/extension/thread_/stream_no_sink_size/thread_stream_no_sink_size.py index e7321500..0f14b7c2 100644 --- a/tests/extension/thread_/stream_no_sink_size/thread_stream_no_sink_size.py +++ b/tests/extension/thread_/stream_no_sink_size/thread_stream_no_sink_size.py @@ -144,9 +144,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_parameter/test_thread_stream_parameter.py b/tests/extension/thread_/stream_parameter/test_thread_stream_parameter.py index efbd82d2..7388093b 100644 --- a/tests/extension/thread_/stream_parameter/test_thread_stream_parameter.py +++ b/tests/extension/thread_/stream_parameter/test_thread_stream_parameter.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_parameter.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_parameter/thread_stream_parameter.py b/tests/extension/thread_/stream_parameter/thread_stream_parameter.py index b470836e..be0d8c9d 100644 --- a/tests/extension/thread_/stream_parameter/thread_stream_parameter.py +++ b/tests/extension/thread_/stream_parameter/thread_stream_parameter.py @@ -134,9 +134,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_parameter_source_join/test_thread_stream_parameter_source_join.py b/tests/extension/thread_/stream_parameter_source_join/test_thread_stream_parameter_source_join.py index fe795a15..2ba8f851 100644 --- a/tests/extension/thread_/stream_parameter_source_join/test_thread_stream_parameter_source_join.py +++ b/tests/extension/thread_/stream_parameter_source_join/test_thread_stream_parameter_source_join.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_parameter_source_join.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_parameter_source_join/thread_stream_parameter_source_join.py b/tests/extension/thread_/stream_parameter_source_join/thread_stream_parameter_source_join.py index 62ab0d28..e8bf5976 100644 --- a/tests/extension/thread_/stream_parameter_source_join/thread_stream_parameter_source_join.py +++ b/tests/extension/thread_/stream_parameter_source_join/thread_stream_parameter_source_join.py @@ -167,9 +167,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_pattern/test_thread_stream_pattern.py b/tests/extension/thread_/stream_pattern/test_thread_stream_pattern.py index 81bed2e7..4bb2c68b 100644 --- a/tests/extension/thread_/stream_pattern/test_thread_stream_pattern.py +++ b/tests/extension/thread_/stream_pattern/test_thread_stream_pattern.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_pattern.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_pattern/thread_stream_pattern.py b/tests/extension/thread_/stream_pattern/thread_stream_pattern.py index 1819adef..6f144edd 100644 --- a/tests/extension/thread_/stream_pattern/thread_stream_pattern.py +++ b/tests/extension/thread_/stream_pattern/thread_stream_pattern.py @@ -150,9 +150,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_pattern_convolv2d/test_thread_stream_pattern_convolv2d.py b/tests/extension/thread_/stream_pattern_convolv2d/test_thread_stream_pattern_convolv2d.py index 99730240..2e807987 100644 --- a/tests/extension/thread_/stream_pattern_convolv2d/test_thread_stream_pattern_convolv2d.py +++ b/tests/extension/thread_/stream_pattern_convolv2d/test_thread_stream_pattern_convolv2d.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_pattern_convolv2d.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_pattern_convolv2d/thread_stream_pattern_convolv2d.py b/tests/extension/thread_/stream_pattern_convolv2d/thread_stream_pattern_convolv2d.py index 126f7974..f62b80c6 100644 --- a/tests/extension/thread_/stream_pattern_convolv2d/thread_stream_pattern_convolv2d.py +++ b/tests/extension/thread_/stream_pattern_convolv2d/thread_stream_pattern_convolv2d.py @@ -161,9 +161,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_pattern_len1/test_thread_stream_pattern_len1.py b/tests/extension/thread_/stream_pattern_len1/test_thread_stream_pattern_len1.py index 16b0adab..532c4cc9 100644 --- a/tests/extension/thread_/stream_pattern_len1/test_thread_stream_pattern_len1.py +++ b/tests/extension/thread_/stream_pattern_len1/test_thread_stream_pattern_len1.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_pattern_len1.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_pattern_len1/thread_stream_pattern_len1.py b/tests/extension/thread_/stream_pattern_len1/thread_stream_pattern_len1.py index adeb2e3a..07ccbc44 100644 --- a/tests/extension/thread_/stream_pattern_len1/thread_stream_pattern_len1.py +++ b/tests/extension/thread_/stream_pattern_len1/thread_stream_pattern_len1.py @@ -145,9 +145,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_pattern_source_join/test_thread_stream_pattern_source_join.py b/tests/extension/thread_/stream_pattern_source_join/test_thread_stream_pattern_source_join.py index 2c94a247..0da22ebf 100644 --- a/tests/extension/thread_/stream_pattern_source_join/test_thread_stream_pattern_source_join.py +++ b/tests/extension/thread_/stream_pattern_source_join/test_thread_stream_pattern_source_join.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_pattern_source_join.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_pattern_source_join/thread_stream_pattern_source_join.py b/tests/extension/thread_/stream_pattern_source_join/thread_stream_pattern_source_join.py index 7d4dac39..8450a684 100644 --- a/tests/extension/thread_/stream_pattern_source_join/thread_stream_pattern_source_join.py +++ b/tests/extension/thread_/stream_pattern_source_join/thread_stream_pattern_source_join.py @@ -151,9 +151,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_pattern_stall/test_thread_stream_pattern_stall.py b/tests/extension/thread_/stream_pattern_stall/test_thread_stream_pattern_stall.py index 7266edc5..7f8818c4 100644 --- a/tests/extension/thread_/stream_pattern_stall/test_thread_stream_pattern_stall.py +++ b/tests/extension/thread_/stream_pattern_stall/test_thread_stream_pattern_stall.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_pattern_stall.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_pattern_stall/thread_stream_pattern_stall.py b/tests/extension/thread_/stream_pattern_stall/thread_stream_pattern_stall.py index 1819adef..6f144edd 100644 --- a/tests/extension/thread_/stream_pattern_stall/thread_stream_pattern_stall.py +++ b/tests/extension/thread_/stream_pattern_stall/thread_stream_pattern_stall.py @@ -150,9 +150,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_pattern_zero/test_thread_stream_pattern_zero.py b/tests/extension/thread_/stream_pattern_zero/test_thread_stream_pattern_zero.py index dbc633ce..ccc8c22f 100644 --- a/tests/extension/thread_/stream_pattern_zero/test_thread_stream_pattern_zero.py +++ b/tests/extension/thread_/stream_pattern_zero/test_thread_stream_pattern_zero.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_pattern_zero.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_pattern_zero/thread_stream_pattern_zero.py b/tests/extension/thread_/stream_pattern_zero/thread_stream_pattern_zero.py index 86e56173..f1a09b2f 100644 --- a/tests/extension/thread_/stream_pattern_zero/thread_stream_pattern_zero.py +++ b/tests/extension/thread_/stream_pattern_zero/thread_stream_pattern_zero.py @@ -131,9 +131,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_predicate/test_thread_stream_predicate.py b/tests/extension/thread_/stream_predicate/test_thread_stream_predicate.py index 9bf169f1..a20258e7 100644 --- a/tests/extension/thread_/stream_predicate/test_thread_stream_predicate.py +++ b/tests/extension/thread_/stream_predicate/test_thread_stream_predicate.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_predicate.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_predicate/thread_stream_predicate.py b/tests/extension/thread_/stream_predicate/thread_stream_predicate.py index c0b52b2c..b4ce5ee0 100644 --- a/tests/extension/thread_/stream_predicate/thread_stream_predicate.py +++ b/tests/extension/thread_/stream_predicate/thread_stream_predicate.py @@ -128,9 +128,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_producer_consumer/test_thread_stream_producer_consumer.py b/tests/extension/thread_/stream_producer_consumer/test_thread_stream_producer_consumer.py index afc70abd..35478855 100644 --- a/tests/extension/thread_/stream_producer_consumer/test_thread_stream_producer_consumer.py +++ b/tests/extension/thread_/stream_producer_consumer/test_thread_stream_producer_consumer.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_producer_consumer.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_producer_consumer/thread_stream_producer_consumer.py b/tests/extension/thread_/stream_producer_consumer/thread_stream_producer_consumer.py index 99812bac..3198ffa9 100644 --- a/tests/extension/thread_/stream_producer_consumer/thread_stream_producer_consumer.py +++ b/tests/extension/thread_/stream_producer_consumer/thread_stream_producer_consumer.py @@ -164,9 +164,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_ram_external_ports/test_thread_stream_ram_external_ports.py b/tests/extension/thread_/stream_ram_external_ports/test_thread_stream_ram_external_ports.py index 4da186aa..3fd4fe95 100644 --- a/tests/extension/thread_/stream_ram_external_ports/test_thread_stream_ram_external_ports.py +++ b/tests/extension/thread_/stream_ram_external_ports/test_thread_stream_ram_external_ports.py @@ -161,7 +161,7 @@ (axis_maskaddr_5 == 1)? _saxi_resetval_1 : (axis_maskaddr_5 == 2)? _saxi_resetval_2 : (axis_maskaddr_5 == 3)? _saxi_resetval_3 : 'hx; - reg _saxi_cond_0_1; + reg _saxi_rdata_cond_0_1; assign saxi_wready = _saxi_register_fsm == 3; reg _mystream_stream_ivalid; wire _mystream_stream_oready; @@ -330,6 +330,27 @@ end + always @(posedge CLK) begin + if(RST) begin + saxi_rdata <= 0; + saxi_rvalid <= 0; + _saxi_rdata_cond_0_1 <= 0; + end else begin + if(_saxi_rdata_cond_0_1) begin + saxi_rvalid <= 0; + end + if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid)) begin + saxi_rdata <= axislite_rdata_6; + saxi_rvalid <= 1; + end + _saxi_rdata_cond_0_1 <= 1; + if(saxi_rvalid && !saxi_rready) begin + saxi_rvalid <= saxi_rvalid; + end + end + end + + always @(posedge CLK) begin if(RST) begin saxi_bvalid <= 0; @@ -338,9 +359,6 @@ writevalid_1 <= 0; readvalid_2 <= 0; addr_0 <= 0; - saxi_rdata <= 0; - saxi_rvalid <= 0; - _saxi_cond_0_1 <= 0; _saxi_register_0 <= 0; _saxi_flag_0 <= 0; _saxi_register_1 <= 0; @@ -350,9 +368,6 @@ _saxi_register_3 <= 0; _saxi_flag_3 <= 0; end else begin - if(_saxi_cond_0_1) begin - saxi_rvalid <= 0; - end if(saxi_bvalid && saxi_bready) begin saxi_bvalid <= 0; end @@ -370,14 +385,6 @@ addr_0 <= saxi_araddr; readvalid_2 <= 1; end - if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid)) begin - saxi_rdata <= axislite_rdata_6; - saxi_rvalid <= 1; - end - _saxi_cond_0_1 <= 1; - if(saxi_rvalid && !saxi_rready) begin - saxi_rvalid <= saxi_rvalid; - end if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid) && axislite_flag_7 && (axis_maskaddr_5 == 0)) begin _saxi_register_0 <= axislite_resetval_8; _saxi_flag_0 <= 0; diff --git a/tests/extension/thread_/stream_rand/test_thread_stream_rand.py b/tests/extension/thread_/stream_rand/test_thread_stream_rand.py index f8e7ac3d..0013c45c 100644 --- a/tests/extension/thread_/stream_rand/test_thread_stream_rand.py +++ b/tests/extension/thread_/stream_rand/test_thread_stream_rand.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_rand.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_rand/thread_stream_rand.py b/tests/extension/thread_/stream_rand/thread_stream_rand.py index 79ca1f9b..a2192d7f 100644 --- a/tests/extension/thread_/stream_rand/thread_stream_rand.py +++ b/tests/extension/thread_/stream_rand/thread_stream_rand.py @@ -152,9 +152,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_rand_xorshift/Makefile b/tests/extension/thread_/stream_rand_xorshift/Makefile new file mode 100644 index 00000000..d1ef91af --- /dev/null +++ b/tests/extension/thread_/stream_rand_xorshift/Makefile @@ -0,0 +1,29 @@ +TARGET=$(shell ls *.py | grep -v test | grep -v parsetab.py) +ARGS= + +PYTHON=python3 +#PYTHON=python +#OPT=-m pdb +#OPT=-m cProfile -s time +#OPT=-m cProfile -o profile.rslt + +.PHONY: all +all: test + +.PHONY: run +run: + $(PYTHON) $(OPT) $(TARGET) $(ARGS) + +.PHONY: test +test: + $(PYTHON) -m pytest -vv + +.PHONY: check +check: + $(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v + iverilog -tnull -Wall tmp.v + rm -f tmp.v + +.PHONY: clean +clean: + rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v *.vcd diff --git a/tests/extension/thread_/stream_rand_xorshift/test_thread_stream_rand_xorshift.py b/tests/extension/thread_/stream_rand_xorshift/test_thread_stream_rand_xorshift.py new file mode 100644 index 00000000..ce21020f --- /dev/null +++ b/tests/extension/thread_/stream_rand_xorshift/test_thread_stream_rand_xorshift.py @@ -0,0 +1,18 @@ +from __future__ import absolute_import +from __future__ import print_function + +import os +import veriloggen +import thread_stream_rand_xorshift + + +def test(request): + veriloggen.reset() + + simtype = request.config.getoption('--sim') + + rslt = thread_stream_rand_xorshift.run(filename=None, simtype=simtype, + outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') + + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] + assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_rand_xorshift/thread_stream_rand_xorshift.py b/tests/extension/thread_/stream_rand_xorshift/thread_stream_rand_xorshift.py new file mode 100644 index 00000000..65b4d0fb --- /dev/null +++ b/tests/extension/thread_/stream_rand_xorshift/thread_stream_rand_xorshift.py @@ -0,0 +1,145 @@ +from __future__ import absolute_import +from __future__ import print_function +import sys +import os + +# the next line can be removed after installation +sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname( + os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) + +from veriloggen import * +import veriloggen.thread as vthread +import veriloggen.types.axi as axi + + +def mkLed(): + m = Module('blinkled') + clk = m.Input('CLK') + rst = m.Input('RST') + + datawidth = 32 + addrwidth = 10 + initval = 0x12345678 + myaxi = vthread.AXIM(m, 'myaxi', clk, rst, datawidth) + ram_a = vthread.RAM(m, 'ram_a', clk, rst, datawidth, addrwidth) + ram_b = vthread.RAM(m, 'ram_b', clk, rst, datawidth, addrwidth) + ram_c = vthread.RAM(m, 'ram_c', clk, rst, datawidth, addrwidth) + + strm = vthread.Stream(m, 'mystream', clk, rst) + rand_hard = strm.RandXorshift(reg_initval=initval) + a = strm.source('a') + b = strm.source('b') + c = a + b - a - b + rand_hard + strm.sink(c, 'c') + + def comp_stream(size, offset): + strm.set_source('a', ram_a, offset, size) + strm.set_source('b', ram_b, offset, size) + strm.set_sink('c', ram_c, offset, size) + strm.run() + strm.join() + + def comp_sequential(size, offset): + rand_soft = initval + for i in range(size): + a = ram_a.read(i + offset) + b = ram_b.read(i + offset) + sum = a + b - a - b + rand_soft + ram_c.write(i + offset, sum) + + rand_soft = (rand_soft ^ (rand_soft << 13)) & ((1 << datawidth) - 1) + rand_soft = rand_soft ^ ((rand_soft >> 17) & ((1 << datawidth - 17) - 1)) + rand_soft = (rand_soft ^ (rand_soft << 5)) & ((1 << datawidth) - 1) + + def check(size, offset_stream, offset_seq): + all_ok = True + for i in range(size): + st = ram_c.read(i + offset_stream) + sq = ram_c.read(i + offset_seq) + if vthread.verilog.NotEql(st, sq): + all_ok = False + if all_ok: + print('# verify: PASSED') + else: + print('# verify: FAILED') + + def comp(size): + # stream + offset = 0 + myaxi.dma_read(ram_a, offset, 0, size) + myaxi.dma_read(ram_b, offset, 512, size) + comp_stream(size, offset) + myaxi.dma_write(ram_c, offset, 1024, size) + + # sequential + offset = size + myaxi.dma_read(ram_a, offset, 0, size) + myaxi.dma_read(ram_b, offset, 512, size) + comp_sequential(size, offset) + myaxi.dma_write(ram_c, offset, 1024 * 2, size) + + # verification + check(size, 0, offset) + + vthread.finish() + + th = vthread.Thread(m, 'th_comp', clk, rst, comp) + fsm = th.start(32) + + return m + + +def mkTest(memimg_name=None): + m = Module('test') + + # target instance + led = mkLed() + + # copy paras and ports + params = m.copy_params(led) + ports = m.copy_sim_ports(led) + + clk = ports['CLK'] + rst = ports['RST'] + + memory = axi.AxiMemoryModel(m, 'memory', clk, rst, memimg_name=memimg_name) + memory.connect(ports, 'myaxi') + + uut = m.Instance(led, 'uut', + params=m.connect_params(led), + ports=m.connect_ports(led)) + + # vcd_name = os.path.splitext(os.path.basename(__file__))[0] + '.vcd' + # simulation.setup_waveform(m, uut, dumpfile=vcd_name) + simulation.setup_clock(m, clk, hperiod=5) + init = simulation.setup_reset(m, rst, m.make_reset(), period=100) + + init.add( + Delay(1000000), + Systask('finish'), + ) + + return m + + +def run(filename='tmp.v', simtype='iverilog', outputfile=None): + + if outputfile is None: + outputfile = os.path.splitext(os.path.basename(__file__))[0] + '.out' + + memimg_name = 'memimg_' + outputfile + + test = mkTest(memimg_name=memimg_name) + + if filename is not None: + test.to_verilog(filename) + + sim = simulation.Simulator(test, sim=simtype) + rslt = sim.run(outputfile=outputfile) + + return rslt + + +if __name__ == '__main__': + rslt = run(filename='tmp.v') + print(rslt) diff --git a/tests/extension/thread_/stream_read_fifo/test_thread_stream_read_fifo.py b/tests/extension/thread_/stream_read_fifo/test_thread_stream_read_fifo.py index 4386ecbd..531a0738 100644 --- a/tests/extension/thread_/stream_read_fifo/test_thread_stream_read_fifo.py +++ b/tests/extension/thread_/stream_read_fifo/test_thread_stream_read_fifo.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_read_fifo.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_read_fifo/thread_stream_read_fifo.py b/tests/extension/thread_/stream_read_fifo/thread_stream_read_fifo.py index 47bc97f4..54c315de 100644 --- a/tests/extension/thread_/stream_read_fifo/thread_stream_read_fifo.py +++ b/tests/extension/thread_/stream_read_fifo/thread_stream_read_fifo.py @@ -166,9 +166,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_read_fifo_when/test_thread_stream_read_fifo_when.py b/tests/extension/thread_/stream_read_fifo_when/test_thread_stream_read_fifo_when.py index 6c025172..af328a83 100644 --- a/tests/extension/thread_/stream_read_fifo_when/test_thread_stream_read_fifo_when.py +++ b/tests/extension/thread_/stream_read_fifo_when/test_thread_stream_read_fifo_when.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_read_fifo_when.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_read_fifo_when/thread_stream_read_fifo_when.py b/tests/extension/thread_/stream_read_fifo_when/thread_stream_read_fifo_when.py index 68696dd2..9a7d9e80 100644 --- a/tests/extension/thread_/stream_read_fifo_when/thread_stream_read_fifo_when.py +++ b/tests/extension/thread_/stream_read_fifo_when/thread_stream_read_fifo_when.py @@ -170,9 +170,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_read_modify_write/test_thread_stream_read_modify_write.py b/tests/extension/thread_/stream_read_modify_write/test_thread_stream_read_modify_write.py index a500e6de..582af83d 100644 --- a/tests/extension/thread_/stream_read_modify_write/test_thread_stream_read_modify_write.py +++ b/tests/extension/thread_/stream_read_modify_write/test_thread_stream_read_modify_write.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_read_modify_write.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_read_modify_write/thread_stream_read_modify_write.py b/tests/extension/thread_/stream_read_modify_write/thread_stream_read_modify_write.py index 45123121..a5fde2b5 100644 --- a/tests/extension/thread_/stream_read_modify_write/thread_stream_read_modify_write.py +++ b/tests/extension/thread_/stream_read_modify_write/thread_stream_read_modify_write.py @@ -149,9 +149,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_read_modify_write_stall/test_thread_stream_read_modify_write_stall.py b/tests/extension/thread_/stream_read_modify_write_stall/test_thread_stream_read_modify_write_stall.py index fd63d22f..0120216b 100644 --- a/tests/extension/thread_/stream_read_modify_write_stall/test_thread_stream_read_modify_write_stall.py +++ b/tests/extension/thread_/stream_read_modify_write_stall/test_thread_stream_read_modify_write_stall.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_read_modify_write_stall.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_read_modify_write_stall/thread_stream_read_modify_write_stall.py b/tests/extension/thread_/stream_read_modify_write_stall/thread_stream_read_modify_write_stall.py index 1e555029..5bd0d664 100644 --- a/tests/extension/thread_/stream_read_modify_write_stall/thread_stream_read_modify_write_stall.py +++ b/tests/extension/thread_/stream_read_modify_write_stall/thread_stream_read_modify_write_stall.py @@ -159,9 +159,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_read_ram/test_thread_stream_read_ram.py b/tests/extension/thread_/stream_read_ram/test_thread_stream_read_ram.py index c11d8fc1..dc15db17 100644 --- a/tests/extension/thread_/stream_read_ram/test_thread_stream_read_ram.py +++ b/tests/extension/thread_/stream_read_ram/test_thread_stream_read_ram.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_read_ram.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_read_ram/thread_stream_read_ram.py b/tests/extension/thread_/stream_read_ram/thread_stream_read_ram.py index d95221db..5f7090b4 100644 --- a/tests/extension/thread_/stream_read_ram/thread_stream_read_ram.py +++ b/tests/extension/thread_/stream_read_ram/thread_stream_read_ram.py @@ -137,9 +137,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_read_ram_counter/test_thread_stream_read_ram_counter.py b/tests/extension/thread_/stream_read_ram_counter/test_thread_stream_read_ram_counter.py index ce11018e..320e59c8 100644 --- a/tests/extension/thread_/stream_read_ram_counter/test_thread_stream_read_ram_counter.py +++ b/tests/extension/thread_/stream_read_ram_counter/test_thread_stream_read_ram_counter.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_read_ram_counter.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_read_ram_counter/thread_stream_read_ram_counter.py b/tests/extension/thread_/stream_read_ram_counter/thread_stream_read_ram_counter.py index 099f63f6..cd7d244e 100644 --- a/tests/extension/thread_/stream_read_ram_counter/thread_stream_read_ram_counter.py +++ b/tests/extension/thread_/stream_read_ram_counter/thread_stream_read_ram_counter.py @@ -139,9 +139,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_read_ram_stall/test_thread_stream_read_ram_stall.py b/tests/extension/thread_/stream_read_ram_stall/test_thread_stream_read_ram_stall.py index 7c132944..fb7dd30b 100644 --- a/tests/extension/thread_/stream_read_ram_stall/test_thread_stream_read_ram_stall.py +++ b/tests/extension/thread_/stream_read_ram_stall/test_thread_stream_read_ram_stall.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_read_ram_stall.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_read_ram_stall/thread_stream_read_ram_stall.py b/tests/extension/thread_/stream_read_ram_stall/thread_stream_read_ram_stall.py index 1f32ca57..c9b59dc2 100644 --- a/tests/extension/thread_/stream_read_ram_stall/thread_stream_read_ram_stall.py +++ b/tests/extension/thread_/stream_read_ram_stall/thread_stream_read_ram_stall.py @@ -147,9 +147,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_read_ram_when/test_thread_stream_read_ram_when.py b/tests/extension/thread_/stream_read_ram_when/test_thread_stream_read_ram_when.py index aa80a25e..d796998c 100644 --- a/tests/extension/thread_/stream_read_ram_when/test_thread_stream_read_ram_when.py +++ b/tests/extension/thread_/stream_read_ram_when/test_thread_stream_read_ram_when.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_read_ram_when.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_read_ram_when/thread_stream_read_ram_when.py b/tests/extension/thread_/stream_read_ram_when/thread_stream_read_ram_when.py index 4568f01b..55c66c93 100644 --- a/tests/extension/thread_/stream_read_ram_when/thread_stream_read_ram_when.py +++ b/tests/extension/thread_/stream_read_ram_when/thread_stream_read_ram_when.py @@ -140,9 +140,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_reduce/test_thread_stream_reduce.py b/tests/extension/thread_/stream_reduce/test_thread_stream_reduce.py index 28b9f447..2ccd3675 100644 --- a/tests/extension/thread_/stream_reduce/test_thread_stream_reduce.py +++ b/tests/extension/thread_/stream_reduce/test_thread_stream_reduce.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_reduce.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_reduce/thread_stream_reduce.py b/tests/extension/thread_/stream_reduce/thread_stream_reduce.py index fd13c959..7fff3091 100644 --- a/tests/extension/thread_/stream_reduce/thread_stream_reduce.py +++ b/tests/extension/thread_/stream_reduce/thread_stream_reduce.py @@ -128,9 +128,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_reduce_arg_max/test_thread_stream_reduce_arg_max.py b/tests/extension/thread_/stream_reduce_arg_max/test_thread_stream_reduce_arg_max.py index 76b871a0..f3364a34 100644 --- a/tests/extension/thread_/stream_reduce_arg_max/test_thread_stream_reduce_arg_max.py +++ b/tests/extension/thread_/stream_reduce_arg_max/test_thread_stream_reduce_arg_max.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_reduce_arg_max.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_reduce_arg_max/thread_stream_reduce_arg_max.py b/tests/extension/thread_/stream_reduce_arg_max/thread_stream_reduce_arg_max.py index 27cb5729..107cadde 100644 --- a/tests/extension/thread_/stream_reduce_arg_max/thread_stream_reduce_arg_max.py +++ b/tests/extension/thread_/stream_reduce_arg_max/thread_stream_reduce_arg_max.py @@ -130,9 +130,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_reduce_div/test_thread_stream_reduce_div.py b/tests/extension/thread_/stream_reduce_div/test_thread_stream_reduce_div.py index dba38cd1..eb2750ea 100644 --- a/tests/extension/thread_/stream_reduce_div/test_thread_stream_reduce_div.py +++ b/tests/extension/thread_/stream_reduce_div/test_thread_stream_reduce_div.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_reduce_div.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_reduce_div/thread_stream_reduce_div.py b/tests/extension/thread_/stream_reduce_div/thread_stream_reduce_div.py index c2c0b3dd..29bc4b46 100644 --- a/tests/extension/thread_/stream_reduce_div/thread_stream_reduce_div.py +++ b/tests/extension/thread_/stream_reduce_div/thread_stream_reduce_div.py @@ -130,9 +130,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_reduce_initiation_interval/Makefile b/tests/extension/thread_/stream_reduce_initiation_interval/Makefile new file mode 100644 index 00000000..d1ef91af --- /dev/null +++ b/tests/extension/thread_/stream_reduce_initiation_interval/Makefile @@ -0,0 +1,29 @@ +TARGET=$(shell ls *.py | grep -v test | grep -v parsetab.py) +ARGS= + +PYTHON=python3 +#PYTHON=python +#OPT=-m pdb +#OPT=-m cProfile -s time +#OPT=-m cProfile -o profile.rslt + +.PHONY: all +all: test + +.PHONY: run +run: + $(PYTHON) $(OPT) $(TARGET) $(ARGS) + +.PHONY: test +test: + $(PYTHON) -m pytest -vv + +.PHONY: check +check: + $(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v + iverilog -tnull -Wall tmp.v + rm -f tmp.v + +.PHONY: clean +clean: + rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v *.vcd diff --git a/tests/extension/thread_/stream_reduce_initiation_interval/test_thread_stream_reduce_initiation_interval.py b/tests/extension/thread_/stream_reduce_initiation_interval/test_thread_stream_reduce_initiation_interval.py new file mode 100644 index 00000000..cae530fd --- /dev/null +++ b/tests/extension/thread_/stream_reduce_initiation_interval/test_thread_stream_reduce_initiation_interval.py @@ -0,0 +1,18 @@ +from __future__ import absolute_import +from __future__ import print_function + +import os +import veriloggen +import thread_stream_reduce_initiation_interval + + +def test(request): + veriloggen.reset() + + simtype = request.config.getoption('--sim') + + rslt = thread_stream_reduce_initiation_interval.run(filename=None, simtype=simtype, + outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') + + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] + assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_reduce_iteration_interval/thread_stream_reduce_iteration_interval.py b/tests/extension/thread_/stream_reduce_initiation_interval/thread_stream_reduce_initiation_interval.py similarity index 95% rename from tests/extension/thread_/stream_reduce_iteration_interval/thread_stream_reduce_iteration_interval.py rename to tests/extension/thread_/stream_reduce_initiation_interval/thread_stream_reduce_initiation_interval.py index 76e73b10..cd21eeff 100644 --- a/tests/extension/thread_/stream_reduce_iteration_interval/thread_stream_reduce_iteration_interval.py +++ b/tests/extension/thread_/stream_reduce_initiation_interval/thread_stream_reduce_initiation_interval.py @@ -27,7 +27,7 @@ def mkLed(): a = strm.source('a') + 1000 size = strm.parameter('size') sum, sum_valid = strm.ReduceAddValid(a, size) - sum.iteration_interval = 5 + sum.initiation_interval = 5 strm.sink(sum, 'sum', when=sum_valid, when_name='sum_valid') def comp_stream(size, offset): @@ -129,9 +129,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_reduce_iteration_interval/test_thread_stream_reduce_iteration_interval.py b/tests/extension/thread_/stream_reduce_iteration_interval/test_thread_stream_reduce_iteration_interval.py deleted file mode 100644 index 94a16137..00000000 --- a/tests/extension/thread_/stream_reduce_iteration_interval/test_thread_stream_reduce_iteration_interval.py +++ /dev/null @@ -1,18 +0,0 @@ -from __future__ import absolute_import -from __future__ import print_function - -import os -import veriloggen -import thread_stream_reduce_iteration_interval - - -def test(request): - veriloggen.reset() - - simtype = request.config.getoption('--sim') - - rslt = thread_stream_reduce_iteration_interval.run(filename=None, simtype=simtype, - outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - - verify_rslt = rslt.splitlines()[-1] - assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_reduce_max/test_thread_stream_reduce_max.py b/tests/extension/thread_/stream_reduce_max/test_thread_stream_reduce_max.py index 721c5e2c..0d13c9fa 100644 --- a/tests/extension/thread_/stream_reduce_max/test_thread_stream_reduce_max.py +++ b/tests/extension/thread_/stream_reduce_max/test_thread_stream_reduce_max.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_reduce_max.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_reduce_max/thread_stream_reduce_max.py b/tests/extension/thread_/stream_reduce_max/thread_stream_reduce_max.py index 65e18303..c2eb4bad 100644 --- a/tests/extension/thread_/stream_reduce_max/thread_stream_reduce_max.py +++ b/tests/extension/thread_/stream_reduce_max/thread_stream_reduce_max.py @@ -124,9 +124,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_reduce_mul/test_thread_stream_reduce_mul.py b/tests/extension/thread_/stream_reduce_mul/test_thread_stream_reduce_mul.py index 2af9654c..a6464d23 100644 --- a/tests/extension/thread_/stream_reduce_mul/test_thread_stream_reduce_mul.py +++ b/tests/extension/thread_/stream_reduce_mul/test_thread_stream_reduce_mul.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_reduce_mul.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_reduce_mul/thread_stream_reduce_mul.py b/tests/extension/thread_/stream_reduce_mul/thread_stream_reduce_mul.py index 78d5d8a6..d62d058d 100644 --- a/tests/extension/thread_/stream_reduce_mul/thread_stream_reduce_mul.py +++ b/tests/extension/thread_/stream_reduce_mul/thread_stream_reduce_mul.py @@ -128,9 +128,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_reduce_source_join/test_thread_stream_reduce_source_join.py b/tests/extension/thread_/stream_reduce_source_join/test_thread_stream_reduce_source_join.py index afe2873e..a5778e0c 100644 --- a/tests/extension/thread_/stream_reduce_source_join/test_thread_stream_reduce_source_join.py +++ b/tests/extension/thread_/stream_reduce_source_join/test_thread_stream_reduce_source_join.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_reduce_source_join.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_reduce_source_join/thread_stream_reduce_source_join.py b/tests/extension/thread_/stream_reduce_source_join/thread_stream_reduce_source_join.py index b3f98345..24b213b6 100644 --- a/tests/extension/thread_/stream_reduce_source_join/thread_stream_reduce_source_join.py +++ b/tests/extension/thread_/stream_reduce_source_join/thread_stream_reduce_source_join.py @@ -154,9 +154,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_reduce_source_join_and_run/test_thread_stream_reduce_source_join_and_run.py b/tests/extension/thread_/stream_reduce_source_join_and_run/test_thread_stream_reduce_source_join_and_run.py index 84c39596..8dcf3e58 100644 --- a/tests/extension/thread_/stream_reduce_source_join_and_run/test_thread_stream_reduce_source_join_and_run.py +++ b/tests/extension/thread_/stream_reduce_source_join_and_run/test_thread_stream_reduce_source_join_and_run.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_reduce_source_join_and_run.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_reduce_source_join_and_run/thread_stream_reduce_source_join_and_run.py b/tests/extension/thread_/stream_reduce_source_join_and_run/thread_stream_reduce_source_join_and_run.py index b4b4a73b..e8a8b12d 100644 --- a/tests/extension/thread_/stream_reduce_source_join_and_run/thread_stream_reduce_source_join_and_run.py +++ b/tests/extension/thread_/stream_reduce_source_join_and_run/thread_stream_reduce_source_join_and_run.py @@ -152,9 +152,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_reduce_stall/test_thread_stream_reduce_stall.py b/tests/extension/thread_/stream_reduce_stall/test_thread_stream_reduce_stall.py index c8868fac..5431e258 100644 --- a/tests/extension/thread_/stream_reduce_stall/test_thread_stream_reduce_stall.py +++ b/tests/extension/thread_/stream_reduce_stall/test_thread_stream_reduce_stall.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_reduce_stall.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_reduce_stall/thread_stream_reduce_stall.py b/tests/extension/thread_/stream_reduce_stall/thread_stream_reduce_stall.py index 21be34f4..9607073f 100644 --- a/tests/extension/thread_/stream_reduce_stall/thread_stream_reduce_stall.py +++ b/tests/extension/thread_/stream_reduce_stall/thread_stream_reduce_stall.py @@ -133,9 +133,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_reg/test_thread_stream_reg.py b/tests/extension/thread_/stream_reg/test_thread_stream_reg.py index 5ca1e078..96a9a062 100644 --- a/tests/extension/thread_/stream_reg/test_thread_stream_reg.py +++ b/tests/extension/thread_/stream_reg/test_thread_stream_reg.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_reg.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_reg/thread_stream_reg.py b/tests/extension/thread_/stream_reg/thread_stream_reg.py index c46136eb..1b7c4c5c 100644 --- a/tests/extension/thread_/stream_reg/thread_stream_reg.py +++ b/tests/extension/thread_/stream_reg/thread_stream_reg.py @@ -139,9 +139,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_reinterpret_cast/test_thread_stream_reinterpret_cast.py b/tests/extension/thread_/stream_reinterpret_cast/test_thread_stream_reinterpret_cast.py index 63e27540..564f579d 100644 --- a/tests/extension/thread_/stream_reinterpret_cast/test_thread_stream_reinterpret_cast.py +++ b/tests/extension/thread_/stream_reinterpret_cast/test_thread_stream_reinterpret_cast.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_reinterpret_cast.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_reinterpret_cast/thread_stream_reinterpret_cast.py b/tests/extension/thread_/stream_reinterpret_cast/thread_stream_reinterpret_cast.py index 20ec51da..78cd61ca 100644 --- a/tests/extension/thread_/stream_reinterpret_cast/thread_stream_reinterpret_cast.py +++ b/tests/extension/thread_/stream_reinterpret_cast/thread_stream_reinterpret_cast.py @@ -133,9 +133,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_ringbuffer/test_thread_stream_ringbuffer.py b/tests/extension/thread_/stream_ringbuffer/test_thread_stream_ringbuffer.py index 5b89d379..9ea5b66c 100644 --- a/tests/extension/thread_/stream_ringbuffer/test_thread_stream_ringbuffer.py +++ b/tests/extension/thread_/stream_ringbuffer/test_thread_stream_ringbuffer.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_ringbuffer.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_ringbuffer/thread_stream_ringbuffer.py b/tests/extension/thread_/stream_ringbuffer/thread_stream_ringbuffer.py index 860783e9..facbd2ac 100644 --- a/tests/extension/thread_/stream_ringbuffer/thread_stream_ringbuffer.py +++ b/tests/extension/thread_/stream_ringbuffer/thread_stream_ringbuffer.py @@ -134,9 +134,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_ringbuffer_multi/test_thread_stream_ringbuffer_multi.py b/tests/extension/thread_/stream_ringbuffer_multi/test_thread_stream_ringbuffer_multi.py index 9ce4fba8..141895ce 100644 --- a/tests/extension/thread_/stream_ringbuffer_multi/test_thread_stream_ringbuffer_multi.py +++ b/tests/extension/thread_/stream_ringbuffer_multi/test_thread_stream_ringbuffer_multi.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_ringbuffer_multi.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_ringbuffer_multi/thread_stream_ringbuffer_multi.py b/tests/extension/thread_/stream_ringbuffer_multi/thread_stream_ringbuffer_multi.py index 5b99f397..292cfd41 100644 --- a/tests/extension/thread_/stream_ringbuffer_multi/thread_stream_ringbuffer_multi.py +++ b/tests/extension/thread_/stream_ringbuffer_multi/thread_stream_ringbuffer_multi.py @@ -152,9 +152,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_ringbuffer_reuse/test_thread_stream_ringbuffer_reuse.py b/tests/extension/thread_/stream_ringbuffer_reuse/test_thread_stream_ringbuffer_reuse.py index dc2dceb6..b05893db 100644 --- a/tests/extension/thread_/stream_ringbuffer_reuse/test_thread_stream_ringbuffer_reuse.py +++ b/tests/extension/thread_/stream_ringbuffer_reuse/test_thread_stream_ringbuffer_reuse.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_ringbuffer_reuse.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_ringbuffer_reuse/thread_stream_ringbuffer_reuse.py b/tests/extension/thread_/stream_ringbuffer_reuse/thread_stream_ringbuffer_reuse.py index baa3f97b..aafdc6cc 100644 --- a/tests/extension/thread_/stream_ringbuffer_reuse/thread_stream_ringbuffer_reuse.py +++ b/tests/extension/thread_/stream_ringbuffer_reuse/thread_stream_ringbuffer_reuse.py @@ -143,9 +143,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_ringbuffer_stall/test_thread_stream_ringbuffer_stall.py b/tests/extension/thread_/stream_ringbuffer_stall/test_thread_stream_ringbuffer_stall.py index 1c2ec7b6..44ea8c63 100644 --- a/tests/extension/thread_/stream_ringbuffer_stall/test_thread_stream_ringbuffer_stall.py +++ b/tests/extension/thread_/stream_ringbuffer_stall/test_thread_stream_ringbuffer_stall.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_ringbuffer_stall.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_ringbuffer_stall/thread_stream_ringbuffer_stall.py b/tests/extension/thread_/stream_ringbuffer_stall/thread_stream_ringbuffer_stall.py index f9221ab3..3024104a 100644 --- a/tests/extension/thread_/stream_ringbuffer_stall/thread_stream_ringbuffer_stall.py +++ b/tests/extension/thread_/stream_ringbuffer_stall/thread_stream_ringbuffer_stall.py @@ -144,9 +144,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_scratchpad/test_thread_stream_scratchpad.py b/tests/extension/thread_/stream_scratchpad/test_thread_stream_scratchpad.py index 82bbf833..8a045191 100644 --- a/tests/extension/thread_/stream_scratchpad/test_thread_stream_scratchpad.py +++ b/tests/extension/thread_/stream_scratchpad/test_thread_stream_scratchpad.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_scratchpad.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_scratchpad/thread_stream_scratchpad.py b/tests/extension/thread_/stream_scratchpad/thread_stream_scratchpad.py index 6d428243..c0a05fce 100644 --- a/tests/extension/thread_/stream_scratchpad/thread_stream_scratchpad.py +++ b/tests/extension/thread_/stream_scratchpad/thread_stream_scratchpad.py @@ -137,9 +137,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_scratchpad_chain/test_thread_stream_scratchpad_chain.py b/tests/extension/thread_/stream_scratchpad_chain/test_thread_stream_scratchpad_chain.py index efa115df..606616e9 100644 --- a/tests/extension/thread_/stream_scratchpad_chain/test_thread_stream_scratchpad_chain.py +++ b/tests/extension/thread_/stream_scratchpad_chain/test_thread_stream_scratchpad_chain.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_scratchpad_chain.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_scratchpad_chain/thread_stream_scratchpad_chain.py b/tests/extension/thread_/stream_scratchpad_chain/thread_stream_scratchpad_chain.py index dc68a589..df5ac045 100644 --- a/tests/extension/thread_/stream_scratchpad_chain/thread_stream_scratchpad_chain.py +++ b/tests/extension/thread_/stream_scratchpad_chain/thread_stream_scratchpad_chain.py @@ -157,9 +157,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_scratchpad_multiread/test_thread_stream_scratchpad_multiread.py b/tests/extension/thread_/stream_scratchpad_multiread/test_thread_stream_scratchpad_multiread.py index a3de88bd..75023ee9 100644 --- a/tests/extension/thread_/stream_scratchpad_multiread/test_thread_stream_scratchpad_multiread.py +++ b/tests/extension/thread_/stream_scratchpad_multiread/test_thread_stream_scratchpad_multiread.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_scratchpad_multiread.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_scratchpad_multiread/thread_stream_scratchpad_multiread.py b/tests/extension/thread_/stream_scratchpad_multiread/thread_stream_scratchpad_multiread.py index c67e4dd6..88bf5f42 100644 --- a/tests/extension/thread_/stream_scratchpad_multiread/thread_stream_scratchpad_multiread.py +++ b/tests/extension/thread_/stream_scratchpad_multiread/thread_stream_scratchpad_multiread.py @@ -155,9 +155,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_scratchpad_stall/test_thread_stream_scratchpad_stall.py b/tests/extension/thread_/stream_scratchpad_stall/test_thread_stream_scratchpad_stall.py index 505c3ecd..70047af0 100644 --- a/tests/extension/thread_/stream_scratchpad_stall/test_thread_stream_scratchpad_stall.py +++ b/tests/extension/thread_/stream_scratchpad_stall/test_thread_stream_scratchpad_stall.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_scratchpad_stall.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_scratchpad_stall/thread_stream_scratchpad_stall.py b/tests/extension/thread_/stream_scratchpad_stall/thread_stream_scratchpad_stall.py index fc3dc839..37e88102 100644 --- a/tests/extension/thread_/stream_scratchpad_stall/thread_stream_scratchpad_stall.py +++ b/tests/extension/thread_/stream_scratchpad_stall/thread_stream_scratchpad_stall.py @@ -147,9 +147,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_scratchpad_when/test_thread_stream_scratchpad_when.py b/tests/extension/thread_/stream_scratchpad_when/test_thread_stream_scratchpad_when.py index b535b2ae..a90502e8 100644 --- a/tests/extension/thread_/stream_scratchpad_when/test_thread_stream_scratchpad_when.py +++ b/tests/extension/thread_/stream_scratchpad_when/test_thread_stream_scratchpad_when.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_scratchpad_when.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_scratchpad_when/thread_stream_scratchpad_when.py b/tests/extension/thread_/stream_scratchpad_when/thread_stream_scratchpad_when.py index 25add509..dbe83fee 100644 --- a/tests/extension/thread_/stream_scratchpad_when/thread_stream_scratchpad_when.py +++ b/tests/extension/thread_/stream_scratchpad_when/thread_stream_scratchpad_when.py @@ -137,9 +137,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_sink_fifo/test_thread_stream_sink_fifo.py b/tests/extension/thread_/stream_sink_fifo/test_thread_stream_sink_fifo.py index ca8ece62..2fbe7fdf 100644 --- a/tests/extension/thread_/stream_sink_fifo/test_thread_stream_sink_fifo.py +++ b/tests/extension/thread_/stream_sink_fifo/test_thread_stream_sink_fifo.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_sink_fifo.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_sink_fifo/thread_stream_sink_fifo.py b/tests/extension/thread_/stream_sink_fifo/thread_stream_sink_fifo.py index f8cab008..2ebe1bd1 100644 --- a/tests/extension/thread_/stream_sink_fifo/thread_stream_sink_fifo.py +++ b/tests/extension/thread_/stream_sink_fifo/thread_stream_sink_fifo.py @@ -163,9 +163,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_source_fifo/test_thread_stream_source_fifo.py b/tests/extension/thread_/stream_source_fifo/test_thread_stream_source_fifo.py index 79b01709..6bb154f6 100644 --- a/tests/extension/thread_/stream_source_fifo/test_thread_stream_source_fifo.py +++ b/tests/extension/thread_/stream_source_fifo/test_thread_stream_source_fifo.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_source_fifo.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_source_fifo/thread_stream_source_fifo.py b/tests/extension/thread_/stream_source_fifo/thread_stream_source_fifo.py index 4fd46c17..4a2db1da 100644 --- a/tests/extension/thread_/stream_source_fifo/thread_stream_source_fifo.py +++ b/tests/extension/thread_/stream_source_fifo/thread_stream_source_fifo.py @@ -161,9 +161,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_source_join/test_thread_stream_source_join.py b/tests/extension/thread_/stream_source_join/test_thread_stream_source_join.py index 1eb21c82..66762574 100644 --- a/tests/extension/thread_/stream_source_join/test_thread_stream_source_join.py +++ b/tests/extension/thread_/stream_source_join/test_thread_stream_source_join.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_source_join.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_source_join/thread_stream_source_join.py b/tests/extension/thread_/stream_source_join/thread_stream_source_join.py index 3d992964..badd86c3 100644 --- a/tests/extension/thread_/stream_source_join/thread_stream_source_join.py +++ b/tests/extension/thread_/stream_source_join/thread_stream_source_join.py @@ -151,9 +151,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_source_join_and_run/test_thread_stream_source_join_and_run.py b/tests/extension/thread_/stream_source_join_and_run/test_thread_stream_source_join_and_run.py index e9cfa79d..54c8f552 100644 --- a/tests/extension/thread_/stream_source_join_and_run/test_thread_stream_source_join_and_run.py +++ b/tests/extension/thread_/stream_source_join_and_run/test_thread_stream_source_join_and_run.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_source_join_and_run.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_source_join_and_run/thread_stream_source_join_and_run.py b/tests/extension/thread_/stream_source_join_and_run/thread_stream_source_join_and_run.py index 94d89653..a93ed088 100644 --- a/tests/extension/thread_/stream_source_join_and_run/thread_stream_source_join_and_run.py +++ b/tests/extension/thread_/stream_source_join_and_run/thread_stream_source_join_and_run.py @@ -140,9 +140,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_split/test_thread_stream_split.py b/tests/extension/thread_/stream_split/test_thread_stream_split.py index be719e15..64fcd493 100644 --- a/tests/extension/thread_/stream_split/test_thread_stream_split.py +++ b/tests/extension/thread_/stream_split/test_thread_stream_split.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_split.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_split/thread_stream_split.py b/tests/extension/thread_/stream_split/thread_stream_split.py index fed6ec21..9cb1abf9 100644 --- a/tests/extension/thread_/stream_split/thread_stream_split.py +++ b/tests/extension/thread_/stream_split/thread_stream_split.py @@ -144,9 +144,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_split_residue/test_thread_stream_split_residue.py b/tests/extension/thread_/stream_split_residue/test_thread_stream_split_residue.py index cc74d8dd..ad9bf397 100644 --- a/tests/extension/thread_/stream_split_residue/test_thread_stream_split_residue.py +++ b/tests/extension/thread_/stream_split_residue/test_thread_stream_split_residue.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_split_residue.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_split_residue/thread_stream_split_residue.py b/tests/extension/thread_/stream_split_residue/thread_stream_split_residue.py index 55f28764..b81632dd 100644 --- a/tests/extension/thread_/stream_split_residue/thread_stream_split_residue.py +++ b/tests/extension/thread_/stream_split_residue/thread_stream_split_residue.py @@ -155,9 +155,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_split_reverse/test_thread_stream_split_reverse.py b/tests/extension/thread_/stream_split_reverse/test_thread_stream_split_reverse.py index 4801805a..99611d5c 100644 --- a/tests/extension/thread_/stream_split_reverse/test_thread_stream_split_reverse.py +++ b/tests/extension/thread_/stream_split_reverse/test_thread_stream_split_reverse.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_split_reverse.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_split_reverse/thread_stream_split_reverse.py b/tests/extension/thread_/stream_split_reverse/thread_stream_split_reverse.py index d397092b..89b519e4 100644 --- a/tests/extension/thread_/stream_split_reverse/thread_stream_split_reverse.py +++ b/tests/extension/thread_/stream_split_reverse/thread_stream_split_reverse.py @@ -144,9 +144,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_stall/test_thread_stream_stall.py b/tests/extension/thread_/stream_stall/test_thread_stream_stall.py index 503152e7..fd4d5d0b 100644 --- a/tests/extension/thread_/stream_stall/test_thread_stream_stall.py +++ b/tests/extension/thread_/stream_stall/test_thread_stream_stall.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_stall.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_stall/thread_stream_stall.py b/tests/extension/thread_/stream_stall/thread_stream_stall.py index ef263662..41f728c8 100644 --- a/tests/extension/thread_/stream_stall/thread_stream_stall.py +++ b/tests/extension/thread_/stream_stall/thread_stream_stall.py @@ -142,9 +142,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_stride/test_thread_stream_stride.py b/tests/extension/thread_/stream_stride/test_thread_stream_stride.py index def84e86..686333d1 100644 --- a/tests/extension/thread_/stream_stride/test_thread_stream_stride.py +++ b/tests/extension/thread_/stream_stride/test_thread_stream_stride.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_stride.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_stride/thread_stream_stride.py b/tests/extension/thread_/stream_stride/thread_stream_stride.py index 131ba72c..92e0b9bc 100644 --- a/tests/extension/thread_/stream_stride/thread_stream_stride.py +++ b/tests/extension/thread_/stream_stride/thread_stream_stride.py @@ -129,9 +129,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_substream/test_thread_stream_substream.py b/tests/extension/thread_/stream_substream/test_thread_stream_substream.py index 314ca1d3..d550c6be 100644 --- a/tests/extension/thread_/stream_substream/test_thread_stream_substream.py +++ b/tests/extension/thread_/stream_substream/test_thread_stream_substream.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_substream.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_substream/thread_stream_substream.py b/tests/extension/thread_/stream_substream/thread_stream_substream.py index ad327124..6c3ff3aa 100644 --- a/tests/extension/thread_/stream_substream/thread_stream_substream.py +++ b/tests/extension/thread_/stream_substream/thread_stream_substream.py @@ -242,9 +242,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_substream_dump/test_thread_stream_substream_dump.py b/tests/extension/thread_/stream_substream_dump/test_thread_stream_substream_dump.py index 60564d62..8d585b88 100644 --- a/tests/extension/thread_/stream_substream_dump/test_thread_stream_substream_dump.py +++ b/tests/extension/thread_/stream_substream_dump/test_thread_stream_substream_dump.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_substream_dump.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_substream_dump/thread_stream_substream_dump.py b/tests/extension/thread_/stream_substream_dump/thread_stream_substream_dump.py index 632cded4..b4344a68 100644 --- a/tests/extension/thread_/stream_substream_dump/thread_stream_substream_dump.py +++ b/tests/extension/thread_/stream_substream_dump/thread_stream_substream_dump.py @@ -236,9 +236,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_substream_multicall/test_thread_stream_substream_multicall.py b/tests/extension/thread_/stream_substream_multicall/test_thread_stream_substream_multicall.py index 419644dd..3538c275 100644 --- a/tests/extension/thread_/stream_substream_multicall/test_thread_stream_substream_multicall.py +++ b/tests/extension/thread_/stream_substream_multicall/test_thread_stream_substream_multicall.py @@ -15,5 +15,5 @@ def test(request): filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_substream_multicall/thread_stream_substream_multicall.py b/tests/extension/thread_/stream_substream_multicall/thread_stream_substream_multicall.py index 58dc4e49..6cb74e9a 100644 --- a/tests/extension/thread_/stream_substream_multicall/thread_stream_substream_multicall.py +++ b/tests/extension/thread_/stream_substream_multicall/thread_stream_substream_multicall.py @@ -275,9 +275,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_substream_multicycle/test_thread_stream_substream_multicycle.py b/tests/extension/thread_/stream_substream_multicycle/test_thread_stream_substream_multicycle.py index 13b16a5d..d5bee4f9 100644 --- a/tests/extension/thread_/stream_substream_multicycle/test_thread_stream_substream_multicycle.py +++ b/tests/extension/thread_/stream_substream_multicycle/test_thread_stream_substream_multicycle.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_substream_multicycle.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_substream_multicycle/thread_stream_substream_multicycle.py b/tests/extension/thread_/stream_substream_multicycle/thread_stream_substream_multicycle.py index 997cde29..9ce814d6 100644 --- a/tests/extension/thread_/stream_substream_multicycle/thread_stream_substream_multicycle.py +++ b/tests/extension/thread_/stream_substream_multicycle/thread_stream_substream_multicycle.py @@ -187,9 +187,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_substream_multicycle2/test_thread_stream_substream_multicycle2.py b/tests/extension/thread_/stream_substream_multicycle2/test_thread_stream_substream_multicycle2.py index cbaf548d..b8c12e87 100644 --- a/tests/extension/thread_/stream_substream_multicycle2/test_thread_stream_substream_multicycle2.py +++ b/tests/extension/thread_/stream_substream_multicycle2/test_thread_stream_substream_multicycle2.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_substream_multicycle2.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_substream_multicycle2/thread_stream_substream_multicycle2.py b/tests/extension/thread_/stream_substream_multicycle2/thread_stream_substream_multicycle2.py index 5ed94b89..72566f4a 100644 --- a/tests/extension/thread_/stream_substream_multicycle2/thread_stream_substream_multicycle2.py +++ b/tests/extension/thread_/stream_substream_multicycle2/thread_stream_substream_multicycle2.py @@ -242,9 +242,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_substream_multicycle_read_write_ram/test_thread_stream_substream_multicycle_read_modify_write.py b/tests/extension/thread_/stream_substream_multicycle_read_write_ram/test_thread_stream_substream_multicycle_read_modify_write.py index 58fe20e6..cd030822 100644 --- a/tests/extension/thread_/stream_substream_multicycle_read_write_ram/test_thread_stream_substream_multicycle_read_modify_write.py +++ b/tests/extension/thread_/stream_substream_multicycle_read_write_ram/test_thread_stream_substream_multicycle_read_modify_write.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_substream_multicycle_read_modify_write.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_substream_multicycle_read_write_ram/thread_stream_substream_multicycle_read_modify_write.py b/tests/extension/thread_/stream_substream_multicycle_read_write_ram/thread_stream_substream_multicycle_read_modify_write.py index e1914f74..5021219c 100644 --- a/tests/extension/thread_/stream_substream_multicycle_read_write_ram/thread_stream_substream_multicycle_read_modify_write.py +++ b/tests/extension/thread_/stream_substream_multicycle_read_write_ram/thread_stream_substream_multicycle_read_modify_write.py @@ -165,9 +165,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_substream_multicycle_reduce/test_thread_stream_substream_multicycle_reduce.py b/tests/extension/thread_/stream_substream_multicycle_reduce/test_thread_stream_substream_multicycle_reduce.py index 4fa19e85..ef1562b8 100644 --- a/tests/extension/thread_/stream_substream_multicycle_reduce/test_thread_stream_substream_multicycle_reduce.py +++ b/tests/extension/thread_/stream_substream_multicycle_reduce/test_thread_stream_substream_multicycle_reduce.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_substream_multicycle_reduce.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_substream_multicycle_reduce/thread_stream_substream_multicycle_reduce.py b/tests/extension/thread_/stream_substream_multicycle_reduce/thread_stream_substream_multicycle_reduce.py index 68634dec..9118873b 100644 --- a/tests/extension/thread_/stream_substream_multicycle_reduce/thread_stream_substream_multicycle_reduce.py +++ b/tests/extension/thread_/stream_substream_multicycle_reduce/thread_stream_substream_multicycle_reduce.py @@ -193,9 +193,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_substream_nested_reduce/test_thread_stream_substream_nested_reduce.py b/tests/extension/thread_/stream_substream_nested_reduce/test_thread_stream_substream_nested_reduce.py index 142b1971..f31bf739 100644 --- a/tests/extension/thread_/stream_substream_nested_reduce/test_thread_stream_substream_nested_reduce.py +++ b/tests/extension/thread_/stream_substream_nested_reduce/test_thread_stream_substream_nested_reduce.py @@ -15,5 +15,5 @@ def test(request): filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_substream_nested_reduce/thread_stream_substream_nested_reduce.py b/tests/extension/thread_/stream_substream_nested_reduce/thread_stream_substream_nested_reduce.py index e6ea513e..6dbb0d2c 100644 --- a/tests/extension/thread_/stream_substream_nested_reduce/thread_stream_substream_nested_reduce.py +++ b/tests/extension/thread_/stream_substream_nested_reduce/thread_stream_substream_nested_reduce.py @@ -226,9 +226,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_substream_nested_reduce2/test_thread_stream_substream_nested_reduce2.py b/tests/extension/thread_/stream_substream_nested_reduce2/test_thread_stream_substream_nested_reduce2.py index a5d1a38e..8c756a2e 100644 --- a/tests/extension/thread_/stream_substream_nested_reduce2/test_thread_stream_substream_nested_reduce2.py +++ b/tests/extension/thread_/stream_substream_nested_reduce2/test_thread_stream_substream_nested_reduce2.py @@ -15,5 +15,5 @@ def test(request): filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_substream_nested_reduce2/thread_stream_substream_nested_reduce2.py b/tests/extension/thread_/stream_substream_nested_reduce2/thread_stream_substream_nested_reduce2.py index 7330f5fb..acb10293 100644 --- a/tests/extension/thread_/stream_substream_nested_reduce2/thread_stream_substream_nested_reduce2.py +++ b/tests/extension/thread_/stream_substream_nested_reduce2/thread_stream_substream_nested_reduce2.py @@ -235,9 +235,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_substream_nested_reduce3/test_thread_stream_substream_nested_reduce3.py b/tests/extension/thread_/stream_substream_nested_reduce3/test_thread_stream_substream_nested_reduce3.py index 66754e42..735f6e0c 100644 --- a/tests/extension/thread_/stream_substream_nested_reduce3/test_thread_stream_substream_nested_reduce3.py +++ b/tests/extension/thread_/stream_substream_nested_reduce3/test_thread_stream_substream_nested_reduce3.py @@ -15,5 +15,5 @@ def test(request): filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_substream_nested_reduce3/thread_stream_substream_nested_reduce3.py b/tests/extension/thread_/stream_substream_nested_reduce3/thread_stream_substream_nested_reduce3.py index ccd5f4c0..6482723d 100644 --- a/tests/extension/thread_/stream_substream_nested_reduce3/thread_stream_substream_nested_reduce3.py +++ b/tests/extension/thread_/stream_substream_nested_reduce3/thread_stream_substream_nested_reduce3.py @@ -236,9 +236,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_substream_reduce/test_thread_stream_substream_reduce.py b/tests/extension/thread_/stream_substream_reduce/test_thread_stream_substream_reduce.py index feb20bb9..850706ea 100644 --- a/tests/extension/thread_/stream_substream_reduce/test_thread_stream_substream_reduce.py +++ b/tests/extension/thread_/stream_substream_reduce/test_thread_stream_substream_reduce.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_substream_reduce.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_substream_reduce/thread_stream_substream_reduce.py b/tests/extension/thread_/stream_substream_reduce/thread_stream_substream_reduce.py index 25db4876..6c69dc5f 100644 --- a/tests/extension/thread_/stream_substream_reduce/thread_stream_substream_reduce.py +++ b/tests/extension/thread_/stream_substream_reduce/thread_stream_substream_reduce.py @@ -204,9 +204,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_substream_stall/test_thread_stream_substream_stall.py b/tests/extension/thread_/stream_substream_stall/test_thread_stream_substream_stall.py index 50b4e64e..faae6abb 100644 --- a/tests/extension/thread_/stream_substream_stall/test_thread_stream_substream_stall.py +++ b/tests/extension/thread_/stream_substream_stall/test_thread_stream_substream_stall.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_substream_stall.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_substream_stall/thread_stream_substream_stall.py b/tests/extension/thread_/stream_substream_stall/thread_stream_substream_stall.py index d48e4eca..5de47de9 100644 --- a/tests/extension/thread_/stream_substream_stall/thread_stream_substream_stall.py +++ b/tests/extension/thread_/stream_substream_stall/thread_stream_substream_stall.py @@ -258,9 +258,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_substream_unbalance/test_thread_stream_substream_unblance.py b/tests/extension/thread_/stream_substream_unbalance/test_thread_stream_substream_unblance.py index 921adf7a..cb35cb9a 100644 --- a/tests/extension/thread_/stream_substream_unbalance/test_thread_stream_substream_unblance.py +++ b/tests/extension/thread_/stream_substream_unbalance/test_thread_stream_substream_unblance.py @@ -15,5 +15,5 @@ def test(request): filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_substream_unbalance/thread_stream_substream_unbalance.py b/tests/extension/thread_/stream_substream_unbalance/thread_stream_substream_unbalance.py index c9f970dd..317a4efa 100644 --- a/tests/extension/thread_/stream_substream_unbalance/thread_stream_substream_unbalance.py +++ b/tests/extension/thread_/stream_substream_unbalance/thread_stream_substream_unbalance.py @@ -203,9 +203,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_sync/test_thread_stream_sync.py b/tests/extension/thread_/stream_sync/test_thread_stream_sync.py index a2091e7a..abeb1486 100644 --- a/tests/extension/thread_/stream_sync/test_thread_stream_sync.py +++ b/tests/extension/thread_/stream_sync/test_thread_stream_sync.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_sync.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_sync/thread_stream_sync.py b/tests/extension/thread_/stream_sync/thread_stream_sync.py index 69321918..6efe0b7d 100644 --- a/tests/extension/thread_/stream_sync/thread_stream_sync.py +++ b/tests/extension/thread_/stream_sync/thread_stream_sync.py @@ -134,9 +134,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_terminate/test_thread_stream_terminate.py b/tests/extension/thread_/stream_terminate/test_thread_stream_terminate.py index efd603f5..089002cf 100644 --- a/tests/extension/thread_/stream_terminate/test_thread_stream_terminate.py +++ b/tests/extension/thread_/stream_terminate/test_thread_stream_terminate.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_terminate.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_terminate/thread_stream_terminate.py b/tests/extension/thread_/stream_terminate/thread_stream_terminate.py index d8ab82fb..8543e03a 100644 --- a/tests/extension/thread_/stream_terminate/thread_stream_terminate.py +++ b/tests/extension/thread_/stream_terminate/thread_stream_terminate.py @@ -147,9 +147,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_terminate_search/test_thread_stream_terminate_search.py b/tests/extension/thread_/stream_terminate_search/test_thread_stream_terminate_search.py index 6aba3108..98eb1eb4 100644 --- a/tests/extension/thread_/stream_terminate_search/test_thread_stream_terminate_search.py +++ b/tests/extension/thread_/stream_terminate_search/test_thread_stream_terminate_search.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_terminate_search.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_terminate_search/thread_stream_terminate_search.py b/tests/extension/thread_/stream_terminate_search/thread_stream_terminate_search.py index 8e91765d..08dd6da0 100644 --- a/tests/extension/thread_/stream_terminate_search/thread_stream_terminate_search.py +++ b/tests/extension/thread_/stream_terminate_search/thread_stream_terminate_search.py @@ -125,9 +125,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_terminate_search_stall/test_thread_stream_terminate_search_stall.py b/tests/extension/thread_/stream_terminate_search_stall/test_thread_stream_terminate_search_stall.py index fecb5aa4..a97cc4f3 100644 --- a/tests/extension/thread_/stream_terminate_search_stall/test_thread_stream_terminate_search_stall.py +++ b/tests/extension/thread_/stream_terminate_search_stall/test_thread_stream_terminate_search_stall.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_terminate_search_stall.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_terminate_search_stall/thread_stream_terminate_search_stall.py b/tests/extension/thread_/stream_terminate_search_stall/thread_stream_terminate_search_stall.py index 8b86a747..68f2ec9c 100644 --- a/tests/extension/thread_/stream_terminate_search_stall/thread_stream_terminate_search_stall.py +++ b/tests/extension/thread_/stream_terminate_search_stall/thread_stream_terminate_search_stall.py @@ -135,9 +135,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_terminate_source_join_and_run/test_thread_stream_terminate_source_join_and_run.py b/tests/extension/thread_/stream_terminate_source_join_and_run/test_thread_stream_terminate_source_join_and_run.py index 5fe755b9..001ce29a 100644 --- a/tests/extension/thread_/stream_terminate_source_join_and_run/test_thread_stream_terminate_source_join_and_run.py +++ b/tests/extension/thread_/stream_terminate_source_join_and_run/test_thread_stream_terminate_source_join_and_run.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_terminate_source_join_and_run.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_terminate_source_join_and_run/thread_stream_terminate_source_join_and_run.py b/tests/extension/thread_/stream_terminate_source_join_and_run/thread_stream_terminate_source_join_and_run.py index 9364ef32..508cb6bd 100644 --- a/tests/extension/thread_/stream_terminate_source_join_and_run/thread_stream_terminate_source_join_and_run.py +++ b/tests/extension/thread_/stream_terminate_source_join_and_run/thread_stream_terminate_source_join_and_run.py @@ -166,9 +166,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_terminate_stall/test_thread_stream_terminate_stall.py b/tests/extension/thread_/stream_terminate_stall/test_thread_stream_terminate_stall.py index a61d096a..26044ae4 100644 --- a/tests/extension/thread_/stream_terminate_stall/test_thread_stream_terminate_stall.py +++ b/tests/extension/thread_/stream_terminate_stall/test_thread_stream_terminate_stall.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_terminate_stall.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_terminate_stall/thread_stream_terminate_stall.py b/tests/extension/thread_/stream_terminate_stall/thread_stream_terminate_stall.py index 75c02931..3b42cd4e 100644 --- a/tests/extension/thread_/stream_terminate_stall/thread_stream_terminate_stall.py +++ b/tests/extension/thread_/stream_terminate_stall/thread_stream_terminate_stall.py @@ -157,9 +157,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_transpose/test_thread_stream_transpose.py b/tests/extension/thread_/stream_transpose/test_thread_stream_transpose.py index 757b6c81..1f7aaf5d 100644 --- a/tests/extension/thread_/stream_transpose/test_thread_stream_transpose.py +++ b/tests/extension/thread_/stream_transpose/test_thread_stream_transpose.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_transpose.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_transpose/thread_stream_transpose.py b/tests/extension/thread_/stream_transpose/thread_stream_transpose.py index 1dd1b7ad..d20286b6 100644 --- a/tests/extension/thread_/stream_transpose/thread_stream_transpose.py +++ b/tests/extension/thread_/stream_transpose/thread_stream_transpose.py @@ -146,9 +146,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_variable_latency/test_thread_stream_variable_latency.py b/tests/extension/thread_/stream_variable_latency/test_thread_stream_variable_latency.py index 67ee78ce..dfdfc7a8 100644 --- a/tests/extension/thread_/stream_variable_latency/test_thread_stream_variable_latency.py +++ b/tests/extension/thread_/stream_variable_latency/test_thread_stream_variable_latency.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_variable_latency.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_variable_latency/thread_stream_variable_latency.py b/tests/extension/thread_/stream_variable_latency/thread_stream_variable_latency.py index 7662c75f..6110459c 100644 --- a/tests/extension/thread_/stream_variable_latency/thread_stream_variable_latency.py +++ b/tests/extension/thread_/stream_variable_latency/thread_stream_variable_latency.py @@ -131,9 +131,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_write_fifo/test_thread_stream_write_fifo.py b/tests/extension/thread_/stream_write_fifo/test_thread_stream_write_fifo.py index 92a36cca..9ab72930 100644 --- a/tests/extension/thread_/stream_write_fifo/test_thread_stream_write_fifo.py +++ b/tests/extension/thread_/stream_write_fifo/test_thread_stream_write_fifo.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_write_fifo.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_write_fifo/thread_stream_write_fifo.py b/tests/extension/thread_/stream_write_fifo/thread_stream_write_fifo.py index 7beb590f..f13e7743 100644 --- a/tests/extension/thread_/stream_write_fifo/thread_stream_write_fifo.py +++ b/tests/extension/thread_/stream_write_fifo/thread_stream_write_fifo.py @@ -167,9 +167,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_write_fifo_when/test_thread_stream_write_fifo_when.py b/tests/extension/thread_/stream_write_fifo_when/test_thread_stream_write_fifo_when.py index 0ff6e70d..c2341132 100644 --- a/tests/extension/thread_/stream_write_fifo_when/test_thread_stream_write_fifo_when.py +++ b/tests/extension/thread_/stream_write_fifo_when/test_thread_stream_write_fifo_when.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_write_fifo_when.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_write_fifo_when/thread_stream_write_fifo_when.py b/tests/extension/thread_/stream_write_fifo_when/thread_stream_write_fifo_when.py index b191ffaa..50c0b258 100644 --- a/tests/extension/thread_/stream_write_fifo_when/thread_stream_write_fifo_when.py +++ b/tests/extension/thread_/stream_write_fifo_when/thread_stream_write_fifo_when.py @@ -173,9 +173,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_write_ram/test_thread_stream_write_ram.py b/tests/extension/thread_/stream_write_ram/test_thread_stream_write_ram.py index 11673541..1ca2a18c 100644 --- a/tests/extension/thread_/stream_write_ram/test_thread_stream_write_ram.py +++ b/tests/extension/thread_/stream_write_ram/test_thread_stream_write_ram.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_write_ram.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_write_ram/thread_stream_write_ram.py b/tests/extension/thread_/stream_write_ram/thread_stream_write_ram.py index 834eb23b..61200f21 100644 --- a/tests/extension/thread_/stream_write_ram/thread_stream_write_ram.py +++ b/tests/extension/thread_/stream_write_ram/thread_stream_write_ram.py @@ -143,9 +143,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_write_ram_dump/test_thread_stream_write_ram_dump.py b/tests/extension/thread_/stream_write_ram_dump/test_thread_stream_write_ram_dump.py index b07e348d..921f71fb 100644 --- a/tests/extension/thread_/stream_write_ram_dump/test_thread_stream_write_ram_dump.py +++ b/tests/extension/thread_/stream_write_ram_dump/test_thread_stream_write_ram_dump.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_write_ram_dump.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_write_ram_dump/thread_stream_write_ram_dump.py b/tests/extension/thread_/stream_write_ram_dump/thread_stream_write_ram_dump.py index 011fa065..6c233c63 100644 --- a/tests/extension/thread_/stream_write_ram_dump/thread_stream_write_ram_dump.py +++ b/tests/extension/thread_/stream_write_ram_dump/thread_stream_write_ram_dump.py @@ -142,9 +142,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/stream_write_ram_stall/test_thread_stream_write_ram_stall.py b/tests/extension/thread_/stream_write_ram_stall/test_thread_stream_write_ram_stall.py index 0d66796d..6ff3f9ca 100644 --- a/tests/extension/thread_/stream_write_ram_stall/test_thread_stream_write_ram_stall.py +++ b/tests/extension/thread_/stream_write_ram_stall/test_thread_stream_write_ram_stall.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_stream_write_ram_stall.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/stream_write_ram_stall/thread_stream_write_ram_stall.py b/tests/extension/thread_/stream_write_ram_stall/thread_stream_write_ram_stall.py index a9fccaf3..341e1cb8 100644 --- a/tests/extension/thread_/stream_write_ram_stall/thread_stream_write_ram_stall.py +++ b/tests/extension/thread_/stream_write_ram_stall/thread_stream_write_ram_stall.py @@ -153,9 +153,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/to_multibank_ram/test_thread_to_multibank_ram.py b/tests/extension/thread_/to_multibank_ram/test_thread_to_multibank_ram.py index addb6581..904135a1 100644 --- a/tests/extension/thread_/to_multibank_ram/test_thread_to_multibank_ram.py +++ b/tests/extension/thread_/to_multibank_ram/test_thread_to_multibank_ram.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_to_multibank_ram.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/to_multibank_ram/thread_to_multibank_ram.py b/tests/extension/thread_/to_multibank_ram/thread_to_multibank_ram.py index 57a639f7..fc6262ec 100644 --- a/tests/extension/thread_/to_multibank_ram/thread_to_multibank_ram.py +++ b/tests/extension/thread_/to_multibank_ram/thread_to_multibank_ram.py @@ -151,9 +151,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/thread_/uart/test_thread_uart.py b/tests/extension/thread_/uart/test_thread_uart.py index 787bad86..6eaf82c7 100644 --- a/tests/extension/thread_/uart/test_thread_uart.py +++ b/tests/extension/thread_/uart/test_thread_uart.py @@ -14,5 +14,5 @@ def test(request): rslt = thread_uart.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/thread_/uart/thread_uart.py b/tests/extension/thread_/uart/thread_uart.py index ace9a5fd..78edde28 100644 --- a/tests/extension/thread_/uart/thread_uart.py +++ b/tests/extension/thread_/uart/thread_uart.py @@ -109,9 +109,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/types_/axi_/memory_model_read/test_types_memory_model_read.py b/tests/extension/types_/axi_/memory_model_read/test_types_memory_model_read.py index d16cbab7..a59eda23 100644 --- a/tests/extension/types_/axi_/memory_model_read/test_types_memory_model_read.py +++ b/tests/extension/types_/axi_/memory_model_read/test_types_memory_model_read.py @@ -14,5 +14,5 @@ def test(request): rslt = types_memory_model_read.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/types_/axi_/memory_model_read/types_memory_model_read.py b/tests/extension/types_/axi_/memory_model_read/types_memory_model_read.py index 14b0cdd7..ee37b8f3 100644 --- a/tests/extension/types_/axi_/memory_model_read/types_memory_model_read.py +++ b/tests/extension/types_/axi_/memory_model_read/types_memory_model_read.py @@ -86,7 +86,8 @@ def mkTest(memimg_name=None): params=m.connect_params(main), ports=m.connect_ports(main)) - # simulation.setup_waveform(m, uut, m.get_vars()) + # vcd_name = os.path.splitext(os.path.basename(__file__))[0] + '.vcd' + # simulation.setup_waveform(m, uut, m.get_vars(), dumpfile=vcd_name) simulation.setup_clock(m, clk, hperiod=5) init = simulation.setup_reset(m, rst, m.make_reset(), period=100) @@ -112,9 +113,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/types_/axi_/memory_model_write/test_types_memory_model_write.py b/tests/extension/types_/axi_/memory_model_write/test_types_memory_model_write.py index 1074ac6f..2209826c 100644 --- a/tests/extension/types_/axi_/memory_model_write/test_types_memory_model_write.py +++ b/tests/extension/types_/axi_/memory_model_write/test_types_memory_model_write.py @@ -14,5 +14,5 @@ def test(request): rslt = types_memory_model_write.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/types_/axi_/memory_model_write/types_memory_model_write.py b/tests/extension/types_/axi_/memory_model_write/types_memory_model_write.py index 20284a34..6992e65b 100644 --- a/tests/extension/types_/axi_/memory_model_write/types_memory_model_write.py +++ b/tests/extension/types_/axi_/memory_model_write/types_memory_model_write.py @@ -118,7 +118,8 @@ def mkTest(memimg_name=None): params=m.connect_params(main), ports=m.connect_ports(main)) - # simulation.setup_waveform(m, uut, m.get_vars()) + # vcd_name = os.path.splitext(os.path.basename(__file__))[0] + '.vcd' + # simulation.setup_waveform(m, uut, m.get_vars(), dumpfile=vcd_name) simulation.setup_clock(m, clk, hperiod=5) init = simulation.setup_reset(m, rst, m.make_reset(), period=100) @@ -144,9 +145,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/types_/axi_/read/test_types_axi_read.py b/tests/extension/types_/axi_/read/test_types_axi_read.py index c06ea6f5..6f190c7a 100644 --- a/tests/extension/types_/axi_/read/test_types_axi_read.py +++ b/tests/extension/types_/axi_/read/test_types_axi_read.py @@ -14,5 +14,5 @@ def test(request): rslt = types_axi_read.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/types_/axi_/read/types_axi_read.py b/tests/extension/types_/axi_/read/types_axi_read.py index 6ed351c9..11c1a7df 100644 --- a/tests/extension/types_/axi_/read/types_axi_read.py +++ b/tests/extension/types_/axi_/read/types_axi_read.py @@ -122,25 +122,22 @@ def mkTest(): ack = Ors(ports['myaxi_rready'], Not(ports['myaxi_rvalid'])) - raddr_fsm.If(Ands(ack, Not(ports['myaxi_rlast'])))( + raddr_fsm.If(ack)( ports['myaxi_rdata'].inc(), ports['myaxi_rvalid'](1), ports['myaxi_rlast'](0), _arlen.dec() ) - raddr_fsm.Then().If(_arlen == 0)( + raddr_fsm.If(ack, _arlen == 0)( ports['myaxi_rlast'](1), ) - raddr_fsm.Delay(1)( + raddr_fsm.If(ack, _arlen == 0).goto_next() + + raddr_fsm.If(ports['myaxi_rready'])( ports['myaxi_rvalid'](0), ports['myaxi_rlast'](0) ) - raddr_fsm.If(Ands(ports['myaxi_rvalid'], Not(ports['myaxi_rready'])))( - ports['myaxi_rvalid'](ports['myaxi_rvalid']), - ports['myaxi_rlast'](ports['myaxi_rlast']), - ) - raddr_fsm.If(Ands(ports['myaxi_rvalid'], ports[ - 'myaxi_rready'], ports['myaxi_rlast'])).goto_next() + raddr_fsm.If(ports['myaxi_rready']).goto_next() raddr_fsm.goto_next() @@ -152,7 +149,8 @@ def mkTest(): params=m.connect_params(main), ports=m.connect_ports(main)) - # simulation.setup_waveform(m, uut, m.get_vars()) + # vcd_name = os.path.splitext(os.path.basename(__file__))[0] + '.vcd' + # simulation.setup_waveform(m, uut, m.get_vars(), dumpfile=vcd_name) simulation.setup_clock(m, clk, hperiod=5) init = simulation.setup_reset(m, rst, m.make_reset(), period=100) @@ -179,9 +177,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/types_/axi_/read_lite/test_types_axi_read_lite.py b/tests/extension/types_/axi_/read_lite/test_types_axi_read_lite.py index d99e9c3c..cc6beea5 100644 --- a/tests/extension/types_/axi_/read_lite/test_types_axi_read_lite.py +++ b/tests/extension/types_/axi_/read_lite/test_types_axi_read_lite.py @@ -14,5 +14,5 @@ def test(request): rslt = types_axi_read_lite.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/types_/axi_/read_lite/types_axi_read_lite.py b/tests/extension/types_/axi_/read_lite/types_axi_read_lite.py index c04ebec8..47b514ba 100644 --- a/tests/extension/types_/axi_/read_lite/types_axi_read_lite.py +++ b/tests/extension/types_/axi_/read_lite/types_axi_read_lite.py @@ -114,19 +114,16 @@ def mkTest(memimg_name=None): ) raddr_fsm.goto_next() - ack = Ors(ports['myaxi_rready'], Not(ports['myaxi_rvalid'])) - - raddr_fsm.If(ack)( + raddr_fsm( ports['myaxi_rdata'].inc(), ports['myaxi_rvalid'](1), ) - raddr_fsm.Delay(1)( - ports['myaxi_rvalid'](0), - ) - raddr_fsm.If(Ands(ports['myaxi_rvalid'], Not(ports['myaxi_rready'])))( - ports['myaxi_rvalid'](ports['myaxi_rvalid']), + raddr_fsm.goto_next() + + raddr_fsm.If(ports['myaxi_rready'])( + ports['myaxi_rvalid'](0) ) - raddr_fsm.If(Ands(ports['myaxi_rvalid'], ports['myaxi_rready'])).goto_next() + raddr_fsm.If(ports['myaxi_rready']).goto_next() raddr_fsm.goto_next() @@ -138,7 +135,8 @@ def mkTest(memimg_name=None): params=m.connect_params(main), ports=m.connect_ports(main)) - # simulation.setup_waveform(m, uut, m.get_vars()) + # vcd_name = os.path.splitext(os.path.basename(__file__))[0] + '.vcd' + # simulation.setup_waveform(m, uut, m.get_vars(), dumpfile=vcd_name) simulation.setup_clock(m, clk, hperiod=5) init = simulation.setup_reset(m, rst, m.make_reset(), period=100) @@ -165,9 +163,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/types_/axi_/slave_read/test_types_axi_slave_read.py b/tests/extension/types_/axi_/slave_read/test_types_axi_slave_read.py index 0b235fff..c053d122 100644 --- a/tests/extension/types_/axi_/slave_read/test_types_axi_slave_read.py +++ b/tests/extension/types_/axi_/slave_read/test_types_axi_slave_read.py @@ -14,5 +14,5 @@ def test(request): rslt = types_axi_slave_read.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/types_/axi_/slave_read/types_axi_slave_read.py b/tests/extension/types_/axi_/slave_read/types_axi_slave_read.py index 2785ae1b..9bdf4ae5 100644 --- a/tests/extension/types_/axi_/slave_read/types_axi_slave_read.py +++ b/tests/extension/types_/axi_/slave_read/types_axi_slave_read.py @@ -111,7 +111,8 @@ def mkTest(): params=m.connect_params(main), ports=m.connect_ports(main)) - # simulation.setup_waveform(m, uut, m.get_vars()) + # vcd_name = os.path.splitext(os.path.basename(__file__))[0] + '.vcd' + # simulation.setup_waveform(m, uut, m.get_vars(), dumpfile=vcd_name) simulation.setup_clock(m, clk, hperiod=5) init = simulation.setup_reset(m, rst, m.make_reset(), period=100) @@ -138,9 +139,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/types_/axi_/slave_read_lite/test_types_axi_slave_read_lite.py b/tests/extension/types_/axi_/slave_read_lite/test_types_axi_slave_read_lite.py index 9ff7d3bf..ce810b96 100644 --- a/tests/extension/types_/axi_/slave_read_lite/test_types_axi_slave_read_lite.py +++ b/tests/extension/types_/axi_/slave_read_lite/test_types_axi_slave_read_lite.py @@ -14,5 +14,5 @@ def test(request): rslt = types_axi_slave_read_lite.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/types_/axi_/slave_read_lite/types_axi_slave_read_lite.py b/tests/extension/types_/axi_/slave_read_lite/types_axi_slave_read_lite.py index a7c6714a..5b1041d2 100644 --- a/tests/extension/types_/axi_/slave_read_lite/types_axi_slave_read_lite.py +++ b/tests/extension/types_/axi_/slave_read_lite/types_axi_slave_read_lite.py @@ -104,7 +104,8 @@ def mkTest(): params=m.connect_params(main), ports=m.connect_ports(main)) - # simulation.setup_waveform(m, uut, m.get_vars()) + # vcd_name = os.path.splitext(os.path.basename(__file__))[0] + '.vcd' + # simulation.setup_waveform(m, uut, m.get_vars(), dumpfile=vcd_name) simulation.setup_clock(m, clk, hperiod=5) init = simulation.setup_reset(m, rst, m.make_reset(), period=100) @@ -131,9 +132,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/types_/axi_/slave_readwrite/test_types_axi_slave_readwrite.py b/tests/extension/types_/axi_/slave_readwrite/test_types_axi_slave_readwrite.py index a765b736..37517ae0 100644 --- a/tests/extension/types_/axi_/slave_readwrite/test_types_axi_slave_readwrite.py +++ b/tests/extension/types_/axi_/slave_readwrite/test_types_axi_slave_readwrite.py @@ -14,5 +14,5 @@ def test(request): rslt = types_axi_slave_readwrite.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/types_/axi_/slave_readwrite/types_axi_slave_readwrite.py b/tests/extension/types_/axi_/slave_readwrite/types_axi_slave_readwrite.py index 11cf6e9c..18d92f4b 100644 --- a/tests/extension/types_/axi_/slave_readwrite/types_axi_slave_readwrite.py +++ b/tests/extension/types_/axi_/slave_readwrite/types_axi_slave_readwrite.py @@ -159,7 +159,8 @@ def mkTest(): params=m.connect_params(main), ports=m.connect_ports(main)) - # simulation.setup_waveform(m, uut, m.get_vars()) + # vcd_name = os.path.splitext(os.path.basename(__file__))[0] + '.vcd' + # simulation.setup_waveform(m, uut, m.get_vars(), dumpfile=vcd_name) simulation.setup_clock(m, clk, hperiod=5) init = simulation.setup_reset(m, rst, m.make_reset(), period=100) @@ -186,9 +187,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/types_/axi_/slave_readwrite_lite/test_types_axi_slave_readwrite_lite.py b/tests/extension/types_/axi_/slave_readwrite_lite/test_types_axi_slave_readwrite_lite.py index a3674f87..4ffadf65 100644 --- a/tests/extension/types_/axi_/slave_readwrite_lite/test_types_axi_slave_readwrite_lite.py +++ b/tests/extension/types_/axi_/slave_readwrite_lite/test_types_axi_slave_readwrite_lite.py @@ -14,5 +14,5 @@ def test(request): rslt = types_axi_slave_readwrite_lite.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/types_/axi_/slave_readwrite_lite/types_axi_slave_readwrite_lite.py b/tests/extension/types_/axi_/slave_readwrite_lite/types_axi_slave_readwrite_lite.py index bb96b948..83e1ae24 100644 --- a/tests/extension/types_/axi_/slave_readwrite_lite/types_axi_slave_readwrite_lite.py +++ b/tests/extension/types_/axi_/slave_readwrite_lite/types_axi_slave_readwrite_lite.py @@ -139,7 +139,8 @@ def mkTest(): params=m.connect_params(main), ports=m.connect_ports(main)) - # simulation.setup_waveform(m, uut, m.get_vars()) + # vcd_name = os.path.splitext(os.path.basename(__file__))[0] + '.vcd' + # simulation.setup_waveform(m, uut, m.get_vars(), dumpfile=vcd_name) simulation.setup_clock(m, clk, hperiod=5) init = simulation.setup_reset(m, rst, m.make_reset(), period=100) @@ -166,9 +167,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/types_/axi_/slave_readwrite_lite_simultaneous/test_types_axi_slave_readwrite_lite_simultaneous.py b/tests/extension/types_/axi_/slave_readwrite_lite_simultaneous/test_types_axi_slave_readwrite_lite_simultaneous.py index c19f91b3..a081a7c0 100644 --- a/tests/extension/types_/axi_/slave_readwrite_lite_simultaneous/test_types_axi_slave_readwrite_lite_simultaneous.py +++ b/tests/extension/types_/axi_/slave_readwrite_lite_simultaneous/test_types_axi_slave_readwrite_lite_simultaneous.py @@ -14,5 +14,5 @@ def test(request): rslt = types_axi_slave_readwrite_lite_simultaneous.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/types_/axi_/slave_readwrite_lite_simultaneous/types_axi_slave_readwrite_lite_simultaneous.py b/tests/extension/types_/axi_/slave_readwrite_lite_simultaneous/types_axi_slave_readwrite_lite_simultaneous.py index 5e977e19..2ad1698d 100644 --- a/tests/extension/types_/axi_/slave_readwrite_lite_simultaneous/types_axi_slave_readwrite_lite_simultaneous.py +++ b/tests/extension/types_/axi_/slave_readwrite_lite_simultaneous/types_axi_slave_readwrite_lite_simultaneous.py @@ -178,9 +178,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/types_/axi_/slave_readwrite_simultaneous/test_types_axi_slave_readwrite_simultaneous.py b/tests/extension/types_/axi_/slave_readwrite_simultaneous/test_types_axi_slave_readwrite_simultaneous.py index 478e1018..92039d28 100644 --- a/tests/extension/types_/axi_/slave_readwrite_simultaneous/test_types_axi_slave_readwrite_simultaneous.py +++ b/tests/extension/types_/axi_/slave_readwrite_simultaneous/test_types_axi_slave_readwrite_simultaneous.py @@ -14,5 +14,5 @@ def test(request): rslt = types_axi_slave_readwrite_simultaneous.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/types_/axi_/slave_readwrite_simultaneous/types_axi_slave_readwrite_simultaneous.py b/tests/extension/types_/axi_/slave_readwrite_simultaneous/types_axi_slave_readwrite_simultaneous.py index bd40e480..639a65e2 100644 --- a/tests/extension/types_/axi_/slave_readwrite_simultaneous/types_axi_slave_readwrite_simultaneous.py +++ b/tests/extension/types_/axi_/slave_readwrite_simultaneous/types_axi_slave_readwrite_simultaneous.py @@ -169,7 +169,8 @@ def mkTest(): params=m.connect_params(main), ports=m.connect_ports(main)) - # simulation.setup_waveform(m, uut, m.get_vars()) + # vcd_name = os.path.splitext(os.path.basename(__file__))[0] + '.vcd' + # simulation.setup_waveform(m, uut, m.get_vars(), dumpfile=vcd_name) simulation.setup_clock(m, clk, hperiod=5) init = simulation.setup_reset(m, rst, m.make_reset(), period=100) @@ -196,9 +197,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/types_/axi_/slave_write/test_types_axi_slave_write.py b/tests/extension/types_/axi_/slave_write/test_types_axi_slave_write.py index 421d87ab..cd47a2a4 100644 --- a/tests/extension/types_/axi_/slave_write/test_types_axi_slave_write.py +++ b/tests/extension/types_/axi_/slave_write/test_types_axi_slave_write.py @@ -14,5 +14,5 @@ def test(request): rslt = types_axi_slave_write.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/types_/axi_/slave_write/types_axi_slave_write.py b/tests/extension/types_/axi_/slave_write/types_axi_slave_write.py index f1ef4aa2..a60e545a 100644 --- a/tests/extension/types_/axi_/slave_write/types_axi_slave_write.py +++ b/tests/extension/types_/axi_/slave_write/types_axi_slave_write.py @@ -97,6 +97,8 @@ def mkTest(): fsm.If(Not(_axi.wdata.wvalid)).goto_next() # verify + fsm.If(_axi.write_completed()).goto_next() + expected_sum = (((0 + awlen1 - 1) * awlen1) // 2 + ((0 + awlen2 - 1) * awlen2) // 2) fsm( @@ -113,7 +115,8 @@ def mkTest(): params=m.connect_params(main), ports=m.connect_ports(main)) - # simulation.setup_waveform(m, uut, m.get_vars()) + # vcd_name = os.path.splitext(os.path.basename(__file__))[0] + '.vcd' + # simulation.setup_waveform(m, uut, m.get_vars(), dumpfile=vcd_name) simulation.setup_clock(m, clk, hperiod=5) init = simulation.setup_reset(m, rst, m.make_reset(), period=100) @@ -140,9 +143,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/types_/axi_/slave_write_lite/test_types_axi_slave_write_lite.py b/tests/extension/types_/axi_/slave_write_lite/test_types_axi_slave_write_lite.py index 5a63f0ee..e582a5d9 100644 --- a/tests/extension/types_/axi_/slave_write_lite/test_types_axi_slave_write_lite.py +++ b/tests/extension/types_/axi_/slave_write_lite/test_types_axi_slave_write_lite.py @@ -14,5 +14,5 @@ def test(request): rslt = types_axi_slave_write_lite.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/types_/axi_/slave_write_lite/types_axi_slave_write_lite.py b/tests/extension/types_/axi_/slave_write_lite/types_axi_slave_write_lite.py index de93d71c..f7f45829 100644 --- a/tests/extension/types_/axi_/slave_write_lite/types_axi_slave_write_lite.py +++ b/tests/extension/types_/axi_/slave_write_lite/types_axi_slave_write_lite.py @@ -85,6 +85,8 @@ def mkTest(): fsm.If(Not(_axi.wdata.wvalid)).goto_next() # verify + fsm.If(_axi.write_completed()).goto_next() + expected_sum = wdata1 + wdata2 fsm( @@ -101,7 +103,8 @@ def mkTest(): params=m.connect_params(main), ports=m.connect_ports(main)) - # simulation.setup_waveform(m, uut, m.get_vars()) + # vcd_name = os.path.splitext(os.path.basename(__file__))[0] + '.vcd' + # simulation.setup_waveform(m, uut, m.get_vars(), dumpfile=vcd_name) simulation.setup_clock(m, clk, hperiod=5) init = simulation.setup_reset(m, rst, m.make_reset(), period=100) @@ -128,9 +131,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/types_/axi_/write/test_types_axi_write.py b/tests/extension/types_/axi_/write/test_types_axi_write.py index 612d09f8..39c65797 100644 --- a/tests/extension/types_/axi_/write/test_types_axi_write.py +++ b/tests/extension/types_/axi_/write/test_types_axi_write.py @@ -14,5 +14,5 @@ def test(request): rslt = types_axi_write.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/types_/axi_/write/types_axi_write.py b/tests/extension/types_/axi_/write/types_axi_write.py index bec643a0..faabf393 100644 --- a/tests/extension/types_/axi_/write/types_axi_write.py +++ b/tests/extension/types_/axi_/write/types_axi_write.py @@ -96,7 +96,8 @@ def mkTest(memimg_name=None): params=m.connect_params(main), ports=m.connect_ports(main)) - # simulation.setup_waveform(m, uut, m.get_vars()) + # vcd_name = os.path.splitext(os.path.basename(__file__))[0] + '.vcd' + # simulation.setup_waveform(m, uut, m.get_vars(), dumpfile=vcd_name) simulation.setup_clock(m, clk, hperiod=5) init = simulation.setup_reset(m, rst, m.make_reset(), period=100) @@ -122,9 +123,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/types_/axi_/write_lite/test_types_axi_write_lite.py b/tests/extension/types_/axi_/write_lite/test_types_axi_write_lite.py index 1c98a783..1b17df9e 100644 --- a/tests/extension/types_/axi_/write_lite/test_types_axi_write_lite.py +++ b/tests/extension/types_/axi_/write_lite/test_types_axi_write_lite.py @@ -14,5 +14,5 @@ def test(request): rslt = types_axi_write_lite.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/types_/axi_/write_lite/types_axi_write_lite.py b/tests/extension/types_/axi_/write_lite/types_axi_write_lite.py index 378ee7cf..ed7431f2 100644 --- a/tests/extension/types_/axi_/write_lite/types_axi_write_lite.py +++ b/tests/extension/types_/axi_/write_lite/types_axi_write_lite.py @@ -84,7 +84,8 @@ def mkTest(memimg_name=None): params=m.connect_params(main), ports=m.connect_ports(main)) - # simulation.setup_waveform(m, uut, m.get_vars()) + # vcd_name = os.path.splitext(os.path.basename(__file__))[0] + '.vcd' + # simulation.setup_waveform(m, uut, m.get_vars(), dumpfile=vcd_name) simulation.setup_clock(m, clk, hperiod=5) init = simulation.setup_reset(m, rst, m.make_reset(), period=100) @@ -110,9 +111,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/types_/ipxact_/master/test_types_ipxact_master.py b/tests/extension/types_/ipxact_/master/test_types_ipxact_master.py index bb435cde..5491ee38 100644 --- a/tests/extension/types_/ipxact_/master/test_types_ipxact_master.py +++ b/tests/extension/types_/ipxact_/master/test_types_ipxact_master.py @@ -64,6 +64,7 @@ wire [2-1:0] memory_bresp; reg memory_bvalid; wire memory_bready; + assign memory_bresp = 0; wire [32-1:0] memory_araddr; wire [8-1:0] memory_arlen; wire [3-1:0] memory_arsize; @@ -80,7 +81,6 @@ reg memory_rlast; reg memory_rvalid; wire memory_rready; - assign memory_bresp = 0; assign memory_rresp = 0; reg [32-1:0] _memory_waddr_fsm; localparam _memory_waddr_fsm_init = 0; @@ -936,10 +936,10 @@ output [2-1:0] myaxi_awuser, output reg myaxi_awvalid, input myaxi_awready, - output reg [32-1:0] myaxi_wdata, - output reg [4-1:0] myaxi_wstrb, - output reg myaxi_wlast, - output reg myaxi_wvalid, + output [32-1:0] myaxi_wdata, + output [4-1:0] myaxi_wstrb, + output myaxi_wlast, + output myaxi_wvalid, input myaxi_wready, input [2-1:0] myaxi_bresp, input myaxi_bvalid, @@ -969,6 +969,44 @@ assign myaxi_awprot = 0; assign myaxi_awqos = 0; assign myaxi_awuser = 0; + reg [32-1:0] _myaxi_wdata_sb_0; + reg [4-1:0] _myaxi_wstrb_sb_0; + reg _myaxi_wlast_sb_0; + reg _myaxi_wvalid_sb_0; + wire _myaxi_wready_sb_0; + wire _sb_myaxi_writedata_s_value_0; + assign _sb_myaxi_writedata_s_value_0 = _myaxi_wlast_sb_0; + wire [4-1:0] _sb_myaxi_writedata_s_value_1; + assign _sb_myaxi_writedata_s_value_1 = _myaxi_wstrb_sb_0; + wire [32-1:0] _sb_myaxi_writedata_s_value_2; + assign _sb_myaxi_writedata_s_value_2 = _myaxi_wdata_sb_0; + wire [37-1:0] _sb_myaxi_writedata_s_data_3; + assign _sb_myaxi_writedata_s_data_3 = { _sb_myaxi_writedata_s_value_0, _sb_myaxi_writedata_s_value_1, _sb_myaxi_writedata_s_value_2 }; + wire _sb_myaxi_writedata_s_valid_4; + assign _sb_myaxi_writedata_s_valid_4 = _myaxi_wvalid_sb_0; + wire _sb_myaxi_writedata_m_ready_5; + assign _sb_myaxi_writedata_m_ready_5 = myaxi_wready; + reg [37-1:0] _sb_myaxi_writedata_data_6; + reg _sb_myaxi_writedata_valid_7; + wire _sb_myaxi_writedata_ready_8; + reg [37-1:0] _sb_myaxi_writedata_tmp_data_9; + reg _sb_myaxi_writedata_tmp_valid_10; + wire [37-1:0] _sb_myaxi_writedata_next_data_11; + wire _sb_myaxi_writedata_next_valid_12; + assign _sb_myaxi_writedata_ready_8 = !_sb_myaxi_writedata_tmp_valid_10; + assign _sb_myaxi_writedata_next_data_11 = (_sb_myaxi_writedata_tmp_valid_10)? _sb_myaxi_writedata_tmp_data_9 : _sb_myaxi_writedata_s_data_3; + assign _sb_myaxi_writedata_next_valid_12 = _sb_myaxi_writedata_tmp_valid_10 || _sb_myaxi_writedata_s_valid_4; + wire _sb_myaxi_writedata_m_value_13; + assign _sb_myaxi_writedata_m_value_13 = _sb_myaxi_writedata_data_6[36:36]; + wire [4-1:0] _sb_myaxi_writedata_m_value_14; + assign _sb_myaxi_writedata_m_value_14 = _sb_myaxi_writedata_data_6[35:32]; + wire [32-1:0] _sb_myaxi_writedata_m_value_15; + assign _sb_myaxi_writedata_m_value_15 = _sb_myaxi_writedata_data_6[31:0]; + assign _myaxi_wready_sb_0 = _sb_myaxi_writedata_ready_8; + assign myaxi_wdata = _sb_myaxi_writedata_m_value_15; + assign myaxi_wstrb = _sb_myaxi_writedata_m_value_14; + assign myaxi_wlast = _sb_myaxi_writedata_m_value_13; + assign myaxi_wvalid = _sb_myaxi_writedata_valid_7; assign myaxi_bready = 1; assign myaxi_arsize = 2; assign myaxi_arburst = 1; @@ -977,57 +1015,118 @@ assign myaxi_arprot = 0; assign myaxi_arqos = 0; assign myaxi_aruser = 0; + wire [32-1:0] _myaxi_rdata_sb_0; + wire _myaxi_rlast_sb_0; + wire _myaxi_rvalid_sb_0; + wire _myaxi_rready_sb_0; + wire _sb_myaxi_readdata_s_value_16; + assign _sb_myaxi_readdata_s_value_16 = myaxi_rlast; + wire [32-1:0] _sb_myaxi_readdata_s_value_17; + assign _sb_myaxi_readdata_s_value_17 = myaxi_rdata; + wire [33-1:0] _sb_myaxi_readdata_s_data_18; + assign _sb_myaxi_readdata_s_data_18 = { _sb_myaxi_readdata_s_value_16, _sb_myaxi_readdata_s_value_17 }; + wire _sb_myaxi_readdata_s_valid_19; + assign _sb_myaxi_readdata_s_valid_19 = myaxi_rvalid; + wire _sb_myaxi_readdata_m_ready_20; + assign _sb_myaxi_readdata_m_ready_20 = _myaxi_rready_sb_0; + reg [33-1:0] _sb_myaxi_readdata_data_21; + reg _sb_myaxi_readdata_valid_22; + wire _sb_myaxi_readdata_ready_23; + reg [33-1:0] _sb_myaxi_readdata_tmp_data_24; + reg _sb_myaxi_readdata_tmp_valid_25; + wire [33-1:0] _sb_myaxi_readdata_next_data_26; + wire _sb_myaxi_readdata_next_valid_27; + assign _sb_myaxi_readdata_ready_23 = !_sb_myaxi_readdata_tmp_valid_25; + assign _sb_myaxi_readdata_next_data_26 = (_sb_myaxi_readdata_tmp_valid_25)? _sb_myaxi_readdata_tmp_data_24 : _sb_myaxi_readdata_s_data_18; + assign _sb_myaxi_readdata_next_valid_27 = _sb_myaxi_readdata_tmp_valid_25 || _sb_myaxi_readdata_s_valid_19; + wire _sb_myaxi_readdata_m_value_28; + assign _sb_myaxi_readdata_m_value_28 = _sb_myaxi_readdata_data_21[32:32]; + wire [32-1:0] _sb_myaxi_readdata_m_value_29; + assign _sb_myaxi_readdata_m_value_29 = _sb_myaxi_readdata_data_21[31:0]; + assign _myaxi_rdata_sb_0 = _sb_myaxi_readdata_m_value_29; + assign _myaxi_rlast_sb_0 = _sb_myaxi_readdata_m_value_28; + assign _myaxi_rvalid_sb_0 = _sb_myaxi_readdata_valid_22; + assign myaxi_rready = _sb_myaxi_readdata_ready_23; reg [3-1:0] _myaxi_outstanding_wcount; wire _myaxi_has_outstanding_write; assign _myaxi_has_outstanding_write = (_myaxi_outstanding_wcount > 0) || myaxi_awvalid; reg [32-1:0] fsm; localparam fsm_init = 0; - reg _myaxi_cond_0_1; + reg _myaxi_raddr_cond_0_1; reg [32-1:0] sum; - reg _myaxi_cond_1_1; - assign myaxi_rready = (fsm == 1) || (fsm == 3); + reg _myaxi_raddr_cond_1_1; + assign _myaxi_rready_sb_0 = (fsm == 1) || (fsm == 3); always @(posedge CLK) begin if(RST) begin - _myaxi_outstanding_wcount <= 0; myaxi_awaddr <= 0; myaxi_awlen <= 0; myaxi_awvalid <= 0; - myaxi_wdata <= 0; - myaxi_wstrb <= 0; - myaxi_wlast <= 0; - myaxi_wvalid <= 0; + end else begin + myaxi_awaddr <= 0; + myaxi_awlen <= 0; + myaxi_awvalid <= 0; + end + end + + + always @(posedge CLK) begin + if(RST) begin + _myaxi_wdata_sb_0 <= 0; + _myaxi_wstrb_sb_0 <= 0; + _myaxi_wlast_sb_0 <= 0; + _myaxi_wvalid_sb_0 <= 0; + end else begin + _myaxi_wdata_sb_0 <= 0; + _myaxi_wstrb_sb_0 <= 0; + _myaxi_wlast_sb_0 <= 0; + _myaxi_wvalid_sb_0 <= 0; + end + end + + + always @(posedge CLK) begin + if(RST) begin + _sb_myaxi_writedata_data_6 <= 0; + _sb_myaxi_writedata_valid_7 <= 0; + _sb_myaxi_writedata_tmp_data_9 <= 0; + _sb_myaxi_writedata_tmp_valid_10 <= 0; + end else begin + if(_sb_myaxi_writedata_m_ready_5 || !_sb_myaxi_writedata_valid_7) begin + _sb_myaxi_writedata_data_6 <= _sb_myaxi_writedata_next_data_11; + _sb_myaxi_writedata_valid_7 <= _sb_myaxi_writedata_next_valid_12; + end + if(!_sb_myaxi_writedata_tmp_valid_10 && _sb_myaxi_writedata_valid_7 && !_sb_myaxi_writedata_m_ready_5) begin + _sb_myaxi_writedata_tmp_data_9 <= _sb_myaxi_writedata_s_data_3; + _sb_myaxi_writedata_tmp_valid_10 <= _sb_myaxi_writedata_s_valid_4; + end + if(_sb_myaxi_writedata_tmp_valid_10 && _sb_myaxi_writedata_m_ready_5) begin + _sb_myaxi_writedata_tmp_valid_10 <= 0; + end + end + end + + + always @(posedge CLK) begin + if(RST) begin myaxi_araddr <= 0; myaxi_arlen <= 0; myaxi_arvalid <= 0; - _myaxi_cond_0_1 <= 0; - _myaxi_cond_1_1 <= 0; + _myaxi_raddr_cond_0_1 <= 0; + _myaxi_raddr_cond_1_1 <= 0; end else begin - if(_myaxi_cond_0_1) begin + if(_myaxi_raddr_cond_0_1) begin myaxi_arvalid <= 0; end - if(_myaxi_cond_1_1) begin + if(_myaxi_raddr_cond_1_1) begin myaxi_arvalid <= 0; end - if(myaxi_awvalid && myaxi_awready && !(myaxi_bvalid && myaxi_bready) && (_myaxi_outstanding_wcount < 7)) begin - _myaxi_outstanding_wcount <= _myaxi_outstanding_wcount + 1; - end - if(!(myaxi_awvalid && myaxi_awready) && (myaxi_bvalid && myaxi_bready) && (_myaxi_outstanding_wcount > 0)) begin - _myaxi_outstanding_wcount <= _myaxi_outstanding_wcount - 1; - end - myaxi_awaddr <= 0; - myaxi_awlen <= 0; - myaxi_awvalid <= 0; - myaxi_wdata <= 0; - myaxi_wstrb <= 0; - myaxi_wlast <= 0; - myaxi_wvalid <= 0; if((fsm == 0) && (myaxi_arready || !myaxi_arvalid)) begin myaxi_araddr <= 1024; myaxi_arlen <= 63; myaxi_arvalid <= 1; end - _myaxi_cond_0_1 <= 1; + _myaxi_raddr_cond_0_1 <= 1; if(myaxi_arvalid && !myaxi_arready) begin myaxi_arvalid <= myaxi_arvalid; end @@ -1036,13 +1135,49 @@ myaxi_arlen <= 127; myaxi_arvalid <= 1; end - _myaxi_cond_1_1 <= 1; + _myaxi_raddr_cond_1_1 <= 1; if(myaxi_arvalid && !myaxi_arready) begin myaxi_arvalid <= myaxi_arvalid; end end end + + always @(posedge CLK) begin + if(RST) begin + _sb_myaxi_readdata_data_21 <= 0; + _sb_myaxi_readdata_valid_22 <= 0; + _sb_myaxi_readdata_tmp_data_24 <= 0; + _sb_myaxi_readdata_tmp_valid_25 <= 0; + end else begin + if(_sb_myaxi_readdata_m_ready_20 || !_sb_myaxi_readdata_valid_22) begin + _sb_myaxi_readdata_data_21 <= _sb_myaxi_readdata_next_data_26; + _sb_myaxi_readdata_valid_22 <= _sb_myaxi_readdata_next_valid_27; + end + if(!_sb_myaxi_readdata_tmp_valid_25 && _sb_myaxi_readdata_valid_22 && !_sb_myaxi_readdata_m_ready_20) begin + _sb_myaxi_readdata_tmp_data_24 <= _sb_myaxi_readdata_s_data_18; + _sb_myaxi_readdata_tmp_valid_25 <= _sb_myaxi_readdata_s_valid_19; + end + if(_sb_myaxi_readdata_tmp_valid_25 && _sb_myaxi_readdata_m_ready_20) begin + _sb_myaxi_readdata_tmp_valid_25 <= 0; + end + end + end + + + always @(posedge CLK) begin + if(RST) begin + _myaxi_outstanding_wcount <= 0; + end else begin + if(myaxi_awvalid && myaxi_awready && !(myaxi_bvalid && myaxi_bready) && (_myaxi_outstanding_wcount < 7)) begin + _myaxi_outstanding_wcount <= _myaxi_outstanding_wcount + 1; + end + if(!(myaxi_awvalid && myaxi_awready) && (myaxi_bvalid && myaxi_bready) && (_myaxi_outstanding_wcount > 0)) begin + _myaxi_outstanding_wcount <= _myaxi_outstanding_wcount - 1; + end + end + end + localparam fsm_1 = 1; localparam fsm_2 = 2; localparam fsm_3 = 3; @@ -1061,10 +1196,10 @@ end end fsm_1: begin - if(myaxi_rvalid) begin - sum <= sum + myaxi_rdata; + if(_myaxi_rvalid_sb_0) begin + sum <= sum + _myaxi_rdata_sb_0; end - if(myaxi_rvalid && myaxi_rlast) begin + if(_myaxi_rvalid_sb_0 && _myaxi_rlast_sb_0) begin fsm <= fsm_2; end end @@ -1074,10 +1209,10 @@ end end fsm_3: begin - if(myaxi_rvalid) begin - sum <= sum + myaxi_rdata; + if(_myaxi_rvalid_sb_0) begin + sum <= sum + _myaxi_rdata_sb_0; end - if(myaxi_rvalid && myaxi_rlast) begin + if(_myaxi_rvalid_sb_0 && _myaxi_rlast_sb_0) begin fsm <= fsm_4; end end diff --git a/tests/extension/types_/ipxact_/master/types_ipxact_master.py b/tests/extension/types_/ipxact_/master/types_ipxact_master.py index e7823ade..43f54b61 100644 --- a/tests/extension/types_/ipxact_/master/types_ipxact_master.py +++ b/tests/extension/types_/ipxact_/master/types_ipxact_master.py @@ -89,7 +89,8 @@ def mkTest(memimg_name=None): params=m.connect_params(main), ports=m.connect_ports(main)) - # simulation.setup_waveform(m, uut, m.get_vars()) + # vcd_name = os.path.splitext(os.path.basename(__file__))[0] + '.vcd' + # simulation.setup_waveform(m, uut, m.get_vars(), dumpfile=vcd_name) simulation.setup_clock(m, clk, hperiod=5) init = simulation.setup_reset(m, rst, m.make_reset(), period=100) @@ -115,9 +116,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/types_/ipxact_/slave_lite/test_types_ipxact_slave_lite.py b/tests/extension/types_/ipxact_/slave_lite/test_types_ipxact_slave_lite.py index b3b29008..eb3055f6 100644 --- a/tests/extension/types_/ipxact_/slave_lite/test_types_ipxact_slave_lite.py +++ b/tests/extension/types_/ipxact_/slave_lite/test_types_ipxact_slave_lite.py @@ -36,135 +36,193 @@ wire [3-1:0] _axi_awprot; reg _axi_awvalid; wire _axi_awready; - reg [32-1:0] _axi_wdata; - reg [4-1:0] _axi_wstrb; - reg _axi_wvalid; + assign _axi_awcache = 3; + assign _axi_awprot = 0; + wire [32-1:0] _axi_wdata; + wire [4-1:0] _axi_wstrb; + wire _axi_wvalid; wire _axi_wready; + reg [32-1:0] __axi_wdata_sb_0; + reg [4-1:0] __axi_wstrb_sb_0; + reg __axi_wvalid_sb_0; + wire __axi_wready_sb_0; + wire [4-1:0] _sb__axi_writedata_s_value_0; + assign _sb__axi_writedata_s_value_0 = __axi_wstrb_sb_0; + wire [32-1:0] _sb__axi_writedata_s_value_1; + assign _sb__axi_writedata_s_value_1 = __axi_wdata_sb_0; + wire [36-1:0] _sb__axi_writedata_s_data_2; + assign _sb__axi_writedata_s_data_2 = { _sb__axi_writedata_s_value_0, _sb__axi_writedata_s_value_1 }; + wire _sb__axi_writedata_s_valid_3; + assign _sb__axi_writedata_s_valid_3 = __axi_wvalid_sb_0; + wire _sb__axi_writedata_m_ready_4; + assign _sb__axi_writedata_m_ready_4 = _axi_wready; + reg [36-1:0] _sb__axi_writedata_data_5; + reg _sb__axi_writedata_valid_6; + wire _sb__axi_writedata_ready_7; + reg [36-1:0] _sb__axi_writedata_tmp_data_8; + reg _sb__axi_writedata_tmp_valid_9; + wire [36-1:0] _sb__axi_writedata_next_data_10; + wire _sb__axi_writedata_next_valid_11; + assign _sb__axi_writedata_ready_7 = !_sb__axi_writedata_tmp_valid_9; + assign _sb__axi_writedata_next_data_10 = (_sb__axi_writedata_tmp_valid_9)? _sb__axi_writedata_tmp_data_8 : _sb__axi_writedata_s_data_2; + assign _sb__axi_writedata_next_valid_11 = _sb__axi_writedata_tmp_valid_9 || _sb__axi_writedata_s_valid_3; + wire [4-1:0] _sb__axi_writedata_m_value_12; + assign _sb__axi_writedata_m_value_12 = _sb__axi_writedata_data_5[35:32]; + wire [32-1:0] _sb__axi_writedata_m_value_13; + assign _sb__axi_writedata_m_value_13 = _sb__axi_writedata_data_5[31:0]; + assign __axi_wready_sb_0 = _sb__axi_writedata_ready_7; + assign _axi_wdata = _sb__axi_writedata_m_value_13; + assign _axi_wstrb = _sb__axi_writedata_m_value_12; + assign _axi_wvalid = _sb__axi_writedata_valid_6; wire [2-1:0] _axi_bresp; wire _axi_bvalid; wire _axi_bready; + assign _axi_bready = 1; reg [32-1:0] _axi_araddr; wire [4-1:0] _axi_arcache; wire [3-1:0] _axi_arprot; reg _axi_arvalid; wire _axi_arready; + assign _axi_arcache = 3; + assign _axi_arprot = 0; wire [32-1:0] _axi_rdata; wire [2-1:0] _axi_rresp; wire _axi_rvalid; wire _axi_rready; - assign _axi_awcache = 3; - assign _axi_awprot = 0; - assign _axi_bready = 1; - assign _axi_arcache = 3; - assign _axi_arprot = 0; + wire [32-1:0] __axi_rdata_sb_0; + wire __axi_rvalid_sb_0; + wire __axi_rready_sb_0; + wire [32-1:0] _sb__axi_readdata_s_value_14; + assign _sb__axi_readdata_s_value_14 = _axi_rdata; + wire [32-1:0] _sb__axi_readdata_s_data_15; + assign _sb__axi_readdata_s_data_15 = { _sb__axi_readdata_s_value_14 }; + wire _sb__axi_readdata_s_valid_16; + assign _sb__axi_readdata_s_valid_16 = _axi_rvalid; + wire _sb__axi_readdata_m_ready_17; + assign _sb__axi_readdata_m_ready_17 = __axi_rready_sb_0; + reg [32-1:0] _sb__axi_readdata_data_18; + reg _sb__axi_readdata_valid_19; + wire _sb__axi_readdata_ready_20; + reg [32-1:0] _sb__axi_readdata_tmp_data_21; + reg _sb__axi_readdata_tmp_valid_22; + wire [32-1:0] _sb__axi_readdata_next_data_23; + wire _sb__axi_readdata_next_valid_24; + assign _sb__axi_readdata_ready_20 = !_sb__axi_readdata_tmp_valid_22; + assign _sb__axi_readdata_next_data_23 = (_sb__axi_readdata_tmp_valid_22)? _sb__axi_readdata_tmp_data_21 : _sb__axi_readdata_s_data_15; + assign _sb__axi_readdata_next_valid_24 = _sb__axi_readdata_tmp_valid_22 || _sb__axi_readdata_s_valid_16; + wire [32-1:0] _sb__axi_readdata_m_value_25; + assign _sb__axi_readdata_m_value_25 = _sb__axi_readdata_data_18[31:0]; + assign __axi_rdata_sb_0 = _sb__axi_readdata_m_value_25; + assign __axi_rvalid_sb_0 = _sb__axi_readdata_valid_19; + assign _axi_rready = _sb__axi_readdata_ready_20; reg [3-1:0] __axi_outstanding_wcount; wire __axi_has_outstanding_write; assign __axi_has_outstanding_write = (__axi_outstanding_wcount > 0) || _axi_awvalid; - wire [32-1:0] _tmp_0; - assign _tmp_0 = _axi_awaddr; + wire [32-1:0] _tmp_26; + assign _tmp_26 = _axi_awaddr; always @(*) begin - myaxi_awaddr = _tmp_0; + myaxi_awaddr = _tmp_26; end - wire [4-1:0] _tmp_1; - assign _tmp_1 = _axi_awcache; + wire [4-1:0] _tmp_27; + assign _tmp_27 = _axi_awcache; always @(*) begin - myaxi_awcache = _tmp_1; + myaxi_awcache = _tmp_27; end - wire [3-1:0] _tmp_2; - assign _tmp_2 = _axi_awprot; + wire [3-1:0] _tmp_28; + assign _tmp_28 = _axi_awprot; always @(*) begin - myaxi_awprot = _tmp_2; + myaxi_awprot = _tmp_28; end - wire _tmp_3; - assign _tmp_3 = _axi_awvalid; + wire _tmp_29; + assign _tmp_29 = _axi_awvalid; always @(*) begin - myaxi_awvalid = _tmp_3; + myaxi_awvalid = _tmp_29; end assign _axi_awready = myaxi_awready; - wire [32-1:0] _tmp_4; - assign _tmp_4 = _axi_wdata; + wire [32-1:0] _tmp_30; + assign _tmp_30 = _axi_wdata; always @(*) begin - myaxi_wdata = _tmp_4; + myaxi_wdata = _tmp_30; end - wire [4-1:0] _tmp_5; - assign _tmp_5 = _axi_wstrb; + wire [4-1:0] _tmp_31; + assign _tmp_31 = _axi_wstrb; always @(*) begin - myaxi_wstrb = _tmp_5; + myaxi_wstrb = _tmp_31; end - wire _tmp_6; - assign _tmp_6 = _axi_wvalid; + wire _tmp_32; + assign _tmp_32 = _axi_wvalid; always @(*) begin - myaxi_wvalid = _tmp_6; + myaxi_wvalid = _tmp_32; end assign _axi_wready = myaxi_wready; assign _axi_bresp = myaxi_bresp; assign _axi_bvalid = myaxi_bvalid; - wire _tmp_7; - assign _tmp_7 = _axi_bready; + wire _tmp_33; + assign _tmp_33 = _axi_bready; always @(*) begin - myaxi_bready = _tmp_7; + myaxi_bready = _tmp_33; end - wire [32-1:0] _tmp_8; - assign _tmp_8 = _axi_araddr; + wire [32-1:0] _tmp_34; + assign _tmp_34 = _axi_araddr; always @(*) begin - myaxi_araddr = _tmp_8; + myaxi_araddr = _tmp_34; end - wire [4-1:0] _tmp_9; - assign _tmp_9 = _axi_arcache; + wire [4-1:0] _tmp_35; + assign _tmp_35 = _axi_arcache; always @(*) begin - myaxi_arcache = _tmp_9; + myaxi_arcache = _tmp_35; end - wire [3-1:0] _tmp_10; - assign _tmp_10 = _axi_arprot; + wire [3-1:0] _tmp_36; + assign _tmp_36 = _axi_arprot; always @(*) begin - myaxi_arprot = _tmp_10; + myaxi_arprot = _tmp_36; end - wire _tmp_11; - assign _tmp_11 = _axi_arvalid; + wire _tmp_37; + assign _tmp_37 = _axi_arvalid; always @(*) begin - myaxi_arvalid = _tmp_11; + myaxi_arvalid = _tmp_37; end assign _axi_arready = myaxi_arready; assign _axi_rdata = myaxi_rdata; assign _axi_rresp = myaxi_rresp; assign _axi_rvalid = myaxi_rvalid; - wire _tmp_12; - assign _tmp_12 = _axi_rready; + wire _tmp_38; + assign _tmp_38 = _axi_rready; always @(*) begin - myaxi_rready = _tmp_12; + myaxi_rready = _tmp_38; end reg [32-1:0] fsm; localparam fsm_init = 0; - reg __axi_cond_0_1; + reg __axi_raddr_cond_0_1; reg [32-1:0] sum; - reg __axi_cond_1_1; - assign _axi_rready = (fsm == 1) || (fsm == 3); + reg __axi_raddr_cond_1_1; + assign __axi_rready_sb_0 = (fsm == 1) || (fsm == 3); main uut @@ -208,16 +266,24 @@ RST = 0; _axi_awaddr = 0; _axi_awvalid = 0; - _axi_wdata = 0; - _axi_wstrb = 0; - _axi_wvalid = 0; + __axi_wdata_sb_0 = 0; + __axi_wstrb_sb_0 = 0; + __axi_wvalid_sb_0 = 0; + _sb__axi_writedata_data_5 = 0; + _sb__axi_writedata_valid_6 = 0; + _sb__axi_writedata_tmp_data_8 = 0; + _sb__axi_writedata_tmp_valid_9 = 0; _axi_araddr = 0; _axi_arvalid = 0; + _sb__axi_readdata_data_18 = 0; + _sb__axi_readdata_valid_19 = 0; + _sb__axi_readdata_tmp_data_21 = 0; + _sb__axi_readdata_tmp_valid_22 = 0; __axi_outstanding_wcount = 0; fsm = fsm_init; - __axi_cond_0_1 = 0; + __axi_raddr_cond_0_1 = 0; sum = 0; - __axi_cond_1_1 = 0; + __axi_raddr_cond_1_1 = 0; #100; RST = 1; #100; @@ -229,39 +295,68 @@ always @(posedge CLK) begin if(RST) begin - __axi_outstanding_wcount <= 0; _axi_awaddr <= 0; _axi_awvalid <= 0; - _axi_wdata <= 0; - _axi_wstrb <= 0; - _axi_wvalid <= 0; + end else begin + _axi_awaddr <= 0; + _axi_awvalid <= 0; + end + end + + + always @(posedge CLK) begin + if(RST) begin + __axi_wdata_sb_0 <= 0; + __axi_wstrb_sb_0 <= 0; + __axi_wvalid_sb_0 <= 0; + end else begin + __axi_wdata_sb_0 <= 0; + __axi_wstrb_sb_0 <= 0; + __axi_wvalid_sb_0 <= 0; + end + end + + + always @(posedge CLK) begin + if(RST) begin + _sb__axi_writedata_data_5 <= 0; + _sb__axi_writedata_valid_6 <= 0; + _sb__axi_writedata_tmp_data_8 <= 0; + _sb__axi_writedata_tmp_valid_9 <= 0; + end else begin + if(_sb__axi_writedata_m_ready_4 || !_sb__axi_writedata_valid_6) begin + _sb__axi_writedata_data_5 <= _sb__axi_writedata_next_data_10; + _sb__axi_writedata_valid_6 <= _sb__axi_writedata_next_valid_11; + end + if(!_sb__axi_writedata_tmp_valid_9 && _sb__axi_writedata_valid_6 && !_sb__axi_writedata_m_ready_4) begin + _sb__axi_writedata_tmp_data_8 <= _sb__axi_writedata_s_data_2; + _sb__axi_writedata_tmp_valid_9 <= _sb__axi_writedata_s_valid_3; + end + if(_sb__axi_writedata_tmp_valid_9 && _sb__axi_writedata_m_ready_4) begin + _sb__axi_writedata_tmp_valid_9 <= 0; + end + end + end + + + always @(posedge CLK) begin + if(RST) begin _axi_araddr <= 0; _axi_arvalid <= 0; - __axi_cond_0_1 <= 0; - __axi_cond_1_1 <= 0; + __axi_raddr_cond_0_1 <= 0; + __axi_raddr_cond_1_1 <= 0; end else begin - if(__axi_cond_0_1) begin + if(__axi_raddr_cond_0_1) begin _axi_arvalid <= 0; end - if(__axi_cond_1_1) begin + if(__axi_raddr_cond_1_1) begin _axi_arvalid <= 0; end - if(_axi_awvalid && _axi_awready && !(_axi_bvalid && _axi_bready) && (__axi_outstanding_wcount < 7)) begin - __axi_outstanding_wcount <= __axi_outstanding_wcount + 1; - end - if(!(_axi_awvalid && _axi_awready) && (_axi_bvalid && _axi_bready) && (__axi_outstanding_wcount > 0)) begin - __axi_outstanding_wcount <= __axi_outstanding_wcount - 1; - end - _axi_awaddr <= 0; - _axi_awvalid <= 0; - _axi_wdata <= 0; - _axi_wstrb <= 0; - _axi_wvalid <= 0; if((fsm == 0) && (_axi_arready || !_axi_arvalid)) begin _axi_araddr <= 1024; _axi_arvalid <= 1; end - __axi_cond_0_1 <= 1; + __axi_raddr_cond_0_1 <= 1; if(_axi_arvalid && !_axi_arready) begin _axi_arvalid <= _axi_arvalid; end @@ -269,13 +364,49 @@ _axi_araddr <= 2048; _axi_arvalid <= 1; end - __axi_cond_1_1 <= 1; + __axi_raddr_cond_1_1 <= 1; if(_axi_arvalid && !_axi_arready) begin _axi_arvalid <= _axi_arvalid; end end end + + always @(posedge CLK) begin + if(RST) begin + _sb__axi_readdata_data_18 <= 0; + _sb__axi_readdata_valid_19 <= 0; + _sb__axi_readdata_tmp_data_21 <= 0; + _sb__axi_readdata_tmp_valid_22 <= 0; + end else begin + if(_sb__axi_readdata_m_ready_17 || !_sb__axi_readdata_valid_19) begin + _sb__axi_readdata_data_18 <= _sb__axi_readdata_next_data_23; + _sb__axi_readdata_valid_19 <= _sb__axi_readdata_next_valid_24; + end + if(!_sb__axi_readdata_tmp_valid_22 && _sb__axi_readdata_valid_19 && !_sb__axi_readdata_m_ready_17) begin + _sb__axi_readdata_tmp_data_21 <= _sb__axi_readdata_s_data_15; + _sb__axi_readdata_tmp_valid_22 <= _sb__axi_readdata_s_valid_16; + end + if(_sb__axi_readdata_tmp_valid_22 && _sb__axi_readdata_m_ready_17) begin + _sb__axi_readdata_tmp_valid_22 <= 0; + end + end + end + + + always @(posedge CLK) begin + if(RST) begin + __axi_outstanding_wcount <= 0; + end else begin + if(_axi_awvalid && _axi_awready && !(_axi_bvalid && _axi_bready) && (__axi_outstanding_wcount < 7)) begin + __axi_outstanding_wcount <= __axi_outstanding_wcount + 1; + end + if(!(_axi_awvalid && _axi_awready) && (_axi_bvalid && _axi_bready) && (__axi_outstanding_wcount > 0)) begin + __axi_outstanding_wcount <= __axi_outstanding_wcount - 1; + end + end + end + localparam fsm_1 = 1; localparam fsm_2 = 2; localparam fsm_3 = 3; @@ -294,10 +425,10 @@ end end fsm_1: begin - if(_axi_rready && _axi_rvalid) begin - sum <= sum + _axi_rdata; + if(__axi_rready_sb_0 && __axi_rvalid_sb_0) begin + sum <= sum + __axi_rdata_sb_0; end - if(_axi_rready && _axi_rvalid) begin + if(__axi_rready_sb_0 && __axi_rvalid_sb_0) begin fsm <= fsm_2; end end @@ -307,10 +438,10 @@ end end fsm_3: begin - if(_axi_rready && _axi_rvalid) begin - sum <= sum + _axi_rdata; + if(__axi_rready_sb_0 && __axi_rvalid_sb_0) begin + sum <= sum + __axi_rdata_sb_0; end - if(_axi_rready && _axi_rvalid) begin + if(__axi_rready_sb_0 && __axi_rvalid_sb_0) begin fsm <= fsm_4; end end @@ -371,21 +502,36 @@ reg prev_arvalid_2; assign myaxi_arready = (fsm == 0) && !valid_1 && prev_arvalid_2; reg [32-1:0] rdata; - reg _myaxi_cond_0_1; + reg _myaxi_rdata_cond_0_1; always @(posedge CLK) begin if(RST) begin - myaxi_bvalid <= 0; - prev_arvalid_2 <= 0; - valid_1 <= 0; - addr_0 <= 0; myaxi_rdata <= 0; myaxi_rvalid <= 0; - _myaxi_cond_0_1 <= 0; + _myaxi_rdata_cond_0_1 <= 0; end else begin - if(_myaxi_cond_0_1) begin + if(_myaxi_rdata_cond_0_1) begin myaxi_rvalid <= 0; end + if((fsm == 1) && (myaxi_rready || !myaxi_rvalid)) begin + myaxi_rdata <= rdata; + myaxi_rvalid <= 1; + end + _myaxi_rdata_cond_0_1 <= 1; + if(myaxi_rvalid && !myaxi_rready) begin + myaxi_rvalid <= myaxi_rvalid; + end + end + end + + + always @(posedge CLK) begin + if(RST) begin + myaxi_bvalid <= 0; + prev_arvalid_2 <= 0; + valid_1 <= 0; + addr_0 <= 0; + end else begin if(myaxi_bvalid && myaxi_bready) begin myaxi_bvalid <= 0; end @@ -398,14 +544,6 @@ addr_0 <= myaxi_araddr; valid_1 <= 1; end - if((fsm == 1) && (myaxi_rready || !myaxi_rvalid)) begin - myaxi_rdata <= rdata; - myaxi_rvalid <= 1; - end - _myaxi_cond_0_1 <= 1; - if(myaxi_rvalid && !myaxi_rready) begin - myaxi_rvalid <= myaxi_rvalid; - end end end diff --git a/tests/extension/types_/ipxact_/slave_lite/types_ipxact_slave_lite.py b/tests/extension/types_/ipxact_/slave_lite/types_ipxact_slave_lite.py index e46bdce0..47b374db 100644 --- a/tests/extension/types_/ipxact_/slave_lite/types_ipxact_slave_lite.py +++ b/tests/extension/types_/ipxact_/slave_lite/types_ipxact_slave_lite.py @@ -107,7 +107,8 @@ def mkTest(): params=m.connect_params(main), ports=m.connect_ports(main)) - # simulation.setup_waveform(m, uut, m.get_vars()) + # vcd_name = os.path.splitext(os.path.basename(__file__))[0] + '.vcd' + # simulation.setup_waveform(m, uut, m.get_vars(), dumpfile=vcd_name) simulation.setup_clock(m, clk, hperiod=5) init = simulation.setup_reset(m, rst, m.make_reset(), period=100) @@ -134,9 +135,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/types_/ram_/async/test_types_ram_async.py b/tests/extension/types_/ram_/async/test_types_ram_async.py index c3384c8a..302a9634 100644 --- a/tests/extension/types_/ram_/async/test_types_ram_async.py +++ b/tests/extension/types_/ram_/async/test_types_ram_async.py @@ -14,5 +14,5 @@ def test(request): rslt = types_ram_async.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/types_/ram_/async/types_ram_async.py b/tests/extension/types_/ram_/async/types_ram_async.py index 36e40c67..29aa7f95 100644 --- a/tests/extension/types_/ram_/async/types_ram_async.py +++ b/tests/extension/types_/ram_/async/types_ram_async.py @@ -125,9 +125,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/types_/ram_/sync/test_types_ram_sync.py b/tests/extension/types_/ram_/sync/test_types_ram_sync.py index 8615c084..80a8f9d2 100644 --- a/tests/extension/types_/ram_/sync/test_types_ram_sync.py +++ b/tests/extension/types_/ram_/sync/test_types_ram_sync.py @@ -14,5 +14,5 @@ def test(request): rslt = types_ram_sync.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/types_/ram_/sync/types_ram_sync.py b/tests/extension/types_/ram_/sync/types_ram_sync.py index 1d854237..f1b7940b 100644 --- a/tests/extension/types_/ram_/sync/types_ram_sync.py +++ b/tests/extension/types_/ram_/sync/types_ram_sync.py @@ -125,9 +125,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/extension/types_/ram_/sync_with_enable/test_types_ram_sync_with_enable.py b/tests/extension/types_/ram_/sync_with_enable/test_types_ram_sync_with_enable.py index c97d3bfe..c288e92e 100644 --- a/tests/extension/types_/ram_/sync_with_enable/test_types_ram_sync_with_enable.py +++ b/tests/extension/types_/ram_/sync_with_enable/test_types_ram_sync_with_enable.py @@ -14,5 +14,5 @@ def test(request): rslt = types_ram_sync_with_enable.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') - verify_rslt = rslt.splitlines()[-1] + verify_rslt = [line for line in rslt.splitlines() if line.startswith('# verify:')][0] assert(verify_rslt == '# verify: PASSED') diff --git a/tests/extension/types_/ram_/sync_with_enable/types_ram_sync_with_enable.py b/tests/extension/types_/ram_/sync_with_enable/types_ram_sync_with_enable.py index 6e9ac4e8..b31cdfb9 100644 --- a/tests/extension/types_/ram_/sync_with_enable/types_ram_sync_with_enable.py +++ b/tests/extension/types_/ram_/sync_with_enable/types_ram_sync_with_enable.py @@ -129,9 +129,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None): sim = simulation.Simulator(test, sim=simtype) rslt = sim.run(outputfile=outputfile) - lines = rslt.splitlines() - if simtype == 'verilator' and lines[-1].startswith('-'): - rslt = '\n'.join(lines[:-1]) + return rslt diff --git a/tests/simulation/simulator/iverilog/simulation_simulator_iverilog.py b/tests/simulation/simulator/iverilog/simulation_simulator_iverilog.py index 269be5c3..534b2388 100644 --- a/tests/simulation/simulator/iverilog/simulation_simulator_iverilog.py +++ b/tests/simulation/simulator/iverilog/simulation_simulator_iverilog.py @@ -65,6 +65,7 @@ def mkTest(): return m + if __name__ == '__main__': test = mkTest() verilog = test.to_verilog() diff --git a/tests/simulation/simulator/iverilog/test_simulation_simulator_iverilog.py b/tests/simulation/simulator/iverilog/test_simulation_simulator_iverilog.py index 8edfaee2..5f090c76 100644 --- a/tests/simulation/simulator/iverilog/test_simulation_simulator_iverilog.py +++ b/tests/simulation/simulator/iverilog/test_simulation_simulator_iverilog.py @@ -198,6 +198,7 @@ LED: 6 count: 3 """ + def test(): veriloggen.reset() test_module = simulation_simulator_iverilog.mkTest() @@ -214,5 +215,5 @@ def test(): sim = simulation.Simulator(test_module, sim='iverilog') rslt = sim.run() - + rslt = '\n'.join([line for line in rslt.splitlines() if line.startswith('LED:')] + ['']) assert(expected_rslt == rslt) diff --git a/tests/simulation/simulator/libdir/test_simulation_simulator_libdir.py b/tests/simulation/simulator/libdir/test_simulation_simulator_libdir.py index 9ece1d6a..4ad57dcc 100644 --- a/tests/simulation/simulator/libdir/test_simulation_simulator_libdir.py +++ b/tests/simulation/simulator/libdir/test_simulation_simulator_libdir.py @@ -10115,5 +10115,5 @@ def test(): sim = simulation.Simulator(test_module, sim='iverilog') libdir = os.path.dirname(os.path.abspath(__file__)) + '/subdir/' rslt = sim.run(libdir=libdir) - + rslt = '\n'.join([line for line in rslt.splitlines() if line.startswith('LED:')] + ['']) assert(expected_rslt == rslt) diff --git a/tests/simulation/simulator/vcs/simulation_simulator_vcs.py b/tests/simulation/simulator/vcs/simulation_simulator_vcs.py index af6c1e59..0d5b7b04 100644 --- a/tests/simulation/simulator/vcs/simulation_simulator_vcs.py +++ b/tests/simulation/simulator/vcs/simulation_simulator_vcs.py @@ -65,6 +65,7 @@ def mkTest(): return m + if __name__ == '__main__': test = mkTest() verilog = test.to_verilog() diff --git a/tests/simulation/simulator/verilator/test_simulation_simulator_verilator.py b/tests/simulation/simulator/verilator/test_simulation_simulator_verilator.py index 85a0ec57..9c694388 100644 --- a/tests/simulation/simulator/verilator/test_simulation_simulator_verilator.py +++ b/tests/simulation/simulator/verilator/test_simulation_simulator_verilator.py @@ -104,4 +104,5 @@ def test(): test_module = simulation_simulator_verilator.mkTest() sim = vg.simulation.Simulator(test_module, sim='verilator') rslt = sim.run(sim_time=1000) + rslt = '\n'.join([line for line in rslt.splitlines() if line.startswith('LED:')] + ['']) assert(expected_rslt == rslt) diff --git a/tests/verilog/from_verilog_/branchpredunit/from_verilog_branchpredunit.py b/tests/verilog/from_verilog_/branchpredunit/from_verilog_branchpredunit.py index 3525c826..32287604 100644 --- a/tests/verilog/from_verilog_/branchpredunit/from_verilog_branchpredunit.py +++ b/tests/verilog/from_verilog_/branchpredunit/from_verilog_branchpredunit.py @@ -5,16 +5,19 @@ import collections # the next line can be removed after installation -sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) +sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname( + os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) from veriloggen import * + def mkMips(): file = os.path.dirname(os.path.abspath(__file__)) + '/branch.v' modules = from_verilog.read_verilog_module(file) return modules + if __name__ == '__main__': mips_modules = mkMips() - verilog = ''.join([ m.to_verilog() for m in mips_modules.values() if not m.used ]) + verilog = ''.join([m.to_verilog() for m in mips_modules.values() if not m.used]) print(verilog) diff --git a/tests/verilog/from_verilog_/branchpredunit/test_from_verilog_branchpredunit.py b/tests/verilog/from_verilog_/branchpredunit/test_from_verilog_branchpredunit.py index dd53ea77..8c672c32 100644 --- a/tests/verilog/from_verilog_/branchpredunit/test_from_verilog_branchpredunit.py +++ b/tests/verilog/from_verilog_/branchpredunit/test_from_verilog_branchpredunit.py @@ -534,26 +534,27 @@ `default_nettype wire """ + def test(): veriloggen.reset() test_modules = from_verilog_branchpredunit.mkMips() - code = ''.join([ m.to_verilog() for m in test_modules.values() if not m.used ]) + code = ''.join([m.to_verilog() for m in test_modules.values() if not m.used]) from pyverilog.vparser.parser import parse from pyverilog.ast_code_generator.codegen import ASTCodeGenerator import sys import tempfile - + # encoding: 'utf-8' ? encode = sys.getdefaultencoding() - + tmp = tempfile.NamedTemporaryFile() tmp.write(expected_verilog.encode(encode)) tmp.read() filename = tmp.name print(filename) - - expected_ast, _ = parse([ filename ]) + + expected_ast, _ = parse([filename]) codegen = ASTCodeGenerator() expected_code = codegen.visit(expected_ast) diff --git a/tests/verilog/from_verilog_/module/from_verilog_module.py b/tests/verilog/from_verilog_/module/from_verilog_module.py index 565198ff..2b55d3be 100644 --- a/tests/verilog/from_verilog_/module/from_verilog_module.py +++ b/tests/verilog/from_verilog_/module/from_verilog_module.py @@ -5,31 +5,35 @@ import collections # the next line can be removed after installation -sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) +sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname( + os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) from veriloggen import * + def mkLed(): filename = os.path.dirname(os.path.abspath(__file__)) + '/led.v' modules = from_verilog.read_verilog_module(filename) m = modules['blinkled'] return m + def mkTop(): m = Module('top') width = m.Parameter('WIDTH', 8) clk = m.Input('CLK') rst = m.Input('RST') led = m.Output('LED', width) - - params = ( width, ) - ports = ( clk, rst, led ) + + params = (width, ) + ports = (clk, rst, led) led = mkLed() m.Instance(led, 'inst_blinkled', params, ports) return m + if __name__ == '__main__': top = mkTop() verilog = top.to_verilog() diff --git a/tests/verilog/from_verilog_/module/test_from_verilog_module.py b/tests/verilog/from_verilog_/module/test_from_verilog_module.py index 2a9bfc59..8704ffec 100644 --- a/tests/verilog/from_verilog_/module/test_from_verilog_module.py +++ b/tests/verilog/from_verilog_/module/test_from_verilog_module.py @@ -58,6 +58,7 @@ endmodule """ + def test(): veriloggen.reset() test_module = from_verilog_module.mkTop() diff --git a/tests/verilog/from_verilog_/module_generate/from_verilog_module_generate.py b/tests/verilog/from_verilog_/module_generate/from_verilog_module_generate.py index 565198ff..2b55d3be 100644 --- a/tests/verilog/from_verilog_/module_generate/from_verilog_module_generate.py +++ b/tests/verilog/from_verilog_/module_generate/from_verilog_module_generate.py @@ -5,31 +5,35 @@ import collections # the next line can be removed after installation -sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) +sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname( + os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) from veriloggen import * + def mkLed(): filename = os.path.dirname(os.path.abspath(__file__)) + '/led.v' modules = from_verilog.read_verilog_module(filename) m = modules['blinkled'] return m + def mkTop(): m = Module('top') width = m.Parameter('WIDTH', 8) clk = m.Input('CLK') rst = m.Input('RST') led = m.Output('LED', width) - - params = ( width, ) - ports = ( clk, rst, led ) + + params = (width, ) + ports = (clk, rst, led) led = mkLed() m.Instance(led, 'inst_blinkled', params, ports) return m + if __name__ == '__main__': top = mkTop() verilog = top.to_verilog() diff --git a/tests/verilog/from_verilog_/module_generate/test_from_verilog_module_generate.py b/tests/verilog/from_verilog_/module_generate/test_from_verilog_module_generate.py index 76c951a2..f5554a95 100644 --- a/tests/verilog/from_verilog_/module_generate/test_from_verilog_module_generate.py +++ b/tests/verilog/from_verilog_/module_generate/test_from_verilog_module_generate.py @@ -78,6 +78,7 @@ endmodule """ + def test(): veriloggen.reset() test_module = from_verilog_module_generate.mkTop() diff --git a/tests/verilog/from_verilog_/module_initial/from_verilog_module_initial.py b/tests/verilog/from_verilog_/module_initial/from_verilog_module_initial.py index 617ba131..2581caab 100644 --- a/tests/verilog/from_verilog_/module_initial/from_verilog_module_initial.py +++ b/tests/verilog/from_verilog_/module_initial/from_verilog_module_initial.py @@ -5,16 +5,19 @@ import collections # the next line can be removed after installation -sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) +sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname( + os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) from veriloggen import * + def mkLedTest(): filename = os.path.dirname(os.path.abspath(__file__)) + '/led.v' modules = from_verilog.read_verilog_module(filename) test = modules['test'] return test + if __name__ == '__main__': test = mkLedTest() verilog = test.to_verilog() diff --git a/tests/verilog/from_verilog_/module_initial/test_from_verilog_module_initial.py b/tests/verilog/from_verilog_/module_initial/test_from_verilog_module_initial.py index 40192e66..1b24062d 100644 --- a/tests/verilog/from_verilog_/module_initial/test_from_verilog_module_initial.py +++ b/tests/verilog/from_verilog_/module_initial/test_from_verilog_module_initial.py @@ -79,6 +79,7 @@ endmodule """ + def test(): veriloggen.reset() test_module = from_verilog_module_initial.mkLedTest() diff --git a/tests/verilog/from_verilog_/module_modify/from_verilog_module_modify.py b/tests/verilog/from_verilog_/module_modify/from_verilog_module_modify.py index ecc1f6d2..30b6d284 100644 --- a/tests/verilog/from_verilog_/module_modify/from_verilog_module_modify.py +++ b/tests/verilog/from_verilog_/module_modify/from_verilog_module_modify.py @@ -5,18 +5,20 @@ import collections # the next line can be removed after installation -sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) +sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname( + os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) from veriloggen import * + def mkLed(): filename = os.path.dirname(os.path.abspath(__file__)) + '/led.v' modules = from_verilog.read_verilog_module(filename) m = modules['blinkled'] - + # change the module name m.name = 'modified_led' - + # add new statements enable = m.Input('enable') busy = m.Output('busy') @@ -27,13 +29,14 @@ def mkLed(): # modify the data width led.width = 32 - + old_statement = m.always[0].statement[0].false_statement m.always[0].statement[0].false_statement = If(enable)(*old_statement) - m.Assign( busy(m.variable['count'] < 1023) ) - + m.Assign(busy(m.variable['count'] < 1023)) + return m + def mkTop(): m = Module('top') width = m.Parameter('WIDTH', 8) @@ -44,11 +47,12 @@ def mkTop(): led = mkLed() params = m.copy_params(led) ports = m.copy_ports(led) - + m.Instance(led, 'inst_blinkled', params, ports) return m + if __name__ == '__main__': top = mkTop() verilog = top.to_verilog() diff --git a/tests/verilog/from_verilog_/module_modify/test_from_verilog_module_modify.py b/tests/verilog/from_verilog_/module_modify/test_from_verilog_module_modify.py index 4e8929f4..6e8845de 100644 --- a/tests/verilog/from_verilog_/module_modify/test_from_verilog_module_modify.py +++ b/tests/verilog/from_verilog_/module_modify/test_from_verilog_module_modify.py @@ -65,6 +65,7 @@ endmodule """ + def test(): veriloggen.reset() test_module = from_verilog_module_modify.mkTop() diff --git a/tests/verilog/from_verilog_/module_oldstylecode/from_verilog_module_oldstylecode.py b/tests/verilog/from_verilog_/module_oldstylecode/from_verilog_module_oldstylecode.py index d5e92232..6f4b09da 100644 --- a/tests/verilog/from_verilog_/module_oldstylecode/from_verilog_module_oldstylecode.py +++ b/tests/verilog/from_verilog_/module_oldstylecode/from_verilog_module_oldstylecode.py @@ -5,30 +5,34 @@ import collections # the next line can be removed after installation -sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) +sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname( + os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) from veriloggen import * + def mkLed(): filename = os.path.dirname(os.path.abspath(__file__)) + '/led.v' modules = from_verilog.read_verilog_module(filename) m = modules['blinkled'] return m + def mkTop(): m = Module('top') clk = m.Input('CLK') rst = m.Input('RST') led = m.Output('LED', 8) - - params = ( ) - ports = ( clk, rst, led ) + + params = () + ports = (clk, rst, led) led = mkLed() m.Instance(led, 'inst_blinkled', params, ports) return m + if __name__ == '__main__': top = mkTop() verilog = top.to_verilog() diff --git a/tests/verilog/from_verilog_/module_oldstylecode/test_from_verilog_module_oldstylecode.py b/tests/verilog/from_verilog_/module_oldstylecode/test_from_verilog_module_oldstylecode.py index adddf88e..2bd2fa48 100644 --- a/tests/verilog/from_verilog_/module_oldstylecode/test_from_verilog_module_oldstylecode.py +++ b/tests/verilog/from_verilog_/module_oldstylecode/test_from_verilog_module_oldstylecode.py @@ -54,6 +54,7 @@ endmodule """ + def test(): veriloggen.reset() test_module = from_verilog_module_oldstylecode.mkTop() diff --git a/tests/verilog/from_verilog_/module_str/from_verilog_module_str.py b/tests/verilog/from_verilog_/module_str/from_verilog_module_str.py index 9d99b0b9..5438dbe9 100644 --- a/tests/verilog/from_verilog_/module_str/from_verilog_module_str.py +++ b/tests/verilog/from_verilog_/module_str/from_verilog_module_str.py @@ -5,7 +5,8 @@ import collections # the next line can be removed after installation -sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) +sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname( + os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) from veriloggen import * @@ -43,26 +44,29 @@ endmodule ''' + def mkLed(): modules = from_verilog.read_verilog_module_str(led_v) m = modules['blinkled'] return m + def mkTop(): m = Module('top') width = m.Parameter('WIDTH', 8) clk = m.Input('CLK') rst = m.Input('RST') led = m.Output('LED', width) - - params = ( width, ) - ports = ( clk, rst, led ) + + params = (width, ) + ports = (clk, rst, led) led = mkLed() m.Instance(led, 'inst_blinkled', params, ports) return m + if __name__ == '__main__': top = mkTop() verilog = top.to_verilog() diff --git a/tests/verilog/from_verilog_/module_str/test_from_verilog_module_str.py b/tests/verilog/from_verilog_/module_str/test_from_verilog_module_str.py index f3985076..e8b21c52 100644 --- a/tests/verilog/from_verilog_/module_str/test_from_verilog_module_str.py +++ b/tests/verilog/from_verilog_/module_str/test_from_verilog_module_str.py @@ -58,6 +58,7 @@ endmodule """ + def test(): veriloggen.reset() test_module = from_verilog_module_str.mkTop() diff --git a/tests/verilog/from_verilog_/pycoram_ctrl_thread/from_verilog_pycoram_ctrl_thread.py b/tests/verilog/from_verilog_/pycoram_ctrl_thread/from_verilog_pycoram_ctrl_thread.py index 99de7773..6bee920b 100644 --- a/tests/verilog/from_verilog_/pycoram_ctrl_thread/from_verilog_pycoram_ctrl_thread.py +++ b/tests/verilog/from_verilog_/pycoram_ctrl_thread/from_verilog_pycoram_ctrl_thread.py @@ -5,16 +5,19 @@ import collections # the next line can be removed after installation -sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) +sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname( + os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) from veriloggen import * + def mkThread(): filename = os.path.dirname(os.path.abspath(__file__)) + '/ctrl_thread.v' modules = from_verilog.read_verilog_module(filename) return modules + if __name__ == '__main__': modules = mkThread() - verilog = ''.join([ m.to_verilog() for m in modules.values() ]) + verilog = ''.join([m.to_verilog() for m in modules.values()]) print(verilog) diff --git a/tests/verilog/from_verilog_/pycoram_ctrl_thread/test_from_verilog_pycoram_ctrl_thread.py b/tests/verilog/from_verilog_/pycoram_ctrl_thread/test_from_verilog_pycoram_ctrl_thread.py index 2c12f031..979e10c9 100644 --- a/tests/verilog/from_verilog_/pycoram_ctrl_thread/test_from_verilog_pycoram_ctrl_thread.py +++ b/tests/verilog/from_verilog_/pycoram_ctrl_thread/test_from_verilog_pycoram_ctrl_thread.py @@ -244,10 +244,11 @@ endmodule """ + def test(): veriloggen.reset() modules = from_verilog_pycoram_ctrl_thread.mkThread() - code = ''.join([ m.to_verilog() for m in modules.values() ]) + code = ''.join([m.to_verilog() for m in modules.values()]) from pyverilog.vparser.parser import VerilogParser from pyverilog.ast_code_generator.codegen import ASTCodeGenerator diff --git a/tests/verilog/from_verilog_/pycoram_object/from_verilog_pycoram_object.py b/tests/verilog/from_verilog_/pycoram_object/from_verilog_pycoram_object.py index c70489a7..db29ed78 100644 --- a/tests/verilog/from_verilog_/pycoram_object/from_verilog_pycoram_object.py +++ b/tests/verilog/from_verilog_/pycoram_object/from_verilog_pycoram_object.py @@ -5,17 +5,20 @@ import collections # the next line can be removed after installation -sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) +sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname( + os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) from veriloggen import * + def mkUserlogic(): here = os.path.dirname(os.path.abspath(__file__)) filename = here + '/userlogic.v' modules = from_verilog.read_verilog_module(filename, include=[here]) return modules + if __name__ == '__main__': modules = mkUserlogic() - verilog = ''.join([ m.to_verilog() for m in modules.values() if not m.used ]) + verilog = ''.join([m.to_verilog() for m in modules.values() if not m.used]) print(verilog) diff --git a/tests/verilog/from_verilog_/pycoram_object/test_from_verilog_pycoram_object.py b/tests/verilog/from_verilog_/pycoram_object/test_from_verilog_pycoram_object.py index 29679b7c..91734a55 100644 --- a/tests/verilog/from_verilog_/pycoram_object/test_from_verilog_pycoram_object.py +++ b/tests/verilog/from_verilog_/pycoram_object/test_from_verilog_pycoram_object.py @@ -296,10 +296,11 @@ endmodule """ + def test(): veriloggen.reset() modules = from_verilog_pycoram_object.mkUserlogic() - code = ''.join([ m.to_verilog() for m in modules.values() if not m.used ]) + code = ''.join([m.to_verilog() for m in modules.values() if not m.used]) from pyverilog.vparser.parser import VerilogParser from pyverilog.ast_code_generator.codegen import ASTCodeGenerator diff --git a/tests/verilog/from_verilog_/sensitiveall/from_verilog_sensitiveall.py b/tests/verilog/from_verilog_/sensitiveall/from_verilog_sensitiveall.py index 565198ff..2b55d3be 100644 --- a/tests/verilog/from_verilog_/sensitiveall/from_verilog_sensitiveall.py +++ b/tests/verilog/from_verilog_/sensitiveall/from_verilog_sensitiveall.py @@ -5,31 +5,35 @@ import collections # the next line can be removed after installation -sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) +sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname( + os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) from veriloggen import * + def mkLed(): filename = os.path.dirname(os.path.abspath(__file__)) + '/led.v' modules = from_verilog.read_verilog_module(filename) m = modules['blinkled'] return m + def mkTop(): m = Module('top') width = m.Parameter('WIDTH', 8) clk = m.Input('CLK') rst = m.Input('RST') led = m.Output('LED', width) - - params = ( width, ) - ports = ( clk, rst, led ) + + params = (width, ) + ports = (clk, rst, led) led = mkLed() m.Instance(led, 'inst_blinkled', params, ports) return m + if __name__ == '__main__': top = mkTop() verilog = top.to_verilog() diff --git a/tests/verilog/from_verilog_/sensitiveall/test_from_verilog_sensitiveall.py b/tests/verilog/from_verilog_/sensitiveall/test_from_verilog_sensitiveall.py index afef2ef8..0fe1e570 100644 --- a/tests/verilog/from_verilog_/sensitiveall/test_from_verilog_sensitiveall.py +++ b/tests/verilog/from_verilog_/sensitiveall/test_from_verilog_sensitiveall.py @@ -67,6 +67,7 @@ endmodule """ + def test(): veriloggen.reset() test_module = from_verilog_sensitiveall.mkTop() diff --git a/tests/verilog/from_verilog_/stub_module/from_verilog_stub_module.py b/tests/verilog/from_verilog_/stub_module/from_verilog_stub_module.py index 867894a3..170c09b5 100644 --- a/tests/verilog/from_verilog_/stub_module/from_verilog_stub_module.py +++ b/tests/verilog/from_verilog_/stub_module/from_verilog_stub_module.py @@ -5,30 +5,34 @@ import collections # the next line can be removed after installation -sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) +sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname( + os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) from veriloggen import * + def mkLed(): filename = os.path.dirname(os.path.abspath(__file__)) + '/led.v' stubs = from_verilog.read_verilog_stubmodule(filename) m = stubs['blinkled'] return m + def mkTop(): m = Module('top') width = m.Parameter('WIDTH', 8) clk = m.Input('CLK') rst = m.Input('RST') led = m.Output('LED', width) - - params = ( width, ) - ports = ( clk, rst, led ) - + + params = (width, ) + ports = (clk, rst, led) + m.Instance(mkLed(), 'inst_blinkled', params, ports) return m + if __name__ == '__main__': top = mkTop() verilog = top.to_verilog() diff --git a/tests/verilog/from_verilog_/stub_module/test_from_verilog_stub_module.py b/tests/verilog/from_verilog_/stub_module/test_from_verilog_stub_module.py index 460356f8..6f8c8081 100644 --- a/tests/verilog/from_verilog_/stub_module/test_from_verilog_stub_module.py +++ b/tests/verilog/from_verilog_/stub_module/test_from_verilog_stub_module.py @@ -58,6 +58,7 @@ endmodule """ + def test(): veriloggen.reset() test_module = from_verilog_stub_module.mkTop() diff --git a/tests/verilog/from_verilog_/stub_module_str/from_verilog_stub_module_str.py b/tests/verilog/from_verilog_/stub_module_str/from_verilog_stub_module_str.py index e722860b..2ed2e5b6 100644 --- a/tests/verilog/from_verilog_/stub_module_str/from_verilog_stub_module_str.py +++ b/tests/verilog/from_verilog_/stub_module_str/from_verilog_stub_module_str.py @@ -5,7 +5,8 @@ import collections # the next line can be removed after installation -sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) +sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname( + os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) from veriloggen import * @@ -43,25 +44,28 @@ endmodule ''' + def mkLed(): stubs = from_verilog.read_verilog_stubmodule_str(led_v) m = stubs['blinkled'] return m + def mkTop(): m = Module('top') width = m.Parameter('WIDTH', 8) clk = m.Input('CLK') rst = m.Input('RST') led = m.Output('LED', width) - - params = ( width, ) - ports = ( clk, rst, led ) - + + params = (width, ) + ports = (clk, rst, led) + m.Instance(mkLed(), 'inst_blinkled', params, ports) return m + if __name__ == '__main__': top = mkTop() verilog = top.to_verilog() diff --git a/tests/verilog/from_verilog_/stub_module_str/test_from_verilog_stub_module_str.py b/tests/verilog/from_verilog_/stub_module_str/test_from_verilog_stub_module_str.py index 757b11c0..80ebbfe9 100644 --- a/tests/verilog/from_verilog_/stub_module_str/test_from_verilog_stub_module_str.py +++ b/tests/verilog/from_verilog_/stub_module_str/test_from_verilog_stub_module_str.py @@ -58,6 +58,7 @@ endmodule """ + def test(): veriloggen.reset() test_module = from_verilog_stub_module_str.mkTop() diff --git a/tests_obsolete/extension/dataflow_/_abs/test_dataflow__abs.py b/tests_obsolete/extension/dataflow_/_abs/test_dataflow__abs.py index 70dab523..718a2564 100644 --- a/tests_obsolete/extension/dataflow_/_abs/test_dataflow__abs.py +++ b/tests_obsolete/extension/dataflow_/_abs/test_dataflow__abs.py @@ -613,6 +613,8 @@ endmodule """ + + def test(): veriloggen.reset() test_module = dataflow__abs.mkTest() diff --git a/tests_obsolete/extension/dataflow_/_iter/test_dataflow__iter.py b/tests_obsolete/extension/dataflow_/_iter/test_dataflow__iter.py index c4815bfb..ddf763d9 100644 --- a/tests_obsolete/extension/dataflow_/_iter/test_dataflow__iter.py +++ b/tests_obsolete/extension/dataflow_/_iter/test_dataflow__iter.py @@ -3433,6 +3433,8 @@ endmodule """ + + def test(): veriloggen.reset() test_module = dataflow__iter.mkTest() diff --git a/tests_obsolete/extension/dataflow_/_slice/test_dataflow__slice.py b/tests_obsolete/extension/dataflow_/_slice/test_dataflow__slice.py index 3c6cfe5b..d51459ba 100644 --- a/tests_obsolete/extension/dataflow_/_slice/test_dataflow__slice.py +++ b/tests_obsolete/extension/dataflow_/_slice/test_dataflow__slice.py @@ -569,6 +569,7 @@ """ + def test(): veriloggen.reset() test_module = dataflow__slice.mkTest() diff --git a/tests_obsolete/extension/dataflow_/add/test_dataflow_add.py b/tests_obsolete/extension/dataflow_/add/test_dataflow_add.py index 6a99a18b..1b9e5c3a 100644 --- a/tests_obsolete/extension/dataflow_/add/test_dataflow_add.py +++ b/tests_obsolete/extension/dataflow_/add/test_dataflow_add.py @@ -553,6 +553,8 @@ endmodule """ + + def test(): veriloggen.reset() test_module = dataflow_add.mkTest() diff --git a/tests_obsolete/extension/dataflow_/add_nocontrol/test_dataflow_add_nocontrol.py b/tests_obsolete/extension/dataflow_/add_nocontrol/test_dataflow_add_nocontrol.py index 6f690e31..aaad20f6 100644 --- a/tests_obsolete/extension/dataflow_/add_nocontrol/test_dataflow_add_nocontrol.py +++ b/tests_obsolete/extension/dataflow_/add_nocontrol/test_dataflow_add_nocontrol.py @@ -250,6 +250,7 @@ """ + def test(): veriloggen.reset() test_module = dataflow_add_nocontrol.mkTest() diff --git a/tests_obsolete/extension/dataflow_/add_nostall/test_dataflow_add_nostall.py b/tests_obsolete/extension/dataflow_/add_nostall/test_dataflow_add_nostall.py index dddc404b..67f74ccb 100644 --- a/tests_obsolete/extension/dataflow_/add_nostall/test_dataflow_add_nostall.py +++ b/tests_obsolete/extension/dataflow_/add_nostall/test_dataflow_add_nostall.py @@ -523,6 +523,7 @@ """ + def test(): veriloggen.reset() test_module = dataflow_add_nostall.mkTest() diff --git a/tests_obsolete/extension/dataflow_/add_signed/test_dataflow_add_signed.py b/tests_obsolete/extension/dataflow_/add_signed/test_dataflow_add_signed.py index 26f38388..266608e1 100644 --- a/tests_obsolete/extension/dataflow_/add_signed/test_dataflow_add_signed.py +++ b/tests_obsolete/extension/dataflow_/add_signed/test_dataflow_add_signed.py @@ -554,6 +554,7 @@ """ + def test(): veriloggen.reset() test_module = dataflow_add_signed.mkTest() diff --git a/tests_obsolete/extension/dataflow_/alias/dataflow_alias.py b/tests_obsolete/extension/dataflow_/alias/dataflow_alias.py index de981bcf..5fd439b6 100644 --- a/tests_obsolete/extension/dataflow_/alias/dataflow_alias.py +++ b/tests_obsolete/extension/dataflow_/alias/dataflow_alias.py @@ -98,6 +98,7 @@ def mkTest(): return m + if __name__ == '__main__': test = mkTest() verilog = test.to_verilog('tmp.v') diff --git a/tests_obsolete/extension/dataflow_/alias/test_dataflow_alias.py b/tests_obsolete/extension/dataflow_/alias/test_dataflow_alias.py index 03b00763..6512abf7 100644 --- a/tests_obsolete/extension/dataflow_/alias/test_dataflow_alias.py +++ b/tests_obsolete/extension/dataflow_/alias/test_dataflow_alias.py @@ -187,6 +187,7 @@ """ + def test(): veriloggen.reset() test_module = dataflow_alias.mkTest() diff --git a/tests_obsolete/extension/dataflow_/average/test_dataflow_average.py b/tests_obsolete/extension/dataflow_/average/test_dataflow_average.py index 62f3c0f1..b8949dfe 100644 --- a/tests_obsolete/extension/dataflow_/average/test_dataflow_average.py +++ b/tests_obsolete/extension/dataflow_/average/test_dataflow_average.py @@ -1245,6 +1245,7 @@ """ + def test(): veriloggen.reset() test_module = dataflow_average.mkTest() diff --git a/tests_obsolete/extension/dataflow_/connect/dataflow_connect.py b/tests_obsolete/extension/dataflow_/connect/dataflow_connect.py index 924ee4fb..73f97521 100644 --- a/tests_obsolete/extension/dataflow_/connect/dataflow_connect.py +++ b/tests_obsolete/extension/dataflow_/connect/dataflow_connect.py @@ -98,6 +98,7 @@ def mkTest(): return m + if __name__ == '__main__': test = mkTest() verilog = test.to_verilog('tmp.v') diff --git a/tests_obsolete/extension/dataflow_/connect/test_dataflow_connect.py b/tests_obsolete/extension/dataflow_/connect/test_dataflow_connect.py index a047faf9..006f4c29 100644 --- a/tests_obsolete/extension/dataflow_/connect/test_dataflow_connect.py +++ b/tests_obsolete/extension/dataflow_/connect/test_dataflow_connect.py @@ -187,6 +187,7 @@ """ + def test(): veriloggen.reset() test_module = dataflow_connect.mkTest() diff --git a/tests_obsolete/extension/dataflow_/counter/dataflow_counter.py b/tests_obsolete/extension/dataflow_/counter/dataflow_counter.py index 66fccb93..2aeddc14 100644 --- a/tests_obsolete/extension/dataflow_/counter/dataflow_counter.py +++ b/tests_obsolete/extension/dataflow_/counter/dataflow_counter.py @@ -74,6 +74,7 @@ def mkTest(): return m + if __name__ == '__main__': test = mkTest() verilog = test.to_verilog('tmp.v') diff --git a/tests_obsolete/extension/dataflow_/counter/test_dataflow_counter.py b/tests_obsolete/extension/dataflow_/counter/test_dataflow_counter.py index 5c4cacd0..dd05fb3c 100644 --- a/tests_obsolete/extension/dataflow_/counter/test_dataflow_counter.py +++ b/tests_obsolete/extension/dataflow_/counter/test_dataflow_counter.py @@ -160,6 +160,8 @@ endmodule """ + + def test(): veriloggen.reset() test_module = dataflow_counter.mkTest() diff --git a/tests_obsolete/extension/dataflow_/counter_enable/dataflow_counter_enable.py b/tests_obsolete/extension/dataflow_/counter_enable/dataflow_counter_enable.py index c6675e4e..b24f1d4d 100644 --- a/tests_obsolete/extension/dataflow_/counter_enable/dataflow_counter_enable.py +++ b/tests_obsolete/extension/dataflow_/counter_enable/dataflow_counter_enable.py @@ -73,6 +73,7 @@ def mkTest(): return m + if __name__ == '__main__': test = mkTest() verilog = test.to_verilog('tmp.v') diff --git a/tests_obsolete/extension/dataflow_/counter_enable/test_dataflow_counter_enable.py b/tests_obsolete/extension/dataflow_/counter_enable/test_dataflow_counter_enable.py index d6e6f7ba..ccdfabdb 100644 --- a/tests_obsolete/extension/dataflow_/counter_enable/test_dataflow_counter_enable.py +++ b/tests_obsolete/extension/dataflow_/counter_enable/test_dataflow_counter_enable.py @@ -269,6 +269,7 @@ """ + def test(): veriloggen.reset() test_module = dataflow_counter_enable.mkTest() diff --git a/tests_obsolete/extension/dataflow_/counter_reset/dataflow_counter_reset.py b/tests_obsolete/extension/dataflow_/counter_reset/dataflow_counter_reset.py index 55f93991..22fb69db 100644 --- a/tests_obsolete/extension/dataflow_/counter_reset/dataflow_counter_reset.py +++ b/tests_obsolete/extension/dataflow_/counter_reset/dataflow_counter_reset.py @@ -73,6 +73,7 @@ def mkTest(): return m + if __name__ == '__main__': test = mkTest() verilog = test.to_verilog('tmp.v') diff --git a/tests_obsolete/extension/dataflow_/counter_reset/test_dataflow_counter_reset.py b/tests_obsolete/extension/dataflow_/counter_reset/test_dataflow_counter_reset.py index 48c6f6d1..7184cadf 100644 --- a/tests_obsolete/extension/dataflow_/counter_reset/test_dataflow_counter_reset.py +++ b/tests_obsolete/extension/dataflow_/counter_reset/test_dataflow_counter_reset.py @@ -275,6 +275,7 @@ """ + def test(): veriloggen.reset() test_module = dataflow_counter_reset.mkTest() diff --git a/tests_obsolete/extension/dataflow_/custom/test_dataflow_custom.py b/tests_obsolete/extension/dataflow_/custom/test_dataflow_custom.py index f1d67b44..942daa2f 100644 --- a/tests_obsolete/extension/dataflow_/custom/test_dataflow_custom.py +++ b/tests_obsolete/extension/dataflow_/custom/test_dataflow_custom.py @@ -554,6 +554,7 @@ """ + def test(): veriloggen.reset() test_module = dataflow_custom.mkTest() diff --git a/tests_obsolete/extension/dataflow_/div/test_dataflow_div.py b/tests_obsolete/extension/dataflow_/div/test_dataflow_div.py index affcf97e..c4cfbe9e 100644 --- a/tests_obsolete/extension/dataflow_/div/test_dataflow_div.py +++ b/tests_obsolete/extension/dataflow_/div/test_dataflow_div.py @@ -1745,6 +1745,7 @@ """ + def test(): veriloggen.reset() test_module = dataflow_div.mkTest() diff --git a/tests_obsolete/extension/dataflow_/div_signed/test_dataflow_div_signed.py b/tests_obsolete/extension/dataflow_/div_signed/test_dataflow_div_signed.py index f183227b..bea55974 100644 --- a/tests_obsolete/extension/dataflow_/div_signed/test_dataflow_div_signed.py +++ b/tests_obsolete/extension/dataflow_/div_signed/test_dataflow_div_signed.py @@ -1745,6 +1745,7 @@ """ + def test(): veriloggen.reset() test_module = dataflow_div_signed.mkTest() diff --git a/tests_obsolete/extension/dataflow_/fixed_add/test_dataflow_fixed_add.py b/tests_obsolete/extension/dataflow_/fixed_add/test_dataflow_fixed_add.py index 0e5803c3..af7b2b59 100644 --- a/tests_obsolete/extension/dataflow_/fixed_add/test_dataflow_fixed_add.py +++ b/tests_obsolete/extension/dataflow_/fixed_add/test_dataflow_fixed_add.py @@ -572,6 +572,7 @@ """ + def test(): veriloggen.reset() test_module = dataflow_fixed_add.mkTest() diff --git a/tests_obsolete/extension/dataflow_/fixed_add_shift/test_dataflow_fixed_add_shift.py b/tests_obsolete/extension/dataflow_/fixed_add_shift/test_dataflow_fixed_add_shift.py index 3493c21f..cc5600f1 100644 --- a/tests_obsolete/extension/dataflow_/fixed_add_shift/test_dataflow_fixed_add_shift.py +++ b/tests_obsolete/extension/dataflow_/fixed_add_shift/test_dataflow_fixed_add_shift.py @@ -572,6 +572,7 @@ """ + def test(): veriloggen.reset() test_module = dataflow_fixed_add_shift.mkTest() diff --git a/tests_obsolete/extension/dataflow_/fixed_add_shift_signed/test_dataflow_fixed_add_shift_signed.py b/tests_obsolete/extension/dataflow_/fixed_add_shift_signed/test_dataflow_fixed_add_shift_signed.py index dd85ad6d..a953b4a2 100644 --- a/tests_obsolete/extension/dataflow_/fixed_add_shift_signed/test_dataflow_fixed_add_shift_signed.py +++ b/tests_obsolete/extension/dataflow_/fixed_add_shift_signed/test_dataflow_fixed_add_shift_signed.py @@ -572,6 +572,7 @@ """ + def test(): veriloggen.reset() test_module = dataflow_fixed_add_shift_signed.mkTest() diff --git a/tests_obsolete/extension/dataflow_/fixed_mul/test_dataflow_fixed_mul.py b/tests_obsolete/extension/dataflow_/fixed_mul/test_dataflow_fixed_mul.py index 877c6aa4..25acf919 100644 --- a/tests_obsolete/extension/dataflow_/fixed_mul/test_dataflow_fixed_mul.py +++ b/tests_obsolete/extension/dataflow_/fixed_mul/test_dataflow_fixed_mul.py @@ -911,6 +911,7 @@ """ + def test(): veriloggen.reset() test_module = dataflow_fixed_mul.mkTest() diff --git a/tests_obsolete/extension/dataflow_/fixed_mul_shift/test_dataflow_fixed_mul_shift.py b/tests_obsolete/extension/dataflow_/fixed_mul_shift/test_dataflow_fixed_mul_shift.py index 38ff05e5..7ba4927b 100644 --- a/tests_obsolete/extension/dataflow_/fixed_mul_shift/test_dataflow_fixed_mul_shift.py +++ b/tests_obsolete/extension/dataflow_/fixed_mul_shift/test_dataflow_fixed_mul_shift.py @@ -911,6 +911,7 @@ """ + def test(): veriloggen.reset() test_module = dataflow_fixed_mul_shift.mkTest() diff --git a/tests_obsolete/extension/dataflow_/fixed_mul_shift_signed/test_dataflow_fixed_mul_shift_signed.py b/tests_obsolete/extension/dataflow_/fixed_mul_shift_signed/test_dataflow_fixed_mul_shift_signed.py index 65da4b57..42b183e6 100644 --- a/tests_obsolete/extension/dataflow_/fixed_mul_shift_signed/test_dataflow_fixed_mul_shift_signed.py +++ b/tests_obsolete/extension/dataflow_/fixed_mul_shift_signed/test_dataflow_fixed_mul_shift_signed.py @@ -911,6 +911,7 @@ """ + def test(): veriloggen.reset() test_module = dataflow_fixed_mul_shift_signed.mkTest() diff --git a/tests_obsolete/extension/dataflow_/getio/dataflow_getio.py b/tests_obsolete/extension/dataflow_/getio/dataflow_getio.py index 1c25544a..0aa784a8 100644 --- a/tests_obsolete/extension/dataflow_/getio/dataflow_getio.py +++ b/tests_obsolete/extension/dataflow_/getio/dataflow_getio.py @@ -98,6 +98,7 @@ def mkTest(): return m + if __name__ == '__main__': test = mkTest() verilog = test.to_verilog('tmp.v') diff --git a/tests_obsolete/extension/dataflow_/getio/test_dataflow_getio.py b/tests_obsolete/extension/dataflow_/getio/test_dataflow_getio.py index 44ab32fb..a64975d2 100644 --- a/tests_obsolete/extension/dataflow_/getio/test_dataflow_getio.py +++ b/tests_obsolete/extension/dataflow_/getio/test_dataflow_getio.py @@ -193,6 +193,7 @@ """ + def test(): veriloggen.reset() test_module = dataflow_getio.mkTest() diff --git a/tests_obsolete/extension/dataflow_/graph_add/test_dataflow_graph_add.py b/tests_obsolete/extension/dataflow_/graph_add/test_dataflow_graph_add.py index fdd770d2..3a59c62e 100644 --- a/tests_obsolete/extension/dataflow_/graph_add/test_dataflow_graph_add.py +++ b/tests_obsolete/extension/dataflow_/graph_add/test_dataflow_graph_add.py @@ -554,6 +554,7 @@ """ + def test(): veriloggen.reset() test_module = dataflow_graph_add.mkTest() diff --git a/tests_obsolete/extension/dataflow_/graph_average/test_dataflow_graph_average.py b/tests_obsolete/extension/dataflow_/graph_average/test_dataflow_graph_average.py index 5c4c2aa8..5c1edcb4 100644 --- a/tests_obsolete/extension/dataflow_/graph_average/test_dataflow_graph_average.py +++ b/tests_obsolete/extension/dataflow_/graph_average/test_dataflow_graph_average.py @@ -1245,6 +1245,7 @@ """ + def test(): veriloggen.reset() test_module = dataflow_graph_average.mkTest() diff --git a/tests_obsolete/extension/dataflow_/graph_pass/test_dataflow_graph_pass.py b/tests_obsolete/extension/dataflow_/graph_pass/test_dataflow_graph_pass.py index 28b0711d..7bcfb643 100644 --- a/tests_obsolete/extension/dataflow_/graph_pass/test_dataflow_graph_pass.py +++ b/tests_obsolete/extension/dataflow_/graph_pass/test_dataflow_graph_pass.py @@ -300,6 +300,7 @@ """ + def test(): veriloggen.reset() test_module = dataflow_graph_pass.mkTest() diff --git a/tests_obsolete/extension/dataflow_/implement_add/test_dataflow_implement_add.py b/tests_obsolete/extension/dataflow_/implement_add/test_dataflow_implement_add.py index 581ad9a4..ccbb6fa3 100644 --- a/tests_obsolete/extension/dataflow_/implement_add/test_dataflow_implement_add.py +++ b/tests_obsolete/extension/dataflow_/implement_add/test_dataflow_implement_add.py @@ -554,6 +554,7 @@ """ + def test(): veriloggen.reset() test_module = dataflow_implement_add.mkTest() diff --git a/tests_obsolete/extension/dataflow_/implement_embedded/test_dataflow_implement_embedded.py b/tests_obsolete/extension/dataflow_/implement_embedded/test_dataflow_implement_embedded.py index e6948dac..30d9e38c 100644 --- a/tests_obsolete/extension/dataflow_/implement_embedded/test_dataflow_implement_embedded.py +++ b/tests_obsolete/extension/dataflow_/implement_embedded/test_dataflow_implement_embedded.py @@ -554,6 +554,7 @@ """ + def test(): veriloggen.reset() test_module = dataflow_implement_embedded.mkTest() diff --git a/tests_obsolete/extension/dataflow_/inc/test_dataflow_inc.py b/tests_obsolete/extension/dataflow_/inc/test_dataflow_inc.py index d8140b32..9da883be 100644 --- a/tests_obsolete/extension/dataflow_/inc/test_dataflow_inc.py +++ b/tests_obsolete/extension/dataflow_/inc/test_dataflow_inc.py @@ -322,6 +322,7 @@ """ + def test(): veriloggen.reset() test_module = dataflow_inc.mkTest() diff --git a/tests_obsolete/extension/dataflow_/loop/dataflow_loop.py b/tests_obsolete/extension/dataflow_/loop/dataflow_loop.py index 2f71f1bf..fda8df63 100644 --- a/tests_obsolete/extension/dataflow_/loop/dataflow_loop.py +++ b/tests_obsolete/extension/dataflow_/loop/dataflow_loop.py @@ -62,6 +62,7 @@ def mkTest(): return m + if __name__ == '__main__': try: test = mkTest() diff --git a/tests_obsolete/extension/dataflow_/lut/test_dataflow_lut.py b/tests_obsolete/extension/dataflow_/lut/test_dataflow_lut.py index 8cdba6ca..ed637d74 100644 --- a/tests_obsolete/extension/dataflow_/lut/test_dataflow_lut.py +++ b/tests_obsolete/extension/dataflow_/lut/test_dataflow_lut.py @@ -1381,6 +1381,7 @@ """ + def test(): veriloggen.reset() test_module = dataflow_lut.mkTest() diff --git a/tests_obsolete/extension/dataflow_/mac/test_dataflow_mac.py b/tests_obsolete/extension/dataflow_/mac/test_dataflow_mac.py index e31dd281..fe316b4a 100644 --- a/tests_obsolete/extension/dataflow_/mac/test_dataflow_mac.py +++ b/tests_obsolete/extension/dataflow_/mac/test_dataflow_mac.py @@ -1068,6 +1068,7 @@ """ + def test(): veriloggen.reset() test_module = dataflow_mac.mkTest() diff --git a/tests_obsolete/extension/dataflow_/manager/test_dataflow_manager.py b/tests_obsolete/extension/dataflow_/manager/test_dataflow_manager.py index a5450133..32dc7bb2 100644 --- a/tests_obsolete/extension/dataflow_/manager/test_dataflow_manager.py +++ b/tests_obsolete/extension/dataflow_/manager/test_dataflow_manager.py @@ -357,6 +357,7 @@ """ + def test(): veriloggen.reset() test_module = dataflow_manager.mkTest() diff --git a/tests_obsolete/extension/dataflow_/manager_readwrite/dataflow_manager_readwrite.py b/tests_obsolete/extension/dataflow_/manager_readwrite/dataflow_manager_readwrite.py index ce2eff30..6de7cfc1 100644 --- a/tests_obsolete/extension/dataflow_/manager_readwrite/dataflow_manager_readwrite.py +++ b/tests_obsolete/extension/dataflow_/manager_readwrite/dataflow_manager_readwrite.py @@ -105,6 +105,7 @@ def mkTest(): return m + if __name__ == '__main__': test = mkTest() verilog = test.to_verilog('tmp.v') diff --git a/tests_obsolete/extension/dataflow_/manager_readwrite/test_dataflow_manager_readwrite.py b/tests_obsolete/extension/dataflow_/manager_readwrite/test_dataflow_manager_readwrite.py index 12de4673..2aa1b1da 100644 --- a/tests_obsolete/extension/dataflow_/manager_readwrite/test_dataflow_manager_readwrite.py +++ b/tests_obsolete/extension/dataflow_/manager_readwrite/test_dataflow_manager_readwrite.py @@ -351,6 +351,7 @@ """ + def test(): veriloggen.reset() test_module = dataflow_manager_readwrite.mkTest() diff --git a/tests_obsolete/extension/dataflow_/mod/test_dataflow_mod.py b/tests_obsolete/extension/dataflow_/mod/test_dataflow_mod.py index 9e18bc55..bc9da477 100644 --- a/tests_obsolete/extension/dataflow_/mod/test_dataflow_mod.py +++ b/tests_obsolete/extension/dataflow_/mod/test_dataflow_mod.py @@ -1745,6 +1745,7 @@ """ + def test(): veriloggen.reset() test_module = dataflow_mod.mkTest() diff --git a/tests_obsolete/extension/dataflow_/mul/dataflow_mul.py b/tests_obsolete/extension/dataflow_/mul/dataflow_mul.py index e3c0a479..438ed606 100644 --- a/tests_obsolete/extension/dataflow_/mul/dataflow_mul.py +++ b/tests_obsolete/extension/dataflow_/mul/dataflow_mul.py @@ -4,11 +4,13 @@ import os # the next line can be removed after installation -sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) +sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname( + os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) from veriloggen import * import veriloggen.dataflow as dataflow + def mkMain(): # input variiable x = dataflow.Variable('xdata', valid='xvalid', ready='xready', signed=False) @@ -22,9 +24,10 @@ def mkMain(): df = dataflow.Dataflow(z) m = df.to_module('main') - + return m + def mkTest(numports=8): m = Module('test') @@ -40,27 +43,27 @@ def mkTest(numports=8): xdata = ports['xdata'] xvalid = ports['xvalid'] xready = ports['xready'] - + ydata = ports['ydata'] yvalid = ports['yvalid'] yready = ports['yready'] - + zdata = ports['zdata'] zvalid = ports['zvalid'] zready = ports['zready'] - + uut = m.Instance(main, 'uut', params=m.connect_params(main), ports=m.connect_ports(main)) reset_done = m.Reg('reset_done', initval=0) reset_stmt = [] - reset_stmt.append( reset_done(0) ) - reset_stmt.append( xdata(0) ) - reset_stmt.append( xvalid(0) ) - reset_stmt.append( ydata(0) ) - reset_stmt.append( yvalid(0) ) - reset_stmt.append( zready(0) ) + reset_stmt.append(reset_done(0)) + reset_stmt.append(xdata(0)) + reset_stmt.append(xvalid(0)) + reset_stmt.append(ydata(0)) + reset_stmt.append(yvalid(0)) + reset_stmt.append(zready(0)) vcd_name = os.path.splitext(os.path.basename(__file__))[0] + '.vcd' simulation.setup_waveform(m, uut, dumpfile=vcd_name) @@ -68,7 +71,7 @@ def mkTest(numports=8): init = simulation.setup_reset(m, rst, reset_stmt, period=100) nclk = simulation.next_clock - + init.add( Delay(1000), reset_done(1), @@ -80,56 +83,53 @@ def mkTest(numports=8): def send(name, data, valid, ready, step=1, waitnum=10): fsm = FSM(m, name + 'fsm', clk, rst) count = m.TmpReg(32, initval=0) - + fsm.add(valid(0)) fsm.goto_next(cond=reset_done) for _ in range(waitnum): fsm.goto_next() - + fsm.add(valid(1)) fsm.goto_next() - + fsm.add(data(data + step), cond=ready) fsm.add(count.inc(), cond=ready) - fsm.add(valid(0), cond=AndList(count==5, ready)) - fsm.goto_next(cond=AndList(count==5, ready)) - + fsm.add(valid(0), cond=AndList(count == 5, ready)) + fsm.goto_next(cond=AndList(count == 5, ready)) + for _ in range(waitnum): fsm.goto_next() fsm.add(valid(1)) - + fsm.add(data(data + step), cond=ready) fsm.add(count.inc(), cond=ready) - fsm.add(valid(0), cond=AndList(count==10, ready)) - fsm.goto_next(cond=AndList(count==10, ready)) - + fsm.add(valid(0), cond=AndList(count == 10, ready)) + fsm.goto_next(cond=AndList(count == 10, ready)) + fsm.make_always() - def receive(name, data, valid, ready, waitnum=10): fsm = FSM(m, name + 'fsm', clk, rst) - + fsm.add(ready(0)) fsm.goto_next(cond=reset_done) fsm.goto_next() - - yinit= fsm.current + + yinit = fsm.current fsm.add(ready(1), cond=valid) fsm.goto_next(cond=valid) for i in range(waitnum): fsm.add(ready(0)) fsm.goto_next() - + fsm.goto(yinit) - + fsm.make_always() - send('x', xdata, xvalid, xready, step=1, waitnum=10) send('y', ydata, yvalid, yready, step=1, waitnum=20) receive('z', zdata, zvalid, zready, waitnum=50) - - + m.Always(Posedge(clk))( If(reset_done)( If(AndList(xvalid, xready))( @@ -143,10 +143,10 @@ def receive(name, data, valid, ready, waitnum=10): ) ) ) - + return m - + if __name__ == '__main__': test = mkTest() verilog = test.to_verilog('tmp.v') @@ -154,10 +154,10 @@ def receive(name, data, valid, ready, waitnum=10): # run simulator (Icarus Verilog) sim = simulation.Simulator(test) - rslt = sim.run() # display=False + rslt = sim.run() # display=False #rslt = sim.run(display=True) print(rslt) # launch waveform viewer (GTKwave) - #sim.view_waveform() # background=False - #sim.view_waveform(background=True) + # sim.view_waveform() # background=False + # sim.view_waveform(background=True) diff --git a/tests_obsolete/extension/dataflow_/mul/test_dataflow_mul.py b/tests_obsolete/extension/dataflow_/mul/test_dataflow_mul.py index 4790d762..c3ae93d5 100644 --- a/tests_obsolete/extension/dataflow_/mul/test_dataflow_mul.py +++ b/tests_obsolete/extension/dataflow_/mul/test_dataflow_mul.py @@ -893,6 +893,7 @@ """ + def test(): veriloggen.reset() test_module = dataflow_mul.mkTest() diff --git a/tests_obsolete/extension/dataflow_/mul_signed/test_dataflow_mul_signed.py b/tests_obsolete/extension/dataflow_/mul_signed/test_dataflow_mul_signed.py index 8f465468..1abe6e99 100644 --- a/tests_obsolete/extension/dataflow_/mul_signed/test_dataflow_mul_signed.py +++ b/tests_obsolete/extension/dataflow_/mul_signed/test_dataflow_mul_signed.py @@ -893,6 +893,7 @@ """ + def test(): veriloggen.reset() test_module = dataflow_mul_signed.mkTest() diff --git a/tests_obsolete/extension/dataflow_/muladd/test_dataflow_muladd.py b/tests_obsolete/extension/dataflow_/muladd/test_dataflow_muladd.py index 4e2f6e03..1b9ebd93 100644 --- a/tests_obsolete/extension/dataflow_/muladd/test_dataflow_muladd.py +++ b/tests_obsolete/extension/dataflow_/muladd/test_dataflow_muladd.py @@ -1125,6 +1125,7 @@ """ + def test(): veriloggen.reset() test_module = dataflow_muladd.mkTest() diff --git a/tests_obsolete/extension/dataflow_/multiple_manager/test_dataflow_multiple_manager.py b/tests_obsolete/extension/dataflow_/multiple_manager/test_dataflow_multiple_manager.py index e8233fac..536c6f4e 100644 --- a/tests_obsolete/extension/dataflow_/multiple_manager/test_dataflow_multiple_manager.py +++ b/tests_obsolete/extension/dataflow_/multiple_manager/test_dataflow_multiple_manager.py @@ -266,6 +266,7 @@ """ + def test(): veriloggen.reset() test_module = dataflow_multiple_manager.mkTest() diff --git a/tests_obsolete/extension/dataflow_/multireadwrite/dataflow_multireadwrite.py b/tests_obsolete/extension/dataflow_/multireadwrite/dataflow_multireadwrite.py index 5c39def9..14ac2c4f 100644 --- a/tests_obsolete/extension/dataflow_/multireadwrite/dataflow_multireadwrite.py +++ b/tests_obsolete/extension/dataflow_/multireadwrite/dataflow_multireadwrite.py @@ -138,6 +138,7 @@ def mkTest(): return m + if __name__ == '__main__': test = mkTest() verilog = test.to_verilog('tmp.v') diff --git a/tests_obsolete/extension/dataflow_/multireadwrite/test_dataflow_multireadwrite.py b/tests_obsolete/extension/dataflow_/multireadwrite/test_dataflow_multireadwrite.py index 764c8719..1664510b 100644 --- a/tests_obsolete/extension/dataflow_/multireadwrite/test_dataflow_multireadwrite.py +++ b/tests_obsolete/extension/dataflow_/multireadwrite/test_dataflow_multireadwrite.py @@ -335,6 +335,7 @@ """ + def test(): veriloggen.reset() test_module = dataflow_multireadwrite.mkTest() diff --git a/tests_obsolete/extension/dataflow_/mux/test_dataflow_mux.py b/tests_obsolete/extension/dataflow_/mux/test_dataflow_mux.py index 1b695a3b..c7500ef2 100644 --- a/tests_obsolete/extension/dataflow_/mux/test_dataflow_mux.py +++ b/tests_obsolete/extension/dataflow_/mux/test_dataflow_mux.py @@ -599,6 +599,7 @@ """ + def test(): veriloggen.reset() test_module = dataflow_mux.mkTest() diff --git a/tests_obsolete/extension/dataflow_/mux_const/test_dataflow_mux_const.py b/tests_obsolete/extension/dataflow_/mux_const/test_dataflow_mux_const.py index bd09ded9..96e3b77a 100644 --- a/tests_obsolete/extension/dataflow_/mux_const/test_dataflow_mux_const.py +++ b/tests_obsolete/extension/dataflow_/mux_const/test_dataflow_mux_const.py @@ -554,6 +554,7 @@ """ + def test(): veriloggen.reset() test_module = dataflow_mux_const.mkTest() diff --git a/tests_obsolete/extension/dataflow_/parameter/dataflow_parameter.py b/tests_obsolete/extension/dataflow_/parameter/dataflow_parameter.py index 16ab92c9..0ec1bbf6 100644 --- a/tests_obsolete/extension/dataflow_/parameter/dataflow_parameter.py +++ b/tests_obsolete/extension/dataflow_/parameter/dataflow_parameter.py @@ -94,6 +94,7 @@ def mkTest(): return m + if __name__ == '__main__': test = mkTest() verilog = test.to_verilog('tmp.v') diff --git a/tests_obsolete/extension/dataflow_/parameter/test_dataflow_parameter.py b/tests_obsolete/extension/dataflow_/parameter/test_dataflow_parameter.py index a4b7ec71..d831feb5 100644 --- a/tests_obsolete/extension/dataflow_/parameter/test_dataflow_parameter.py +++ b/tests_obsolete/extension/dataflow_/parameter/test_dataflow_parameter.py @@ -316,6 +316,7 @@ """ + def test(): veriloggen.reset() test_module = dataflow_parameter.mkTest() diff --git a/tests_obsolete/extension/dataflow_/pass/test_dataflow_pass.py b/tests_obsolete/extension/dataflow_/pass/test_dataflow_pass.py index 1f9ad4f1..7f75ef59 100644 --- a/tests_obsolete/extension/dataflow_/pass/test_dataflow_pass.py +++ b/tests_obsolete/extension/dataflow_/pass/test_dataflow_pass.py @@ -300,6 +300,7 @@ """ + def test(): veriloggen.reset() test_module = dataflow_pass.mkTest() diff --git a/tests_obsolete/extension/dataflow_/pass_nocontrol/dataflow_pass_nocontrol.py b/tests_obsolete/extension/dataflow_/pass_nocontrol/dataflow_pass_nocontrol.py index d8e1bd11..6daf04fc 100644 --- a/tests_obsolete/extension/dataflow_/pass_nocontrol/dataflow_pass_nocontrol.py +++ b/tests_obsolete/extension/dataflow_/pass_nocontrol/dataflow_pass_nocontrol.py @@ -4,11 +4,13 @@ import os # the next line can be removed after installation -sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) +sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname( + os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) from veriloggen import * import veriloggen.dataflow as dataflow + def mkMain(): # input variiable x = dataflow.Variable('xdata', signed=False) @@ -21,9 +23,10 @@ def mkMain(): df = dataflow.Dataflow(z) m = df.to_module('main') - + return m + def mkTest(numports=8): m = Module('test') @@ -42,24 +45,24 @@ def mkTest(numports=8): xvalid = m.Reg('xvalid') xready = m.Wire('xready') m.Assign(xready(1)) - + zdata = ports['zdata'] #zvalid = ports['zvalid'] #zready = ports['zready'] zvalid = m.Wire('zvalid') zready = m.Reg('zready') m.Assign(zvalid(1)) - + uut = m.Instance(main, 'uut', params=m.connect_params(main), ports=m.connect_ports(main)) reset_done = m.Reg('reset_done', initval=0) reset_stmt = [] - reset_stmt.append( reset_done(0) ) - reset_stmt.append( xdata(0) ) - reset_stmt.append( xvalid(0) ) - reset_stmt.append( zready(0) ) + reset_stmt.append(reset_done(0)) + reset_stmt.append(xdata(0)) + reset_stmt.append(xvalid(0)) + reset_stmt.append(zready(0)) vcd_name = os.path.splitext(os.path.basename(__file__))[0] + '.vcd' simulation.setup_waveform(m, uut, dumpfile=vcd_name) @@ -67,7 +70,7 @@ def mkTest(numports=8): init = simulation.setup_reset(m, rst, reset_stmt, period=100) nclk = simulation.next_clock - + init.add( Delay(1000), reset_done(1), @@ -79,71 +82,68 @@ def mkTest(numports=8): def send(name, data, valid, ready, step=1, waitnum=10): fsm = FSM(m, name + 'fsm', clk, rst) count = m.TmpReg(32, initval=0) - + fsm.add(valid(0)) fsm.goto_next(cond=reset_done) - #for _ in range(waitnum): + # for _ in range(waitnum): # fsm.goto_next() - + fsm.add(valid(1)) fsm.goto_next() - + fsm.add(data(data + step), cond=ready) fsm.add(count.inc(), cond=ready) #fsm.add(valid(0), cond=AndList(count==5, ready)) - fsm.goto_next(cond=AndList(count==5, ready)) - - #for _ in range(waitnum): + fsm.goto_next(cond=AndList(count == 5, ready)) + + # for _ in range(waitnum): # fsm.goto_next() - #fsm.add(valid(1)) - + # fsm.add(valid(1)) + fsm.add(data(data + step), cond=ready) fsm.add(count.inc(), cond=ready) #fsm.add(valid(0), cond=AndList(count==10, ready)) - fsm.goto_next(cond=AndList(count==10, ready)) - + fsm.goto_next(cond=AndList(count == 10, ready)) + fsm.make_always() - def receive(name, data, valid, ready, waitnum=10): fsm = FSM(m, name + 'fsm', clk, rst) - + fsm.add(ready(0)) fsm.goto_next(cond=reset_done) fsm.goto_next() - + yinit = fsm.current fsm.add(ready(1), cond=valid) - #fsm.goto_next(cond=valid) - #for i in range(waitnum): + # fsm.goto_next(cond=valid) + # for i in range(waitnum): # fsm.add(ready(0)) # fsm.goto_next() - - #fsm.goto(yinit) - + + # fsm.goto(yinit) + fsm.make_always() - send('x', xdata, xvalid, xready, step=1, waitnum=10) receive('z', zdata, zvalid, zready, waitnum=5) - - + m.Always(Posedge(clk))( If(reset_done)( - # If(AndList(xvalid, xready))( - # Systask('display', 'xdata=%d', xdata) - # ), - # If(AndList(zvalid, zready))( - # Systask('display', 'zdata=%d', zdata) - # ) + # If(AndList(xvalid, xready))( + # Systask('display', 'xdata=%d', xdata) + # ), + # If(AndList(zvalid, zready))( + # Systask('display', 'zdata=%d', zdata) + # ) Systask('display', 'xdata=%d', xdata), Systask('display', 'zdata=%d', zdata) ) ) - + return m - + if __name__ == '__main__': test = mkTest() verilog = test.to_verilog('tmp.v') @@ -151,10 +151,10 @@ def receive(name, data, valid, ready, waitnum=10): # run simulator (Icarus Verilog) sim = simulation.Simulator(test) - rslt = sim.run() # display=False + rslt = sim.run() # display=False #rslt = sim.run(display=True) print(rslt) # launch waveform viewer (GTKwave) - #sim.view_waveform() # background=False - #sim.view_waveform(background=True) + # sim.view_waveform() # background=False + # sim.view_waveform(background=True) diff --git a/tests_obsolete/extension/dataflow_/pass_nocontrol/test_dataflow_pass_nocontrol.py b/tests_obsolete/extension/dataflow_/pass_nocontrol/test_dataflow_pass_nocontrol.py index 9622b342..666d4b48 100644 --- a/tests_obsolete/extension/dataflow_/pass_nocontrol/test_dataflow_pass_nocontrol.py +++ b/tests_obsolete/extension/dataflow_/pass_nocontrol/test_dataflow_pass_nocontrol.py @@ -169,6 +169,7 @@ """ + def test(): veriloggen.reset() test_module = dataflow_pass_nocontrol.mkTest() diff --git a/tests_obsolete/extension/dataflow_/prev/test_dataflow_prev.py b/tests_obsolete/extension/dataflow_/prev/test_dataflow_prev.py index e014553f..a43a8969 100644 --- a/tests_obsolete/extension/dataflow_/prev/test_dataflow_prev.py +++ b/tests_obsolete/extension/dataflow_/prev/test_dataflow_prev.py @@ -362,6 +362,7 @@ """ + def test(): veriloggen.reset() test_module = dataflow_prev.mkTest() diff --git a/tests_obsolete/extension/dataflow_/readwrite/dataflow_readwrite.py b/tests_obsolete/extension/dataflow_/readwrite/dataflow_readwrite.py index 4db44ae3..81e03c22 100644 --- a/tests_obsolete/extension/dataflow_/readwrite/dataflow_readwrite.py +++ b/tests_obsolete/extension/dataflow_/readwrite/dataflow_readwrite.py @@ -101,6 +101,7 @@ def mkTest(): return m + if __name__ == '__main__': test = mkTest() verilog = test.to_verilog('tmp.v') diff --git a/tests_obsolete/extension/dataflow_/readwrite/test_dataflow_readwrite.py b/tests_obsolete/extension/dataflow_/readwrite/test_dataflow_readwrite.py index 0daf25a8..d9343934 100644 --- a/tests_obsolete/extension/dataflow_/readwrite/test_dataflow_readwrite.py +++ b/tests_obsolete/extension/dataflow_/readwrite/test_dataflow_readwrite.py @@ -188,6 +188,7 @@ """ + def test(): veriloggen.reset() test_module = dataflow_readwrite.mkTest() diff --git a/tests_obsolete/extension/dataflow_/reduceadd/test_dataflow_reduceadd.py b/tests_obsolete/extension/dataflow_/reduceadd/test_dataflow_reduceadd.py index 6841deeb..56ae67d8 100644 --- a/tests_obsolete/extension/dataflow_/reduceadd/test_dataflow_reduceadd.py +++ b/tests_obsolete/extension/dataflow_/reduceadd/test_dataflow_reduceadd.py @@ -322,6 +322,7 @@ """ + def test(): veriloggen.reset() test_module = dataflow_reduceadd.mkTest() diff --git a/tests_obsolete/extension/dataflow_/reduceadd_enable/test_dataflow_reduceadd_enable.py b/tests_obsolete/extension/dataflow_/reduceadd_enable/test_dataflow_reduceadd_enable.py index 4d57fa8f..a360728b 100644 --- a/tests_obsolete/extension/dataflow_/reduceadd_enable/test_dataflow_reduceadd_enable.py +++ b/tests_obsolete/extension/dataflow_/reduceadd_enable/test_dataflow_reduceadd_enable.py @@ -436,6 +436,7 @@ """ + def test(): veriloggen.reset() test_module = dataflow_reduceadd_enable.mkTest() diff --git a/tests_obsolete/extension/dataflow_/reduceadd_reset/test_dataflow_reduceadd_reset.py b/tests_obsolete/extension/dataflow_/reduceadd_reset/test_dataflow_reduceadd_reset.py index 41c57013..be64eee8 100644 --- a/tests_obsolete/extension/dataflow_/reduceadd_reset/test_dataflow_reduceadd_reset.py +++ b/tests_obsolete/extension/dataflow_/reduceadd_reset/test_dataflow_reduceadd_reset.py @@ -379,6 +379,7 @@ """ + def test(): veriloggen.reset() test_module = dataflow_reduceadd_reset.mkTest() diff --git a/tests_obsolete/extension/dataflow_/reduceadd_valid/test_dataflow_reduceadd_valid.py b/tests_obsolete/extension/dataflow_/reduceadd_valid/test_dataflow_reduceadd_valid.py index 748eea56..8d3e4280 100644 --- a/tests_obsolete/extension/dataflow_/reduceadd_valid/test_dataflow_reduceadd_valid.py +++ b/tests_obsolete/extension/dataflow_/reduceadd_valid/test_dataflow_reduceadd_valid.py @@ -556,6 +556,7 @@ """ + def test(): veriloggen.reset() test_module = dataflow_reduceadd_valid.mkTest() diff --git a/tests_obsolete/extension/dataflow_/reduceadd_valid_enable/test_dataflow_reduceadd_valid_enable.py b/tests_obsolete/extension/dataflow_/reduceadd_valid_enable/test_dataflow_reduceadd_valid_enable.py index 46afa650..fb9907aa 100644 --- a/tests_obsolete/extension/dataflow_/reduceadd_valid_enable/test_dataflow_reduceadd_valid_enable.py +++ b/tests_obsolete/extension/dataflow_/reduceadd_valid_enable/test_dataflow_reduceadd_valid_enable.py @@ -892,6 +892,7 @@ """ + def test(): veriloggen.reset() test_module = dataflow_reduceadd_valid_enable.mkTest() diff --git a/tests_obsolete/extension/dataflow_/reducecustom/test_dataflow_reducecustom.py b/tests_obsolete/extension/dataflow_/reducecustom/test_dataflow_reducecustom.py index f5e4cb82..cfc1aa77 100644 --- a/tests_obsolete/extension/dataflow_/reducecustom/test_dataflow_reducecustom.py +++ b/tests_obsolete/extension/dataflow_/reducecustom/test_dataflow_reducecustom.py @@ -321,6 +321,8 @@ endmodule """ + + def test(): veriloggen.reset() test_module = dataflow_reducecustom.mkTest() diff --git a/tests_obsolete/extension/dataflow_/reducemul/test_dataflow_reducemul.py b/tests_obsolete/extension/dataflow_/reducemul/test_dataflow_reducemul.py index 15b95923..3660f218 100644 --- a/tests_obsolete/extension/dataflow_/reducemul/test_dataflow_reducemul.py +++ b/tests_obsolete/extension/dataflow_/reducemul/test_dataflow_reducemul.py @@ -322,6 +322,7 @@ """ + def test(): veriloggen.reset() test_module = dataflow_reducemul.mkTest() diff --git a/tests_obsolete/extension/dataflow_/sign/test_dataflow_sign.py b/tests_obsolete/extension/dataflow_/sign/test_dataflow_sign.py index 6d12e94b..19bb5fed 100644 --- a/tests_obsolete/extension/dataflow_/sign/test_dataflow_sign.py +++ b/tests_obsolete/extension/dataflow_/sign/test_dataflow_sign.py @@ -584,6 +584,7 @@ """ + def test(): veriloggen.reset() test_module = dataflow_sign.mkTest() diff --git a/tests_obsolete/extension/dataflow_/two_outputs_addsub/test_dataflow_two_outputs_addsub.py b/tests_obsolete/extension/dataflow_/two_outputs_addsub/test_dataflow_two_outputs_addsub.py index b734bcb6..e192f56e 100644 --- a/tests_obsolete/extension/dataflow_/two_outputs_addsub/test_dataflow_two_outputs_addsub.py +++ b/tests_obsolete/extension/dataflow_/two_outputs_addsub/test_dataflow_two_outputs_addsub.py @@ -668,6 +668,8 @@ endmodule """ + + def test(): veriloggen.reset() test_module = dataflow_two_outputs_addsub.mkTest() diff --git a/tests_obsolete/extension/dataflow_/two_outputs_mul/test_dataflow_two_outputs_mul.py b/tests_obsolete/extension/dataflow_/two_outputs_mul/test_dataflow_two_outputs_mul.py index 620082c1..14d39986 100644 --- a/tests_obsolete/extension/dataflow_/two_outputs_mul/test_dataflow_two_outputs_mul.py +++ b/tests_obsolete/extension/dataflow_/two_outputs_mul/test_dataflow_two_outputs_mul.py @@ -927,6 +927,7 @@ """ + def test(): veriloggen.reset() test_module = dataflow_two_outputs_mul.mkTest() diff --git a/tests_obsolete/extension/dataflow_/unbalanced_outputs/test_dataflow_unbalanced_outputs.py b/tests_obsolete/extension/dataflow_/unbalanced_outputs/test_dataflow_unbalanced_outputs.py index 37a16786..10fd4207 100644 --- a/tests_obsolete/extension/dataflow_/unbalanced_outputs/test_dataflow_unbalanced_outputs.py +++ b/tests_obsolete/extension/dataflow_/unbalanced_outputs/test_dataflow_unbalanced_outputs.py @@ -699,6 +699,7 @@ """ + def test(): veriloggen.reset() test_module = dataflow_unbalanced_outputs.mkTest() diff --git a/tests_obsolete/extension/pipeline_/acc_add/pipeline_acc_add.py b/tests_obsolete/extension/pipeline_/acc_add/pipeline_acc_add.py index 4f12d9ac..2975c813 100644 --- a/tests_obsolete/extension/pipeline_/acc_add/pipeline_acc_add.py +++ b/tests_obsolete/extension/pipeline_/acc_add/pipeline_acc_add.py @@ -4,10 +4,12 @@ import os # the next line can be removed after installation -sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) +sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname( + os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) from veriloggen import * + def mkLed(): m = Module('blinkled') clk = m.Input('CLK') @@ -15,28 +17,29 @@ def mkLed(): x = m.Input('x', 32) y = m.Output('y', 32) prst = m.Input('prst') - + df = Pipeline(m, 'df', clk, rst) - + px = df.input(x) psum = df.acc_add(px, initval=0, resetcond=prst) psum.output(y) - + df.make_always() try: df.draw_graph() except: print('Dataflow graph could not be generated.', file=sys.stderr) - + return m + def mkTest(numports=8): m = Module('test') # target instance led = mkLed() - + # copy paras and ports params = m.copy_params(led) ports = m.copy_sim_ports(led) @@ -46,25 +49,25 @@ def mkTest(numports=8): x = ports['x'] y = ports['y'] prst = ports['prst'] - + uut = m.Instance(led, 'uut', params=m.connect_params(led), ports=m.connect_ports(led)) reset_done = m.Reg('reset_done', initval=0) - + reset_stmt = [] - reset_stmt.append( reset_done(0) ) - reset_stmt.append( prst(0) ) - reset_stmt.append( x(0) ) - + reset_stmt.append(reset_done(0)) + reset_stmt.append(prst(0)) + reset_stmt.append(x(0)) + vcd_name = os.path.splitext(os.path.basename(__file__))[0] + '.vcd' simulation.setup_waveform(m, uut, dumpfile=vcd_name) simulation.setup_clock(m, clk, hperiod=5) init = simulation.setup_reset(m, rst, reset_stmt, period=100) nclk = simulation.next_clock - + init.add( Delay(1000), reset_done(1), @@ -79,15 +82,14 @@ def mkTest(numports=8): xfsm.goto_next(cond=reset_done) xfsm.add(x.inc()) xfsm.add(x_count.inc()) - xfsm.goto_next(cond=x_count==10) + xfsm.goto_next(cond=x_count == 10) xfsm.add(x(0)) for i in range(5): xfsm.goto_next() xfsm.add(Systask('finish')) - + xfsm.make_always() - - + m.Always(Posedge(clk))( If(reset_done)( Systask('display', 'x=%d', x), @@ -96,7 +98,8 @@ def mkTest(numports=8): ) return m - + + if __name__ == '__main__': test = mkTest() verilog = test.to_verilog('tmp.v') @@ -104,10 +107,10 @@ def mkTest(numports=8): # run simulator (Icarus Verilog) sim = simulation.Simulator(test) - rslt = sim.run() # display=False + rslt = sim.run() # display=False #rslt = sim.run(display=True) print(rslt) # launch waveform viewer (GTKwave) - #sim.view_waveform() # background=False - #sim.view_waveform(background=True) + # sim.view_waveform() # background=False + # sim.view_waveform(background=True) diff --git a/tests_obsolete/extension/pipeline_/acc_add/test_pipeline_acc_add.py b/tests_obsolete/extension/pipeline_/acc_add/test_pipeline_acc_add.py index 2ba03046..8154ecba 100644 --- a/tests_obsolete/extension/pipeline_/acc_add/test_pipeline_acc_add.py +++ b/tests_obsolete/extension/pipeline_/acc_add/test_pipeline_acc_add.py @@ -142,6 +142,7 @@ endmodule """ + def test(): veriloggen.reset() test_module = pipeline_acc_add.mkTest() diff --git a/tests_obsolete/extension/pipeline_/acc_add_valid/pipeline_acc_add_valid.py b/tests_obsolete/extension/pipeline_/acc_add_valid/pipeline_acc_add_valid.py index 558d381c..24e615eb 100644 --- a/tests_obsolete/extension/pipeline_/acc_add_valid/pipeline_acc_add_valid.py +++ b/tests_obsolete/extension/pipeline_/acc_add_valid/pipeline_acc_add_valid.py @@ -4,10 +4,12 @@ import os # the next line can be removed after installation -sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) +sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname( + os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) from veriloggen import * + def mkLed(): m = Module('blinkled') clk = m.Input('CLK') @@ -17,13 +19,13 @@ def mkLed(): y = m.Output('y', 32) vy = m.Output('vy') prst = m.Input('prst') - + df = Pipeline(m, 'df', clk, rst) px = df.input(x, valid=vx) psum = df.acc_add(px, initval=0, resetcond=prst) psum.output(y, valid=vy) - + df.make_always() try: @@ -33,12 +35,13 @@ def mkLed(): return m + def mkTest(numports=8): m = Module('test') # target instance led = mkLed() - + # copy paras and ports params = m.copy_params(led) ports = m.copy_sim_ports(led) @@ -50,26 +53,26 @@ def mkTest(numports=8): y = ports['y'] vy = ports['vy'] prst = ports['prst'] - + uut = m.Instance(led, 'uut', params=m.connect_params(led), ports=m.connect_ports(led)) reset_done = m.Reg('reset_done', initval=0) - + reset_stmt = [] - reset_stmt.append( reset_done(0) ) - reset_stmt.append( prst(0) ) - reset_stmt.append( x(0) ) - reset_stmt.append( vx(0) ) - + reset_stmt.append(reset_done(0)) + reset_stmt.append(prst(0)) + reset_stmt.append(x(0)) + reset_stmt.append(vx(0)) + vcd_name = os.path.splitext(os.path.basename(__file__))[0] + '.vcd' simulation.setup_waveform(m, uut, dumpfile=vcd_name) simulation.setup_clock(m, clk, hperiod=5) init = simulation.setup_reset(m, rst, reset_stmt, period=100) nclk = simulation.next_clock - + init.add( Delay(1000), reset_done(1), @@ -89,17 +92,17 @@ def mkTest(numports=8): xfsm.goto_next() xfsm.add(x.inc()) xfsm.add(x_count.inc()) - xfsm.goto_next(cond=x_count==5) + xfsm.goto_next(cond=x_count == 5) xfsm.add(vx(0)) for _ in range(10): xfsm.goto_next() xfsm.add(vx(1)) xfsm.add(x.inc()) xfsm.add(x_count.inc()) - xfsm.goto_next(cond=x_count==10) + xfsm.goto_next(cond=x_count == 10) xfsm.add(vx(0)) xfsm.make_always() - + m.Always(Posedge(clk))( If(reset_done)( If(vx)( @@ -112,7 +115,8 @@ def mkTest(numports=8): ) return m - + + if __name__ == '__main__': test = mkTest() verilog = test.to_verilog('tmp.v') @@ -120,10 +124,10 @@ def mkTest(numports=8): # run simulator (Icarus Verilog) sim = simulation.Simulator(test) - rslt = sim.run() # display=False + rslt = sim.run() # display=False #rslt = sim.run(display=True) print(rslt) # launch waveform viewer (GTKwave) - #sim.view_waveform() # background=False - #sim.view_waveform(background=True) + # sim.view_waveform() # background=False + # sim.view_waveform(background=True) diff --git a/tests_obsolete/extension/pipeline_/acc_add_valid/test_pipeline_acc_add_valid.py b/tests_obsolete/extension/pipeline_/acc_add_valid/test_pipeline_acc_add_valid.py index f861148f..212fae02 100644 --- a/tests_obsolete/extension/pipeline_/acc_add_valid/test_pipeline_acc_add_valid.py +++ b/tests_obsolete/extension/pipeline_/acc_add_valid/test_pipeline_acc_add_valid.py @@ -237,6 +237,7 @@ endmodule """ + def test(): veriloggen.reset() test_module = pipeline_acc_add_valid.mkTest() diff --git a/tests_obsolete/extension/pipeline_/acc_add_validready/pipeline_acc_add_validready.py b/tests_obsolete/extension/pipeline_/acc_add_validready/pipeline_acc_add_validready.py index fbe5da83..fe87161b 100644 --- a/tests_obsolete/extension/pipeline_/acc_add_validready/pipeline_acc_add_validready.py +++ b/tests_obsolete/extension/pipeline_/acc_add_validready/pipeline_acc_add_validready.py @@ -4,10 +4,12 @@ import os # the next line can be removed after installation -sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) +sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname( + os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) from veriloggen import * + def mkLed(): m = Module('blinkled') clk = m.Input('CLK') @@ -19,13 +21,13 @@ def mkLed(): vy = m.Output('vy') ry = m.Input('ry') prst = m.Input('prst') - + df = Pipeline(m, 'df', clk, rst) px = df.input(x, valid=vx, ready=rx) psum = df.acc_add(px, initval=0, resetcond=prst) psum.output(y, valid=vy, ready=ry) - + df.make_always() try: @@ -35,12 +37,13 @@ def mkLed(): return m + def mkTest(numports=8): m = Module('test') # target instance led = mkLed() - + # copy paras and ports params = m.copy_params(led) ports = m.copy_sim_ports(led) @@ -54,27 +57,27 @@ def mkTest(numports=8): vy = ports['vy'] ry = ports['ry'] prst = ports['prst'] - + uut = m.Instance(led, 'uut', params=m.connect_params(led), ports=m.connect_ports(led)) reset_done = m.Reg('reset_done', initval=0) - + reset_stmt = [] - reset_stmt.append( reset_done(0) ) - reset_stmt.append( prst(0) ) - reset_stmt.append( x(0) ) - reset_stmt.append( vx(0) ) - reset_stmt.append( ry(0) ) - + reset_stmt.append(reset_done(0)) + reset_stmt.append(prst(0)) + reset_stmt.append(x(0)) + reset_stmt.append(vx(0)) + reset_stmt.append(ry(0)) + vcd_name = os.path.splitext(os.path.basename(__file__))[0] + '.vcd' simulation.setup_waveform(m, uut, dumpfile=vcd_name) simulation.setup_clock(m, clk, hperiod=5) init = simulation.setup_reset(m, rst, reset_stmt, period=100) nclk = simulation.next_clock - + init.add( Delay(1000), reset_done(1), @@ -85,7 +88,6 @@ def mkTest(numports=8): x_count = m.TmpReg(32, initval=0) y_count = m.TmpReg(32, initval=0) - xfsm = FSM(m, 'xfsm', clk, rst) xfsm.add(vx(0)) @@ -96,23 +98,22 @@ def mkTest(numports=8): xfsm.goto_next() xfsm.add(x.inc(), cond=rx) xfsm.add(x_count.inc(), cond=rx) - xfsm.goto_next(cond=AndList(x_count==5, rx)) + xfsm.goto_next(cond=AndList(x_count == 5, rx)) xfsm.add(vx(0)) for _ in range(10): xfsm.goto_next() xfsm.add(vx(1)) xfsm.add(x.inc(), cond=rx) xfsm.add(x_count.inc(), cond=rx) - xfsm.goto_next(cond=AndList(x_count==10, rx)) + xfsm.goto_next(cond=AndList(x_count == 10, rx)) xfsm.add(vx(0)) xfsm.make_always() - - + yfsm = FSM(m, 'yfsm', clk, rst) yfsm.add(ry(0)) yfsm.goto_next(cond=reset_done) yfsm.goto_next() - yinit= yfsm.current + yinit = yfsm.current yfsm.add(ry(1), cond=vy) yfsm.goto_next(cond=vy) for i in range(10): @@ -121,7 +122,6 @@ def mkTest(numports=8): yfsm.goto(yinit) yfsm.make_always() - m.Always(Posedge(clk))( If(reset_done)( If(AndList(vx, rx))( @@ -134,7 +134,8 @@ def mkTest(numports=8): ) return m - + + if __name__ == '__main__': test = mkTest() verilog = test.to_verilog('tmp.v') @@ -142,10 +143,10 @@ def mkTest(numports=8): # run simulator (Icarus Verilog) sim = simulation.Simulator(test) - rslt = sim.run() # display=False + rslt = sim.run() # display=False #rslt = sim.run(display=True) print(rslt) # launch waveform viewer (GTKwave) - #sim.view_waveform() # background=False - #sim.view_waveform(background=True) + # sim.view_waveform() # background=False + # sim.view_waveform(background=True) diff --git a/tests_obsolete/extension/pipeline_/acc_add_validready/test_pipeline_acc_add_validready.py b/tests_obsolete/extension/pipeline_/acc_add_validready/test_pipeline_acc_add_validready.py index fa8ea181..efc1dafe 100644 --- a/tests_obsolete/extension/pipeline_/acc_add_validready/test_pipeline_acc_add_validready.py +++ b/tests_obsolete/extension/pipeline_/acc_add_validready/test_pipeline_acc_add_validready.py @@ -348,6 +348,7 @@ endmodule """ + def test(): veriloggen.reset() test_module = pipeline_acc_add_validready.mkTest() diff --git a/tests_obsolete/extension/pipeline_/acc_custom/pipeline_acc_custom.py b/tests_obsolete/extension/pipeline_/acc_custom/pipeline_acc_custom.py index f79ddcec..0c5f53f3 100644 --- a/tests_obsolete/extension/pipeline_/acc_custom/pipeline_acc_custom.py +++ b/tests_obsolete/extension/pipeline_/acc_custom/pipeline_acc_custom.py @@ -4,10 +4,12 @@ import os # the next line can be removed after installation -sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) +sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname( + os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) from veriloggen import * + def mkLed(): m = Module('blinkled') clk = m.Input('CLK') @@ -19,7 +21,7 @@ def mkLed(): vy = m.Output('vy') ry = m.Input('ry') prst = m.Input('prst') - + df = Pipeline(m, 'df', clk, rst) px = df.input(x, valid=vx, ready=rx) @@ -27,12 +29,12 @@ def mkLed(): # custom operator: should return vtypes._Numeric object def op_max(left, right): return Cond(left > right, left, right) - + psum = df.acc_custom(px, op_max, initval=0, resetcond=prst, label='custom') psum.output(y, valid=vy, ready=ry) - + df.make_always() - + try: df.draw_graph() except: @@ -40,12 +42,13 @@ def op_max(left, right): return m + def mkTest(numports=8): m = Module('test') # target instance led = mkLed() - + # copy paras and ports params = m.copy_params(led) ports = m.copy_sim_ports(led) @@ -59,27 +62,27 @@ def mkTest(numports=8): vy = ports['vy'] ry = ports['ry'] prst = ports['prst'] - + uut = m.Instance(led, 'uut', params=m.connect_params(led), ports=m.connect_ports(led)) reset_done = m.Reg('reset_done', initval=0) - + reset_stmt = [] - reset_stmt.append( reset_done(0) ) - reset_stmt.append( prst(0) ) - reset_stmt.append( x(0) ) - reset_stmt.append( vx(0) ) - reset_stmt.append( ry(0) ) - + reset_stmt.append(reset_done(0)) + reset_stmt.append(prst(0)) + reset_stmt.append(x(0)) + reset_stmt.append(vx(0)) + reset_stmt.append(ry(0)) + vcd_name = os.path.splitext(os.path.basename(__file__))[0] + '.vcd' simulation.setup_waveform(m, uut, dumpfile=vcd_name) simulation.setup_clock(m, clk, hperiod=5) init = simulation.setup_reset(m, rst, reset_stmt, period=100) nclk = simulation.next_clock - + init.add( Delay(1000), reset_done(1), @@ -90,56 +93,54 @@ def mkTest(numports=8): x_count = m.TmpReg(32, initval=0) y_count = m.TmpReg(32, initval=0) - xfsm = FSM(m, 'xfsm', clk, rst) xfsm.add(vx(0)) xfsm.goto_next(cond=reset_done) for _ in range(10): xfsm.goto_next() - + xfsm.add(vx(1)) xfsm.goto_next() xfsm.add(x.inc(), cond=rx) xfsm.add(x_count.inc(), cond=rx) - xfsm.goto_next(cond=AndList(x_count==5, rx)) - + xfsm.goto_next(cond=AndList(x_count == 5, rx)) + xfsm.add(vx(0)) for _ in range(10): xfsm.goto_next() - + xfsm.add(vx(1)) xfsm.add(x.inc(), cond=rx) xfsm.add(x_count.inc(), cond=rx) - xfsm.goto_next(cond=AndList(x_count==10, rx)) + xfsm.goto_next(cond=AndList(x_count == 10, rx)) xfsm.add(vx(0)) for _ in range(10): xfsm.goto_next() - + xfsm.add(vx(1)) xfsm.add(x.dec(), cond=rx) xfsm.add(x_count.inc(), cond=rx) - xfsm.goto_next(cond=AndList(x_count==15, rx)) - + xfsm.goto_next(cond=AndList(x_count == 15, rx)) + xfsm.add(vx(0)) for _ in range(10): xfsm.goto_next() - + xfsm.add(vx(1)) xfsm.add(x.dec(), cond=rx) xfsm.add(x_count.inc(), cond=rx) - xfsm.goto_next(cond=AndList(x_count==22, rx)) - + xfsm.goto_next(cond=AndList(x_count == 22, rx)) + xfsm.add(vx(0)) xfsm.make_always() - - + yfsm = FSM(m, 'yfsm', clk, rst) yfsm.add(ry(0)) yfsm.goto_next(cond=reset_done) yfsm.goto_next() - yinit= yfsm.current + yinit = yfsm.current yfsm.add(ry(1), cond=vy) yfsm.goto_next(cond=vy) for i in range(10): @@ -148,7 +149,6 @@ def mkTest(numports=8): yfsm.goto(yinit) yfsm.make_always() - m.Always(Posedge(clk))( If(reset_done)( If(AndList(vx, rx))( @@ -161,7 +161,8 @@ def mkTest(numports=8): ) return m - + + if __name__ == '__main__': test = mkTest() verilog = test.to_verilog('tmp.v') @@ -169,10 +170,10 @@ def mkTest(numports=8): # run simulator (Icarus Verilog) sim = simulation.Simulator(test) - rslt = sim.run() # display=False + rslt = sim.run() # display=False #rslt = sim.run(display=True) print(rslt) # launch waveform viewer (GTKwave) - #sim.view_waveform() # background=False - #sim.view_waveform(background=True) + # sim.view_waveform() # background=False + # sim.view_waveform(background=True) diff --git a/tests_obsolete/extension/pipeline_/acc_custom/test_pipeline_acc_custom.py b/tests_obsolete/extension/pipeline_/acc_custom/test_pipeline_acc_custom.py index e93a15ae..3d4bc2f8 100644 --- a/tests_obsolete/extension/pipeline_/acc_custom/test_pipeline_acc_custom.py +++ b/tests_obsolete/extension/pipeline_/acc_custom/test_pipeline_acc_custom.py @@ -458,6 +458,7 @@ endmodule """ + def test(): veriloggen.reset() test_module = pipeline_acc_custom.mkTest() diff --git a/tests_obsolete/extension/pipeline_/draw_graph/pipeline_draw_graph.py b/tests_obsolete/extension/pipeline_/draw_graph/pipeline_draw_graph.py index 133ed9ea..6c21ec6c 100644 --- a/tests_obsolete/extension/pipeline_/draw_graph/pipeline_draw_graph.py +++ b/tests_obsolete/extension/pipeline_/draw_graph/pipeline_draw_graph.py @@ -4,19 +4,21 @@ import os # the next line can be removed after installation -sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) +sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname( + os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) from veriloggen import * + def mkLed(): m = Module('blinkled') clk = m.Input('CLK') rst = m.Input('RST') - + x = m.Input('x', 32) vx = m.Input('vx') rx = m.Output('rx') - + y = m.Input('y', 32) vy = m.Input('vy') ry = m.Output('ry') @@ -24,36 +26,37 @@ def mkLed(): z = m.Output('z', 32) vz = m.Output('vz') rz = m.Input('rz') - + df = Pipeline(m, 'df', clk, rst) - + px = df.input(x, valid=vx, ready=rx) py = df.input(y, valid=vy, ready=ry) pz = df(px + py) pz.output(z, valid=vz, ready=rz) - + df.make_always() try: df.draw_graph() except: print('Dataflow graph could not be generated.', file=sys.stderr) - + return m + def mkTest(numports=8): m = Module('test') # target instance led = mkLed() - + # copy paras and ports params = m.copy_params(led) ports = m.copy_sim_ports(led) clk = ports['CLK'] rst = ports['RST'] - + x = ports['x'] vx = ports['vx'] rx = ports['rx'] @@ -63,28 +66,28 @@ def mkTest(numports=8): z = ports['z'] vz = ports['vz'] rz = ports['rz'] - + uut = m.Instance(led, 'uut', params=m.connect_params(led), ports=m.connect_ports(led)) reset_done = m.Reg('reset_done', initval=0) - + reset_stmt = [] - reset_stmt.append( reset_done(0) ) - reset_stmt.append( x(0) ) - reset_stmt.append( y(0) ) - reset_stmt.append( vx(0) ) - reset_stmt.append( vy(0) ) - reset_stmt.append( rz(0) ) - + reset_stmt.append(reset_done(0)) + reset_stmt.append(x(0)) + reset_stmt.append(y(0)) + reset_stmt.append(vx(0)) + reset_stmt.append(vy(0)) + reset_stmt.append(rz(0)) + vcd_name = os.path.splitext(os.path.basename(__file__))[0] + '.vcd' simulation.setup_waveform(m, uut, dumpfile=vcd_name) simulation.setup_clock(m, clk, hperiod=5) init = simulation.setup_reset(m, rst, reset_stmt, period=100) nclk = simulation.next_clock - + init.add( Delay(1000), reset_done(1), @@ -93,39 +96,35 @@ def mkTest(numports=8): Systask('finish'), ) - x_count = m.TmpReg(32, initval=0) y_count = m.TmpReg(32, initval=0) z_count = m.TmpReg(32, initval=0) - xfsm = FSM(m, 'xfsm', clk, rst) xfsm.add(vx(0)) xfsm.goto_next(cond=reset_done) xfsm.add(vx(1)) xfsm.add(x.inc(), cond=rx) xfsm.add(x_count.inc(), cond=rx) - xfsm.goto_next(cond=AndList(x_count==10, rx)) + xfsm.goto_next(cond=AndList(x_count == 10, rx)) xfsm.add(vx(0)) xfsm.make_always() - - + yfsm = FSM(m, 'yfsm', clk, rst) yfsm.add(vy(0)) yfsm.goto_next(cond=reset_done) yfsm.add(vy(1)) yfsm.add(y.add(2), cond=ry) yfsm.add(y_count.inc(), cond=ry) - yfsm.goto_next(cond=AndList(y_count==10, ry)) + yfsm.goto_next(cond=AndList(y_count == 10, ry)) yfsm.add(vy(0)) yfsm.make_always() - zfsm = FSM(m, 'zfsm', clk, rst) zfsm.add(rz(0)) zfsm.goto_next(cond=reset_done) zfsm.goto_next() - zinit= zfsm.current + zinit = zfsm.current zfsm.add(rz(1), cond=vz) zfsm.goto_next(cond=vz) for i in range(10): @@ -134,7 +133,6 @@ def mkTest(numports=8): zfsm.goto(zinit) zfsm.make_always() - m.Always(Posedge(clk))( If(reset_done)( If(AndList(vx, rx))( @@ -148,9 +146,10 @@ def mkTest(numports=8): ) ) ) - + return m - + + if __name__ == '__main__': test = mkTest() verilog = test.to_verilog('tmp.v') @@ -158,10 +157,10 @@ def mkTest(numports=8): # run simulator (Icarus Verilog) sim = simulation.Simulator(test) - rslt = sim.run() # display=False + rslt = sim.run() # display=False #rslt = sim.run(display=True) print(rslt) # launch waveform viewer (GTKwave) - #sim.view_waveform() # background=False - #sim.view_waveform(background=True) + # sim.view_waveform() # background=False + # sim.view_waveform(background=True) diff --git a/tests_obsolete/extension/pipeline_/draw_graph/test_pipeline_draw_graph.py b/tests_obsolete/extension/pipeline_/draw_graph/test_pipeline_draw_graph.py index 04d46b75..8f441300 100644 --- a/tests_obsolete/extension/pipeline_/draw_graph/test_pipeline_draw_graph.py +++ b/tests_obsolete/extension/pipeline_/draw_graph/test_pipeline_draw_graph.py @@ -291,6 +291,7 @@ endmodule """ + def test(): veriloggen.reset() test_module = pipeline_draw_graph.mkTest() diff --git a/tests_obsolete/extension/pipeline_/inc/pipeline_inc.py b/tests_obsolete/extension/pipeline_/inc/pipeline_inc.py index a52c5998..87d56efb 100644 --- a/tests_obsolete/extension/pipeline_/inc/pipeline_inc.py +++ b/tests_obsolete/extension/pipeline_/inc/pipeline_inc.py @@ -4,10 +4,12 @@ import os # the next line can be removed after installation -sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) +sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname( + os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) from veriloggen import * + def mkLed(): m = Module('blinkled') clk = m.Input('CLK') @@ -18,13 +20,13 @@ def mkLed(): y = m.Output('y', 32) vy = m.Output('vy') ry = m.Input('ry') - + df = Pipeline(m, 'df', clk, rst) - + px = df.input(x, valid=vx, ready=rx) py = df(px + 1) py.output(y, valid=vy, ready=ry) - + df.make_always() try: @@ -34,12 +36,13 @@ def mkLed(): return m + def mkTest(numports=8): m = Module('test') # target instance led = mkLed() - + # copy paras and ports params = m.copy_params(led) ports = m.copy_sim_ports(led) @@ -52,26 +55,26 @@ def mkTest(numports=8): y = ports['y'] vy = ports['vy'] ry = ports['ry'] - + uut = m.Instance(led, 'uut', params=m.connect_params(led), ports=m.connect_ports(led)) reset_done = m.Reg('reset_done', initval=0) - + reset_stmt = [] - reset_stmt.append( reset_done(0) ) - reset_stmt.append( x(0) ) - reset_stmt.append( vx(0) ) - reset_stmt.append( ry(0) ) - + reset_stmt.append(reset_done(0)) + reset_stmt.append(x(0)) + reset_stmt.append(vx(0)) + reset_stmt.append(ry(0)) + vcd_name = os.path.splitext(os.path.basename(__file__))[0] + '.vcd' simulation.setup_waveform(m, uut, dumpfile=vcd_name) simulation.setup_clock(m, clk, hperiod=5) init = simulation.setup_reset(m, rst, reset_stmt, period=100) nclk = simulation.next_clock - + init.add( Delay(1000), reset_done(1), @@ -83,7 +86,6 @@ def mkTest(numports=8): x_count = m.TmpReg(32, initval=0) y_count = m.TmpReg(32, initval=0) - xfsm = FSM(m, 'xfsm', clk, rst) xfsm.add(vx(0)) xfsm.goto_next(cond=reset_done) @@ -93,23 +95,22 @@ def mkTest(numports=8): xfsm.goto_next() xfsm.add(x.inc(), cond=rx) xfsm.add(x_count.inc(), cond=rx) - xfsm.goto_next(cond=AndList(x_count==5, rx)) + xfsm.goto_next(cond=AndList(x_count == 5, rx)) xfsm.add(vx(0)) for _ in range(10): xfsm.goto_next() xfsm.add(vx(1)) xfsm.add(x.inc(), cond=rx) xfsm.add(x_count.inc(), cond=rx) - xfsm.goto_next(cond=AndList(x_count==10, rx)) + xfsm.goto_next(cond=AndList(x_count == 10, rx)) xfsm.add(vx(0)) xfsm.make_always() - - + yfsm = FSM(m, 'yfsm', clk, rst) yfsm.add(ry(0)) yfsm.goto_next(cond=reset_done) yfsm.goto_next() - yinit= yfsm.current + yinit = yfsm.current yfsm.add(ry(1), cond=vy) yfsm.goto_next(cond=vy) for i in range(10): @@ -118,7 +119,6 @@ def mkTest(numports=8): yfsm.goto(yinit) yfsm.make_always() - m.Always(Posedge(clk))( If(reset_done)( If(AndList(vx, rx))( @@ -129,9 +129,10 @@ def mkTest(numports=8): ) ) ) - + return m - + + if __name__ == '__main__': test = mkTest() verilog = test.to_verilog('tmp.v') @@ -139,10 +140,10 @@ def mkTest(numports=8): # run simulator (Icarus Verilog) sim = simulation.Simulator(test) - rslt = sim.run() # display=False + rslt = sim.run() # display=False #rslt = sim.run(display=True) print(rslt) # launch waveform viewer (GTKwave) - #sim.view_waveform() # background=False - #sim.view_waveform(background=True) + # sim.view_waveform() # background=False + # sim.view_waveform(background=True) diff --git a/tests_obsolete/extension/pipeline_/inc/test_pipeline_inc.py b/tests_obsolete/extension/pipeline_/inc/test_pipeline_inc.py index f50f309f..ef551e04 100644 --- a/tests_obsolete/extension/pipeline_/inc/test_pipeline_inc.py +++ b/tests_obsolete/extension/pipeline_/inc/test_pipeline_inc.py @@ -340,6 +340,7 @@ endmodule """ + def test(): veriloggen.reset() test_module = pipeline_inc.mkTest() diff --git a/tests_obsolete/extension/pipeline_/multi_input/pipeline_multi_input.py b/tests_obsolete/extension/pipeline_/multi_input/pipeline_multi_input.py index e32f11e9..f14ac373 100644 --- a/tests_obsolete/extension/pipeline_/multi_input/pipeline_multi_input.py +++ b/tests_obsolete/extension/pipeline_/multi_input/pipeline_multi_input.py @@ -4,19 +4,21 @@ import os # the next line can be removed after installation -sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) +sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname( + os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) from veriloggen import * + def mkLed(): m = Module('blinkled') clk = m.Input('CLK') rst = m.Input('RST') - + x = m.Input('x', 32) vx = m.Input('vx') rx = m.Output('rx') - + y = m.Input('y', 32) vy = m.Input('vy') ry = m.Output('ry') @@ -24,14 +26,14 @@ def mkLed(): z = m.Output('z', 32) vz = m.Output('vz') rz = m.Input('rz') - + df = Pipeline(m, 'df', clk, rst) - + px = df.input(x, valid=vx, ready=rx) py = df.input(y, valid=vy, ready=ry) pz = df(px + py) pz.output(z, valid=vz, ready=rz) - + df.make_always() try: @@ -41,19 +43,20 @@ def mkLed(): return m + def mkTest(numports=8): m = Module('test') # target instance led = mkLed() - + # copy paras and ports params = m.copy_params(led) ports = m.copy_sim_ports(led) clk = ports['CLK'] rst = ports['RST'] - + x = ports['x'] vx = ports['vx'] rx = ports['rx'] @@ -63,28 +66,28 @@ def mkTest(numports=8): z = ports['z'] vz = ports['vz'] rz = ports['rz'] - + uut = m.Instance(led, 'uut', params=m.connect_params(led), ports=m.connect_ports(led)) reset_done = m.Reg('reset_done', initval=0) - + reset_stmt = [] - reset_stmt.append( reset_done(0) ) - reset_stmt.append( x(0) ) - reset_stmt.append( y(0) ) - reset_stmt.append( vx(0) ) - reset_stmt.append( vy(0) ) - reset_stmt.append( rz(0) ) - + reset_stmt.append(reset_done(0)) + reset_stmt.append(x(0)) + reset_stmt.append(y(0)) + reset_stmt.append(vx(0)) + reset_stmt.append(vy(0)) + reset_stmt.append(rz(0)) + vcd_name = os.path.splitext(os.path.basename(__file__))[0] + '.vcd' simulation.setup_waveform(m, uut, dumpfile=vcd_name) simulation.setup_clock(m, clk, hperiod=5) init = simulation.setup_reset(m, rst, reset_stmt, period=100) nclk = simulation.next_clock - + init.add( Delay(1000), reset_done(1), @@ -93,42 +96,38 @@ def mkTest(numports=8): Systask('finish'), ) - x_count = m.TmpReg(32, initval=0) y_count = m.TmpReg(32, initval=0) z_count = m.TmpReg(32, initval=0) - xfsm = FSM(m, 'xfsm', clk, rst) xfsm.add(vx(0)) xfsm.goto_next(cond=reset_done) xfsm.add(vx(1)) xfsm.add(x.inc(), cond=rx) xfsm.add(x_count.inc(), cond=rx) - xfsm.goto_next(cond=AndList(x_count==10, rx)) + xfsm.goto_next(cond=AndList(x_count == 10, rx)) xfsm.add(vx(0)) xfsm.make_always() - - + yfsm = FSM(m, 'yfsm', clk, rst) yfsm.add(vy(0)) yfsm.goto_next(cond=reset_done) for _ in range(10): - yfsm.goto_next() # delay + yfsm.goto_next() # delay yfsm.add(vy(1)) yfsm.goto_next() yfsm.add(y.add(2), cond=ry) yfsm.add(y_count.inc(), cond=ry) - yfsm.goto_next(cond=AndList(y_count==10, ry)) + yfsm.goto_next(cond=AndList(y_count == 10, ry)) yfsm.add(vy(0)) yfsm.make_always() - zfsm = FSM(m, 'zfsm', clk, rst) zfsm.add(rz(0)) zfsm.goto_next(cond=reset_done) zfsm.goto_next() - zinit= zfsm.current + zinit = zfsm.current zfsm.add(rz(1), cond=vz) zfsm.goto_next(cond=vz) for i in range(10): @@ -137,7 +136,6 @@ def mkTest(numports=8): zfsm.goto(zinit) zfsm.make_always() - m.Always(Posedge(clk))( If(reset_done)( If(AndList(vx, rx))( @@ -151,9 +149,10 @@ def mkTest(numports=8): ) ) ) - + return m - + + if __name__ == '__main__': test = mkTest() verilog = test.to_verilog('tmp.v') @@ -161,10 +160,10 @@ def mkTest(numports=8): # run simulator (Icarus Verilog) sim = simulation.Simulator(test) - rslt = sim.run() # display=False + rslt = sim.run() # display=False #rslt = sim.run(display=True) print(rslt) # launch waveform viewer (GTKwave) - #sim.view_waveform() # background=False - #sim.view_waveform(background=True) + # sim.view_waveform() # background=False + # sim.view_waveform(background=True) diff --git a/tests_obsolete/extension/pipeline_/multi_input/test_pipeline_multi_input.py b/tests_obsolete/extension/pipeline_/multi_input/test_pipeline_multi_input.py index 9c72faeb..ba375014 100644 --- a/tests_obsolete/extension/pipeline_/multi_input/test_pipeline_multi_input.py +++ b/tests_obsolete/extension/pipeline_/multi_input/test_pipeline_multi_input.py @@ -337,6 +337,7 @@ endmodule """ + def test(): veriloggen.reset() test_module = pipeline_multi_input.mkTest() diff --git a/tests_obsolete/extension/pipeline_/multi_output/pipeline_multi_output.py b/tests_obsolete/extension/pipeline_/multi_output/pipeline_multi_output.py index 0ce78406..116e1586 100644 --- a/tests_obsolete/extension/pipeline_/multi_output/pipeline_multi_output.py +++ b/tests_obsolete/extension/pipeline_/multi_output/pipeline_multi_output.py @@ -4,19 +4,21 @@ import os # the next line can be removed after installation -sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) +sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname( + os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) from veriloggen import * + def mkLed(): m = Module('blinkled') clk = m.Input('CLK') rst = m.Input('RST') - + x = m.Input('x', 32) vx = m.Input('vx') rx = m.Output('rx') - + y = m.Input('y', 32) vy = m.Input('vy') ry = m.Output('ry') @@ -24,20 +26,20 @@ def mkLed(): z = m.Output('z', 32) vz = m.Output('vz') rz = m.Input('rz') - + a = m.Output('a', 32) va = m.Output('va') ra = m.Input('ra') - + df = Pipeline(m, 'df', clk, rst) - + px = df.input(x, valid=vx, ready=rx) py = df.input(y, valid=vy, ready=ry) pz = df(px + py) pa = df(py - px) pz.output(z, valid=vz, ready=rz) pa.output(a, valid=va, ready=ra) - + df.make_always() try: @@ -47,57 +49,58 @@ def mkLed(): return m + def mkTest(numports=8): m = Module('test') # target instance led = mkLed() - + # copy paras and ports params = m.copy_params(led) ports = m.copy_sim_ports(led) clk = ports['CLK'] rst = ports['RST'] - + x = ports['x'] vx = ports['vx'] rx = ports['rx'] - + y = ports['y'] vy = ports['vy'] ry = ports['ry'] - + z = ports['z'] vz = ports['vz'] rz = ports['rz'] - + a = ports['a'] va = ports['va'] ra = ports['ra'] - + uut = m.Instance(led, 'uut', params=m.connect_params(led), ports=m.connect_ports(led)) - + reset_done = m.Reg('reset_done', initval=0) reset_stmt = [] - reset_stmt.append( reset_done(0) ) - reset_stmt.append( x(0) ) - reset_stmt.append( y(0) ) - reset_stmt.append( vx(0) ) - reset_stmt.append( vy(0) ) - reset_stmt.append( rz(0) ) - reset_stmt.append( ra(0) ) - + reset_stmt.append(reset_done(0)) + reset_stmt.append(x(0)) + reset_stmt.append(y(0)) + reset_stmt.append(vx(0)) + reset_stmt.append(vy(0)) + reset_stmt.append(rz(0)) + reset_stmt.append(ra(0)) + vcd_name = os.path.splitext(os.path.basename(__file__))[0] + '.vcd' simulation.setup_waveform(m, uut, dumpfile=vcd_name) simulation.setup_clock(m, clk, hperiod=5) init = simulation.setup_reset(m, rst, reset_stmt, period=100) nclk = simulation.next_clock - + init.add( Delay(1000), reset_done(1), @@ -105,44 +108,40 @@ def mkTest(numports=8): Delay(10000), Systask('finish'), ) - - + x_count = m.TmpReg(32, initval=0) y_count = m.TmpReg(32, initval=0) z_count = m.TmpReg(32, initval=0) a_count = m.TmpReg(32, initval=0) - xfsm = FSM(m, 'xfsm', clk, rst) xfsm.add(vx(0)) xfsm.goto_next(cond=reset_done) xfsm.add(vx(1)) xfsm.add(x.inc(), cond=rx) xfsm.add(x_count.inc(), cond=rx) - xfsm.goto_next(cond=AndList(x_count==10, rx)) + xfsm.goto_next(cond=AndList(x_count == 10, rx)) xfsm.add(vx(0)) xfsm.make_always() - - + yfsm = FSM(m, 'yfsm', clk, rst) yfsm.add(vy(0)) yfsm.goto_next(cond=reset_done) for _ in range(10): - yfsm.goto_next() # delay + yfsm.goto_next() # delay yfsm.add(vy(1)) yfsm.goto_next() yfsm.add(y.add(2), cond=ry) yfsm.add(y_count.inc(), cond=ry) - yfsm.goto_next(cond=AndList(y_count==10, ry)) + yfsm.goto_next(cond=AndList(y_count == 10, ry)) yfsm.add(vy(0)) yfsm.make_always() - zfsm = FSM(m, 'zfsm', clk, rst) zfsm.add(rz(0)) zfsm.goto_next(cond=reset_done) zfsm.goto_next() - zinit= zfsm.current + zinit = zfsm.current zfsm.add(rz(1), cond=vz) zfsm.goto_next(cond=vz) for i in range(10): @@ -151,12 +150,11 @@ def mkTest(numports=8): zfsm.goto(zinit) zfsm.make_always() - afsm = FSM(m, 'afsm', clk, rst) afsm.add(ra(0)) afsm.goto_next(cond=reset_done) afsm.goto_next() - ainit= afsm.current + ainit = afsm.current afsm.add(ra(1), cond=va) afsm.goto_next(cond=va) for i in range(20): @@ -165,7 +163,6 @@ def mkTest(numports=8): afsm.goto(ainit) afsm.make_always() - m.Always(Posedge(clk))( If(reset_done)( If(AndList(vx, rx))( @@ -182,9 +179,10 @@ def mkTest(numports=8): ) ) ) - + return m - + + if __name__ == '__main__': test = mkTest() verilog = test.to_verilog('tmp.v') @@ -192,10 +190,10 @@ def mkTest(numports=8): # run simulator (Icarus Verilog) sim = simulation.Simulator(test) - rslt = sim.run() # display=False + rslt = sim.run() # display=False #rslt = sim.run(display=True) print(rslt) # launch waveform viewer (GTKwave) - #sim.view_waveform() # background=False - #sim.view_waveform(background=True) + # sim.view_waveform() # background=False + # sim.view_waveform(background=True) diff --git a/tests_obsolete/extension/pipeline_/multi_output/test_pipeline_multi_output.py b/tests_obsolete/extension/pipeline_/multi_output/test_pipeline_multi_output.py index 657f8132..82c98190 100644 --- a/tests_obsolete/extension/pipeline_/multi_output/test_pipeline_multi_output.py +++ b/tests_obsolete/extension/pipeline_/multi_output/test_pipeline_multi_output.py @@ -503,6 +503,7 @@ endmodule """ + def test(): veriloggen.reset() test_module = pipeline_multi_output.mkTest() diff --git a/tests_obsolete/extension/pipeline_/select/pipeline_select.py b/tests_obsolete/extension/pipeline_/select/pipeline_select.py index b6df1d81..a3ea200c 100644 --- a/tests_obsolete/extension/pipeline_/select/pipeline_select.py +++ b/tests_obsolete/extension/pipeline_/select/pipeline_select.py @@ -4,19 +4,21 @@ import os # the next line can be removed after installation -sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) +sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname( + os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) from veriloggen import * + def mkLed(): m = Module('blinkled') clk = m.Input('CLK') rst = m.Input('RST') - + x = m.Input('x', 32) vx = m.Input('vx') rx = m.Output('rx') - + y = m.Input('y', 32) vy = m.Input('vy') ry = m.Output('ry') @@ -24,14 +26,14 @@ def mkLed(): z = m.Output('z', 32) vz = m.Output('vz') rz = m.Input('rz') - + df = Pipeline(m, 'df', clk, rst) - + px = df.input(x, valid=vx, ready=rx) py = df.input(y, valid=vy, ready=ry) pz = df(Cond(px > py, px, py)) pz.output(z, valid=vz, ready=rz) - + df.make_always() try: @@ -41,19 +43,20 @@ def mkLed(): return m + def mkTest(numports=8): m = Module('test') # target instance led = mkLed() - + # copy paras and ports params = m.copy_params(led) ports = m.copy_sim_ports(led) clk = ports['CLK'] rst = ports['RST'] - + x = ports['x'] vx = ports['vx'] rx = ports['rx'] @@ -63,28 +66,28 @@ def mkTest(numports=8): z = ports['z'] vz = ports['vz'] rz = ports['rz'] - + uut = m.Instance(led, 'uut', params=m.connect_params(led), ports=m.connect_ports(led)) reset_done = m.Reg('reset_done', initval=0) - + reset_stmt = [] - reset_stmt.append( reset_done(0) ) - reset_stmt.append( x(11) ) - reset_stmt.append( y(0) ) - reset_stmt.append( vx(0) ) - reset_stmt.append( vy(0) ) - reset_stmt.append( rz(0) ) - + reset_stmt.append(reset_done(0)) + reset_stmt.append(x(11)) + reset_stmt.append(y(0)) + reset_stmt.append(vx(0)) + reset_stmt.append(vy(0)) + reset_stmt.append(rz(0)) + vcd_name = os.path.splitext(os.path.basename(__file__))[0] + '.vcd' simulation.setup_waveform(m, uut, dumpfile=vcd_name) simulation.setup_clock(m, clk, hperiod=5) init = simulation.setup_reset(m, rst, reset_stmt, period=100) nclk = simulation.next_clock - + init.add( Delay(1000), reset_done(1), @@ -93,42 +96,38 @@ def mkTest(numports=8): Systask('finish'), ) - x_count = m.TmpReg(32, initval=0) y_count = m.TmpReg(32, initval=0) z_count = m.TmpReg(32, initval=0) - xfsm = FSM(m, 'xfsm', clk, rst) xfsm.add(vx(0)) xfsm.goto_next(cond=reset_done) xfsm.add(vx(1)) xfsm.add(x.dec(), cond=rx) xfsm.add(x_count.inc(), cond=rx) - xfsm.goto_next(cond=AndList(x_count==10, rx)) + xfsm.goto_next(cond=AndList(x_count == 10, rx)) xfsm.add(vx(0)) xfsm.make_always() - - + yfsm = FSM(m, 'yfsm', clk, rst) yfsm.add(vy(0)) yfsm.goto_next(cond=reset_done) for _ in range(10): - yfsm.goto_next() # delay + yfsm.goto_next() # delay yfsm.add(vy(1)) yfsm.goto_next() yfsm.add(y.inc(), cond=ry) yfsm.add(y_count.inc(), cond=ry) - yfsm.goto_next(cond=AndList(y_count==10, ry)) + yfsm.goto_next(cond=AndList(y_count == 10, ry)) yfsm.add(vy(0)) yfsm.make_always() - zfsm = FSM(m, 'zfsm', clk, rst) zfsm.add(rz(0)) zfsm.goto_next(cond=reset_done) zfsm.goto_next() - zinit= zfsm.current + zinit = zfsm.current zfsm.add(rz(1), cond=vz) zfsm.goto_next(cond=vz) for i in range(10): @@ -137,7 +136,6 @@ def mkTest(numports=8): zfsm.goto(zinit) zfsm.make_always() - m.Always(Posedge(clk))( If(reset_done)( If(AndList(vx, rx))( @@ -151,9 +149,10 @@ def mkTest(numports=8): ) ) ) - + return m - + + if __name__ == '__main__': test = mkTest() verilog = test.to_verilog('tmp.v') @@ -161,10 +160,10 @@ def mkTest(numports=8): # run simulator (Icarus Verilog) sim = simulation.Simulator(test) - rslt = sim.run() # display=False + rslt = sim.run() # display=False #rslt = sim.run(display=True) print(rslt) # launch waveform viewer (GTKwave) - #sim.view_waveform() # background=False - #sim.view_waveform(background=True) + # sim.view_waveform() # background=False + # sim.view_waveform(background=True) diff --git a/tests_obsolete/extension/pipeline_/select/test_pipeline_select.py b/tests_obsolete/extension/pipeline_/select/test_pipeline_select.py index 362b42ba..336454ce 100644 --- a/tests_obsolete/extension/pipeline_/select/test_pipeline_select.py +++ b/tests_obsolete/extension/pipeline_/select/test_pipeline_select.py @@ -338,6 +338,7 @@ endmodule """ + def test(): veriloggen.reset() test_module = pipeline_select.mkTest() diff --git a/tests_obsolete/extension/pipeline_/single_add/pipeline_single_add.py b/tests_obsolete/extension/pipeline_/single_add/pipeline_single_add.py index d7f8ab0f..795ef925 100644 --- a/tests_obsolete/extension/pipeline_/single_add/pipeline_single_add.py +++ b/tests_obsolete/extension/pipeline_/single_add/pipeline_single_add.py @@ -4,24 +4,26 @@ import os # the next line can be removed after installation -sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) +sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname( + os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) from veriloggen import * + def mkLed(): m = Module('blinkled') clk = m.Input('CLK') rst = m.Input('RST') x = m.Input('x', 32) y = m.Output('y', 32) - + df = Pipeline(m, 'df', clk, rst) - + px = df.input(x) t0 = df(px.prev(1) + px.prev(2)) py = df(t0 + px) py.output(y) - + df.make_always() try: @@ -31,12 +33,13 @@ def mkLed(): return m + def mkTest(numports=8): m = Module('test') # target instance led = mkLed() - + # copy paras and ports params = m.copy_params(led) ports = m.copy_sim_ports(led) @@ -45,24 +48,24 @@ def mkTest(numports=8): rst = ports['RST'] x = ports['x'] y = ports['y'] - + uut = m.Instance(led, 'uut', params=m.connect_params(led), ports=m.connect_ports(led)) reset_done = m.Reg('reset_done', initval=0) - + reset_stmt = [] - reset_stmt.append( reset_done(0) ) - reset_stmt.append( x(0) ) - + reset_stmt.append(reset_done(0)) + reset_stmt.append(x(0)) + vcd_name = os.path.splitext(os.path.basename(__file__))[0] + '.vcd' simulation.setup_waveform(m, uut, dumpfile=vcd_name) simulation.setup_clock(m, clk, hperiod=5) init = simulation.setup_reset(m, rst, reset_stmt, period=100) nclk = simulation.next_clock - + init.add( Delay(1000), reset_done(1), @@ -77,24 +80,24 @@ def mkTest(numports=8): xfsm.goto_next(cond=reset_done) xfsm.add(x.inc()) xfsm.add(x_count.inc()) - xfsm.goto_next(cond=x_count==10) + xfsm.goto_next(cond=x_count == 10) xfsm.add(x(0)) for i in range(5): xfsm.goto_next() - xfsm.add( Systask('finish') ) - + xfsm.add(Systask('finish')) + xfsm.make_always() - - + m.Always(Posedge(clk))( If(reset_done)( Systask('display', 'x=%d', x), Systask('display', 'y=%d', y) ) ) - + return m - + + if __name__ == '__main__': test = mkTest() verilog = test.to_verilog('tmp.v') @@ -102,10 +105,10 @@ def mkTest(numports=8): # run simulator (Icarus Verilog) sim = simulation.Simulator(test) - rslt = sim.run() # display=False + rslt = sim.run() # display=False #rslt = sim.run(display=True) print(rslt) # launch waveform viewer (GTKwave) - #sim.view_waveform() # background=False - #sim.view_waveform(background=True) + # sim.view_waveform() # background=False + # sim.view_waveform(background=True) diff --git a/tests_obsolete/extension/pipeline_/single_add/test_pipeline_single_add.py b/tests_obsolete/extension/pipeline_/single_add/test_pipeline_single_add.py index 4fc72392..b6519929 100644 --- a/tests_obsolete/extension/pipeline_/single_add/test_pipeline_single_add.py +++ b/tests_obsolete/extension/pipeline_/single_add/test_pipeline_single_add.py @@ -150,6 +150,7 @@ endmodule """ + def test(): veriloggen.reset() test_module = pipeline_single_add.mkTest() diff --git a/tests_obsolete/extension/pipeline_/single_add_valid/pipeline_single_add_valid.py b/tests_obsolete/extension/pipeline_/single_add_valid/pipeline_single_add_valid.py index 53cf956c..0e7bf78c 100644 --- a/tests_obsolete/extension/pipeline_/single_add_valid/pipeline_single_add_valid.py +++ b/tests_obsolete/extension/pipeline_/single_add_valid/pipeline_single_add_valid.py @@ -4,10 +4,12 @@ import os # the next line can be removed after installation -sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) +sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname( + os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) from veriloggen import * + def mkLed(): m = Module('blinkled') clk = m.Input('CLK') @@ -16,14 +18,14 @@ def mkLed(): vx = m.Input('vx') y = m.Output('y', 32) vy = m.Output('vy') - + df = Pipeline(m, 'df', clk, rst) - + px = df.input(x, valid=vx) t0 = df(px.prev(1) + px.prev(2)) py = df(t0 + px) py.output(y, valid=vy) - + df.make_always() try: @@ -33,12 +35,13 @@ def mkLed(): return m + def mkTest(numports=8): m = Module('test') # target instance led = mkLed() - + # copy paras and ports params = m.copy_params(led) ports = m.copy_sim_ports(led) @@ -49,25 +52,25 @@ def mkTest(numports=8): vx = ports['vx'] y = ports['y'] vy = ports['vy'] - + uut = m.Instance(led, 'uut', params=m.connect_params(led), ports=m.connect_ports(led)) reset_done = m.Reg('reset_done', initval=0) - + reset_stmt = [] - reset_stmt.append( reset_done(0) ) - reset_stmt.append( x(0) ) - reset_stmt.append( vx(0) ) - + reset_stmt.append(reset_done(0)) + reset_stmt.append(x(0)) + reset_stmt.append(vx(0)) + vcd_name = os.path.splitext(os.path.basename(__file__))[0] + '.vcd' simulation.setup_waveform(m, uut, dumpfile=vcd_name) simulation.setup_clock(m, clk, hperiod=5) init = simulation.setup_reset(m, rst, reset_stmt, period=100) nclk = simulation.next_clock - + init.add( Delay(1000), reset_done(1), @@ -76,9 +79,8 @@ def mkTest(numports=8): Systask('finish'), ) - x_count = m.TmpReg(32, initval=0) - + xfsm = FSM(m, 'xfsm', clk, rst) xfsm.add(vx(0)) xfsm.goto_next(cond=reset_done) @@ -88,18 +90,17 @@ def mkTest(numports=8): xfsm.goto_next() xfsm.add(x.inc()) xfsm.add(x_count.inc()) - xfsm.goto_next(cond=x_count==5) + xfsm.goto_next(cond=x_count == 5) xfsm.add(vx(0)) for _ in range(10): xfsm.goto_next() xfsm.add(vx(1)) xfsm.add(x.inc()) xfsm.add(x_count.inc()) - xfsm.goto_next(cond=x_count==10) + xfsm.goto_next(cond=x_count == 10) xfsm.add(vx(0)) xfsm.make_always() - m.Always(Posedge(clk))( If(reset_done)( If(vx)( @@ -110,9 +111,10 @@ def mkTest(numports=8): ) ) ) - + return m - + + if __name__ == '__main__': test = mkTest() verilog = test.to_verilog('tmp.v') @@ -120,10 +122,10 @@ def mkTest(numports=8): # run simulator (Icarus Verilog) sim = simulation.Simulator(test) - rslt = sim.run() # display=False + rslt = sim.run() # display=False #rslt = sim.run(display=True) print(rslt) # launch waveform viewer (GTKwave) - #sim.view_waveform() # background=False - #sim.view_waveform(background=True) + # sim.view_waveform() # background=False + # sim.view_waveform(background=True) diff --git a/tests_obsolete/extension/pipeline_/single_add_valid/test_pipeline_single_add_valid.py b/tests_obsolete/extension/pipeline_/single_add_valid/test_pipeline_single_add_valid.py index b018a5ab..0bfdb05f 100644 --- a/tests_obsolete/extension/pipeline_/single_add_valid/test_pipeline_single_add_valid.py +++ b/tests_obsolete/extension/pipeline_/single_add_valid/test_pipeline_single_add_valid.py @@ -257,6 +257,7 @@ endmodule """ + def test(): veriloggen.reset() test_module = pipeline_single_add_valid.mkTest() diff --git a/tests_obsolete/extension/pipeline_/single_add_validready/pipeline_single_add_validready.py b/tests_obsolete/extension/pipeline_/single_add_validready/pipeline_single_add_validready.py index 027f1325..b42afe24 100644 --- a/tests_obsolete/extension/pipeline_/single_add_validready/pipeline_single_add_validready.py +++ b/tests_obsolete/extension/pipeline_/single_add_validready/pipeline_single_add_validready.py @@ -4,10 +4,12 @@ import os # the next line can be removed after installation -sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) +sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname( + os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) from veriloggen import * + def mkLed(): m = Module('blinkled') clk = m.Input('CLK') @@ -18,14 +20,14 @@ def mkLed(): y = m.Output('y', 32) vy = m.Output('vy') ry = m.Input('ry') - + df = Pipeline(m, 'df', clk, rst) - + px = df.input(x, valid=vx, ready=rx) t0 = df(px.prev(1) + px.prev(2)) py = df(t0 + px) py.output(y, valid=vy, ready=ry) - + df.make_always() try: @@ -35,12 +37,13 @@ def mkLed(): return m + def mkTest(numports=8): m = Module('test') # target instance led = mkLed() - + # copy paras and ports params = m.copy_params(led) ports = m.copy_sim_ports(led) @@ -53,26 +56,26 @@ def mkTest(numports=8): y = ports['y'] vy = ports['vy'] ry = ports['ry'] - + uut = m.Instance(led, 'uut', params=m.connect_params(led), ports=m.connect_ports(led)) reset_done = m.Reg('reset_done', initval=0) - + reset_stmt = [] - reset_stmt.append( reset_done(0) ) - reset_stmt.append( x(0) ) - reset_stmt.append( vx(0) ) - reset_stmt.append( ry(0) ) - + reset_stmt.append(reset_done(0)) + reset_stmt.append(x(0)) + reset_stmt.append(vx(0)) + reset_stmt.append(ry(0)) + vcd_name = os.path.splitext(os.path.basename(__file__))[0] + '.vcd' simulation.setup_waveform(m, uut, dumpfile=vcd_name) simulation.setup_clock(m, clk, hperiod=5) init = simulation.setup_reset(m, rst, reset_stmt, period=100) nclk = simulation.next_clock - + init.add( Delay(1000), reset_done(1), @@ -84,7 +87,6 @@ def mkTest(numports=8): x_count = m.TmpReg(32, initval=0) y_count = m.TmpReg(32, initval=0) - xfsm = FSM(m, 'xfsm', clk, rst) xfsm.add(vx(0)) xfsm.goto_next(cond=reset_done) @@ -94,23 +96,22 @@ def mkTest(numports=8): xfsm.goto_next() xfsm.add(x.inc(), cond=rx) xfsm.add(x_count.inc(), cond=rx) - xfsm.goto_next(cond=AndList(x_count==5, rx)) + xfsm.goto_next(cond=AndList(x_count == 5, rx)) xfsm.add(vx(0)) for _ in range(10): xfsm.goto_next() xfsm.add(vx(1)) xfsm.add(x.inc(), cond=rx) xfsm.add(x_count.inc(), cond=rx) - xfsm.goto_next(cond=AndList(x_count==10, rx)) + xfsm.goto_next(cond=AndList(x_count == 10, rx)) xfsm.add(vx(0)) xfsm.make_always() - - + yfsm = FSM(m, 'yfsm', clk, rst) yfsm.add(ry(0)) yfsm.goto_next(cond=reset_done) yfsm.goto_next() - yinit= yfsm.current + yinit = yfsm.current yfsm.add(ry(1), cond=vy) yfsm.goto_next(cond=vy) for i in range(10): @@ -119,7 +120,6 @@ def mkTest(numports=8): yfsm.goto(yinit) yfsm.make_always() - m.Always(Posedge(clk))( If(reset_done)( If(AndList(vx, rx))( @@ -130,9 +130,10 @@ def mkTest(numports=8): ) ) ) - + return m - + + if __name__ == '__main__': test = mkTest() verilog = test.to_verilog('tmp.v') @@ -140,10 +141,10 @@ def mkTest(numports=8): # run simulator (Icarus Verilog) sim = simulation.Simulator(test) - rslt = sim.run() # display=False + rslt = sim.run() # display=False #rslt = sim.run(display=True) print(rslt) # launch waveform viewer (GTKwave) - #sim.view_waveform() # background=False - #sim.view_waveform(background=True) + # sim.view_waveform() # background=False + # sim.view_waveform(background=True) diff --git a/tests_obsolete/extension/pipeline_/single_add_validready/test_pipeline_single_add_validready.py b/tests_obsolete/extension/pipeline_/single_add_validready/test_pipeline_single_add_validready.py index da5cba39..4fbe5ad0 100644 --- a/tests_obsolete/extension/pipeline_/single_add_validready/test_pipeline_single_add_validready.py +++ b/tests_obsolete/extension/pipeline_/single_add_validready/test_pipeline_single_add_validready.py @@ -379,6 +379,7 @@ endmodule """ + def test(): veriloggen.reset() test_module = pipeline_single_add_validready.mkTest() diff --git a/tests_obsolete/extension/pipeline_/single_passthrough/pipeline_single_passthrough.py b/tests_obsolete/extension/pipeline_/single_passthrough/pipeline_single_passthrough.py index a9cda268..8abf0eea 100644 --- a/tests_obsolete/extension/pipeline_/single_passthrough/pipeline_single_passthrough.py +++ b/tests_obsolete/extension/pipeline_/single_passthrough/pipeline_single_passthrough.py @@ -4,10 +4,12 @@ import os # the next line can be removed after installation -sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) +sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname( + os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) from veriloggen import * + def mkLed(): m = Module('blinkled') clk = m.Input('CLK') @@ -18,13 +20,13 @@ def mkLed(): y = m.Output('y', 32) vy = m.Output('vy') ry = m.Input('ry') - + df = Pipeline(m, 'df', clk, rst) - + px = df.input(x, valid=vx, ready=rx) dummy = df(px) px.output(y, valid=vy, ready=ry) - + df.make_always() try: @@ -34,12 +36,13 @@ def mkLed(): return m + def mkTest(numports=8): m = Module('test') # target instance led = mkLed() - + # copy paras and ports params = m.copy_params(led) ports = m.copy_sim_ports(led) @@ -52,26 +55,26 @@ def mkTest(numports=8): y = ports['y'] vy = ports['vy'] ry = ports['ry'] - + uut = m.Instance(led, 'uut', params=m.connect_params(led), ports=m.connect_ports(led)) reset_done = m.Reg('reset_done', initval=0) - + reset_stmt = [] - reset_stmt.append( reset_done(0) ) - reset_stmt.append( x(0) ) - reset_stmt.append( vx(0) ) - reset_stmt.append( ry(0) ) - + reset_stmt.append(reset_done(0)) + reset_stmt.append(x(0)) + reset_stmt.append(vx(0)) + reset_stmt.append(ry(0)) + vcd_name = os.path.splitext(os.path.basename(__file__))[0] + '.vcd' simulation.setup_waveform(m, uut, dumpfile=vcd_name) simulation.setup_clock(m, clk, hperiod=5) init = simulation.setup_reset(m, rst, reset_stmt, period=100) nclk = simulation.next_clock - + init.add( Delay(1000), reset_done(1), @@ -83,7 +86,6 @@ def mkTest(numports=8): x_count = m.TmpReg(32, initval=0) y_count = m.TmpReg(32, initval=0) - xfsm = FSM(m, 'xfsm', clk, rst) xfsm.add(vx(0)) xfsm.goto_next(cond=reset_done) @@ -93,23 +95,22 @@ def mkTest(numports=8): xfsm.goto_next() xfsm.add(x.inc(), cond=rx) xfsm.add(x_count.inc(), cond=rx) - xfsm.goto_next(cond=AndList(x_count==5, rx)) + xfsm.goto_next(cond=AndList(x_count == 5, rx)) xfsm.add(vx(0)) for _ in range(10): xfsm.goto_next() xfsm.add(vx(1)) xfsm.add(x.inc(), cond=rx) xfsm.add(x_count.inc(), cond=rx) - xfsm.goto_next(cond=AndList(x_count==10, rx)) + xfsm.goto_next(cond=AndList(x_count == 10, rx)) xfsm.add(vx(0)) xfsm.make_always() - - + yfsm = FSM(m, 'yfsm', clk, rst) yfsm.add(ry(0)) yfsm.goto_next(cond=reset_done) yfsm.goto_next() - yinit= yfsm.current + yinit = yfsm.current yfsm.add(ry(1), cond=vy) yfsm.goto_next(cond=vy) for i in range(10): @@ -118,7 +119,6 @@ def mkTest(numports=8): yfsm.goto(yinit) yfsm.make_always() - m.Always(Posedge(clk))( If(reset_done)( If(AndList(vx, rx))( @@ -129,9 +129,10 @@ def mkTest(numports=8): ) ) ) - + return m - + + if __name__ == '__main__': test = mkTest() verilog = test.to_verilog('tmp.v') @@ -139,10 +140,10 @@ def mkTest(numports=8): # run simulator (Icarus Verilog) sim = simulation.Simulator(test) - rslt = sim.run() # display=False + rslt = sim.run() # display=False #rslt = sim.run(display=True) print(rslt) # launch waveform viewer (GTKwave) - #sim.view_waveform() # background=False - #sim.view_waveform(background=True) + # sim.view_waveform() # background=False + # sim.view_waveform(background=True) diff --git a/tests_obsolete/extension/pipeline_/single_passthrough/test_pipeline_single_passthrough.py b/tests_obsolete/extension/pipeline_/single_passthrough/test_pipeline_single_passthrough.py index 9a6c2d5f..f824be76 100644 --- a/tests_obsolete/extension/pipeline_/single_passthrough/test_pipeline_single_passthrough.py +++ b/tests_obsolete/extension/pipeline_/single_passthrough/test_pipeline_single_passthrough.py @@ -355,6 +355,7 @@ endmodule """ + def test(): veriloggen.reset() test_module = pipeline_single_passthrough.mkTest() diff --git a/tests_obsolete/extension/pipeline_/unbalanced_output/pipeline_unbalanced_output.py b/tests_obsolete/extension/pipeline_/unbalanced_output/pipeline_unbalanced_output.py index 191e91d5..7df2de47 100644 --- a/tests_obsolete/extension/pipeline_/unbalanced_output/pipeline_unbalanced_output.py +++ b/tests_obsolete/extension/pipeline_/unbalanced_output/pipeline_unbalanced_output.py @@ -4,19 +4,21 @@ import os # the next line can be removed after installation -sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) +sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname( + os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) from veriloggen import * + def mkLed(): m = Module('blinkled') clk = m.Input('CLK') rst = m.Input('RST') - + x = m.Input('x', 32) vx = m.Input('vx') rx = m.Output('rx') - + y = m.Output('y', 32) vy = m.Output('vy') ry = m.Input('ry') @@ -24,16 +26,16 @@ def mkLed(): z = m.Output('z', 32) vz = m.Output('vz') rz = m.Input('rz') - + df = Pipeline(m, 'df', clk, rst) - + px = df.input(x, valid=vx, ready=rx) py = df(px + 1) pz = df(py + 1) - + py.output(y, valid=vy, ready=ry) pz.output(z, valid=vz, ready=rz) - + df.make_always() try: @@ -43,51 +45,52 @@ def mkLed(): return m + def mkTest(numports=8): m = Module('test') # target instance led = mkLed() - + # copy paras and ports params = m.copy_params(led) ports = m.copy_sim_ports(led) clk = ports['CLK'] rst = ports['RST'] - + x = ports['x'] vx = ports['vx'] rx = ports['rx'] - + y = ports['y'] vy = ports['vy'] ry = ports['ry'] - + z = ports['z'] vz = ports['vz'] rz = ports['rz'] - + uut = m.Instance(led, 'uut', params=m.connect_params(led), ports=m.connect_ports(led)) - + reset_done = m.Reg('reset_done', initval=0) reset_stmt = [] - reset_stmt.append( reset_done(0) ) - reset_stmt.append( x(0) ) - reset_stmt.append( vx(0) ) - reset_stmt.append( ry(0) ) - reset_stmt.append( rz(0) ) - + reset_stmt.append(reset_done(0)) + reset_stmt.append(x(0)) + reset_stmt.append(vx(0)) + reset_stmt.append(ry(0)) + reset_stmt.append(rz(0)) + vcd_name = os.path.splitext(os.path.basename(__file__))[0] + '.vcd' simulation.setup_waveform(m, uut, dumpfile=vcd_name) simulation.setup_clock(m, clk, hperiod=5) init = simulation.setup_reset(m, rst, reset_stmt, period=100) nclk = simulation.next_clock - + init.add( Delay(1000), reset_done(1), @@ -95,13 +98,11 @@ def mkTest(numports=8): Delay(10000), Systask('finish'), ) - - + x_count = m.TmpReg(32, initval=0) y_count = m.TmpReg(32, initval=0) z_count = m.TmpReg(32, initval=0) - xfsm = FSM(m, 'xfsm', clk, rst) xfsm.add(vx(0)) xfsm.goto_next(cond=reset_done) @@ -111,23 +112,22 @@ def mkTest(numports=8): xfsm.goto_next() xfsm.add(x.inc(), cond=rx) xfsm.add(x_count.inc(), cond=rx) - xfsm.goto_next(cond=AndList(x_count==5, rx)) + xfsm.goto_next(cond=AndList(x_count == 5, rx)) xfsm.add(vx(0)) for _ in range(10): xfsm.goto_next() xfsm.add(vx(1)) xfsm.add(x.inc(), cond=rx) xfsm.add(x_count.inc(), cond=rx) - xfsm.goto_next(cond=AndList(x_count==10, rx)) + xfsm.goto_next(cond=AndList(x_count == 10, rx)) xfsm.add(vx(0)) xfsm.make_always() - - + yfsm = FSM(m, 'yfsm', clk, rst) yfsm.add(ry(0)) yfsm.goto_next(cond=reset_done) yfsm.goto_next() - yinit= yfsm.current + yinit = yfsm.current yfsm.add(ry(1), cond=vy) yfsm.goto_next(cond=vy) for i in range(5): @@ -136,12 +136,11 @@ def mkTest(numports=8): yfsm.goto(yinit) yfsm.make_always() - zfsm = FSM(m, 'zfsm', clk, rst) zfsm.add(rz(0)) zfsm.goto_next(cond=reset_done) zfsm.goto_next() - zinit= zfsm.current + zinit = zfsm.current zfsm.add(rz(1), cond=vz) zfsm.goto_next(cond=vz) for i in range(20): @@ -150,7 +149,6 @@ def mkTest(numports=8): zfsm.goto(zinit) zfsm.make_always() - m.Always(Posedge(clk))( If(reset_done)( If(AndList(vx, rx))( @@ -164,9 +162,10 @@ def mkTest(numports=8): ), ) ) - + return m - + + if __name__ == '__main__': test = mkTest() verilog = test.to_verilog('tmp.v') @@ -174,10 +173,10 @@ def mkTest(numports=8): # run simulator (Icarus Verilog) sim = simulation.Simulator(test) - rslt = sim.run() # display=False + rslt = sim.run() # display=False #rslt = sim.run(display=True) print(rslt) # launch waveform viewer (GTKwave) - #sim.view_waveform() # background=False - #sim.view_waveform(background=True) + # sim.view_waveform() # background=False + # sim.view_waveform(background=True) diff --git a/tests_obsolete/extension/pipeline_/unbalanced_output/test_pipeline_unbalanced_output.py b/tests_obsolete/extension/pipeline_/unbalanced_output/test_pipeline_unbalanced_output.py index 4e880058..c00084a7 100644 --- a/tests_obsolete/extension/pipeline_/unbalanced_output/test_pipeline_unbalanced_output.py +++ b/tests_obsolete/extension/pipeline_/unbalanced_output/test_pipeline_unbalanced_output.py @@ -497,6 +497,7 @@ endmodule """ + def test(): veriloggen.reset() test_module = pipeline_unbalanced_output.mkTest() diff --git a/veriloggen/VERSION b/veriloggen/VERSION index ccbccc3d..276cbf9e 100644 --- a/veriloggen/VERSION +++ b/veriloggen/VERSION @@ -1 +1 @@ -2.2.0 +2.3.0 diff --git a/veriloggen/core/module.py b/veriloggen/core/module.py index 7f154bf2..a43a4f56 100644 --- a/veriloggen/core/module.py +++ b/veriloggen/core/module.py @@ -1296,6 +1296,11 @@ def check_existing_identifier(self, name, *types): class StubModule(vtypes.VeriloggenNode): """ Verilog Module class """ + def __eq__(self, other): + if isinstance(other, StubModule): + return (self.name == other.name and self.code == other.code) + return False + def __init__(self, name=None, code=''): vtypes.VeriloggenNode.__init__(self) self.name = name if name is not None else self.__class__.__name__ diff --git a/veriloggen/core/vtypes.py b/veriloggen/core/vtypes.py index 917d2faf..490d63bd 100644 --- a/veriloggen/core/vtypes.py +++ b/veriloggen/core/vtypes.py @@ -151,6 +151,7 @@ def get_value(obj): return obj.value return None + def get_initval(obj): if hasattr(obj, 'initval'): return obj.initval diff --git a/veriloggen/pipeline/pipeline.py b/veriloggen/pipeline/pipeline.py index 38a1e413..e62d5445 100644 --- a/veriloggen/pipeline/pipeline.py +++ b/veriloggen/pipeline/pipeline.py @@ -63,7 +63,7 @@ def __init__(self, m, name, clk, rst, width=32): self.done = False - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- def input(self, data, valid=None, ready=None, width=None): if ready is not None and not isinstance(ready, (vtypes.Wire, vtypes.Output)): raise TypeError('ready port of PipelineVariable must be Wire., not %s' % @@ -73,7 +73,7 @@ def input(self, data, valid=None, ready=None, width=None): self.vars.append(ret) return ret - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- # self.__call__() calls this method def stage(self, data, initval=0, width=None, preg=None): if width is None: @@ -96,7 +96,7 @@ def stage(self, data, initval=0, width=None, preg=None): return ret - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- # Accumulator def acc_and(self, data, initval=0, resetcond=None, width=None): return self._accumulate([vtypes.And], data, width, initval, resetcond) @@ -146,7 +146,7 @@ def acc_custom(self, data, ops, initval=0, resetcond=None, width=None, label=Non ops = [ops] return self._accumulate(ops, data, width, initval, resetcond, label) - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- def make_always(self, reset=(), body=()): if self.done: raise ValueError('make_always() has been already called.') @@ -165,19 +165,19 @@ def make_always(self, reset=(), body=()): self.make_code() )) - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- def make_reset(self): return self.seq.make_reset() - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- def make_code(self): return self.seq.make_code() - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- def draw_graph(self, filename='out.png', prog='dot'): _draw_graph(self, filename, prog) - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- def _accumulate(self, ops, data, width=None, initval=0, resetcond=None, oplabel=None): if width is None: width = self.width @@ -197,7 +197,7 @@ def _accumulate(self, ops, data, width=None, initval=0, resetcond=None, oplabel= return ret - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- def _add_reg(self, prefix, count, width=None, initval=0): tmp_name = '_'.join(['', self.name, prefix, str(count)]) tmp = self.m.Reg(tmp_name, width, initval=initval) @@ -208,7 +208,7 @@ def _add_wire(self, prefix, count, width=None): tmp = self.m.Wire(tmp_name, width) return tmp - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- def _make_tmp(self, data, valid, ready, width=None, initval=0, acc_ops=()): tmp_data = self._add_reg( 'data', self.tmp_count, width=width, initval=initval) @@ -298,7 +298,7 @@ def _make_tmp(self, data, valid, ready, width=None, initval=0, acc_ops=()): return tmp_data, tmp_valid, tmp_ready - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- def _make_prev(self, data, valid, ready, width=None, initval=0): tmp_data = self._add_reg( 'data', self.tmp_count, width=width, initval=initval) @@ -320,11 +320,11 @@ def _make_prev(self, data, valid, ready, width=None, initval=0): return tmp_data, tmp_valid, tmp_ready - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- def __call__(self, data, initval=0, width=None): return self.stage(data, initval=initval, width=width) -#------------------------------------------------------------------------- +# ------------------------------------------------------------------------- class _PipelineInterface(object): @@ -339,7 +339,7 @@ def __str__(self): args = [self.data, self.valid, self.ready] return ','.join([str(arg) for arg in args]) -#------------------------------------------------------------------------- +# ------------------------------------------------------------------------- class _PipelineNumeric(vtypes._Numeric): @@ -451,7 +451,7 @@ def _get_preg(self, stage_id): return self return self.preg_dict[stage_id] -#------------------------------------------------------------------------- +# ------------------------------------------------------------------------- class _PipelineVisitor(object): @@ -520,7 +520,7 @@ def visit_str(self, node): def visit_float(self, node): raise NotImplementedError('visit__Constant() must be implemented') -#------------------------------------------------------------------------- +# ------------------------------------------------------------------------- class DataVisitor(_PipelineVisitor): @@ -655,7 +655,7 @@ def visit_str(self, node): def visit_float(self, node): return (None, vtypes.Float(node), None, []) -#------------------------------------------------------------------------- +# ------------------------------------------------------------------------- def _draw_graph(df, filename='out.png', prog='dot'): diff --git a/veriloggen/stream/scheduler.py b/veriloggen/stream/scheduler.py index 1c3bdb32..500106c3 100644 --- a/veriloggen/stream/scheduler.py +++ b/veriloggen/stream/scheduler.py @@ -90,8 +90,8 @@ def visit__BinaryOperator(self, node): node._set_start_stage(mine) if getattr(node, 'variable_latency', None): node.latency = getattr(node, node.variable_latency)() - if getattr(node, 'variable_iteration_interval', None): - node.iteration_interval = getattr(node, node.variable_iteration_interval)() + if getattr(node, 'variable_initiation_interval', None): + node.initiation_interval = getattr(node, node.variable_initiation_interval)() end = self.next_stage(node, mine) node._set_end_stage(end) return end @@ -107,8 +107,8 @@ def visit__UnaryOperator(self, node): node._set_start_stage(mine) if getattr(node, 'variable_latency', None): node.latency = getattr(node, node.variable_latency)() - if getattr(node, 'variable_iteration_interval', None): - node.iteration_interval = getattr(node, node.variable_iteration_interval)() + if getattr(node, 'variable_initiation_interval', None): + node.initiation_interval = getattr(node, node.variable_initiation_interval)() end = self.next_stage(node, mine) node._set_end_stage(end) return end @@ -127,8 +127,8 @@ def visit__SpecialOperator(self, node): node._set_start_stage(mine) if getattr(node, 'variable_latency', None): node.latency = getattr(node, node.variable_latency)() - if getattr(node, 'variable_iteration_interval', None): - node.iteration_interval = getattr(node, node.variable_iteration_interval)() + if getattr(node, 'variable_initiation_interval', None): + node.initiation_interval = getattr(node, node.variable_initiation_interval)() end = self.next_stage(node, mine) node._set_end_stage(end) return end @@ -167,8 +167,8 @@ def visit__Accumulator(self, node): node._set_start_stage(mine) if getattr(node, 'variable_latency', None): node.latency = getattr(node, node.variable_latency)() - if getattr(node, 'variable_iteration_interval', None): - node.iteration_interval = getattr(node, node.variable_iteration_interval)() + if getattr(node, 'variable_initiation_interval', None): + node.initiation_interval = getattr(node, node.variable_initiation_interval)() end = self.next_stage(node, mine) node._set_end_stage(end) return end diff --git a/veriloggen/stream/stypes.py b/veriloggen/stream/stypes.py index 10900609..aadec006 100644 --- a/veriloggen/stream/stypes.py +++ b/veriloggen/stream/stypes.py @@ -97,7 +97,7 @@ def name_chain(self): class _Numeric(_Node): latency = 0 - iteration_interval = 1 + initiation_interval = 1 def __hash__(self): object_id = self.object_id if hasattr(self, 'object_id') else None @@ -457,7 +457,7 @@ def data(self): class _Operator(_Numeric): latency = 1 - iteration_interval = 1 + initiation_interval = 1 def _implement(self, m, seq, svalid=None, senable=None): raise NotImplementedError('_implement() is not implemented.') @@ -500,7 +500,7 @@ def _implement(self, m, seq, svalid=None, senable=None): lpoint, rpoint, signed) enable_cond = senable - if self.iteration_interval != 1: + if self.initiation_interval != 1: enable_cond = _and_vars(enable_cond, svalid) if self.latency == 0: @@ -514,9 +514,9 @@ def _implement(self, m, seq, svalid=None, senable=None): seq(data(self.op(ldata, rdata)), cond=enable_cond) # multicycle control - if self.iteration_interval != 1: + if self.initiation_interval != 1: ii_count = m.Reg(self.name('ii_count'), - int(ceil(log(self.iteration_interval, 2))) + 1, initval=0) + int(ceil(log(self.initiation_interval, 2))) + 1, initval=0) ii_stall_cond = m.Wire(self.name('ii_stall_cond')) ii_stall_cond.assign(ii_count > 0) util.add_disable_cond(self.strm.internal_oready, @@ -528,7 +528,7 @@ def _implement(self, m, seq, svalid=None, senable=None): seq.If(ii_count > 0)( ii_count.inc() ) - seq.If(ii_count == self.iteration_interval - 1)( + seq.If(ii_count == self.initiation_interval - 1)( ii_count(0) ) @@ -576,7 +576,7 @@ def _implement(self, m, seq, svalid=None, senable=None): rdata = self.right.sig_data enable_cond = senable - if self.iteration_interval != 1: + if self.initiation_interval != 1: enable_cond = _and_vars(enable_cond, svalid) if self.latency == 0: @@ -590,9 +590,9 @@ def _implement(self, m, seq, svalid=None, senable=None): seq(data(self.op(rdata)), cond=enable_cond) # multicycle control - if self.iteration_interval != 1: + if self.initiation_interval != 1: ii_count = m.Reg(self.name('ii_count'), - int(ceil(log(self.iteration_interval, 2))) + 1, initval=0) + int(ceil(log(self.initiation_interval, 2))) + 1, initval=0) ii_stall_cond = m.Wire(self.name('ii_stall_cond')) ii_stall_cond.assign(ii_count > 0) util.add_disable_cond(self.strm.internal_oready, @@ -604,7 +604,7 @@ def _implement(self, m, seq, svalid=None, senable=None): seq.If(ii_count > 0)( ii_count.inc() ) - seq.If(ii_count == self.iteration_interval - 1)( + seq.If(ii_count == self.initiation_interval - 1)( ii_count(0) ) @@ -837,8 +837,8 @@ def _implement(self, m, seq, svalid=None, senable=None): class DivideMultiCycle(_BinaryOperator): latency = 1 - iteration_interval = 32 + 2 - variable_iteration_interval = 'get_latency' + initiation_interval = 32 + 2 + variable_initiation_interval = 'get_latency' def get_latency(self): return self.get_width() + 2 @@ -869,7 +869,7 @@ def _implement(self, m, seq, svalid=None, senable=None): enable_cond = _and_vars(senable, svalid) ii_count = m.Reg(self.name('ii_count'), - int(ceil(log(self.iteration_interval, 2))) + 1, initval=0) + int(ceil(log(self.initiation_interval, 2))) + 1, initval=0) ii_stall_cond = m.Wire(self.name('ii_stall_cond')) ii_stall_cond.assign(ii_count > 0) util.add_disable_cond(self.strm.internal_oready, ii_stall_cond, vtypes.Int(0)) @@ -880,7 +880,7 @@ def _implement(self, m, seq, svalid=None, senable=None): seq.If(ii_count > 0)( ii_count.inc() ) - seq.If(ii_count == self.iteration_interval - 1)( + seq.If(ii_count == self.initiation_interval - 1)( ii_count(0) ) @@ -1530,7 +1530,7 @@ def _implement(self, m, seq, svalid=None, senable=None): arg_data = [arg.sig_data for arg in self.args] enable_cond = senable - if self.iteration_interval != 1: + if self.initiation_interval != 1: enable_cond = _and_vars(enable_cond, svalid) if self.latency == 0: @@ -1544,9 +1544,9 @@ def _implement(self, m, seq, svalid=None, senable=None): seq(data(self.op(*arg_data)), cond=enable_cond) # multicycle control - if self.iteration_interval != 1: + if self.initiation_interval != 1: ii_count = m.Reg(self.name('ii_count'), - int(ceil(log(self.iteration_interval, 2))) + 1, initval=0) + int(ceil(log(self.initiation_interval, 2))) + 1, initval=0) ii_stall_cond = m.Wire(self.name('ii_stall_cond')) ii_stall_cond.assign(ii_count > 0) util.add_disable_cond(self.strm.internal_oready, @@ -1558,7 +1558,7 @@ def _implement(self, m, seq, svalid=None, senable=None): seq.If(ii_count > 0)( ii_count.inc() ) - seq.If(ii_count == self.iteration_interval - 1)( + seq.If(ii_count == self.initiation_interval - 1)( ii_count(0) ) @@ -3017,12 +3017,12 @@ def _implement(self, m, seq, svalid=None, senable=None): raise ValueError("Latency must be '%d', not '%d'" % (self.latency, 1)) - if self.iteration_interval != 1 and self.latency != 1: - raise ValueError("When iteration_interval != 1, latency must be '%d', not '%d'" % + if self.initiation_interval != 1 and self.latency != 1: + raise ValueError("When initiation_interval != 1, latency must be '%d', not '%d'" % (self.latency, 1)) - if self.iteration_interval != 1 and self.strm is None: - raise ValueError("When iteration_interval != 1, strm must be assigned.") + if self.initiation_interval != 1 and self.strm is None: + raise ValueError("When initiation_interval != 1, strm must be assigned.") size_data = self.size.sig_data if self.size is not None else None interval_data = self.interval.sig_data if self.interval is not None else None @@ -3130,9 +3130,9 @@ def _implement(self, m, seq, svalid=None, senable=None): seq(data(value), cond=enable_cond) # multicycle control - if self.iteration_interval != 1: + if self.initiation_interval != 1: ii_count = m.Reg(self.name('ii_count'), - int(ceil(log(self.iteration_interval, 2))) + 1, initval=0) + int(ceil(log(self.initiation_interval, 2))) + 1, initval=0) ii_stall_cond = m.Wire(self.name('ii_stall_cond')) ii_stall_cond.assign(ii_count > 0) util.add_disable_cond(self.strm.internal_oready, ii_stall_cond, vtypes.Int(0)) @@ -3143,7 +3143,7 @@ def _implement(self, m, seq, svalid=None, senable=None): seq.If(ii_count > 0)( ii_count.inc() ) - seq.If(ii_count == self.iteration_interval - 1)( + seq.If(ii_count == self.initiation_interval - 1)( ii_count(0) ) @@ -3187,7 +3187,7 @@ def __init__(self, right, size=None, interval=None, initval=0, class ReduceMul(_Accumulator): latency = 1 - iteration_interval = 2 + 1 + initiation_interval = 2 + 1 ops = () def __init__(self, right, size=None, interval=None, initval=0, @@ -3203,12 +3203,12 @@ def _implement(self, m, seq, svalid=None, senable=None): raise ValueError("Latency must be '%d', not '%d'" % (self.latency, 1)) - if self.iteration_interval != 1 and self.latency != 1: - raise ValueError("When iteration_interval != 1, latency must be '%d', not '%d'" % + if self.initiation_interval != 1 and self.latency != 1: + raise ValueError("When initiation_interval != 1, latency must be '%d', not '%d'" % (self.latency, 1)) - if self.iteration_interval != 1 and self.strm is None: - raise ValueError("When iteration_interval != 1, strm must be assigned.") + if self.initiation_interval != 1 and self.strm is None: + raise ValueError("When initiation_interval != 1, strm must be assigned.") size_data = self.size.sig_data if self.size is not None else None interval_data = self.interval.sig_data if self.interval is not None else None @@ -3297,7 +3297,7 @@ def _implement(self, m, seq, svalid=None, senable=None): # multicycle control ii_count = m.Reg(self.name('ii_count'), - int(ceil(log(self.iteration_interval, 2))) + 1, initval=0) + int(ceil(log(self.initiation_interval, 2))) + 1, initval=0) ii_stall_cond = m.Wire(self.name('ii_stall_cond')) ii_stall_cond.assign(ii_count > 0) util.add_disable_cond(self.strm.internal_oready, ii_stall_cond, vtypes.Int(0)) @@ -3308,13 +3308,13 @@ def _implement(self, m, seq, svalid=None, senable=None): seq.If(ii_count > 0)( ii_count.inc() ) - seq.If(ii_count == self.iteration_interval - 1)( + seq.If(ii_count == self.initiation_interval - 1)( ii_count(0) ) comp_cond = vtypes.Ors(enable_cond, ii_stall_cond) - depth = self.iteration_interval - 1 + depth = self.initiation_interval - 1 inst = mul.get_mul(width, width, signed, rsigned, depth) clk = m._clock @@ -3336,13 +3336,13 @@ def _implement(self, m, seq, svalid=None, senable=None): else: value = odata - seq(data(value), cond=ii_count == self.iteration_interval - 1) + seq(data(value), cond=ii_count == self.initiation_interval - 1) class ReduceDiv(_Accumulator): latency = 1 - iteration_interval = 32 + 3 - variable_iteration_interval = 'get_latency' + initiation_interval = 32 + 3 + variable_initiation_interval = 'get_latency' ops = () def get_latency(self): @@ -3361,12 +3361,12 @@ def _implement(self, m, seq, svalid=None, senable=None): raise ValueError("Latency must be '%d', not '%d'" % (self.latency, 1)) - if self.iteration_interval != 1 and self.latency != 1: - raise ValueError("When iteration_interval != 1, latency must be '%d', not '%d'" % + if self.initiation_interval != 1 and self.latency != 1: + raise ValueError("When initiation_interval != 1, latency must be '%d', not '%d'" % (self.latency, 1)) - if self.iteration_interval != 1 and self.strm is None: - raise ValueError("When iteration_interval != 1, strm must be assigned.") + if self.initiation_interval != 1 and self.strm is None: + raise ValueError("When initiation_interval != 1, strm must be assigned.") size_data = self.size.sig_data if self.size is not None else None interval_data = self.interval.sig_data if self.interval is not None else None @@ -3462,7 +3462,7 @@ def _implement(self, m, seq, svalid=None, senable=None): # multicycle control ii_count = m.Reg(self.name('ii_count'), - int(ceil(log(self.iteration_interval, 2))) + 1, initval=0) + int(ceil(log(self.initiation_interval, 2))) + 1, initval=0) ii_stall_cond = m.Wire(self.name('ii_stall_cond')) ii_stall_cond.assign(ii_count > 0) util.add_disable_cond(self.strm.internal_oready, ii_stall_cond, vtypes.Int(0)) @@ -3473,7 +3473,7 @@ def _implement(self, m, seq, svalid=None, senable=None): seq.If(ii_count > 0)( ii_count.inc() ) - seq.If(ii_count == self.iteration_interval - 1)( + seq.If(ii_count == self.initiation_interval - 1)( ii_count(0) ) @@ -3504,7 +3504,7 @@ def _implement(self, m, seq, svalid=None, senable=None): value = odata - seq(data(value), cond=ii_count == self.iteration_interval - 1) + seq(data(value), cond=ii_count == self.initiation_interval - 1) class ReduceMax(_Accumulator): @@ -3630,6 +3630,62 @@ def _implement(self, m, seq, svalid=None, senable=None): seq(count(next_count_value), cond=enable_cond) +class RandXorshift(_Accumulator): + + def __init__(self, reg_initval=0x12345678, dependency=None, enable=None, width=32): + + right = 0 + size = None + interval = None + initval = None + offset = None + reset = None + signed = False + + _Accumulator.__init__(self, right, size, interval, initval, offset, + dependency, enable, reset, reg_initval, width, signed) + self.graph_label = 'RandXorshift' + + def _implement(self, m, seq, svalid=None, senable=None): + if self.latency != 1: + raise ValueError("Latency mismatch '%d' vs '%s'" % + (self.latency, 1)) + + width = self.get_width() + signed = self.get_signed() + + reg_initval_data = self.reg_initval.sig_data + + data = m.Reg(self.name('data'), width, + initval=reg_initval_data, signed=signed) + + randval = m.Reg(self.name('randval'), width, + initval=reg_initval_data, signed=signed) + + self.sig_data = data + + enabledata = self.enable.sig_data if self.enable is not None else None + + if width == 32: + next_value = randval ^ (randval << 13) + next_value = next_value ^ (next_value >> 17) + next_value = next_value ^ (next_value << 5) + elif width == 64: + next_value = randval ^ (randval << 13) + next_value = next_value ^ (next_value >> 7) + next_value = next_value ^ (next_value << 17) + else: + raise ValueError("Invalid width value '%d', please specify 32 or 64" % width) + + enable_cond = _and_vars(svalid, senable) + + if self.enable is not None: + enable_cond = _and_vars(enable_cond, enabledata) + + seq(data(randval), cond=enable_cond) + seq(randval(next_value), cond=enable_cond) + + class Pulse(_Accumulator): ops = () @@ -3801,7 +3857,7 @@ def _implement(self, m, seq, svalid=None, senable=None): arg_data = [arg.sig_data for arg in self.args] enable_cond = senable - if self.iteration_interval != 1: + if self.initiation_interval != 1: enable_cond = _and_vars(enable_cond, svalid) resetdata = arg_data[-1] if self.reset is not None else None @@ -3832,9 +3888,9 @@ def _implement(self, m, seq, svalid=None, senable=None): seq(var(initval), cond=reset_cond) # multicycle control - if self.iteration_interval != 1: + if self.initiation_interval != 1: ii_count = m.Reg(self.name('ii_count'), - int(ceil(log(self.iteration_interval, 2))) + 1, initval=0) + int(ceil(log(self.initiation_interval, 2))) + 1, initval=0) ii_stall_cond = m.Wire(self.name('ii_stall_cond')) ii_stall_cond.assign(ii_count > 0) util.add_disable_cond(self.strm.internal_oready, @@ -3846,7 +3902,7 @@ def _implement(self, m, seq, svalid=None, senable=None): seq.If(ii_count > 0)( ii_count.inc() ) - seq.If(ii_count == self.iteration_interval - 1)( + seq.If(ii_count == self.initiation_interval - 1)( ii_count(0) ) @@ -3989,9 +4045,9 @@ def __init__(self, child, strm=None): self.graph_label = child.name if hasattr(child, 'name') else 'SubstreamMultiCycle' # conservative scheduling - # self.iteration_interval = self.latency - 1 + # self.initiation_interval = self.latency - 1 # aggressive scheduling - self.iteration_interval = self.latency - 1 - 1 + self.initiation_interval = self.latency - 1 - 1 self.latency = 1 + 1 def _implement(self, m, seq, svalid=None, senable=None): @@ -3999,7 +4055,7 @@ def _implement(self, m, seq, svalid=None, senable=None): # multicycle control ii_count = m.Reg(self.name('ii_count'), - int(ceil(log(self.iteration_interval, 2))) + 1, initval=0) + int(ceil(log(self.initiation_interval, 2))) + 1, initval=0) ii_stall_cond = m.Wire(self.name('ii_stall_cond')) ii_stall_cond.assign(ii_count > 0) util.add_disable_cond(self.strm.internal_oready, ii_stall_cond, vtypes.Int(0)) @@ -4023,7 +4079,7 @@ def _implement(self, m, seq, svalid=None, senable=None): seq.If(ii_count > 0, self.child.internal_oready)( ii_count.inc() ) - seq.If(ii_count == self.iteration_interval - 1, self.child.internal_oready)( + seq.If(ii_count == self.initiation_interval - 1, self.child.internal_oready)( ii_count(0) ) diff --git a/veriloggen/stream/visitor.py b/veriloggen/stream/visitor.py index 2513d4cb..6e9ae731 100644 --- a/veriloggen/stream/visitor.py +++ b/veriloggen/stream/visitor.py @@ -111,7 +111,7 @@ def visit__Accumulator(self, node): reset = (self.visit(node.reset) if node.reset is not None else set()) reg_initval = (self.visit(node.reg_initval) - if node.reg_initval is not None else set()) + if node.reg_initval is not None else set()) return right | size | interval | initval | offset | dependency | enable | reset | reg_initval def visit__ParameterVariable(self, node): @@ -163,7 +163,7 @@ def visit__Accumulator(self, node): reset = (self.visit(node.reset) if node.reset is not None else set()) reg_initval = (self.visit(node.reg_initval) - if node.reg_initval is not None else set()) + if node.reg_initval is not None else set()) mine = set([node]) if node._has_output() else set() return right | size | interval | initval | offset | dependency | enable | reset | reg_initval | mine @@ -219,7 +219,7 @@ def visit__Accumulator(self, node): reset = (self.visit(node.reset) if node.reset is not None else set()) reg_initval = (self.visit(node.reg_initval) - if node.reg_initval is not None else set()) + if node.reg_initval is not None else set()) mine = set([node]) return right | size | interval | initval | offset | dependency | enable | reset | reg_initval | mine diff --git a/veriloggen/thread/axim.py b/veriloggen/thread/axim.py index aee5ca65..41c6c161 100644 --- a/veriloggen/thread/axim.py +++ b/veriloggen/thread/axim.py @@ -43,10 +43,12 @@ def __init__(self, m, name, clk, rst, datawidth=32, addrwidth=32, waddr_prot_mode=axi.AxPROT_NONCOHERENT, raddr_prot_mode=axi.AxPROT_NONCOHERENT, waddr_user_mode=axi.AxUSER_NONCOHERENT, wdata_user_mode=axi.xUSER_DEFAULT, raddr_user_mode=axi.AxUSER_NONCOHERENT, - noio=False, + noio=False, sb_depth=1, use_global_base_addr=False, - op_sel_width=8, req_fifo_addrwidth=3, fsm_as_module=False): + op_sel_width=8, req_fifo_addrwidth=3, + fsm_as_module=False): + outstanding_wcount_width = req_fifo_addrwidth axi.AxiMaster.__init__(self, m, name, clk, rst, datawidth, addrwidth, waddr_id_width, wdata_id_width, wresp_id_width, raddr_id_width, rdata_id_width, @@ -57,7 +59,7 @@ def __init__(self, m, name, clk, rst, datawidth=32, addrwidth=32, waddr_prot_mode, raddr_prot_mode, waddr_user_mode, wdata_user_mode, raddr_user_mode, - noio, req_fifo_addrwidth) + noio, outstanding_wcount_width, sb_depth) self.use_global_base_addr = use_global_base_addr self.op_sel_width = op_sel_width @@ -1807,14 +1809,15 @@ class AXIMLite(axi.AxiLiteMaster, _MutexFunction): def __init__(self, m, name, clk, rst, datawidth=32, addrwidth=32, waddr_cache_mode=axi.AxCACHE_NONCOHERENT, raddr_cache_mode=axi.AxCACHE_NONCOHERENT, waddr_prot_mode=axi.AxPROT_NONCOHERENT, raddr_prot_mode=axi.AxPROT_NONCOHERENT, - noio=False, + noio=False, sb_depth=1, use_global_base_addr=False, fsm_as_module=False): + outstanding_wcount_width = 3 axi.AxiLiteMaster.__init__(self, m, name, clk, rst, datawidth, addrwidth, waddr_cache_mode, raddr_cache_mode, waddr_prot_mode, raddr_prot_mode, - noio) + noio, outstanding_wcount_width, sb_depth) self.use_global_base_addr = use_global_base_addr self.fsm_as_module = fsm_as_module diff --git a/veriloggen/thread/axistreamout.py b/veriloggen/thread/axistreamout.py index 2635a4ca..71c546cb 100644 --- a/veriloggen/thread/axistreamout.py +++ b/veriloggen/thread/axistreamout.py @@ -58,7 +58,7 @@ def __init__(self, m, name, clk, rst, datawidth=32, addrwidth=32, 'write_local_stride_fifo']), self.addrwidth) self.write_size_fifo = self.m.Wire('_'.join(['', self.name, - 'write_size_fifo']), + 'write_size_fifo']), self.addrwidth + 1) write_unpack_values = self.unpack_write_req(self.write_req_fifo.rdata) @@ -539,7 +539,7 @@ def __init__(self, m, name, clk, rst, datawidth=32, addrwidth=32, 'write_op_sel_fifo']), self.op_sel_width) self.write_size_fifo = self.m.Wire('_'.join(['', self.name, - 'write_size_fifo']), + 'write_size_fifo']), self.addrwidth + 1) write_unpack_values = self.unpack_write_req(self.write_req_fifo.rdata) @@ -615,7 +615,7 @@ def _set_write_request(self, fifo, start, size): vtypes.Not(self.write_req_fifo.almost_full)) _ = self.write_req_fifo.enq_rtl(self.pack_write_req(op_id, - local_size), + local_size), cond=enq_cond) def _synthesize_write_data_fsm(self, fifo, fifo_datawidth): @@ -669,7 +669,7 @@ def _synthesize_write_data_fsm_same(self, fifo, fifo_datawidth): # Data state 1 cur_rvalid = self.m.TmpWire(prefix='cur_rvalid') - #rready = vtypes.Ands(vtypes.Ors(self.tdata.tready, vtypes.Not(self.tdata.tvalid)), + # rready = vtypes.Ands(vtypes.Ors(self.tdata.tready, vtypes.Not(self.tdata.tvalid)), # self.write_size_buf > 0) rready = vtypes.Ors(self.tdata.tready, vtypes.Not(self.tdata.tvalid)) deq_cond = vtypes.Ands(data_fsm.here, vtypes.Not(fifo.empty), @@ -751,7 +751,7 @@ def _synthesize_write_data_fsm_narrow(self, fifo, fifo_datawidth): # Data state 1 cur_rvalid = self.m.TmpWire(prefix='cur_rvalid') - #rready = vtypes.Ands(vtypes.Ors(self.tdata.tready, vtypes.Not(self.tdata.tvalid)), + # rready = vtypes.Ands(vtypes.Ors(self.tdata.tready, vtypes.Not(self.tdata.tvalid)), # self.write_size_buf > 0) rready = vtypes.Ors(self.tdata.tready, vtypes.Not(self.tdata.tvalid)) deq_cond = vtypes.Ands(data_fsm.here, vtypes.Not(fifo.empty), diff --git a/veriloggen/thread/compiler.py b/veriloggen/thread/compiler.py index 8769d8c0..5bdd1b24 100644 --- a/veriloggen/thread/compiler.py +++ b/veriloggen/thread/compiler.py @@ -471,6 +471,25 @@ def _call_Name_print(self, node): formatstring_list.append(form) formatstring_list.append(" ") + elif (sys.version_info >= (3, 6) and + isinstance(arg, ast.JoinedStr)): + # Formatted String Literals (f-strings) in print statement + values, form = self._print_f_strings(arg) + + for value in values: + if isinstance(value, fxd._FixedBase): + if value.point >= 0: + argvalues.append(vtypes.Div(vtypes.SystemTask('itor', value), + 1.0 * (2 ** value.point))) + else: + argvalues.append(vtypes.Times(value, 2 ** -value.point)) + + else: + argvalues.append(value) + + formatstring_list.append(form) + formatstring_list.append(" ") + elif isinstance(arg, ast.Tuple): for e in arg.elts: value = self.visit(e) @@ -535,6 +554,27 @@ def _print_binop_mod(self, arg): form = arg.left.s return values, form + def _print_f_strings(self, arg): + values = [] + form = '' + for val in arg.values: + if isinstance(val, ast.Constant): + form += val.value + elif isinstance(val, ast.FormattedValue): + values.append(self.visit(val.value)) + if val.format_spec: + # no guarantee if a simulator accepts it or not + if len(val.format_spec.values) == 1: + # e.g. f"{reg0:x} {reg1:0b}" + form += '%' + val.format_spec.values[0].value + else: + # do not allow nested f-strings + raise SyntaxError('Illegal format_spec of f-strings') + else: + # interpret as integer by default + form += '%d' + return values, form + def _call_Name_int(self, node): if len(node.args) > 1: raise TypeError( diff --git a/veriloggen/thread/ram.py b/veriloggen/thread/ram.py index 05e75a0d..feafe521 100644 --- a/veriloggen/thread/ram.py +++ b/veriloggen/thread/ram.py @@ -948,7 +948,7 @@ def __init__(self, src=None, name=None, keep_hierarchy=False): if not isinstance(ram, MultibankRAM) and isinstance(first, MultibankRAM): raise ValueError('RAM type must be same') if (isinstance(ram, MultibankRAM) and isinstance(first, MultibankRAM) and - ram.numbanks != first.numbanks): + ram.numbanks != first.numbanks): raise ValueError('numbanks must be same') self.m = src[0].m diff --git a/veriloggen/thread/thread.py b/veriloggen/thread/thread.py index 467b787a..eafdcf2f 100644 --- a/veriloggen/thread/thread.py +++ b/veriloggen/thread/thread.py @@ -174,7 +174,7 @@ def ret(self, fsm): return self.return_value - #-------------------------------------------------------------------------- + # -------------------------------------------------------------------------- def add_function(self, func): name = func.__name__ if name in self.function_lib: diff --git a/veriloggen/types/axi.py b/veriloggen/types/axi.py index f9b68ca8..bcb720b6 100644 --- a/veriloggen/types/axi.py +++ b/veriloggen/types/axi.py @@ -15,6 +15,7 @@ from veriloggen.seq.seq import make_condition from . import util +from .skidbuffer import SkidBuffer BURST_FIXED = 0b00 @@ -375,44 +376,816 @@ def __init__(self, m, name=None, datawidth=32, addrwidth=32, # AXI-Full Master class AxiMasterWriteAddress(AxiWriteAddress): - pass + + def __init__(self, m, name, clk, rst, datawidth=32, addrwidth=32, + id_width=0, user_width=2, + burst_mode=BURST_INCR, cache_mode=AxCACHE_NONCOHERENT, + prot_mode=AxPROT_NONCOHERENT, user_mode=AxUSER_NONCOHERENT, + itype=None, otype=None): + + AxiWriteAddress.__init__(self, m, name, datawidth, addrwidth, + id_width, user_width, itype, otype) + + self.clk = clk + self.rst = rst + self.seq = Seq(m, name + '_waddr', clk, rst) + + # default values + self.awsize.assign(int(math.log(self.datawidth / 8, 2))) + self.awburst.assign(burst_mode) + self.awlock.assign(0) + self.awcache.assign(cache_mode) + self.awprot.assign(prot_mode) + self.awqos.assign(0) + if self.awuser is not None: + self.awuser.assign(user_mode) + + def disable_write(self): + ports = [self.awaddr(0), + self.awlen(0), + self.awvalid(0)] + + if self.awid is not None: + ports.insert(0, self.awid(0)) + + self.seq( + *ports + ) + + def write_request(self, addr, acceptable, length=1, cond=None): + """ + @return ack + """ + if cond is not None: + self.seq.If(cond) + + ack = vtypes.Ands(acceptable, + vtypes.Ors(self.awready, vtypes.Not(self.awvalid))) + + self.seq.If(ack)( + self.awid(0) if self.awid is not None else (), + self.awaddr(addr), + self.awlen(length - 1), + self.awvalid(1) + ) + self.seq.Then().If(length == 0)( + self.awvalid(0) + ) + + # de-assert + self.seq.Delay(1)( + self.awvalid(0) + ) + + # retry + self.seq.If(vtypes.Ands(self.awvalid, vtypes.Not(self.awready)))( + self.awvalid(self.awvalid) + ) + + return ack + + def connect(self, ports, name): + if '_'.join([name, 'awid']) in ports: + awid = ports['_'.join([name, 'awid'])] + else: + awid = None + awaddr = ports['_'.join([name, 'awaddr'])] + awlen = ports['_'.join([name, 'awlen'])] + awsize = ports['_'.join([name, 'awsize'])] + awburst = ports['_'.join([name, 'awburst'])] + awlock = ports['_'.join([name, 'awlock'])] + awcache = ports['_'.join([name, 'awcache'])] + awprot = ports['_'.join([name, 'awprot'])] + awqos = ports['_'.join([name, 'awqos'])] + if '_'.join([name, 'awuser']) in ports: + awuser = ports['_'.join([name, 'awuser'])] + else: + awuser = None + awvalid = ports['_'.join([name, 'awvalid'])] + awready = ports['_'.join([name, 'awready'])] + + if awid is not None: + awid.connect(self.awid if self.awid is not None else 0) + awaddr.connect(self.awaddr) + awlen.connect(self.awlen) + awsize.connect(self.awsize) + awburst.connect(self.awburst) + awlock.connect(self.awlock) + awcache.connect(self.awcache) + awprot.connect(self.awprot) + awqos.connect(self.awqos) + if awuser is not None: + awuser.connect(self.awuser if self.awuser is not None else 0) + awvalid.connect(self.awvalid) + self.awready.connect(awready) class AxiMasterWriteData(AxiWriteData): - pass + _O = util.t_Output + + def __init__(self, m, name, clk, rst, datawidth=32, addrwidth=32, + id_width=0, user_width=0, + user_mode=xUSER_DEFAULT, + sb_depth=1, + itype=None, otype=None): + + if sb_depth < 1: + raise ValueError('sb_depth must be equal to or greater than 1.') + + AxiWriteData.__init__(self, m, name, datawidth, addrwidth, + id_width, user_width, itype, otype) + + self.clk = clk + self.rst = rst + self.seq = Seq(m, name + '_wdata', clk, rst) + + # default values + if self.wuser is not None: + self.wuser.assign(user_mode) + + # save AXI-side references for skid buffer + self.ext_wdata = self.wdata + self.ext_wstrb = self.wstrb + self.ext_wlast = self.wlast + self.ext_wvalid = self.wvalid + self.ext_wready = self.wready + + # multi-stage skid buffer + for i in range(sb_depth): + # user-side signals before skidbuffer + method = m.WireLike if i < sb_depth - 1 else m.RegLike + kwargs = {} if i < sb_depth - 1 else {'initval': 0} + index = str(sb_depth - i - 1) + + wdata = method(self.wdata, + name='_'.join(['', name, 'wdata', 'sb', index]), + **kwargs) + wstrb = method(self.wstrb, + name='_'.join(['', name, 'wstrb', 'sb', index]), + **kwargs) + wlast = method(self.wlast, + name='_'.join(['', name, 'wlast', 'sb', index]), + **kwargs) + wvalid = method(self.wvalid, + name='_'.join(['', name, 'wvalid', 'sb', index]), + **kwargs) + wready = m.WireLike(self.wready, + name='_'.join(['', name, 'wready', 'sb', index])) + + # skidbuffer + sb = SkidBuffer(m, clk, rst, + wvalid, self.wready, *[wlast, wstrb, wdata], + prefix='_'.join(['', 'sb', name, 'writedata'])) + wready.assign(sb.ready) + + # AXI-side signals after skidbuffer + self.wdata.assign(sb[2]) + self.wstrb.assign(sb[1]) + self.wlast.assign(sb[0]) + self.wvalid.assign(sb.valid) + + # update references for user-side + self.wdata = wdata + self.wstrb = wstrb + self.wlast = wlast + self.wvalid = wvalid + self.wready = wready + + def disable_write(self): + ports = [self.wdata(0), + self.wstrb(0), + self.wlast(0), + self.wvalid(0)] + + self.seq( + *ports + ) + + def write_data(self, data, last, cond=None): + """ + @return ack + """ + if cond is not None: + self.seq.If(cond) + + ack = vtypes.Ors(self.wready, vtypes.Not(self.wvalid)) + + self.seq.If(ack)( + self.wdata(data), + self.wvalid(1), + self.wlast(last), + self.wstrb(vtypes.Repeat( + vtypes.Int(1, 1), (self.datawidth // 8))), + ) + + # de-assert + self.seq.Delay(1)( + self.wvalid(0), + self.wlast(0), + ) + + # retry + self.seq.If(vtypes.Ands(self.wvalid, vtypes.Not(self.wready)))( + self.wvalid(self.wvalid), + self.wlast(self.wlast), + ) + + return ack + + def connect(self, ports, name): + wdata = ports['_'.join([name, 'wdata'])] + wstrb = ports['_'.join([name, 'wstrb'])] + wlast = ports['_'.join([name, 'wlast'])] + if '_'.join([name, 'wuser']) in ports: + wuser = ports['_'.join([name, 'wuser'])] + else: + wuser = None + wvalid = ports['_'.join([name, 'wvalid'])] + wready = ports['_'.join([name, 'wready'])] + + wdata.connect(self.ext_wdata) + wstrb.connect(self.ext_wstrb) + wlast.connect(self.ext_wlast) + if wuser is not None: + wuser.connect(self.wuser if self.wuser is not None else 0) + wvalid.connect(self.ext_wvalid) + self.ext_wready.connect(wready) class AxiMasterWriteResponse(AxiWriteResponse): - pass + + def __init__(self, m, name, clk, rst, datawidth=32, addrwidth=32, + id_width=0, user_width=0, + itype=None, otype=None): + + AxiWriteResponse.__init__(self, m, name, datawidth, addrwidth, + id_width, user_width, itype, otype) + + self.clk = clk + self.rst = rst + + # default values + self.bready.assign(1) + + def connect(self, ports, name): + if '_'.join([name, 'bid']) in ports: + bid = ports['_'.join([name, 'bid'])] + else: + bid = None + bresp = ports['_'.join([name, 'bresp'])] + if '_'.join([name, 'buser']) in ports: + buser = ports['_'.join([name, 'buser'])] + else: + buser = None + bvalid = ports['_'.join([name, 'bvalid'])] + bready = ports['_'.join([name, 'bready'])] + + if self.bid is not None: + self.bid.connect(bid if bid is not None else 0) + self.bresp.connect(bresp) + if self.buser is not None: + self.buser.connect(buser if buser is not None else 0) + self.bvalid.connect(bvalid) + bready.connect(self.bready) class AxiMasterReadAddress(AxiReadAddress): - pass + + def __init__(self, m, name, clk, rst, datawidth=32, addrwidth=32, + id_width=0, user_width=2, + burst_mode=BURST_INCR, cache_mode=AxCACHE_NONCOHERENT, + prot_mode=AxPROT_NONCOHERENT, user_mode=AxUSER_NONCOHERENT, + itype=None, otype=None): + + AxiReadAddress.__init__(self, m, name, datawidth, addrwidth, + id_width, user_width, itype, otype) + + self.clk = clk + self.rst = rst + self.seq = Seq(m, name + '_raddr', clk, rst) + + # default values + self.arsize.assign(int(math.log(self.datawidth / 8, 2))) + self.arburst.assign(burst_mode) + self.arlock.assign(0) + self.arcache.assign(cache_mode) + self.arprot.assign(prot_mode) + self.arqos.assign(0) + if self.aruser is not None: + self.aruser.assign(user_mode) + + def disable_read(self): + ports = [self.araddr(0), + self.arlen(0), + self.arvalid(0)] + + if self.arid is not None: + ports.insert(0, self.arid(0)) + + self.seq( + *ports + ) + + def read_request(self, addr, length=1, cond=None): + """ + @return ack + """ + if cond is not None: + self.seq.If(cond) + + ack = vtypes.Ors(self.arready, vtypes.Not(self.arvalid)) + + self.seq.If(ack)( + self.arid(0) if self.arid is not None else (), + self.araddr(addr), + self.arlen(length - 1), + self.arvalid(1) + ) + + # de-assert + self.seq.Delay(1)( + self.arvalid(0) + ) + + # retry + self.seq.If(vtypes.Ands(self.arvalid, vtypes.Not(self.arready)))( + self.arvalid(self.arvalid) + ) + + return ack + + def connect(self, ports, name): + if '_'.join([name, 'arid']) in ports: + arid = ports['_'.join([name, 'arid'])] + else: + arid = None + araddr = ports['_'.join([name, 'araddr'])] + arlen = ports['_'.join([name, 'arlen'])] + arsize = ports['_'.join([name, 'arsize'])] + arburst = ports['_'.join([name, 'arburst'])] + arlock = ports['_'.join([name, 'arlock'])] + arcache = ports['_'.join([name, 'arcache'])] + arprot = ports['_'.join([name, 'arprot'])] + arqos = ports['_'.join([name, 'arqos'])] + if '_'.join([name, 'aruser']) in ports: + aruser = ports['_'.join([name, 'aruser'])] + else: + aruser = None + arvalid = ports['_'.join([name, 'arvalid'])] + arready = ports['_'.join([name, 'arready'])] + + if arid is not None: + arid.connect(self.arid if self.arid is not None else 0) + araddr.connect(self.araddr) + arlen.connect(self.arlen) + arsize.connect(self.arsize) + arburst.connect(self.arburst) + arlock.connect(self.arlock) + arcache.connect(self.arcache) + arprot.connect(self.arprot) + arqos.connect(self.arqos) + if aruser is not None: + aruser.connect(self.aruser if self.aruser is not None else 0) + arvalid.connect(self.arvalid) + self.arready.connect(arready) class AxiMasterReadData(AxiReadData): - pass + + def __init__(self, m, name, clk, rst, datawidth=32, addrwidth=32, + id_width=0, user_width=0, + sb_depth=1, + itype=None, otype=None): + + if sb_depth < 1: + raise ValueError('sb_depth must be equal to or greater than 1.') + + AxiReadData.__init__(self, m, name, datawidth, addrwidth, + id_width, user_width, itype, otype) + + self.clk = clk + self.rst = rst + + # save AXI-side references for skid buffer + self.ext_rdata = self.rdata + self.ext_rlast = self.rlast + self.ext_rvalid = self.rvalid + self.ext_rready = self.rready + + # multi-stage skid buffer + for i in range(sb_depth): + # user-side signals before skidbuffer + index = str(sb_depth - i - 1) + + rdata = m.WireLike(self.rdata, + name='_'.join(['', name, 'rdata', 'sb', index])) + rlast = m.WireLike(self.rlast, + name='_'.join(['', name, 'rlast', 'sb', index])) + rvalid = m.WireLike(self.rvalid, + name='_'.join(['', name, 'rvalid', 'sb', index])) + rready = m.WireLike(self.rready, + name='_'.join(['', name, 'rready', 'sb', index])) + + # skidbuffer + sb = SkidBuffer(m, clk, rst, + self.rvalid, rready, *[self.rlast, self.rdata], + prefix='_'.join(['', 'sb', name, 'readdata'])) + rdata.assign(sb[1]) + rlast.assign(sb[0]) + rvalid.assign(sb.valid) + + # AXI-side signals after skidbuffer + self.rready.assign(sb.ready) + + # update references for user-side + self.rdata = rdata + self.rlast = rlast + self.rvalid = rvalid + self.rready = rready + + def disable_read(self): + self.rready.assign(0) + + def read_data(self, cond=None): + """ + @return data, valid, last + """ + ready = make_condition(cond) + val = 1 if ready is None else ready + + _connect_ready(self.rready._get_module(), self.rready, val) + + data = self.rdata + valid = self.rvalid + last = self.rlast + + return data, valid, last + + def connect(self, ports, name): + if '_'.join([name, 'rid']) in ports: + rid = ports['_'.join([name, 'rid'])] + else: + rid = None + rdata = ports['_'.join([name, 'rdata'])] + rresp = ports['_'.join([name, 'rresp'])] + rlast = ports['_'.join([name, 'rlast'])] + if '_'.join([name, 'ruser']) in ports: + ruser = ports['_'.join([name, 'ruser'])] + else: + ruser = None + rvalid = ports['_'.join([name, 'rvalid'])] + rready = ports['_'.join([name, 'rready'])] + + if self.rid is not None: + self.rid.connect(rid if rid is not None else 0) + self.ext_rdata.connect(rdata) + self.rresp.connect(rresp) + self.ext_rlast.connect(rlast) + if self.ruser is not None: + self.ruser.connect(ruser if ruser is not None else 0) + self.ext_rvalid.connect(rvalid) + rready.connect(self.ext_rready) # AXI-Lite Master class AxiLiteMasterWriteAddress(AxiLiteWriteAddress): - pass + def __init__(self, m, name, clk, rst, datawidth=32, addrwidth=32, + cache_mode=AxCACHE_NONCOHERENT, prot_mode=AxPROT_NONCOHERENT, + itype=None, otype=None): -class AxiLiteMasterWriteData(AxiLiteWriteData): - pass - + AxiLiteWriteAddress.__init__(self, m, name, datawidth, addrwidth, + itype, otype) -class AxiLiteMasterWriteResponse(AxiLiteWriteResponse): - pass + self.clk = clk + self.rst = rst + self.seq = Seq(m, name + '_waddr', clk, rst) + # default values + self.awcache.assign(cache_mode) + self.awprot.assign(prot_mode) -class AxiLiteMasterReadAddress(AxiLiteReadAddress): - pass + def disable_write(self): + ports = [self.awaddr(0), + self.awvalid(0)] + self.seq( + *ports + ) -class AxiLiteMasterReadData(AxiLiteReadData): - pass + def write_request(self, addr, acceptable, length=1, cond=None): + """ + @return ack + """ + if cond is not None: + self.seq.If(cond) + + ack = vtypes.Ands(acceptable, + vtypes.Ors(self.awready, vtypes.Not(self.awvalid))) + + self.seq.If(ack)( + self.awaddr(addr), + self.awvalid(1), + ) + + # de-assert + self.seq.Delay(1)( + self.awvalid(0) + ) + + # retry + self.seq.If(vtypes.Ands(self.awvalid, vtypes.Not(self.awready)))( + self.awvalid(self.awvalid) + ) + + return ack + + def connect(self, ports, name): + awaddr = ports['_'.join([name, 'awaddr'])] + awcache = ports['_'.join([name, 'awcache'])] + awprot = ports['_'.join([name, 'awprot'])] + awvalid = ports['_'.join([name, 'awvalid'])] + awready = ports['_'.join([name, 'awready'])] + + awaddr.connect(self.awaddr) + awcache.connect(self.awcache) + awprot.connect(self.awprot) + awvalid.connect(self.awvalid) + self.awready.connect(awready) + + +class AxiLiteMasterWriteData(AxiLiteWriteData): + _O = util.t_Output + + def __init__(self, m, name, clk, rst, datawidth=32, addrwidth=32, + sb_depth=1, + itype=None, otype=None): + + if sb_depth < 1: + raise ValueError('sb_depth must be equal to or greater than 1.') + + AxiLiteWriteData.__init__(self, m, name, datawidth, addrwidth, + itype, otype) + + self.clk = clk + self.rst = rst + self.seq = Seq(m, name + '_wdata', clk, rst) + + # save AXI-side references for skid buffer + self.ext_wdata = self.wdata + self.ext_wstrb = self.wstrb + self.ext_wvalid = self.wvalid + self.ext_wready = self.wready + + # multi-stage skid buffer + for i in range(sb_depth): + # user-side signals before skidbuffer + method = m.WireLike if i < sb_depth - 1 else m.RegLike + kwargs = {} if i < sb_depth - 1 else {'initval': 0} + index = str(sb_depth - i - 1) + + wdata = method(self.wdata, + name='_'.join(['', name, 'wdata', 'sb', index]), + **kwargs) + wstrb = method(self.wstrb, + name='_'.join(['', name, 'wstrb', 'sb', index]), + **kwargs) + wvalid = method(self.wvalid, + name='_'.join(['', name, 'wvalid', 'sb', index]), + **kwargs) + wready = m.WireLike(self.wready, + name='_'.join(['', name, 'wready', 'sb', index])) + + # skidbuffer + sb = SkidBuffer(m, clk, rst, + wvalid, self.wready, *[wstrb, wdata], + prefix='_'.join(['', 'sb', name, 'writedata'])) + wready.assign(sb.ready) + + # AXI-side signals after skidbuffer + self.wdata.assign(sb[1]) + self.wstrb.assign(sb[0]) + self.wvalid.assign(sb.valid) + + # update references for user-side + self.wdata = wdata + self.wstrb = wstrb + self.wvalid = wvalid + self.wready = wready + + def disable_write(self): + ports = [self.wdata(0), + self.wstrb(0), + self.wvalid(0)] + + self.seq( + *ports + ) + + def write_data(self, data, cond=None): + """ + @return ack + """ + if cond is not None: + self.seq.If(cond) + + ack = vtypes.Ors(self.wready, vtypes.Not(self.wvalid)) + + self.seq.If(ack)( + self.wdata(data), + self.wvalid(1), + self.wstrb(vtypes.Repeat( + vtypes.Int(1, 1), (self.datawidth // 8))) + ) + + # de-assert + self.seq.Delay(1)( + self.wvalid(0), + ) + + # retry + self.seq.If(vtypes.Ands(self.wvalid, vtypes.Not(self.wready)))( + self.wvalid(self.wvalid) + ) + + return ack + + def connect(self, ports, name): + wdata = ports['_'.join([name, 'wdata'])] + wstrb = ports['_'.join([name, 'wstrb'])] + wvalid = ports['_'.join([name, 'wvalid'])] + wready = ports['_'.join([name, 'wready'])] + + wdata.connect(self.ext_wdata) + wstrb.connect(self.ext_wstrb) + wvalid.connect(self.ext_wvalid) + self.ext_wready.connect(wready) + + +class AxiLiteMasterWriteResponse(AxiLiteWriteResponse): + + def __init__(self, m, name, clk, rst, datawidth=32, addrwidth=32, + itype=None, otype=None): + + AxiLiteWriteResponse.__init__(self, m, name, datawidth, addrwidth, + itype, otype) + + self.clk = clk + self.rst = rst + + # default values + self.bready.assign(1) + + def connect(self, ports, name): + bresp = ports['_'.join([name, 'bresp'])] + bvalid = ports['_'.join([name, 'bvalid'])] + bready = ports['_'.join([name, 'bready'])] + + self.bresp.connect(bresp) + self.bvalid.connect(bvalid) + bready.connect(self.bready) + + +class AxiLiteMasterReadAddress(AxiLiteReadAddress): + + def __init__(self, m, name, clk, rst, datawidth=32, addrwidth=32, + cache_mode=AxCACHE_NONCOHERENT, prot_mode=AxPROT_NONCOHERENT, + itype=None, otype=None): + + AxiLiteReadAddress.__init__(self, m, name, datawidth, addrwidth, + itype, otype) + + self.clk = clk + self.rst = rst + self.seq = Seq(m, name + '_raddr', clk, rst) + + # default values + self.arcache.assign(cache_mode) + self.arprot.assign(prot_mode) + + def disable_read(self): + ports = [self.araddr(0), + self.arvalid(0)] + + self.seq( + *ports + ) + + def read_request(self, addr, length=1, cond=None): + """ + @return ack + """ + if cond is not None: + self.seq.If(cond) + + ack = vtypes.Ors(self.arready, vtypes.Not(self.arvalid)) + + self.seq.If(ack)( + self.araddr(addr), + self.arvalid(1) + ) + + # de-assert + self.seq.Delay(1)( + self.arvalid(0) + ) + + # retry + self.seq.If(vtypes.Ands(self.arvalid, vtypes.Not(self.arready)))( + self.arvalid(self.arvalid) + ) + + return ack + + def connect(self, ports, name): + araddr = ports['_'.join([name, 'araddr'])] + arcache = ports['_'.join([name, 'arcache'])] + arprot = ports['_'.join([name, 'arprot'])] + arvalid = ports['_'.join([name, 'arvalid'])] + arready = ports['_'.join([name, 'arready'])] + + araddr.connect(self.araddr) + arcache.connect(self.arcache) + arprot.connect(self.arprot) + arvalid.connect(self.arvalid) + self.arready.connect(arready) + + +class AxiLiteMasterReadData(AxiLiteReadData): + + def __init__(self, m, name, clk, rst, datawidth=32, addrwidth=32, + sb_depth=1, + itype=None, otype=None): + + if sb_depth < 1: + raise ValueError('sb_depth must be equal to or greater than 1.') + + AxiLiteReadData.__init__(self, m, name, datawidth, addrwidth, + itype, otype) + + self.clk = clk + self.rst = rst + + # save AXI-side references for skid buffer + self.ext_rdata = self.rdata + self.ext_rvalid = self.rvalid + self.ext_rready = self.rready + + # multi-stage skid buffer + for i in range(sb_depth): + # user-side signals before skidbuffer + index = str(sb_depth - i - 1) + + rdata = m.WireLike(self.rdata, + name='_'.join(['', name, 'rdata', 'sb', index])) + rvalid = m.WireLike(self.rvalid, + name='_'.join(['', name, 'rvalid', 'sb', index])) + rready = m.WireLike(self.rready, + name='_'.join(['', name, 'rready', 'sb', index])) + + # skidbuffer + sb = SkidBuffer(m, clk, rst, + self.rvalid, rready, *[self.rdata], + prefix='_'.join(['', 'sb', name, 'readdata'])) + rdata.assign(sb[0]) + rvalid.assign(sb.valid) + + # AXI-side signals after skidbuffer + self.rready.assign(sb.ready) + + # update references for user-side + self.rdata = rdata + self.rvalid = rvalid + self.rready = rready + + def disable_read(self): + self.rready.assign(0) + + def read_data(self, cond=None): + """ + @return data, valid + """ + ready = make_condition(cond) + val = 1 if ready is None else ready + + _connect_ready(self.rready._get_module(), self.rready, val) + + ack = vtypes.Ands(self.rready, self.rvalid) + data = self.rdata + valid = ack + + return data, valid + + def connect(self, ports, name): + rdata = ports['_'.join([name, 'rdata'])] + rresp = ports['_'.join([name, 'rresp'])] + rvalid = ports['_'.join([name, 'rvalid'])] + rready = ports['_'.join([name, 'rready'])] + + self.ext_rdata.connect(rdata) + self.rresp.connect(rresp) + self.ext_rvalid.connect(rvalid) + rready.connect(self.ext_rready) # AXI-Full Slave @@ -420,57 +1193,486 @@ class AxiSlaveWriteAddress(AxiWriteAddress): _I = util.t_Output _O = util.t_Input + def __init__(self, m, name, clk, rst, datawidth=32, addrwidth=32, + id_width=0, user_width=2, + itype=None, otype=None): + + AxiWriteAddress.__init__(self, m, name, datawidth, addrwidth, + id_width, user_width, itype, otype) + + self.clk = clk + self.rst = rst + + def disable_write(self): + self.awready.assign(0) + + def connect(self, ports, name): + if '_'.join([name, 'awid']) in ports: + awid = ports['_'.join([name, 'awid'])] + else: + awid = None + awaddr = ports['_'.join([name, 'awaddr'])] + awlen = ports['_'.join([name, 'awlen'])] + awsize = ports['_'.join([name, 'awsize'])] + awburst = ports['_'.join([name, 'awburst'])] + awlock = ports['_'.join([name, 'awlock'])] + awcache = ports['_'.join([name, 'awcache'])] + awprot = ports['_'.join([name, 'awprot'])] + awqos = ports['_'.join([name, 'awqos'])] + if '_'.join([name, 'awuser']) in ports: + awuser = ports['_'.join([name, 'awuser'])] + else: + awuser = None + awvalid = ports['_'.join([name, 'awvalid'])] + awready = ports['_'.join([name, 'awready'])] + + if self.awid is not None: + self.awid.connect(awid if awid is not None else 0) + self.awaddr.connect(awaddr) + self.awlen.connect(awlen if awlen is not None else 0) + self.awsize.connect(awsize if awsize is not None else + int(math.log(self.datawidth // 8))) + self.awburst.connect(awburst if awburst is not None else BURST_INCR) + self.awlock.connect(awlock if awlock is not None else 0) + self.awcache.connect(awcache) + self.awprot.connect(awprot) + self.awqos.connect(awqos if awqos is not None else 0) + if self.awuser is not None: + self.awuser.connect(awuser if awuser is not None else 0) + self.awvalid.connect(awvalid) + awready.connect(self.awready) + + +class AxiSlaveWriteData(AxiWriteData): + _I = util.t_Output + _O = util.t_Input + + def __init__(self, m, name, clk, rst, datawidth=32, addrwidth=32, + id_width=0, user_width=0, + itype=None, otype=None): + + AxiWriteData.__init__(self, m, name, datawidth, addrwidth, + id_width, user_width, itype, otype) + + self.clk = clk + self.rst = rst + + def disable_write(self): + self.wready.assign(0) + + def pull_write_data(self, cond=None): + """ + @return data, mask, valid, last + """ + ready = make_condition(cond) + val = 1 if ready is None else ready + + _connect_ready(self.wready._get_module(), self.wready, val) + + data = self.wdata + mask = self.wstrb + valid = self.wvalid + last = self.wlast + + return data, mask, valid, last + + def connect(self, ports, name): + wdata = ports['_'.join([name, 'wdata'])] + wstrb = ports['_'.join([name, 'wstrb'])] + wlast = ports['_'.join([name, 'wlast'])] + if '_'.join([name, 'wuser']) in ports: + wuser = ports['_'.join([name, 'wuser'])] + else: + wuser = None + wvalid = ports['_'.join([name, 'wvalid'])] + wready = ports['_'.join([name, 'wready'])] + + self.wdata.connect(wdata) + self.wstrb.connect(wstrb) + self.wlast.connect(wlast if wlast is not None else 1) + if self.wuser is not None: + self.wuser.connect(wuser if wuser is not None else 0) + self.wvalid.connect(wvalid) + wready.connect(self.wready) + + +class AxiSlaveWriteResponse(AxiWriteResponse): + _I = util.t_OutputReg + _O = util.t_Input + + def __init__(self, m, name, clk, rst, datawidth=32, addrwidth=32, + id_width=0, user_width=0, + user_mode=xUSER_DEFAULT, + itype=None, otype=None): + + AxiWriteResponse.__init__(self, m, name, datawidth, addrwidth, + id_width, user_width, itype, otype) + + self.clk = clk + self.rst = rst + + # default values + self.bresp.assign(0) + if self.buser is not None: + self.buser.assign(user_mode) + + def connect(self, ports, name): + if '_'.join([name, 'bid']) in ports: + bid = ports['_'.join([name, 'bid'])] + else: + bid = None + bresp = ports['_'.join([name, 'bresp'])] + if '_'.join([name, 'buser']) in ports: + buser = ports['_'.join([name, 'buser'])] + else: + buser = None + bvalid = ports['_'.join([name, 'bvalid'])] + bready = ports['_'.join([name, 'bready'])] + + if bid is not None: + bid.connect(self.bid if self.bid is not None else 0) + bresp.connect(self.bresp) + if buser is not None: + buser.connect(self.buser if self.buser is not None else 0) + bvalid.connect(self.bvalid) + self.bready.connect(bready) + + +class AxiSlaveReadAddress(AxiReadAddress): + _I = util.t_Output + _O = util.t_Input + + def __init__(self, m, name, clk, rst, datawidth=32, addrwidth=32, + id_width=0, user_width=2, + itype=None, otype=None): + + AxiReadAddress.__init__(self, m, name, datawidth, addrwidth, + id_width, user_width, itype, otype) + + self.clk = clk + self.rst = rst + + def disable_read(self): + self.arready.assign(0) + + def connect(self, ports, name): + if '_'.join([name, 'arid']) in ports: + arid = ports['_'.join([name, 'arid'])] + else: + arid = None + araddr = ports['_'.join([name, 'araddr'])] + arlen = ports['_'.join([name, 'arlen'])] + arsize = ports['_'.join([name, 'arsize'])] + arburst = ports['_'.join([name, 'arburst'])] + arlock = ports['_'.join([name, 'arlock'])] + arcache = ports['_'.join([name, 'arcache'])] + arprot = ports['_'.join([name, 'arprot'])] + arqos = ports['_'.join([name, 'arqos'])] + if '_'.join([name, 'aruser']) in ports: + aruser = ports['_'.join([name, 'aruser'])] + else: + aruser = None + arvalid = ports['_'.join([name, 'arvalid'])] + arready = ports['_'.join([name, 'arready'])] + + if self.arid is not None: + self.arid.connect(arid if arid is not None else 0) + self.araddr.connect(araddr) + self.arlen.connect(arlen if arlen is not None else 0) + self.arsize.connect(arsize if arsize is not None else + int(math.log(self.datawidth // 8))) + self.arburst.connect(arburst if arburst is not None else BURST_INCR) + self.arlock.connect(arlock if arlock is not None else 0) + self.arcache.connect(arcache) + self.arprot.connect(arprot) + self.arqos.connect(arqos if arqos is not None else 0) + if self.aruser is not None: + self.aruser.connect(aruser if aruser is not None else 0) + self.arvalid.connect(arvalid) + arready.connect(self.arready) + + +class AxiSlaveReadData(AxiReadData): + _I = util.t_OutputReg + _O = util.t_Input + + def __init__(self, m, name, clk, rst, datawidth=32, addrwidth=32, + id_width=0, user_width=0, + user_mode=xUSER_DEFAULT, + itype=None, otype=None): + + AxiReadData.__init__(self, m, name, datawidth, addrwidth, + id_width, user_width, itype, otype) + + self.clk = clk + self.rst = rst + self.seq = Seq(m, name + '_rdata', clk, rst) + + # default values + self.rresp.assign(0) + if self.ruser is not None: + self.ruser.assign(user_mode) + + def disable_read(self): + ports = [self.rvalid(0), + self.rlast(0)] + + self.seq( + *ports + ) + + def push_read_data(self, data, last, cond=None): + """ + @return ack + """ + if cond is not None: + self.seq.If(cond) + + ack = vtypes.Ors(self.rready, vtypes.Not(self.rvalid)) + + self.seq.If(ack)( + self.rdata(data), + self.rvalid(1), + self.rlast(last), + ) + + # de-assert + self.seq.Delay(1)( + self.rvalid(0), + self.rlast(0) + ) + + # retry + self.seq.If(vtypes.Ands(self.rvalid, vtypes.Not(self.rready)))( + self.rvalid(self.rvalid), + self.rlast(self.rlast) + ) + + return ack + + def connect(self, ports, name): + if '_'.join([name, 'rid']) in ports: + rid = ports['_'.join([name, 'rid'])] + else: + rid = None + rdata = ports['_'.join([name, 'rdata'])] + rresp = ports['_'.join([name, 'rresp'])] + rlast = ports['_'.join([name, 'rlast'])] + if '_'.join([name, 'ruser']) in ports: + ruser = ports['_'.join([name, 'ruser'])] + else: + ruser = None + rvalid = ports['_'.join([name, 'rvalid'])] + rready = ports['_'.join([name, 'rready'])] + + if rid is not None: + rid.connect(self.rid if self.rid is not None else 0) + rdata.connect(self.rdata) + rresp.connect(self.rresp) + if rlast is not None: + rlast.connect(self.rlast) + if ruser is not None: + ruser.connect(self.ruser if self.ruser is not None else 0) + rvalid.connect(self.rvalid) + self.rready.connect(rready) + + +# AXI-Lite Slave +class AxiLiteSlaveWriteAddress(AxiLiteWriteAddress): + _I = util.t_Output + _O = util.t_Input + + def __init__(self, m, name, clk, rst, datawidth=32, addrwidth=32, + itype=None, otype=None): + + AxiLiteWriteAddress.__init__(self, m, name, datawidth, addrwidth, + itype, otype) + + self.clk = clk + self.rst = rst + + def disable_write(self): + self.awready.assign(0) + + def connect(self, ports, name): + awaddr = ports['_'.join([name, 'awaddr'])] + awcache = ports['_'.join([name, 'awcache'])] + awprot = ports['_'.join([name, 'awprot'])] + awvalid = ports['_'.join([name, 'awvalid'])] + awready = ports['_'.join([name, 'awready'])] + + self.awaddr.connect(awaddr) + self.awcache.connect(awcache) + self.awprot.connect(awprot) + self.awvalid.connect(awvalid) + awready.connect(self.awready) + + +class AxiLiteSlaveWriteData(AxiLiteWriteData): + _I = util.t_Output + _O = util.t_Input + + def __init__(self, m, name, clk, rst, datawidth=32, addrwidth=32, + itype=None, otype=None): + + AxiLiteWriteData.__init__(self, m, name, datawidth, addrwidth, + itype, otype) + + self.clk = clk + self.rst = rst + + def disable_write(self): + self.wready.assign(0) + + def pull_write_data(self, cond=None): + """ + @return data, mask, valid + """ + ready = make_condition(cond) + val = 1 if ready is None else ready + + _connect_ready(self.wready._get_module(), self.wready, val) + + data = self.wdata + mask = self.wstrb + valid = self.wvalid + + return data, mask, valid + + def connect(self, ports, name): + wdata = ports['_'.join([name, 'wdata'])] + wstrb = ports['_'.join([name, 'wstrb'])] + wvalid = ports['_'.join([name, 'wvalid'])] + wready = ports['_'.join([name, 'wready'])] + + self.wdata.connect(wdata) + self.wstrb.connect(wstrb) + self.wvalid.connect(wvalid) + wready.connect(self.wready) + + +class AxiLiteSlaveWriteResponse(AxiLiteWriteResponse): + _I = util.t_OutputReg + _O = util.t_Input + + def __init__(self, m, name, clk, rst, datawidth=32, addrwidth=32, + itype=None, otype=None): + + AxiLiteWriteResponse.__init__(self, m, name, datawidth, addrwidth, + itype, otype) + + self.clk = clk + self.rst = rst + + # default values + self.bresp.assign(0) + + def connect(self, ports, name): + bresp = ports['_'.join([name, 'bresp'])] + bvalid = ports['_'.join([name, 'bvalid'])] + bready = ports['_'.join([name, 'bready'])] + + bresp.connect(self.bresp) + bvalid.connect(self.bvalid) + self.bready.connect(bready) + + +class AxiLiteSlaveReadAddress(AxiLiteReadAddress): + _I = util.t_Output + _O = util.t_Input + + def __init__(self, m, name, clk, rst, datawidth=32, addrwidth=32, + itype=None, otype=None): + + AxiLiteReadAddress.__init__(self, m, name, datawidth, addrwidth, + itype, otype) + + self.clk = clk + self.rst = rst + + def disable_read(self): + self.arready.assign(0) -class AxiSlaveWriteData(AxiWriteData): - _I = util.t_Output - _O = util.t_Input + def connect(self, ports, name): + araddr = ports['_'.join([name, 'araddr'])] + arcache = ports['_'.join([name, 'arcache'])] + arprot = ports['_'.join([name, 'arprot'])] + arvalid = ports['_'.join([name, 'arvalid'])] + arready = ports['_'.join([name, 'arready'])] + self.araddr.connect(araddr) + self.arcache.connect(arcache) + self.arprot.connect(arprot) + self.arvalid.connect(arvalid) + arready.connect(self.arready) -class AxiSlaveWriteResponse(AxiWriteResponse): + +class AxiLiteSlaveReadData(AxiLiteReadData): _I = util.t_OutputReg _O = util.t_Input + def __init__(self, m, name, clk, rst, datawidth=32, addrwidth=32, + itype=None, otype=None): -class AxiSlaveReadAddress(AxiReadAddress): - _I = util.t_Output - _O = util.t_Input + AxiLiteReadData.__init__(self, m, name, datawidth, addrwidth, + itype, otype) + self.clk = clk + self.rst = rst + self.seq = Seq(m, name + '_rdata', clk, rst) -class AxiSlaveReadData(AxiReadData): - _I = util.t_OutputReg - _O = util.t_Input + # default values + self.rresp.assign(0) + def disable_read(self): + ports = [self.rvalid(0)] -# AXI-Lite Slave -class AxiLiteSlaveWriteAddress(AxiLiteWriteAddress): - _I = util.t_Output - _O = util.t_Input + self.seq( + *ports + ) + def push_read_data(self, data, cond=None): + """ + @return ack + """ + if cond is not None: + self.seq.If(cond) -class AxiLiteSlaveWriteData(AxiLiteWriteData): - _I = util.t_Output - _O = util.t_Input + ack = vtypes.Ors(self.rready, vtypes.Not(self.rvalid)) + self.seq.If(ack)( + self.rdata(data), + self.rvalid(1) + ) -class AxiLiteSlaveWriteResponse(AxiLiteWriteResponse): - _I = util.t_OutputReg - _O = util.t_Input + # de-assert + self.seq.Delay(1)( + self.rvalid(0) + ) + # retry + self.seq.If(vtypes.Ands(self.rvalid, vtypes.Not(self.rready)))( + self.rvalid(self.rvalid) + ) -class AxiLiteSlaveReadAddress(AxiLiteReadAddress): - _I = util.t_Output - _O = util.t_Input + return ack + def connect(self, ports, name): + rdata = ports['_'.join([name, 'rdata'])] + rresp = ports['_'.join([name, 'rresp'])] + rvalid = ports['_'.join([name, 'rvalid'])] + rready = ports['_'.join([name, 'rready'])] -class AxiLiteSlaveReadData(AxiLiteReadData): - _I = util.t_OutputReg - _O = util.t_Input + rdata.connect(self.rdata) + rresp.connect(self.rresp) + rvalid.connect(self.rvalid) + self.rready.connect(rready) class AxiStreamInData(AxiStreamInterfaceBase): _O = util.t_Output - def __init__(self, m, name=None, datawidth=32, + def __init__(self, m, name, clk, rst, datawidth=32, with_last=True, with_strb=False, id_width=0, user_width=0, dest_width=0, itype=None, otype=None): @@ -479,6 +1681,10 @@ def __init__(self, m, name=None, datawidth=32, id_width, user_width, dest_width, itype, otype) + self.clk = clk + self.rst = rst + self.seq = Seq(m, name, clk, rst) + self.tdata = util.make_port( m, self.itype, name + '_tdata', self.datawidth, initval=0) self.tvalid = util.make_port( @@ -516,11 +1722,274 @@ def __init__(self, m, name=None, datawidth=32, self.tdest = util.make_port( m, self.itype, name + '_tdest', self.dest_width, initval=0) + def read_data(self, cond=None): + """ + @return data, last, _id, user, dest, valid + """ + ready = make_condition(cond) + val = 1 if ready is None else ready + + _connect_ready(self.tready._get_module(), self.tready, val) + + data = self.tdata + valid = self.tvalid + last = self.tlast + _id = self.tid + user = self.tuser + dest = self.tdest + + return data, last, _id, user, dest, valid + + def connect(self, ports, name): + tdata = ports['_'.join([name, 'tdata'])] + tvalid = ports['_'.join([name, 'tvalid'])] + tready = ports['_'.join([name, 'tready'])] + + if '_'.join([name, 'tlast']) in ports: + tlast = ports['_'.join([name, 'tlast'])] + else: + tlast = None + + if '_'.join([name, 'tid']) in ports: + tid = ports['_'.join([name, 'tid'])] + else: + tid = None + + if '_'.join([name, 'tuser']) in ports: + tuser = ports['_'.join([name, 'tuser'])] + else: + tuser = None + + if '_'.join([name, 'tdest']) in ports: + tdest = ports['_'.join([name, 'tdest'])] + else: + tdest = None + + self.tdata.connect(tdata) + self.tvalid.connect(tvalid) + tready.connect(self.tready) + + if self.tlast is not None: + self.tlast.connect(tlast if tlast is not None else 1) + if self.tid is not None: + self.tid.connect(tid if tid is not None else 0) + if self.tuser is not None: + self.tuser.connect(tuser if tuser is not None else 0) + if self.tdest is not None: + self.tdest.connect(tdest if tdest is not None else 0) + + def connect_stream(self, outdata): + if not isinstance(outdata, AxiStreamOutData): + raise TypeError('outdata must be an instance of AxiStreamOutData.') + + tdata = outdata.tdata + tvalid = outdata.tvalid + tready = outdata.tready + + if outdata.tlast is not None: + tlast = outdata.tlast + else: + tlast = None + + if outdata.tid is not None: + tid = outdata.tid + else: + tid = None + + if outdata.tuser is not None: + tuser = outdata.tuser + else: + tuser = None + + if outdata.tdest is not None: + tdest = outdata.tdest + else: + tdest = None + + self.tdata.connect(tdata) + self.tvalid.connect(tvalid) + tready.connect(self.tready) + + if self.tlast is not None: + self.tlast.connect(tlast if tlast is not None else 1) + if self.tid is not None: + self.tid.connect(tid if tid is not None else 0) + if self.tuser is not None: + self.tuser.connect(tuser if tuser is not None else 0) + if self.tdest is not None: + self.tdest.connect(tdest if tdest is not None else 0) + + def connect_master_rdata(self, rdata): + if not isinstance(rdata, AxiMasterReadData): + raise TypeError('rdata must be an instance of AxiMasterReadData.') + + tdata = rdata.rdata + tvalid = rdata.rvalid + tready = rdata.rready + + tlast = 0 + + if rdata.rid is not None: + tid = rdata.rid + else: + tid = None + + if rdata.ruser is not None: + tuser = rdata.ruser + else: + tuser = None + + tdest = None + + self.tdata.connect(tdata) + self.tvalid.connect(tvalid) + tready.connect(self.tready) + + if self.tlast is not None: + self.tlast.connect(tlast if tlast is not None else 1) + if self.tid is not None: + self.tid.connect(tid if tid is not None else 0) + if self.tuser is not None: + self.tuser.connect(tuser if tuser is not None else 0) + if self.tdest is not None: + self.tdest.connect(tdest if tdest is not None else 0) + class AxiStreamOutData(AxiStreamInData): _I = util.t_OutputReg _O = util.t_Input + def __init__(self, m, name, clk, rst, datawidth=32, + with_last=True, with_strb=False, + id_width=0, user_width=0, dest_width=0, + itype=None, otype=None): + + AxiStreamInData.__init__(self, m, name, clk, rst, datawidth, + with_last, with_strb, + id_width, user_width, dest_width, + itype, otype) + + # default values + if self.tuser is not None: + self.tuser.assign(0) + + if self.tid is not None: + self.tid.assign(0) + + def write_data(self, data, last=None, _id=None, user=None, dest=None, cond=None): + """ + @return ack + """ + if cond is not None: + self.seq.If(cond) + + ack = vtypes.Ors(self.tready, vtypes.Not(self.tvalid)) + + self.seq.If(ack)( + self.tdata(data), + self.tvalid(1), + self.tlast(last) if self.tlast is not None else (), + self.tid(_id) if self.tid is not None else (), + self.tuser(user) if self.tuser is not None else (), + self.tdest(dest) if self.tdest is not None else (), + ) + + # de-assert + self.seq.Delay(1)( + self.tvalid(0), + self.tlast(0) if self.tlast is not None else () + ) + + # retry + self.seq.If(vtypes.Ands(self.tvalid, vtypes.Not(self.tready)))( + self.tvalid(self.tvalid), + self.tlast(self.tlast) if self.tlast is not None else () + ) + + return ack + + def connect(self, ports, name): + tdata = ports['_'.join([name, 'tdata'])] + tvalid = ports['_'.join([name, 'tvalid'])] + tready = ports['_'.join([name, 'tready'])] + + if '_'.join([name, 'tlast']) in ports: + tlast = ports['_'.join([name, 'tlast'])] + else: + tlast = None + + if '_'.join([name, 'tid']) in ports: + tid = ports['_'.join([name, 'tid'])] + else: + tid = None + + if '_'.join([name, 'tuser']) in ports: + tuser = ports['_'.join([name, 'tuser'])] + else: + tuser = None + + if '_'.join([name, 'tdest']) in ports: + tdest = ports['_'.join([name, 'tdest'])] + else: + tdest = None + + tdata.connect(self.tdata) + tvalid.connect(self.tvalid) + self.tready.connect(tready) + + if tlast is not None: + tlast.connect(self.tlast if self.tlast is not None else 1) + + if tuser is not None: + tuser.connect(self.tuser if self.tuser is not None else 0) + + if tid is not None: + tid.connect(self.tid if self.tid is not None else 0) + + if tdest is not None: + tdest.connect(self.tdest if self.tdest is not None else 0) + + def connect_stream(self, indata): + if not isinstance(indata, AxiStreamInData): + raise TypeError('indata must be an instance of AxiStreamInData.') + + tdata = indata.tdata + tvalid = indata.tvalid + tready = indata.tready + + if indata.tlast is not None: + tlast = indata.tlast + else: + tlast = None + + if indata.tid is not None: + tid = indata.tid + else: + tid = None + + if indata.tuser is not None: + tuser = indata.tuser + else: + tuser = None + + if indata.tdest is not None: + tdest = indata.tdest + else: + tdest = None + + tdata.connect(self.tdata) + tvalid.connect(self.tvalid) + self.tready.connect(tready) + + if tlast is not None: + tlast.connect(self.tlast if self.tlast is not None else 1) + if tuser is not None: + tuser.connect(self.tuser if self.tuser is not None else 0) + if tid is not None: + tid.connect(self.tid if self.tid is not None else 0) + if tdest is not None: + tdest.connect(self.tdest if self.tdest is not None else 0) + # AXI-Full class AxiMaster(object): @@ -537,7 +2006,7 @@ def __init__(self, m, name, clk, rst, datawidth=32, addrwidth=32, waddr_prot_mode=AxPROT_NONCOHERENT, raddr_prot_mode=AxPROT_NONCOHERENT, waddr_user_mode=AxUSER_NONCOHERENT, wdata_user_mode=xUSER_DEFAULT, raddr_user_mode=AxUSER_NONCOHERENT, - noio=False, outstanding_wcount_width=3): + noio=False, outstanding_wcount_width=3, sb_depth=1): self.m = m self.name = name @@ -557,44 +2026,32 @@ def __init__(self, m, name, clk, rst, datawidth=32, addrwidth=32, itype = util.t_Wire if noio else None otype = util.t_Reg if noio else None + wdata_otype = util.t_Wire if noio else None + rdata_otype = util.t_Wire if noio else None - self.waddr = AxiMasterWriteAddress(m, name, datawidth, addrwidth, - waddr_id_width, waddr_user_width, itype, otype) - self.wdata = AxiMasterWriteData(m, name, datawidth, addrwidth, - wdata_id_width, wdata_user_width, itype, otype) - self.wresp = AxiMasterWriteResponse(m, name, datawidth, addrwidth, + self.waddr = AxiMasterWriteAddress(m, name, clk, rst, datawidth, addrwidth, + waddr_id_width, waddr_user_width, + waddr_burst_mode, waddr_cache_mode, + waddr_prot_mode, waddr_user_mode, + itype, otype) + self.wdata = AxiMasterWriteData(m, name, clk, rst, datawidth, addrwidth, + wdata_id_width, wdata_user_width, + wdata_user_mode, sb_depth, + itype, wdata_otype) + self.wresp = AxiMasterWriteResponse(m, name, clk, rst, datawidth, addrwidth, wresp_id_width, wresp_user_width, itype, otype) - self.raddr = AxiMasterReadAddress(m, name, datawidth, addrwidth, - raddr_id_width, raddr_user_width, itype, otype) - - otype = util.t_Wire if noio else None - - self.rdata = AxiMasterReadData(m, name, datawidth, addrwidth, - rdata_id_width, rdata_user_width, itype, otype) + self.raddr = AxiMasterReadAddress(m, name, clk, rst, datawidth, addrwidth, + raddr_id_width, raddr_user_width, + raddr_burst_mode, raddr_cache_mode, + raddr_prot_mode, raddr_user_mode, + itype, otype) + self.rdata = AxiMasterReadData(m, name, clk, rst, datawidth, addrwidth, + rdata_id_width, rdata_user_width, + sb_depth, + itype, rdata_otype) self.seq = Seq(m, name, clk, rst) - # default values - self.waddr.awsize.assign(int(math.log(self.datawidth / 8, 2))) - self.waddr.awburst.assign(waddr_burst_mode) - self.waddr.awlock.assign(0) - self.waddr.awcache.assign(waddr_cache_mode) - self.waddr.awprot.assign(waddr_prot_mode) - self.waddr.awqos.assign(0) - if self.waddr.awuser is not None: - self.waddr.awuser.assign(waddr_user_mode) - if self.wdata.wuser is not None: - self.wdata.wuser.assign(wdata_user_mode) - self.wresp.bready.assign(1) - self.raddr.arsize.assign(int(math.log(self.datawidth / 8, 2))) - self.raddr.arburst.assign(raddr_burst_mode) - self.raddr.arlock.assign(0) - self.raddr.arcache.assign(raddr_cache_mode) - self.raddr.arprot.assign(raddr_prot_mode) - self.raddr.arqos.assign(0) - if self.raddr.aruser is not None: - self.raddr.aruser.assign(raddr_user_mode) - # outstanding write request if outstanding_wcount_width < 2: raise ValueError("outstanding_wcount_width must be 2 or more.") @@ -622,37 +2079,13 @@ def __init__(self, m, name, clk, rst, datawidth=32, addrwidth=32, self._read_disabled = False def disable_write(self): - ports = [self.waddr.awaddr(0), - self.waddr.awlen(0), - self.waddr.awvalid(0), - self.wdata.wdata(0), - self.wdata.wstrb(0), - self.wdata.wlast(0), - self.wdata.wvalid(0)] - - if self.waddr.awid is not None: - ports.insert(0, self.waddr.awid(0)) - - self.seq( - *ports - ) - + self.waddr.disable_write() + self.wdata.disable_write() self._write_disabled = True def disable_read(self): - ports = [self.raddr.araddr(0), - self.raddr.arlen(0), - self.raddr.arvalid(0)] - - if self.raddr.arid is not None: - ports.insert(0, self.raddr.arid(0)) - - self.seq( - *ports - ) - - self.rdata.rready.assign(0) - + self.raddr.disable_read() + self.rdata.disable_read() self._read_disabled = True def mask_addr(self, addr): @@ -689,40 +2122,15 @@ def write_request(self, addr, length=1, cond=None): @return ack """ if self._write_disabled: - raise TypeError('Write disabled.') - - if isinstance(length, int) and length > 2 ** self.burst_size_width: - raise ValueError("length must be less than 257.") - - if isinstance(length, int) and length < 1: - raise ValueError("length must be more than 0.") - - if cond is not None: - self.seq.If(cond) - - ack = vtypes.Ands(self.write_acceptable(), - vtypes.Ors(self.waddr.awready, vtypes.Not(self.waddr.awvalid))) - - self.seq.If(ack)( - self.waddr.awid(0) if self.waddr.awid is not None else (), - self.waddr.awaddr(addr), - self.waddr.awlen(length - 1), - self.waddr.awvalid(1) - ) - self.seq.Then().If(length == 0)( - self.waddr.awvalid(0) - ) - - # de-assert - self.seq.Delay(1)( - self.waddr.awvalid(0) - ) + raise TypeError('Write disabled.') - # retry - self.seq.If(vtypes.Ands(self.waddr.awvalid, vtypes.Not(self.waddr.awready)))( - self.waddr.awvalid(self.waddr.awvalid) - ) + if isinstance(length, int) and length > 2 ** self.burst_size_width: + raise ValueError("length must be less than 257.") + + if isinstance(length, int) and length < 1: + raise ValueError("length must be more than 0.") + ack = self.waddr.write_request(addr, self.write_acceptable(), length, cond) return ack def write_data(self, data, last, cond=None): @@ -732,31 +2140,7 @@ def write_data(self, data, last, cond=None): if self._write_disabled: raise TypeError('Write disabled.') - if cond is not None: - self.seq.If(cond) - - ack = vtypes.Ors(self.wdata.wready, vtypes.Not(self.wdata.wvalid)) - - self.seq.If(ack)( - self.wdata.wdata(data), - self.wdata.wvalid(1), - self.wdata.wlast(last), - self.wdata.wstrb(vtypes.Repeat( - vtypes.Int(1, 1), (self.wdata.datawidth // 8))), - ) - - # de-assert - self.seq.Delay(1)( - self.wdata.wvalid(0), - self.wdata.wlast(0), - ) - - # retry - self.seq.If(vtypes.Ands(self.wdata.wvalid, vtypes.Not(self.wdata.wready)))( - self.wdata.wvalid(self.wdata.wvalid), - self.wdata.wlast(self.wdata.wlast), - ) - + ack = self.wdata.write_data(data, last, cond) return ack def write_completed(self): @@ -775,28 +2159,7 @@ def read_request(self, addr, length=1, cond=None): if isinstance(length, int) and length < 1: raise ValueError("length must be more than 0.") - if cond is not None: - self.seq.If(cond) - - ack = vtypes.Ors(self.raddr.arready, vtypes.Not(self.raddr.arvalid)) - - self.seq.If(ack)( - self.raddr.arid(0) if self.raddr.arid is not None else (), - self.raddr.araddr(addr), - self.raddr.arlen(length - 1), - self.raddr.arvalid(1) - ) - - # de-assert - self.seq.Delay(1)( - self.raddr.arvalid(0) - ) - - # retry - self.seq.If(vtypes.Ands(self.raddr.arvalid, vtypes.Not(self.raddr.arready)))( - self.raddr.arvalid(self.raddr.arvalid) - ) - + ack = self.raddr.read_request(addr, length, cond) return ack def read_data(self, cond=None): @@ -806,150 +2169,18 @@ def read_data(self, cond=None): if self._read_disabled: raise TypeError('Read disabled.') - ready = make_condition(cond) - val = 1 if ready is None else ready - - _connect_ready(self.rdata.rready._get_module(), self.rdata.rready, val) - - data = self.rdata.rdata - valid = self.rdata.rvalid - last = self.rdata.rlast - + data, valid, last = self.rdata.read_data(cond) return data, valid, last def connect(self, ports, name): if not self.noio: raise ValueError('I/O ports can not be connected to others.') - if '_'.join([name, 'awid']) in ports: - awid = ports['_'.join([name, 'awid'])] - else: - awid = None - awaddr = ports['_'.join([name, 'awaddr'])] - awlen = ports['_'.join([name, 'awlen'])] - awsize = ports['_'.join([name, 'awsize'])] - awburst = ports['_'.join([name, 'awburst'])] - awlock = ports['_'.join([name, 'awlock'])] - awcache = ports['_'.join([name, 'awcache'])] - awprot = ports['_'.join([name, 'awprot'])] - awqos = ports['_'.join([name, 'awqos'])] - if '_'.join([name, 'awuser']) in ports: - awuser = ports['_'.join([name, 'awuser'])] - else: - awuser = None - awvalid = ports['_'.join([name, 'awvalid'])] - awready = ports['_'.join([name, 'awready'])] - - if awid is not None: - awid.connect(self.waddr.awid if self.waddr.awid is not None else 0) - awaddr.connect(self.waddr.awaddr) - awlen.connect(self.waddr.awlen) - awsize.connect(self.waddr.awsize) - awburst.connect(self.waddr.awburst) - awlock.connect(self.waddr.awlock) - awcache.connect(self.waddr.awcache) - awprot.connect(self.waddr.awprot) - awqos.connect(self.waddr.awqos) - if awuser is not None: - awuser.connect(self.waddr.awuser if self.waddr.awuser is not None else 0) - awvalid.connect(self.waddr.awvalid) - self.waddr.awready.connect(awready) - - wdata = ports['_'.join([name, 'wdata'])] - wstrb = ports['_'.join([name, 'wstrb'])] - wlast = ports['_'.join([name, 'wlast'])] - if '_'.join([name, 'wuser']) in ports: - wuser = ports['_'.join([name, 'wuser'])] - else: - wuser = None - wvalid = ports['_'.join([name, 'wvalid'])] - wready = ports['_'.join([name, 'wready'])] - - wdata.connect(self.wdata.wdata) - wstrb.connect(self.wdata.wstrb) - wlast.connect(self.wdata.wlast) - if wuser is not None: - wuser.connect(self.wdata.wuser if self.wdata.wuser is not None else 0) - wvalid.connect(self.wdata.wvalid) - self.wdata.wready.connect(wready) - - if '_'.join([name, 'bid']) in ports: - bid = ports['_'.join([name, 'bid'])] - else: - bid = None - bresp = ports['_'.join([name, 'bresp'])] - if '_'.join([name, 'buser']) in ports: - buser = ports['_'.join([name, 'buser'])] - else: - buser = None - bvalid = ports['_'.join([name, 'bvalid'])] - bready = ports['_'.join([name, 'bready'])] - - if self.wresp.bid is not None: - self.wresp.bid.connect(bid if bid is not None else 0) - self.wresp.bresp.connect(bresp) - if self.wresp.buser is not None: - self.wresp.buser.connect(buser if buser is not None else 0) - self.wresp.bvalid.connect(bvalid) - bready.connect(self.wresp.bready) - - if '_'.join([name, 'arid']) in ports: - arid = ports['_'.join([name, 'arid'])] - else: - arid = None - araddr = ports['_'.join([name, 'araddr'])] - arlen = ports['_'.join([name, 'arlen'])] - arsize = ports['_'.join([name, 'arsize'])] - arburst = ports['_'.join([name, 'arburst'])] - arlock = ports['_'.join([name, 'arlock'])] - arcache = ports['_'.join([name, 'arcache'])] - arprot = ports['_'.join([name, 'arprot'])] - arqos = ports['_'.join([name, 'arqos'])] - if '_'.join([name, 'aruser']) in ports: - aruser = ports['_'.join([name, 'aruser'])] - else: - aruser = None - arvalid = ports['_'.join([name, 'arvalid'])] - arready = ports['_'.join([name, 'arready'])] - - if arid is not None: - arid.connect(self.raddr.arid if self.raddr.arid is not None else 0) - araddr.connect(self.raddr.araddr) - arlen.connect(self.raddr.arlen) - arsize.connect(self.raddr.arsize) - arburst.connect(self.raddr.arburst) - arlock.connect(self.raddr.arlock) - arcache.connect(self.raddr.arcache) - arprot.connect(self.raddr.arprot) - arqos.connect(self.raddr.arqos) - if aruser is not None: - aruser.connect(self.raddr.aruser if self.raddr.aruser is not None else 0) - arvalid.connect(self.raddr.arvalid) - self.raddr.arready.connect(arready) - - if '_'.join([name, 'rid']) in ports: - rid = ports['_'.join([name, 'rid'])] - else: - rid = None - rdata = ports['_'.join([name, 'rdata'])] - rresp = ports['_'.join([name, 'rresp'])] - rlast = ports['_'.join([name, 'rlast'])] - if '_'.join([name, 'ruser']) in ports: - ruser = ports['_'.join([name, 'ruser'])] - else: - ruser = None - rvalid = ports['_'.join([name, 'rvalid'])] - rready = ports['_'.join([name, 'rready'])] - - if self.rdata.rid is not None: - self.rdata.rid.connect(rid if rid is not None else 0) - self.rdata.rdata.connect(rdata) - self.rdata.rresp.connect(rresp) - self.rdata.rlast.connect(rlast) - if self.rdata.ruser is not None: - self.rdata.ruser.connect(ruser if ruser is not None else 0) - self.rdata.rvalid.connect(rvalid) - rready.connect(self.rdata.rready) + self.waddr.connect(ports, name) + self.wdata.connect(ports, name) + self.wresp.connect(ports, name) + self.raddr.connect(ports, name) + self.rdata.connect(ports, name) # AXI-Lite @@ -958,7 +2189,7 @@ class AxiLiteMaster(AxiMaster): def __init__(self, m, name, clk, rst, datawidth=32, addrwidth=32, waddr_cache_mode=AxCACHE_NONCOHERENT, raddr_cache_mode=AxCACHE_NONCOHERENT, waddr_prot_mode=AxPROT_NONCOHERENT, raddr_prot_mode=AxPROT_NONCOHERENT, - noio=False, outstanding_wcount_width=3): + noio=False, outstanding_wcount_width=3, sb_depth=1): self.m = m self.name = name @@ -978,30 +2209,26 @@ def __init__(self, m, name, clk, rst, datawidth=32, addrwidth=32, itype = util.t_Wire if noio else None otype = util.t_Reg if noio else None + wdata_otype = util.t_Wire if noio else None + rdata_otype = util.t_Wire if noio else None - self.waddr = AxiLiteMasterWriteAddress(m, name, datawidth, addrwidth, + self.waddr = AxiLiteMasterWriteAddress(m, name, clk, rst, datawidth, addrwidth, + waddr_cache_mode, waddr_prot_mode, itype, otype) - self.wdata = AxiLiteMasterWriteData(m, name, datawidth, addrwidth, - itype, otype) - self.wresp = AxiLiteMasterWriteResponse(m, name, datawidth, addrwidth, + self.wdata = AxiLiteMasterWriteData(m, name, clk, rst, datawidth, addrwidth, + sb_depth, + itype, wdata_otype) + self.wresp = AxiLiteMasterWriteResponse(m, name, clk, rst, datawidth, addrwidth, itype, otype) - self.raddr = AxiLiteMasterReadAddress(m, name, datawidth, addrwidth, + self.raddr = AxiLiteMasterReadAddress(m, name, clk, rst, datawidth, addrwidth, + raddr_cache_mode, raddr_prot_mode, itype, otype) - - otype = util.t_Wire if noio else None - - self.rdata = AxiLiteMasterReadData(m, name, datawidth, addrwidth, - itype, otype) + self.rdata = AxiLiteMasterReadData(m, name, clk, rst, datawidth, addrwidth, + sb_depth, + itype, rdata_otype) self.seq = Seq(m, name, clk, rst) - # default values - self.waddr.awcache.assign(waddr_cache_mode) - self.waddr.awprot.assign(waddr_prot_mode) - self.wresp.bready.assign(1) - self.raddr.arcache.assign(raddr_cache_mode) - self.raddr.arprot.assign(raddr_prot_mode) - # outstanding write request if outstanding_wcount_width < 2: raise ValueError("outstanding_wcount_width must be 2 or more.") @@ -1029,28 +2256,13 @@ def __init__(self, m, name, clk, rst, datawidth=32, addrwidth=32, self._read_disabled = False def disable_write(self): - ports = [self.waddr.awaddr(0), - self.waddr.awvalid(0), - self.wdata.wdata(0), - self.wdata.wstrb(0), - self.wdata.wvalid(0)] - - self.seq( - *ports - ) - + self.waddr.disable_write() + self.wdata.disable_write() self._write_disabled = True def disable_read(self): - ports = [self.raddr.araddr(0), - self.raddr.arvalid(0)] - - self.seq( - *ports - ) - - self.rdata.rready.assign(0) - + self.raddr.disable_read() + self.rdata.disable_read() self._read_disabled = True def write_acceptable(self): @@ -1067,27 +2279,7 @@ def write_request(self, addr, length=1, cond=None): if length != 1: raise ValueError('length must be 1 for lite-interface.') - if cond is not None: - self.seq.If(cond) - - ack = vtypes.Ands(self.write_acceptable(), - vtypes.Ors(self.waddr.awready, vtypes.Not(self.waddr.awvalid))) - - self.seq.If(ack)( - self.waddr.awaddr(addr), - self.waddr.awvalid(1), - ) - - # de-assert - self.seq.Delay(1)( - self.waddr.awvalid(0) - ) - - # retry - self.seq.If(vtypes.Ands(self.waddr.awvalid, vtypes.Not(self.waddr.awready)))( - self.waddr.awvalid(self.waddr.awvalid) - ) - + ack = self.waddr.write_request(addr, self.write_acceptable(), length, cond) return ack def write_data(self, data, cond=None): @@ -1097,28 +2289,7 @@ def write_data(self, data, cond=None): if self._write_disabled: raise TypeError('Write disabled.') - if cond is not None: - self.seq.If(cond) - - ack = vtypes.Ors(self.wdata.wready, vtypes.Not(self.wdata.wvalid)) - - self.seq.If(ack)( - self.wdata.wdata(data), - self.wdata.wvalid(1), - self.wdata.wstrb(vtypes.Repeat( - vtypes.Int(1, 1), (self.wdata.datawidth // 8))) - ) - - # de-assert - self.seq.Delay(1)( - self.wdata.wvalid(0), - ) - - # retry - self.seq.If(vtypes.Ands(self.wdata.wvalid, vtypes.Not(self.wdata.wready)))( - self.wdata.wvalid(self.wdata.wvalid) - ) - + ack = self.wdata.write_data(data, cond) return ack def read_request(self, addr, length=1, cond=None): @@ -1131,26 +2302,7 @@ def read_request(self, addr, length=1, cond=None): if length != 1: raise ValueError('length must be 1 for lite-interface.') - if cond is not None: - self.seq.If(cond) - - ack = vtypes.Ors(self.raddr.arready, vtypes.Not(self.raddr.arvalid)) - - self.seq.If(ack)( - self.raddr.araddr(addr), - self.raddr.arvalid(1) - ) - - # de-assert - self.seq.Delay(1)( - self.raddr.arvalid(0) - ) - - # retry - self.seq.If(vtypes.Ands(self.raddr.arvalid, vtypes.Not(self.raddr.arready)))( - self.raddr.arvalid(self.raddr.arvalid) - ) - + ack = self.raddr.read_request(addr, length, cond) return ack def read_data(self, cond=None): @@ -1160,72 +2312,18 @@ def read_data(self, cond=None): if self._read_disabled: raise TypeError('Read disabled.') - ready = make_condition(cond) - val = 1 if ready is None else ready - - _connect_ready(self.rdata.rready._get_module(), self.rdata.rready, val) - - ack = vtypes.Ands(self.rdata.rready, self.rdata.rvalid) - data = self.rdata.rdata - valid = ack - + data, valid = self.rdata.read_data(cond) return data, valid def connect(self, ports, name): if not self.noio: raise ValueError('I/O ports can not be connected to others.') - awaddr = ports['_'.join([name, 'awaddr'])] - awcache = ports['_'.join([name, 'awcache'])] - awprot = ports['_'.join([name, 'awprot'])] - awvalid = ports['_'.join([name, 'awvalid'])] - awready = ports['_'.join([name, 'awready'])] - - awaddr.connect(self.waddr.awaddr) - awcache.connect(self.waddr.awcache) - awprot.connect(self.waddr.awprot) - awvalid.connect(self.waddr.awvalid) - self.waddr.awready.connect(awready) - - wdata = ports['_'.join([name, 'wdata'])] - wstrb = ports['_'.join([name, 'wstrb'])] - wvalid = ports['_'.join([name, 'wvalid'])] - wready = ports['_'.join([name, 'wready'])] - - wdata.connect(self.wdata.wdata) - wstrb.connect(self.wdata.wstrb) - wvalid.connect(self.wdata.wvalid) - self.wdata.wready.connect(wready) - - bresp = ports['_'.join([name, 'bresp'])] - bvalid = ports['_'.join([name, 'bvalid'])] - bready = ports['_'.join([name, 'bready'])] - - self.wresp.bresp.connect(bresp) - self.wresp.bvalid.connect(bvalid) - bready.connect(self.wresp.bready) - - araddr = ports['_'.join([name, 'araddr'])] - arcache = ports['_'.join([name, 'arcache'])] - arprot = ports['_'.join([name, 'arprot'])] - arvalid = ports['_'.join([name, 'arvalid'])] - arready = ports['_'.join([name, 'arready'])] - - araddr.connect(self.raddr.araddr) - arcache.connect(self.raddr.arcache) - arprot.connect(self.raddr.arprot) - arvalid.connect(self.raddr.arvalid) - self.raddr.arready.connect(arready) - - rdata = ports['_'.join([name, 'rdata'])] - rresp = ports['_'.join([name, 'rresp'])] - rvalid = ports['_'.join([name, 'rvalid'])] - rready = ports['_'.join([name, 'rready'])] - - self.rdata.rdata.connect(rdata) - self.rdata.rresp.connect(rresp) - self.rdata.rvalid.connect(rvalid) - rready.connect(self.rdata.rready) + self.waddr.connect(ports, name) + self.wdata.connect(ports, name) + self.wresp.connect(ports, name) + self.raddr.connect(ports, name) + self.rdata.connect(ports, name) class AxiSlave(object): @@ -1258,31 +2356,23 @@ def __init__(self, m, name, clk, rst, datawidth=32, addrwidth=32, itype = util.t_Wire if noio else None otype = util.t_Wire if noio else None + rdata_itype = util.t_Reg if noio else None - self.waddr = AxiSlaveWriteAddress(m, name, datawidth, addrwidth, + self.waddr = AxiSlaveWriteAddress(m, name, clk, rst, datawidth, addrwidth, waddr_id_width, waddr_user_width, itype, otype) - self.wdata = AxiSlaveWriteData(m, name, datawidth, addrwidth, + self.wdata = AxiSlaveWriteData(m, name, clk, rst, datawidth, addrwidth, wdata_id_width, wdata_user_width, itype, otype) - self.wresp = AxiSlaveWriteResponse(m, name, datawidth, addrwidth, - wresp_id_width, wresp_user_width, itype, otype) - self.raddr = AxiSlaveReadAddress(m, name, datawidth, addrwidth, + self.wresp = AxiSlaveWriteResponse(m, name, clk, rst, datawidth, addrwidth, + wresp_id_width, wresp_user_width, wresp_user_mode, + itype, otype) + self.raddr = AxiSlaveReadAddress(m, name, clk, rst, datawidth, addrwidth, raddr_id_width, raddr_user_width, itype, otype) - - itype = util.t_Reg if noio else None - - self.rdata = AxiSlaveReadData(m, name, datawidth, addrwidth, - rdata_id_width, rdata_user_width, itype, otype) + self.rdata = AxiSlaveReadData(m, name, clk, rst, datawidth, addrwidth, + rdata_id_width, rdata_user_width, rdata_user_mode, + rdata_itype, otype) self.seq = Seq(m, name, clk, rst) - # default values - self.wresp.bresp.assign(0) - if self.wresp.buser is not None: - self.wresp.buser.assign(wresp_user_mode) - self.rdata.rresp.assign(0) - if self.rdata.ruser is not None: - self.rdata.ruser.assign(rdata_user_mode) - # write response if self.wresp.bid is not None: self.seq.If(self.waddr.awvalid, self.waddr.awready, vtypes.Not(self.wresp.bvalid))( @@ -1305,21 +2395,13 @@ def __init__(self, m, name, clk, rst, datawidth=32, addrwidth=32, self._read_disabled = False def disable_write(self): - self.waddr.awready.assign(0) - self.wdata.wready.assign(0) - + self.waddr.disable_write() + self.wdata.disable_write() self._write_disabled = True def disable_read(self): - self.raddr.arready.assign(0) - - ports = [self.rdata.rvalid(0), - self.rdata.rlast(0)] - - self.seq( - *ports - ) - + self.raddr.disable_read() + self.rdata.disable_read() self._read_disabled = True def pull_request(self, cond): @@ -1412,30 +2494,11 @@ def pull_write_request(self, cond=None): ) self.seq.If(ack)( addr(self.waddr.awaddr), - length(self.waddr.awlen + 1), - valid(1) - ) - - return addr, length, valid - - def pull_write_data(self, cond=None): - """ - @return data, mask, valid, last - """ - if self._write_disabled: - raise TypeError('Write disabled.') - - ready = make_condition(cond) - val = 1 if ready is None else ready - - _connect_ready(self.wdata.wready._get_module(), self.wdata.wready, val) - - data = self.wdata.wdata - mask = self.wdata.wstrb - valid = self.wdata.wvalid - last = self.wdata.wlast + length(self.waddr.awlen + 1), + valid(1) + ) - return data, mask, valid, last + return addr, length, valid def pull_read_request(self, cond=None): """ @@ -1473,6 +2536,16 @@ def pull_read_request(self, cond=None): return addr, length, valid + def pull_write_data(self, cond=None): + """ + @return data, mask, valid, last + """ + if self._write_disabled: + raise TypeError('Write disabled.') + + data, mask, valid, last = self.wdata.pull_write_data(cond) + return data, mask, valid, last + def push_read_data(self, data, last, cond=None): """ @return ack @@ -1480,29 +2553,7 @@ def push_read_data(self, data, last, cond=None): if self._read_disabled: raise TypeError('Read disabled.') - if cond is not None: - self.seq.If(cond) - - ack = vtypes.Ors(self.rdata.rready, vtypes.Not(self.rdata.rvalid)) - - self.seq.If(ack)( - self.rdata.rdata(data), - self.rdata.rvalid(1), - self.rdata.rlast(last), - ) - - # de-assert - self.seq.Delay(1)( - self.rdata.rvalid(0), - self.rdata.rlast(0) - ) - - # retry - self.seq.If(vtypes.Ands(self.rdata.rvalid, vtypes.Not(self.rdata.rready)))( - self.rdata.rvalid(self.rdata.rvalid), - self.rdata.rlast(self.rdata.rlast) - ) - + ack = self.rdata.push_read_data(data, last, cond) return ack def connect(self, ports, name): @@ -1511,138 +2562,11 @@ def connect(self, ports, name): ports = defaultdict(lambda: None, ports) - if '_'.join([name, 'awid']) in ports: - awid = ports['_'.join([name, 'awid'])] - else: - awid = None - awaddr = ports['_'.join([name, 'awaddr'])] - awlen = ports['_'.join([name, 'awlen'])] - awsize = ports['_'.join([name, 'awsize'])] - awburst = ports['_'.join([name, 'awburst'])] - awlock = ports['_'.join([name, 'awlock'])] - awcache = ports['_'.join([name, 'awcache'])] - awprot = ports['_'.join([name, 'awprot'])] - awqos = ports['_'.join([name, 'awqos'])] - if '_'.join([name, 'awuser']) in ports: - awuser = ports['_'.join([name, 'awuser'])] - else: - awuser = None - awvalid = ports['_'.join([name, 'awvalid'])] - awready = ports['_'.join([name, 'awready'])] - - if self.waddr.awid is not None: - self.waddr.awid.connect(awid if awid is not None else 0) - self.waddr.awaddr.connect(awaddr) - self.waddr.awlen.connect(awlen if awlen is not None else 0) - self.waddr.awsize.connect(awsize if awsize is not None else - int(math.log(self.datawidth // 8))) - self.waddr.awburst.connect(awburst if awburst is not None else BURST_INCR) - self.waddr.awlock.connect(awlock if awlock is not None else 0) - self.waddr.awcache.connect(awcache) - self.waddr.awprot.connect(awprot) - self.waddr.awqos.connect(awqos if awqos is not None else 0) - if self.waddr.awuser is not None: - self.waddr.awuser.connect(awuser if awuser is not None else 0) - self.waddr.awvalid.connect(awvalid) - awready.connect(self.waddr.awready) - - wdata = ports['_'.join([name, 'wdata'])] - wstrb = ports['_'.join([name, 'wstrb'])] - wlast = ports['_'.join([name, 'wlast'])] - if '_'.join([name, 'wuser']) in ports: - wuser = ports['_'.join([name, 'wuser'])] - else: - wuser = None - wvalid = ports['_'.join([name, 'wvalid'])] - wready = ports['_'.join([name, 'wready'])] - - self.wdata.wdata.connect(wdata) - self.wdata.wstrb.connect(wstrb) - self.wdata.wlast.connect(wlast if wlast is not None else 1) - if self.wdata.wuser is not None: - self.wdata.wuser.connect(wuser if wuser is not None else 0) - self.wdata.wvalid.connect(wvalid) - wready.connect(self.wdata.wready) - - if '_'.join([name, 'bid']) in ports: - bid = ports['_'.join([name, 'bid'])] - else: - bid = None - bresp = ports['_'.join([name, 'bresp'])] - if '_'.join([name, 'buser']) in ports: - buser = ports['_'.join([name, 'buser'])] - else: - buser = None - bvalid = ports['_'.join([name, 'bvalid'])] - bready = ports['_'.join([name, 'bready'])] - - if bid is not None: - bid.connect(self.wresp.bid if self.wresp.bid is not None else 0) - bresp.connect(self.wresp.bresp) - if buser is not None: - buser.connect(self.wresp.buser if self.wresp.buser is not None else 0) - bvalid.connect(self.wresp.bvalid) - self.wresp.bready.connect(bready) - - if '_'.join([name, 'arid']) in ports: - arid = ports['_'.join([name, 'arid'])] - else: - arid = None - araddr = ports['_'.join([name, 'araddr'])] - arlen = ports['_'.join([name, 'arlen'])] - arsize = ports['_'.join([name, 'arsize'])] - arburst = ports['_'.join([name, 'arburst'])] - arlock = ports['_'.join([name, 'arlock'])] - arcache = ports['_'.join([name, 'arcache'])] - arprot = ports['_'.join([name, 'arprot'])] - arqos = ports['_'.join([name, 'arqos'])] - if '_'.join([name, 'aruser']) in ports: - aruser = ports['_'.join([name, 'aruser'])] - else: - aruser = None - arvalid = ports['_'.join([name, 'arvalid'])] - arready = ports['_'.join([name, 'arready'])] - - if self.raddr.arid is not None: - self.raddr.arid.connect(arid if arid is not None else 0) - self.raddr.araddr.connect(araddr) - self.raddr.arlen.connect(arlen if arlen is not None else 0) - self.raddr.arsize.connect(arsize if arsize is not None else - int(math.log(self.datawidth // 8))) - self.raddr.arburst.connect(arburst if arburst is not None else BURST_INCR) - self.raddr.arlock.connect(arlock if arlock is not None else 0) - self.raddr.arcache.connect(arcache) - self.raddr.arprot.connect(arprot) - self.raddr.arqos.connect(arqos if arqos is not None else 0) - if self.raddr.aruser is not None: - self.raddr.aruser.connect(aruser if aruser is not None else 0) - self.raddr.arvalid.connect(arvalid) - arready.connect(self.raddr.arready) - - if '_'.join([name, 'rid']) in ports: - rid = ports['_'.join([name, 'rid'])] - else: - rid = None - rdata = ports['_'.join([name, 'rdata'])] - rresp = ports['_'.join([name, 'rresp'])] - rlast = ports['_'.join([name, 'rlast'])] - if '_'.join([name, 'ruser']) in ports: - ruser = ports['_'.join([name, 'ruser'])] - else: - ruser = None - rvalid = ports['_'.join([name, 'rvalid'])] - rready = ports['_'.join([name, 'rready'])] - - if rid is not None: - rid.connect(self.rdata.rid if self.rdata.rid is not None else 0) - rdata.connect(self.rdata.rdata) - rresp.connect(self.rdata.rresp) - if rlast is not None: - rlast.connect(self.rdata.rlast) - if ruser is not None: - ruser.connect(self.rdata.ruser if self.rdata.ruser is not None else 0) - rvalid.connect(self.rdata.rvalid) - self.rdata.rready.connect(rready) + self.waddr.connect(ports, name) + self.wdata.connect(ports, name) + self.wresp.connect(ports, name) + self.raddr.connect(ports, name) + self.rdata.connect(ports, name) class AxiLiteSlave(AxiSlave): @@ -1668,27 +2592,21 @@ def __init__(self, m, name, clk, rst, datawidth=32, addrwidth=32, itype = util.t_Wire if noio else None otype = util.t_Wire if noio else None + rdata_itype = util.t_Reg if noio else None - self.waddr = AxiLiteSlaveWriteAddress(m, name, datawidth, addrwidth, + self.waddr = AxiLiteSlaveWriteAddress(m, name, clk, rst, datawidth, addrwidth, itype, otype) - self.wdata = AxiLiteSlaveWriteData(m, name, datawidth, addrwidth, + self.wdata = AxiLiteSlaveWriteData(m, name, clk, rst, datawidth, addrwidth, itype, otype) - self.wresp = AxiLiteSlaveWriteResponse(m, name, datawidth, addrwidth, + self.wresp = AxiLiteSlaveWriteResponse(m, name, clk, rst, datawidth, addrwidth, itype, otype) - self.raddr = AxiLiteSlaveReadAddress(m, name, datawidth, addrwidth, + self.raddr = AxiLiteSlaveReadAddress(m, name, clk, rst, datawidth, addrwidth, itype, otype) - - itype = util.t_Reg if noio else None - - self.rdata = AxiLiteSlaveReadData(m, name, datawidth, addrwidth, - itype, otype) + self.rdata = AxiLiteSlaveReadData(m, name, clk, rst, datawidth, addrwidth, + rdata_itype, otype) self.seq = Seq(m, name, clk, rst) - # default values - self.wresp.bresp.assign(0) - self.rdata.rresp.assign(0) - # write response self.seq.If(self.wresp.bvalid, self.wresp.bready)( self.wresp.bvalid(0) @@ -1701,20 +2619,13 @@ def __init__(self, m, name, clk, rst, datawidth=32, addrwidth=32, self._read_disabled = False def disable_write(self): - self.waddr.awready.assign(0) - self.wdata.wready.assign(0) - + self.waddr.disable_write() + self.wdata.disable_write() self._write_disabled = True def disable_read(self): - self.raddr.arready.assign(0) - - ports = [self.rdata.rvalid(0)] - - self.seq( - *ports - ) - + self.raddr.disable_read() + self.rdata.disable_read() self._read_disabled = True def pull_request(self, cond): @@ -1808,24 +2719,6 @@ def pull_write_request(self, cond=None): return addr, valid - def pull_write_data(self, cond=None): - """ - @return data, mask, valid - """ - if self._write_disabled: - raise TypeError('Write disabled.') - - ready = make_condition(cond) - val = 1 if ready is None else ready - - _connect_ready(self.wdata.wready._get_module(), self.wdata.wready, val) - - data = self.wdata.wdata - mask = self.wdata.wstrb - valid = self.wdata.wvalid - - return data, mask, valid - def pull_read_request(self, cond=None): """ @return addr, valid @@ -1859,6 +2752,16 @@ def pull_read_request(self, cond=None): return addr, valid + def pull_write_data(self, cond=None): + """ + @return data, mask, valid + """ + if self._write_disabled: + raise TypeError('Write disabled.') + + data, mask, valid = self.wdata.pull_write_data(cond) + return data, mask, valid + def push_read_data(self, data, cond=None): """ @return ack @@ -1866,83 +2769,18 @@ def push_read_data(self, data, cond=None): if self._read_disabled: raise TypeError('Read disabled.') - if cond is not None: - self.seq.If(cond) - - ack = vtypes.Ors(self.rdata.rready, vtypes.Not(self.rdata.rvalid)) - - self.seq.If(ack)( - self.rdata.rdata(data), - self.rdata.rvalid(1) - ) - - # de-assert - self.seq.Delay(1)( - self.rdata.rvalid(0) - ) - - # retry - self.seq.If(vtypes.Ands(self.rdata.rvalid, vtypes.Not(self.rdata.rready)))( - self.rdata.rvalid(self.rdata.rvalid) - ) - + ack = self.rdata.push_read_data(data, cond) return ack def connect(self, ports, name): if not self.noio: raise ValueError('I/O ports can not be connected to others.') - awaddr = ports['_'.join([name, 'awaddr'])] - awcache = ports['_'.join([name, 'awcache'])] - awprot = ports['_'.join([name, 'awprot'])] - awvalid = ports['_'.join([name, 'awvalid'])] - awready = ports['_'.join([name, 'awready'])] - - self.waddr.awaddr.connect(awaddr) - self.waddr.awcache.connect(awcache) - self.waddr.awprot.connect(awprot) - self.waddr.awvalid.connect(awvalid) - awready.connect(self.waddr.awready) - - wdata = ports['_'.join([name, 'wdata'])] - wstrb = ports['_'.join([name, 'wstrb'])] - wvalid = ports['_'.join([name, 'wvalid'])] - wready = ports['_'.join([name, 'wready'])] - - self.wdata.wdata.connect(wdata) - self.wdata.wstrb.connect(wstrb) - self.wdata.wvalid.connect(wvalid) - wready.connect(self.wdata.wready) - - bresp = ports['_'.join([name, 'bresp'])] - bvalid = ports['_'.join([name, 'bvalid'])] - bready = ports['_'.join([name, 'bready'])] - - bresp.connect(self.wresp.bresp) - bvalid.connect(self.wresp.bvalid) - self.wresp.bready.connect(bready) - - araddr = ports['_'.join([name, 'araddr'])] - arcache = ports['_'.join([name, 'arcache'])] - arprot = ports['_'.join([name, 'arprot'])] - arvalid = ports['_'.join([name, 'arvalid'])] - arready = ports['_'.join([name, 'arready'])] - - self.raddr.araddr.connect(araddr) - self.raddr.arcache.connect(arcache) - self.raddr.arprot.connect(arprot) - self.raddr.arvalid.connect(arvalid) - arready.connect(self.raddr.arready) - - rdata = ports['_'.join([name, 'rdata'])] - rresp = ports['_'.join([name, 'rresp'])] - rvalid = ports['_'.join([name, 'rvalid'])] - rready = ports['_'.join([name, 'rready'])] - - rdata.connect(self.rdata.rdata) - rresp.connect(self.rdata.rresp) - rvalid.connect(self.rdata.rvalid) - self.rdata.rready.connect(rready) + self.waddr.connect(ports, name) + self.wdata.connect(ports, name) + self.wresp.connect(ports, name) + self.raddr.connect(ports, name) + self.rdata.connect(ports, name) class AxiStreamIn(object): @@ -1970,7 +2808,7 @@ def __init__(self, m, name, clk, rst, datawidth=32, itype = util.t_Wire if noio else None otype = util.t_Wire if noio else None - self.tdata = AxiStreamInData(m, name, datawidth, + self.tdata = AxiStreamInData(m, name, clk, rst, datawidth, with_last, with_strb, id_width, user_width, dest_width, itype, otype) @@ -1981,60 +2819,14 @@ def read_data(self, cond=None): """ @return data, last, _id, user, dest, valid """ - ready = make_condition(cond) - val = 1 if ready is None else ready - - _connect_ready(self.tdata.tready._get_module(), self.tdata.tready, val) - - data = self.tdata.tdata - valid = self.tdata.tvalid - last = self.tdata.tlast - _id = self.tdata.tid - user = self.tdata.tuser - dest = self.tdata.tdest - + data, last, _id, user, dest, valid = self.tdata.read_data(cond) return data, last, _id, user, dest, valid def connect(self, ports, name): if not self.noio: raise ValueError('I/O ports can not be connected to others.') - tdata = ports['_'.join([name, 'tdata'])] - tvalid = ports['_'.join([name, 'tvalid'])] - tready = ports['_'.join([name, 'tready'])] - - if '_'.join([name, 'tlast']) in ports: - tlast = ports['_'.join([name, 'tlast'])] - else: - tlast = None - - if '_'.join([name, 'tid']) in ports: - tid = ports['_'.join([name, 'tid'])] - else: - tid = None - - if '_'.join([name, 'tuser']) in ports: - tuser = ports['_'.join([name, 'tuser'])] - else: - tuser = None - - if '_'.join([name, 'tdest']) in ports: - tdest = ports['_'.join([name, 'tdest'])] - else: - tdest = None - - self.tdata.tdata.connect(tdata) - self.tdata.tvalid.connect(tvalid) - tready.connect(self.tdata.tready) - - if self.tdata.tlast is not None: - self.tdata.tlast.connect(tlast if tlast is not None else 1) - if self.tdata.tid is not None: - self.tdata.tid.connect(tid if tid is not None else 0) - if self.tdata.tuser is not None: - self.tdata.tuser.connect(tuser if tuser is not None else 0) - if self.tdata.tdest is not None: - self.tdata.tdest.connect(tdest if tdest is not None else 0) + self.tdata.connect(ports, name) def connect_stream(self, stream): if not isinstance(stream, AxiStreamOut): @@ -2043,42 +2835,8 @@ def connect_stream(self, stream): if not self.noio: raise ValueError('I/O ports can not be connected to others.') - tdata = stream.tdata.tdata - tvalid = stream.tdata.tvalid - tready = stream.tdata.tready - - if stream.tdata.tlast is not None: - tlast = stream.tdata.tlast - else: - tlast = None - - if stream.tdata.tid is not None: - tid = stream.tdata.tid - else: - tid = None - - if stream.tdata.tuser is not None: - tuser = stream.tdata.tuser - else: - tuser = None - - if stream.tdata.tdest is not None: - tdest = stream.tdata.tdest - else: - tdest = None - - self.tdata.tdata.connect(tdata) - self.tdata.tvalid.connect(tvalid) - tready.connect(self.tdata.tready) - - if self.tdata.tlast is not None: - self.tdata.tlast.connect(tlast if tlast is not None else 1) - if self.tdata.tid is not None: - self.tdata.tid.connect(tid if tid is not None else 0) - if self.tdata.tuser is not None: - self.tdata.tuser.connect(tuser if tuser is not None else 0) - if self.tdata.tdest is not None: - self.tdata.tdest.connect(tdest if tdest is not None else 0) + outdata = stream.tdata + self.tdata.connect_stream(outdata) def connect_master_rdata(self, master): if not isinstance(master, AxiMaster): @@ -2087,36 +2845,8 @@ def connect_master_rdata(self, master): if not self.noio: raise ValueError('I/O ports can not be connected to others.') - tdata = master.rdata.rdata - tvalid = master.rdata.rvalid - tready = master.rdata.rready - - tlast = 0 - - if master.rdata.rid is not None: - tid = master.rdata.rid - else: - tid = None - - if master.rdata.ruser is not None: - tuser = master.rdata.ruser - else: - tuser = None - - tdest = None - - self.tdata.tdata.connect(tdata) - self.tdata.tvalid.connect(tvalid) - tready.connect(self.tdata.tready) - - if self.tdata.tlast is not None: - self.tdata.tlast.connect(tlast if tlast is not None else 1) - if self.tdata.tid is not None: - self.tdata.tid.connect(tid if tid is not None else 0) - if self.tdata.tuser is not None: - self.tdata.tuser.connect(tuser if tuser is not None else 0) - if self.tdata.tdest is not None: - self.tdata.tdest.connect(tdest if tdest is not None else 0) + rdata = master.rdata + self.tdata.connect_master_rdata(rdata) class AxiStreamOut(object): @@ -2144,95 +2874,25 @@ def __init__(self, m, name, clk, rst, datawidth=32, itype = util.t_Reg if noio else None otype = util.t_Wire if noio else None - self.tdata = AxiStreamOutData(m, name, datawidth, + self.tdata = AxiStreamOutData(m, name, clk, rst, datawidth, with_last, with_strb, id_width, user_width, dest_width, - itype, otype) - - self.seq = Seq(m, name, clk, rst) - - # default values - if self.tdata.tuser is not None: - self.tdata.tuser.assign(0) + itype, otype) - if self.tdata.tid is not None: - self.tdata.tid.assign(0) + self.seq = Seq(m, name, clk, rst) def write_data(self, data, last=None, _id=None, user=None, dest=None, cond=None): """ @return ack """ - if cond is not None: - self.seq.If(cond) - - ack = vtypes.Ors(self.tdata.tready, vtypes.Not(self.tdata.tvalid)) - - self.seq.If(ack)( - self.tdata.tdata(data), - self.tdata.tvalid(1), - self.tdata.tlast(last) if self.tdata.tlast is not None else (), - self.tdata.tid(_id) if self.tdata.tid is not None else (), - self.tdata.tuser(user) if self.tdata.tuser is not None else (), - self.tdata.tdest(dest) if self.tdata.tdest is not None else (), - ) - - # de-assert - self.seq.Delay(1)( - self.tdata.tvalid(0), - self.tdata.tlast(0) if self.tdata.tlast is not None else () - ) - - # retry - self.seq.If(vtypes.Ands(self.tdata.tvalid, vtypes.Not(self.tdata.tready)))( - self.tdata.tvalid(self.tdata.tvalid), - self.tdata.tlast(self.tdata.tlast) if self.tdata.tlast is not None else () - ) - + ack = self.tdata.write_data(data, last, _id, user, dest, cond) return ack def connect(self, ports, name): if not self.noio: raise ValueError('I/O ports can not be connected to others.') - tdata = ports['_'.join([name, 'tdata'])] - tvalid = ports['_'.join([name, 'tvalid'])] - tready = ports['_'.join([name, 'tready'])] - - if '_'.join([name, 'tlast']) in ports: - tlast = ports['_'.join([name, 'tlast'])] - else: - tlast = None - - if '_'.join([name, 'tid']) in ports: - tid = ports['_'.join([name, 'tid'])] - else: - tid = None - - if '_'.join([name, 'tuser']) in ports: - tuser = ports['_'.join([name, 'tuser'])] - else: - tuser = None - - if '_'.join([name, 'tdest']) in ports: - tdest = ports['_'.join([name, 'tdest'])] - else: - tdest = None - - tdata.connect(self.tdata.tdata) - tvalid.connect(self.tdata.tvalid) - self.tdata.tready.connect(tready) - - if tlast is not None: - tlast.connect(self.tdata.tlast if self.tdata.tlast is not None else 1) - - if tuser is not None: - tuser.connect(self.tdata.tuser if self.tdata.tuser is not None else 0) - - if tid is not None: - tid.connect(self.tdata.tid if self.tdata.tid is not None else 0) - - if tdest is not None: - tdest.connect(self.tdata.tdest if self.tdata.tdest is not None else 0) + self.tdata.connect(ports, name) def connect_stream(self, stream): if not isinstance(stream, AxiStreamIn): @@ -2241,42 +2901,8 @@ def connect_stream(self, stream): if not self.noio: raise ValueError('I/O ports can not be connected to others.') - tdata = stream.tdata.tdata - tvalid = stream.tdata.tvalid - tready = stream.tdata.tready - - if stream.tdata.tlast is not None: - tlast = stream.tdata.tlast - else: - tlast = None - - if stream.tdata.tid is not None: - tid = stream.tdata.tid - else: - tid = None - - if stream.tdata.tuser is not None: - tuser = stream.tdata.tuser - else: - tuser = None - - if stream.tdata.tdest is not None: - tdest = stream.tdata.tdest - else: - tdest = None - - tdata.connect(self.tdata.tdata) - tvalid.connect(self.tdata.tvalid) - self.tdata.tready.connect(tready) - - if tlast is not None: - tlast.connect(self.tdata.tlast if self.tdata.tlast is not None else 1) - if tuser is not None: - tuser.connect(self.tdata.tuser if self.tdata.tuser is not None else 0) - if tid is not None: - tid.connect(self.tdata.tid if self.tdata.tid is not None else 0) - if tdest is not None: - tdest.connect(self.tdata.tdest if self.tdata.tdest is not None else 0) + indata = stream.tdata + self.tdata.connect_stream(indata) class AxiMemoryModel(AxiSlave): @@ -2319,26 +2945,21 @@ def __init__(self, m, name, clk, rst, datawidth=32, addrwidth=32, otype = util.t_Wire wdata_itype = util.t_Wire - self.waddr = AxiSlaveWriteAddress(m, name, datawidth, addrwidth, + self.waddr = AxiSlaveWriteAddress(m, name, clk, rst, datawidth, addrwidth, waddr_id_width, waddr_user_width, itype, otype) - self.wdata = AxiSlaveWriteData(m, name, datawidth, addrwidth, + self.wdata = AxiSlaveWriteData(m, name, clk, rst, datawidth, addrwidth, wdata_id_width, wdata_user_width, wdata_itype, otype) - self.wresp = AxiSlaveWriteResponse(m, name, datawidth, addrwidth, - wresp_id_width, wresp_user_width, itype, otype) - self.raddr = AxiSlaveReadAddress(m, name, datawidth, addrwidth, + self.wresp = AxiSlaveWriteResponse(m, name, clk, rst, datawidth, addrwidth, + wresp_id_width, wresp_user_width, wresp_user_mode, + itype, otype) + self.raddr = AxiSlaveReadAddress(m, name, clk, rst, datawidth, addrwidth, raddr_id_width, raddr_user_width, itype, otype) - self.rdata = AxiSlaveReadData(m, name, datawidth, addrwidth, - rdata_id_width, rdata_user_width, itype, otype) - - # default values - self.wresp.bresp.assign(0) - if self.wresp.buser is not None: - self.wresp.buser.assign(wresp_user_mode) - self.rdata.rresp.assign(0) - if self.rdata.ruser is not None: - self.rdata.ruser.assign(rdata_user_mode) + self.rdata = AxiSlaveReadData(m, name, clk, rst, datawidth, addrwidth, + rdata_id_width, rdata_user_width, rdata_user_mode, + itype, otype) self.seq = Seq(self.m, '_'.join(['', self.name, 'seq']), clk, rst) + self.waddr_fsm = FSM(self.m, '_'.join(['', self.name, 'waddr_fsm']), clk, rst) self.wdata_fsm = FSM(self.m, '_'.join(['', self.name, 'wdata_fsm']), clk, rst) self.raddr_fsm = FSM(self.m, '_'.join(['', self.name, 'raddr_fsm']), clk, rst) @@ -2904,33 +3525,24 @@ def __init__(self, m, name, clk, rst, datawidth=32, addrwidth=32, numports=2, otype = util.t_Wire wdata_itype = util.t_Wire - self.waddrs = [AxiSlaveWriteAddress(m, name + '_%d' % i, datawidth, addrwidth, + self.waddrs = [AxiSlaveWriteAddress(m, name + '_%d' % i, clk, rst, datawidth, addrwidth, waddr_id_width, waddr_user_width, itype, otype) for i in range(numports)] - self.wdatas = [AxiSlaveWriteData(m, name + '_%d' % i, datawidth, addrwidth, + self.wdatas = [AxiSlaveWriteData(m, name + '_%d' % i, clk, rst, datawidth, addrwidth, wdata_id_width, wdata_user_width, wdata_itype, otype) for i in range(numports)] - self.wresps = [AxiSlaveWriteResponse(m, name + '%d' % i, datawidth, addrwidth, - wresp_id_width, wresp_user_width, itype, otype) + self.wresps = [AxiSlaveWriteResponse(m, name + '_%d' % i, clk, rst, datawidth, addrwidth, + wresp_id_width, wresp_user_width, wresp_user_mode, + itype, otype) for i in range(numports)] - self.raddrs = [AxiSlaveReadAddress(m, name + '_%d' % i, datawidth, addrwidth, + self.raddrs = [AxiSlaveReadAddress(m, name + '_%d' % i, clk, rst, datawidth, addrwidth, raddr_id_width, raddr_user_width, itype, otype) for i in range(numports)] - self.rdatas = [AxiSlaveReadData(m, name + '_%d' % i, datawidth, addrwidth, - rdata_id_width, rdata_user_width, itype, otype) + self.rdatas = [AxiSlaveReadData(m, name + '_%d' % i, clk, rst, datawidth, addrwidth, + rdata_id_width, rdata_user_width, rdata_user_mode, + itype, otype) for i in range(numports)] - # default values - for wresp in self.wresps: - wresp.bresp.assign(0) - if wresp.buser is not None: - wresp.buser.assign(wresp_user_mode) - - for rdata in self.rdatas: - rdata.rresp.assign(0) - if rdata.ruser is not None: - rdata.ruser.assign(rdata_user_mode) - self.seq = Seq(self.m, '_'.join(['', self.name, 'seq']), clk, rst) self.waddr_fsms = [FSM(self.m, '_'.join(['', self.name, 'waddr_fsm_%d' % i]), clk, rst) @@ -3242,138 +3854,11 @@ def connect(self, index, ports, name): ports = defaultdict(lambda: None, ports) - if '_'.join([name, 'awid']) in ports: - awid = ports['_'.join([name, 'awid'])] - else: - awid = None - awaddr = ports['_'.join([name, 'awaddr'])] - awlen = ports['_'.join([name, 'awlen'])] - awsize = ports['_'.join([name, 'awsize'])] - awburst = ports['_'.join([name, 'awburst'])] - awlock = ports['_'.join([name, 'awlock'])] - awcache = ports['_'.join([name, 'awcache'])] - awprot = ports['_'.join([name, 'awprot'])] - awqos = ports['_'.join([name, 'awqos'])] - if '_'.join([name, 'awuser']) in ports: - awuser = ports['_'.join([name, 'awuser'])] - else: - awuser = None - awvalid = ports['_'.join([name, 'awvalid'])] - awready = ports['_'.join([name, 'awready'])] - - if self.waddrs[index].awid is not None: - self.waddrs[index].awid.connect(awid if awid is not None else 0) - self.waddrs[index].awaddr.connect(awaddr) - self.waddrs[index].awlen.connect(awlen if awlen is not None else 0) - self.waddrs[index].awsize.connect(awsize if awsize is not None else - int(math.log(self.datawidth // 8))) - self.waddrs[index].awburst.connect(awburst if awburst is not None else BURST_INCR) - self.waddrs[index].awlock.connect(awlock if awlock is not None else 0) - self.waddrs[index].awcache.connect(awcache) - self.waddrs[index].awprot.connect(awprot) - self.waddrs[index].awqos.connect(awqos if awqos is not None else 0) - if self.waddrs[index].awuser is not None: - self.waddrs[index].awuser.connect(awuser if awuser is not None else 0) - self.waddrs[index].awvalid.connect(awvalid) - awready.connect(self.waddrs[index].awready) - - wdata = ports['_'.join([name, 'wdata'])] - wstrb = ports['_'.join([name, 'wstrb'])] - wlast = ports['_'.join([name, 'wlast'])] - if '_'.join([name, 'wuser']) in ports: - wuser = ports['_'.join([name, 'wuser'])] - else: - wuser = None - wvalid = ports['_'.join([name, 'wvalid'])] - wready = ports['_'.join([name, 'wready'])] - - self.wdatas[index].wdata.connect(wdata) - self.wdatas[index].wstrb.connect(wstrb) - self.wdatas[index].wlast.connect(wlast if wlast is not None else 1) - if self.wdatas[index].wuser is not None: - self.wdatas[index].wuser.connect(wuser if wuser is not None else 0) - self.wdatas[index].wvalid.connect(wvalid) - wready.connect(self.wdatas[index].wready) - - if '_'.join([name, 'bid']) in ports: - bid = ports['_'.join([name, 'bid'])] - else: - bid = None - bresp = ports['_'.join([name, 'bresp'])] - if '_'.join([name, 'buser']) in ports: - buser = ports['_'.join([name, 'buser'])] - else: - buser = None - bvalid = ports['_'.join([name, 'bvalid'])] - bready = ports['_'.join([name, 'bready'])] - - if bid is not None: - bid.connect(self.wresps[index].bid if self.wresps[index].bid is not None else 0) - bresp.connect(self.wresps[index].bresp) - if buser is not None: - buser.connect(self.wresps[index].buser if self.wresps[index].buser is not None else 0) - bvalid.connect(self.wresps[index].bvalid) - self.wresps[index].bready.connect(bready) - - if '_'.join([name, 'arid']) in ports: - arid = ports['_'.join([name, 'arid'])] - else: - arid = None - araddr = ports['_'.join([name, 'araddr'])] - arlen = ports['_'.join([name, 'arlen'])] - arsize = ports['_'.join([name, 'arsize'])] - arburst = ports['_'.join([name, 'arburst'])] - arlock = ports['_'.join([name, 'arlock'])] - arcache = ports['_'.join([name, 'arcache'])] - arprot = ports['_'.join([name, 'arprot'])] - arqos = ports['_'.join([name, 'arqos'])] - if '_'.join([name, 'aruser']) in ports: - aruser = ports['_'.join([name, 'aruser'])] - else: - aruser = None - arvalid = ports['_'.join([name, 'arvalid'])] - arready = ports['_'.join([name, 'arready'])] - - if self.raddrs[index].arid is not None: - self.raddrs[index].arid.connect(arid if arid is not None else 0) - self.raddrs[index].araddr.connect(araddr) - self.raddrs[index].arlen.connect(arlen if arlen is not None else 0) - self.raddrs[index].arsize.connect(arsize if arsize is not None else - int(math.log(self.datawidth // 8))) - self.raddrs[index].arburst.connect(arburst if arburst is not None else BURST_INCR) - self.raddrs[index].arlock.connect(arlock if arlock is not None else 0) - self.raddrs[index].arcache.connect(arcache) - self.raddrs[index].arprot.connect(arprot) - self.raddrs[index].arqos.connect(arqos if arqos is not None else 0) - if self.raddrs[index].aruser is not None: - self.raddrs[index].aruser.connect(aruser if aruser is not None else 0) - self.raddrs[index].arvalid.connect(arvalid) - arready.connect(self.raddrs[index].arready) - - if '_'.join([name, 'rid']) in ports: - rid = ports['_'.join([name, 'rid'])] - else: - rid = None - rdata = ports['_'.join([name, 'rdata'])] - rresp = ports['_'.join([name, 'rresp'])] - rlast = ports['_'.join([name, 'rlast'])] - if '_'.join([name, 'ruser']) in ports: - ruser = ports['_'.join([name, 'ruser'])] - else: - ruser = None - rvalid = ports['_'.join([name, 'rvalid'])] - rready = ports['_'.join([name, 'rready'])] - - if rid is not None: - rid.connect(self.rdatas[index].rid if self.rdatas[index].rid is not None else 0) - rdata.connect(self.rdatas[index].rdata) - rresp.connect(self.rdatas[index].rresp) - if rlast is not None: - rlast.connect(self.rdatas[index].rlast) - if ruser is not None: - ruser.connect(self.rdatas[index].ruser if self.rdatas[index].ruser is not None else 0) - rvalid.connect(self.rdatas[index].rvalid) - self.rdatas[index].rready.connect(rready) + self.waddrs[index].connect(ports, name) + self.wdatas[index].connect(ports, name) + self.wresps[index].connect(ports, name) + self.raddrs[index].connect(ports, name) + self.rdatas[index].connect(ports, name) class AxiSerialMemoryModel(AxiSlave): @@ -3417,19 +3902,13 @@ def __init__(self, m, name, clk, rst, datawidth=32, addrwidth=32, self.wdata = AxiSlaveWriteData(m, name, datawidth, addrwidth, wdata_id_width, wdata_user_width, itype, otype) self.wresp = AxiSlaveWriteResponse(m, name, datawidth, addrwidth, - wresp_id_width, wresp_user_width, itype, otype) + wresp_id_width, wresp_user_width, wresp_user_mode, + itype, otype) self.raddr = AxiSlaveReadAddress(m, name, datawidth, addrwidth, raddr_id_width, raddr_user_width, itype, otype) self.rdata = AxiSlaveReadData(m, name, datawidth, addrwidth, - rdata_id_width, rdata_user_width, itype, otype) - - # default values - self.wresp.bresp.assign(0) - if self.wresp.buser is not None: - self.wresp.buser.assign(wresp_user_mode) - self.rdata.rresp.assign(0) - if self.rdata.ruser is not None: - self.rdata.ruser.assign(rdata_user_mode) + rdata_id_width, rdata_user_width, rdata_user_mode, + itype, otype) self.fsm = FSM(self.m, '_'.join(['', self.name, 'fsm']), clk, rst) self.seq = self.fsm.seq @@ -3793,33 +4272,24 @@ def __init__(self, m, name, clk, rst, datawidth=32, addrwidth=32, numports=2, itype = util.t_Reg otype = util.t_Wire - self.waddrs = [AxiSlaveWriteAddress(m, name + '_%d' % i, datawidth, addrwidth, + self.waddrs = [AxiSlaveWriteAddress(m, name + '_%d' % i, clk, rst, datawidth, addrwidth, waddr_id_width, waddr_user_width, itype, otype) for i in range(numports)] - self.wdatas = [AxiSlaveWriteData(m, name + '_%d' % i, datawidth, addrwidth, + self.wdatas = [AxiSlaveWriteData(m, name + '_%d' % i, clk, rst, datawidth, addrwidth, wdata_id_width, wdata_user_width, itype, otype) for i in range(numports)] - self.wresps = [AxiSlaveWriteResponse(m, name + '%d' % i, datawidth, addrwidth, - wresp_id_width, wresp_user_width, itype, otype) + self.wresps = [AxiSlaveWriteResponse(m, name + '_%d' % i, clk, rst, datawidth, addrwidth, + wresp_id_width, wresp_user_width, wresp_user_mode, + itype, otype) for i in range(numports)] - self.raddrs = [AxiSlaveReadAddress(m, name + '_%d' % i, datawidth, addrwidth, + self.raddrs = [AxiSlaveReadAddress(m, name + '_%d' % i, clk, rst, datawidth, addrwidth, raddr_id_width, raddr_user_width, itype, otype) for i in range(numports)] - self.rdatas = [AxiSlaveReadData(m, name + '_%d' % i, datawidth, addrwidth, - rdata_id_width, rdata_user_width, itype, otype) + self.rdatas = [AxiSlaveReadData(m, name + '_%d' % i, clk, rst, datawidth, addrwidth, + rdata_id_width, rdata_user_width, rdata_user_mode, + itype, otype) for i in range(numports)] - # default values - for wresp in self.wresps: - wresp.bresp.assign(0) - if wresp.buser is not None: - wresp.buser.assign(wresp_user_mode) - - for rdata in self.rdatas: - rdata.rresp.assign(0) - if rdata.ruser is not None: - rdata.ruser.assign(rdata_user_mode) - self.seq = Seq(self.m, '_'.join(['', self.name, 'seq']), clk, rst) self.fsms = [FSM(self.m, '_'.join(['', self.name, 'fsm_%d' % i]), clk, rst) for i in range(numports)] @@ -4054,138 +4524,11 @@ def connect(self, index, ports, name): ports = defaultdict(lambda: None, ports) - if '_'.join([name, 'awid']) in ports: - awid = ports['_'.join([name, 'awid'])] - else: - awid = None - awaddr = ports['_'.join([name, 'awaddr'])] - awlen = ports['_'.join([name, 'awlen'])] - awsize = ports['_'.join([name, 'awsize'])] - awburst = ports['_'.join([name, 'awburst'])] - awlock = ports['_'.join([name, 'awlock'])] - awcache = ports['_'.join([name, 'awcache'])] - awprot = ports['_'.join([name, 'awprot'])] - awqos = ports['_'.join([name, 'awqos'])] - if '_'.join([name, 'awuser']) in ports: - awuser = ports['_'.join([name, 'awuser'])] - else: - awuser = None - awvalid = ports['_'.join([name, 'awvalid'])] - awready = ports['_'.join([name, 'awready'])] - - if self.waddrs[index].awid is not None: - self.waddrs[index].awid.connect(awid if awid is not None else 0) - self.waddrs[index].awaddr.connect(awaddr) - self.waddrs[index].awlen.connect(awlen if awlen is not None else 0) - self.waddrs[index].awsize.connect(awsize if awsize is not None else - int(math.log(self.datawidth // 8))) - self.waddrs[index].awburst.connect(awburst if awburst is not None else BURST_INCR) - self.waddrs[index].awlock.connect(awlock if awlock is not None else 0) - self.waddrs[index].awcache.connect(awcache) - self.waddrs[index].awprot.connect(awprot) - self.waddrs[index].awqos.connect(awqos if awqos is not None else 0) - if self.waddrs[index].awuser is not None: - self.waddrs[index].awuser.connect(awuser if awuser is not None else 0) - self.waddrs[index].awvalid.connect(awvalid) - awready.connect(self.waddrs[index].awready) - - wdata = ports['_'.join([name, 'wdata'])] - wstrb = ports['_'.join([name, 'wstrb'])] - wlast = ports['_'.join([name, 'wlast'])] - if '_'.join([name, 'wuser']) in ports: - wuser = ports['_'.join([name, 'wuser'])] - else: - wuser = None - wvalid = ports['_'.join([name, 'wvalid'])] - wready = ports['_'.join([name, 'wready'])] - - self.wdatas[index].wdata.connect(wdata) - self.wdatas[index].wstrb.connect(wstrb) - self.wdatas[index].wlast.connect(wlast if wlast is not None else 1) - if self.wdatas[index].wuser is not None: - self.wdatas[index].wuser.connect(wuser if wuser is not None else 0) - self.wdatas[index].wvalid.connect(wvalid) - wready.connect(self.wdatas[index].wready) - - if '_'.join([name, 'bid']) in ports: - bid = ports['_'.join([name, 'bid'])] - else: - bid = None - bresp = ports['_'.join([name, 'bresp'])] - if '_'.join([name, 'buser']) in ports: - buser = ports['_'.join([name, 'buser'])] - else: - buser = None - bvalid = ports['_'.join([name, 'bvalid'])] - bready = ports['_'.join([name, 'bready'])] - - if bid is not None: - bid.connect(self.wresps[index].bid if self.wresps[index].bid is not None else 0) - bresp.connect(self.wresps[index].bresp) - if buser is not None: - buser.connect(self.wresps[index].buser if self.wresps[index].buser is not None else 0) - bvalid.connect(self.wresps[index].bvalid) - self.wresps[index].bready.connect(bready) - - if '_'.join([name, 'arid']) in ports: - arid = ports['_'.join([name, 'arid'])] - else: - arid = None - araddr = ports['_'.join([name, 'araddr'])] - arlen = ports['_'.join([name, 'arlen'])] - arsize = ports['_'.join([name, 'arsize'])] - arburst = ports['_'.join([name, 'arburst'])] - arlock = ports['_'.join([name, 'arlock'])] - arcache = ports['_'.join([name, 'arcache'])] - arprot = ports['_'.join([name, 'arprot'])] - arqos = ports['_'.join([name, 'arqos'])] - if '_'.join([name, 'aruser']) in ports: - aruser = ports['_'.join([name, 'aruser'])] - else: - aruser = None - arvalid = ports['_'.join([name, 'arvalid'])] - arready = ports['_'.join([name, 'arready'])] - - if self.raddrs[index].arid is not None: - self.raddrs[index].arid.connect(arid if arid is not None else 0) - self.raddrs[index].araddr.connect(araddr) - self.raddrs[index].arlen.connect(arlen if arlen is not None else 0) - self.raddrs[index].arsize.connect(arsize if arsize is not None else - int(math.log(self.datawidth // 8))) - self.raddrs[index].arburst.connect(arburst if arburst is not None else BURST_INCR) - self.raddrs[index].arlock.connect(arlock if arlock is not None else 0) - self.raddrs[index].arcache.connect(arcache) - self.raddrs[index].arprot.connect(arprot) - self.raddrs[index].arqos.connect(arqos if arqos is not None else 0) - if self.raddrs[index].aruser is not None: - self.raddrs[index].aruser.connect(aruser if aruser is not None else 0) - self.raddrs[index].arvalid.connect(arvalid) - arready.connect(self.raddrs[index].arready) - - if '_'.join([name, 'rid']) in ports: - rid = ports['_'.join([name, 'rid'])] - else: - rid = None - rdata = ports['_'.join([name, 'rdata'])] - rresp = ports['_'.join([name, 'rresp'])] - rlast = ports['_'.join([name, 'rlast'])] - if '_'.join([name, 'ruser']) in ports: - ruser = ports['_'.join([name, 'ruser'])] - else: - ruser = None - rvalid = ports['_'.join([name, 'rvalid'])] - rready = ports['_'.join([name, 'rready'])] - - if rid is not None: - rid.connect(self.rdatas[index].rid if self.rdatas[index].rid is not None else 0) - rdata.connect(self.rdatas[index].rdata) - rresp.connect(self.rdatas[index].rresp) - if rlast is not None: - rlast.connect(self.rdatas[index].rlast) - if ruser is not None: - ruser.connect(self.rdatas[index].ruser if self.rdatas[index].ruser is not None else 0) - rvalid.connect(self.rdatas[index].rvalid) - self.rdatas[index].rready.connect(rready) + self.waddrs[index].connect(ports, name) + self.wdatas[index].connect(ports, name) + self.wresps[index].connect(ports, name) + self.raddrs[index].connect(ports, name) + self.rdatas[index].connect(ports, name) def make_memory_image(filename, length, pattern='inc', dtype=None, diff --git a/veriloggen/types/componentgen.py b/veriloggen/types/componentgen.py index 8a1489b1..402da5b7 100644 --- a/veriloggen/types/componentgen.py +++ b/veriloggen/types/componentgen.py @@ -315,12 +315,16 @@ def mkLogicalPort(self, attr): def mkPhysicalPortMemory(self, obj, attr): if hasattr(obj.waddr, attr.lower()): name = getattr(obj.waddr, attr.lower()).name + elif hasattr(obj.wdata, 'ext_' + attr.lower()): + name = getattr(obj.wdata, 'ext_' + attr.lower()).name elif hasattr(obj.wdata, attr.lower()): name = getattr(obj.wdata, attr.lower()).name elif hasattr(obj.wresp, attr.lower()): name = getattr(obj.wresp, attr.lower()).name elif hasattr(obj.raddr, attr.lower()): name = getattr(obj.raddr, attr.lower()).name + elif hasattr(obj.rdata, 'ext_' + attr.lower()): + name = getattr(obj.rdata, 'ext_' + attr.lower()).name elif hasattr(obj.rdata, attr.lower()): name = getattr(obj.rdata, attr.lower()).name else: diff --git a/veriloggen/types/ipxact.py b/veriloggen/types/ipxact.py index 8c0fe2de..f484bd90 100644 --- a/veriloggen/types/ipxact.py +++ b/veriloggen/types/ipxact.py @@ -53,9 +53,9 @@ def to_ipxact(m, ip_name=None, ip_ver='1.0', if not os.path.exists(dirname): os.mkdir(dirname) - #if not os.path.exists(dirname + '/' + 'data'): + # if not os.path.exists(dirname + '/' + 'data'): # os.mkdir(dirname + '/' + 'data') - #if not os.path.exists(dirname + '/' + 'bd'): + # if not os.path.exists(dirname + '/' + 'bd'): # os.mkdir(dirname + '/' + 'bd') if not os.path.exists(dirname + '/' + 'xgui'): os.mkdir(dirname + '/' + 'xgui') @@ -109,19 +109,19 @@ def to_ipxact(m, ip_name=None, ip_ver='1.0', f.write(xml_code) f.close() - ## xdc + # xdc #xdc_code = open(TEMPLATE_DIR + 'ipxact.xdc', 'r').read() #f = open(xdcpath + xdcname, 'w') - #f.write(xdc_code) - #f.close() + # f.write(xdc_code) + # f.close() - ## bd + # bd #bd_code = open(TEMPLATE_DIR + 'bd.tcl', 'r').read() #f = open(bdpath + bdname, 'w') - #f.write(bd_code) - #f.close() + # f.write(bd_code) + # f.close() # xgui file xgui_code = open(TEMPLATE_DIR + 'xgui_tcl.txt', 'r').read() diff --git a/veriloggen/types/skidbuffer.py b/veriloggen/types/skidbuffer.py new file mode 100644 index 00000000..7dc92e79 --- /dev/null +++ b/veriloggen/types/skidbuffer.py @@ -0,0 +1,120 @@ +from __future__ import absolute_import +from __future__ import print_function + +import veriloggen.core.vtypes as vtypes +from veriloggen.seq.seq import TmpSeq + + +class SkidBuffer(vtypes.VeriloggenNode): + + def __init__(self, m, clk, rst, + s_valid, m_ready, *s_values, prefix=None): + + if prefix is None: + prefix = 'skidbuffer' + + if not s_values: + raise ValueError("'s_values' must not be empty.") + + self.m = m + self.clk = clk + self.rst = rst + self.s_values = s_values + self.s_valid = s_valid + self.m_ready = m_ready + + width = 0 + _s_values = [] + for s_value in s_values: + v = m.TmpWireLike(s_value, prefix=prefix + '_s_value') + v.assign(s_value) + _s_values.append(v) + w = s_value.get_width() + if w is None: + w = 1 + width += w + + _s_data = m.TmpWire(width, prefix=prefix + '_s_data') + _s_data.assign(vtypes.Cat(*_s_values)) + + _s_valid = m.TmpWire(prefix=prefix + '_s_valid') + _s_valid.assign(s_valid) + _m_ready = m.TmpWire(prefix=prefix + '_m_ready') + _m_ready.assign(m_ready) + + (m_data, m_valid, s_ready) = make_skidbuffer(m, clk, rst, + _s_data, _s_valid, _m_ready, + prefix=prefix) + + self.m_values = [] + msb = width - 1 + for s_value in s_values: + v = m.TmpWireLike(s_value, prefix=prefix + '_m_value') + w = v.get_width() + if w is None: + w = 1 + lsb = msb - w + 1 + v.assign(vtypes.Slice(m_data, msb, lsb)) + self.m_values.append(v) + msb -= w + + self.m_valid = m_valid + self.s_ready = s_ready + + @property + def values(self): + return self.m_values + + @property + def valid(self): + return self.m_valid + + @property + def ready(self): + return self.s_ready + + def __getitem__(self, index): + return self.m_values[index] + + +def make_skidbuffer(m, clk, rst, + s_data, s_valid, m_ready, + prefix=None): + + if prefix is None: + if hasattr(s_data, 'name'): + prefix = '_'.join([s_data.name, 'skidbuffer']) + else: + prefix = 'skidbuffer' + + m_data = m.TmpRegLike(s_data, prefix=prefix + '_data', initval=0) + m_valid = m.TmpReg(prefix=prefix + '_valid', initval=0) + + s_ready = m.TmpWire(prefix=prefix + '_ready') + + tmp_data = m.TmpRegLike(s_data, prefix=prefix + '_tmp_data', initval=0) + tmp_valid = m.TmpReg(prefix=prefix + '_tmp_valid', initval=0) + + next_data = m.TmpWireLike(s_data, prefix=prefix + '_next_data') + next_valid = m.TmpWire(prefix=prefix + '_next_valid') + + s_ready.assign(vtypes.Not(tmp_valid)) + + next_data.assign(vtypes.Mux(tmp_valid, tmp_data, s_data)) + next_valid.assign(vtypes.Ors(tmp_valid, s_valid)) + + seq = TmpSeq(m, clk, rst, prefix=prefix + '_seq') + + seq.If(vtypes.Ors(m_ready, vtypes.Not(m_valid)))( + m_data(next_data), + m_valid(next_valid), + ) + seq.If(vtypes.Not(tmp_valid), m_valid, vtypes.Not(m_ready))( + tmp_data(s_data), + tmp_valid(s_valid), + ) + seq.If(tmp_valid, m_ready)( + tmp_valid(0) + ) + + return m_data, m_valid, s_ready diff --git a/veriloggen/verilog/to_verilog.py b/veriloggen/verilog/to_verilog.py index e9aead78..6e415c1f 100644 --- a/veriloggen/verilog/to_verilog.py +++ b/veriloggen/verilog/to_verilog.py @@ -12,7 +12,7 @@ from pyverilog.ast_code_generator.codegen import ASTCodeGenerator -#------------------------------------------------------------------------- +# ------------------------------------------------------------------------- def write_verilog(node, filename=None, for_verilator=False): visitor = VerilogModuleVisitor(for_verilator) modules = tuple(node.get_modules().values()) @@ -36,7 +36,7 @@ def write_verilog(node, filename=None, for_verilator=False): return code -#------------------------------------------------------------------------- +# ------------------------------------------------------------------------- class VerilogCommonVisitor(object): def __init__(self, for_verilator=False, in_initial=False): @@ -53,7 +53,7 @@ def visit(self, node): visitor = getattr(self, 'visit_' + name, self.generic_visit) return visitor(node) - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- # First class object wrapper def visit_Int(self, node): value_list = [] @@ -127,7 +127,7 @@ def visit_Float(self, node): def visit_Str(self, node): return vast.StringConst(node.value) - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- def visit_bool(self, node): if node: return vast.IntConst('1') @@ -159,7 +159,7 @@ def _optimize_block(self, node): ret.append(n) return vast.Block(tuple(ret)) - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- def visit_Parameter(self, node): name = node.name return vast.Identifier(name) @@ -168,7 +168,7 @@ def visit_Localparam(self, node): name = node.name return vast.Identifier(name) - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- def visit_Input(self, node): name = node.name return vast.Identifier(name) @@ -205,11 +205,11 @@ def visit_AnyType(self, node): name = node.name return vast.Identifier(name) - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- def visit__SkipUnaryOperator(self, node): return self.visit(node.right) - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- def visit_Power(self, node): left = self.visit(node.left) right = self.visit(node.right) @@ -325,7 +325,7 @@ def visit_Lor(self, node): right = self.visit(node.right) return vast.Lor(left, right) - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- def visit_Uplus(self, node): right = self.visit(node.right) return vast.Uplus(right) @@ -366,7 +366,7 @@ def visit_Uxnor(self, node): right = self.visit(node.right) return vast.Uxnor(right) - #--------------------------------------------------------------------------- + # --------------------------------------------------------------------------- def visit_Pointer(self, node): var = self.visit(node.var) pos = self.visit(node.pos) @@ -388,14 +388,14 @@ def visit_Repeat(self, node): times = self.visit(node.times) return vast.Repeat(var, times) - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- def visit_Cond(self, node): cond = self.visit(node.condition) true_value = self.visit(node.true_value) false_value = self.visit(node.false_value) return vast.Cond(cond, true_value, false_value) - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- def visit_If(self, node): cond = self.visit(node.condition) true_statement = self.visit(node.true_statement) @@ -410,7 +410,7 @@ def visit_If(self, node): false_statement = false_statement.statements[0] return vast.IfStatement(cond, true_statement, false_statement) - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- def visit_For(self, node): for_visitor = VerilogBlockingVisitor(self.for_verilator, self.in_initial) pre = for_visitor.visit(node.pre) @@ -419,13 +419,13 @@ def visit_For(self, node): statement = self.visit(node.statement) return vast.ForStatement(pre, cond, post, statement) - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- def visit_While(self, node): cond = self.visit(node.condition) statement = self.visit(node.statement) return vast.WhileStatement(cond, statement) - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- def visit_Case(self, node): comp = self.visit(node.comp) statement = tuple([self.visit(s) for s in node.statement]) @@ -442,7 +442,7 @@ def visit_When(self, node): statement = self.visit(node.statement) return vast.Case(cond, statement) - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- def visit_ScopeIndex(self, node): name = node.name index = self.visit(node.index) @@ -479,7 +479,7 @@ def visit_Scope(self, node): return vast.Identifier(scope[0].name) return vast.Identifier(scope[-1].name, vast.IdentifierScope(tuple(scope[:-1]))) - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- def visit_SystemTask(self, node): cmd = node.cmd if (self.for_verilator and (cmd == 'dumpfile' or cmd == 'dumpvars')): @@ -494,7 +494,7 @@ def visit_SingleStatement(self, node): statement = self.visit(node.statement) return vast.SingleStatement(statement) - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- def visit_Event(self, node): sensitivity = vast.SensList( tuple([self.visit(n) if isinstance(n, vtypes.Sensitive) else @@ -507,7 +507,7 @@ def visit_Delay(self, node): delay = self.visit(node.value) return vast.SingleStatement(vast.DelayStatement(delay)) - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- def visit_Function(self, node): name = node.name return vast.Identifier(name) @@ -517,7 +517,7 @@ def visit_FunctionCall(self, node): args = tuple([self.visit(a) for a in node.args]) return vast.FunctionCall(func, args) - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- def visit_Task(self, node): name = node.name return vast.Identifier(name) @@ -527,11 +527,11 @@ def visit_TaskCall(self, node): args = tuple([self.visit(a) for a in node.args]) return vast.TaskCall(name, args) - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- def visit_Instance(self, node): return vast.Identifier(node.instname) - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- def visit_EmbeddedCode(self, node): return vast.EmbeddedCode(node.code) @@ -539,7 +539,7 @@ def visit_EmbeddedNumeric(self, node): return vast.EmbeddedCode(node.code) -#------------------------------------------------------------------------- +# ------------------------------------------------------------------------- class VerilogModuleVisitor(VerilogCommonVisitor): def __init__(self, for_verilator=False): @@ -549,7 +549,7 @@ def __init__(self, for_verilator=False): self.blocking_visitor = VerilogBlockingVisitor(for_verilator) self.module = None - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- def make_width(self, node): if node.raw_width is not None: msb = self.bind_visitor.visit(node.raw_width[0]) @@ -582,7 +582,7 @@ def make_dims(self, node): return None - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- def visit(self, node): if isinstance(node, module.Module) and not isinstance(node, module.Generate): return self.visit_Module(node) @@ -592,7 +592,7 @@ def visit(self, node): visitor = getattr(self, 'visit_' + name, self.generic_visit) return visitor(node) - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- def visit_Module(self, node): self.module = node name = node.name @@ -617,7 +617,7 @@ def visit_Module(self, node): self.module = None return m - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- def visit_Parameter(self, node): name = node.name value = self.bind_visitor.visit(node.value) @@ -634,7 +634,7 @@ def visit_Localparam(self, node): signed = node.signed return vast.Localparam(name, value, width, signed) - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- def visit_Input(self, node): name = node.name width = self.make_width(node) @@ -698,7 +698,7 @@ def visit_Genvar(self, node): def visit_AnyType(self, node): return None - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- def visit_Posedge(self, node): sig = self.bind_visitor.visit(node.name) t = 'posedge' @@ -714,7 +714,7 @@ def visit_SensitiveAll(self, node): t = 'all' return vast.Sens(sig, t) - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- def visit_Always(self, node): sens = (tuple([self.visit(n) if isinstance(n, vtypes.Sensitive) else vast.Sens(self.always_visitor.visit(n), 'level') @@ -725,7 +725,7 @@ def visit_Always(self, node): vast.Block(tuple([self.always_visitor.visit(n) for n in node.statement]))) return vast.Always(sensitivity, statement) - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- def visit_Assign(self, node): if not isinstance(node.statement, vtypes.Subst): raise TypeError("Assign expects Subst object.") @@ -735,7 +735,7 @@ def visit_Assign(self, node): rvalue = vast.Rvalue(right) return vast.Assign(lvalue, rvalue) - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- def visit_Initial(self, node): self.blocking_visitor.in_initial = True statement = self._optimize_block( @@ -743,7 +743,7 @@ def visit_Initial(self, node): self.blocking_visitor.in_initial = False return vast.Initial(statement) - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- def visit_Function(self, node): name = node.name retwidth = self.make_width(node) @@ -753,7 +753,7 @@ def visit_Function(self, node): vast.Block(tuple([self.blocking_visitor.visit(s) for s in node.statement])))) return vast.Function(name, retwidth, statement) - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- def visit_Task(self, node): name = node.name statement = ([self.visit(v).first for v in node.io_variable.values()] + @@ -762,7 +762,7 @@ def visit_Task(self, node): vast.Block(tuple([self.blocking_visitor.visit(s) for s in node.statement])))) return vast.Task(name, statement) - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- def visit_Instance(self, node): module = node.module.name parameterlist = [vast.ParamArg( @@ -773,7 +773,7 @@ def visit_Instance(self, node): instance = vast.Instance(module, name, portlist, parameterlist) return vast.InstanceList(module, parameterlist, (instance,)) - #------------------------------------------------------------------------- + # ------------------------------------------------------------------------- def _visit_Generate(self, node): params = ([self.visit(v) for v in node.global_constant.values()]) params = [i for i in params if i is not None] @@ -815,12 +815,12 @@ def visit_GenerateIfElse(self, node): return None -#------------------------------------------------------------------------- +# ------------------------------------------------------------------------- class VerilogBindVisitor(VerilogCommonVisitor): pass -#------------------------------------------------------------------------- +# ------------------------------------------------------------------------- class VerilogAlwaysVisitor(VerilogCommonVisitor): def visit_Subst(self, node): @@ -835,7 +835,7 @@ def visit_Subst(self, node): return vast.NonblockingSubstitution(lvalue, rvalue, ldelay, rdelay) -#------------------------------------------------------------------------- +# ------------------------------------------------------------------------- class VerilogBlockingVisitor(VerilogCommonVisitor): def visit_Subst(self, node):