Skip to content

Pull requests: PyHDI/Pyverilog

New pull request New
Clear current search query, filters, and sorts
7 Open 33 Closed
7 Open 33 Closed
Author
Filter by author
Loading
Label
Filter by label
Loading
Use alt + click/return to exclude labels
or ⇧ + click/return for logical OR
Projects
Filter by project
Loading
Milestones
Filter by milestone
Loading
Reviews
Filter by reviews
No reviews Review required Approved review Changes requested
Assignee
Filter by who’s assigned
Assigned to nobody Loading
Sort
Sort by
Newest Oldest Most commented Least commented Recently updated Least recently updated Best match
Most reactions
👍 👎 😄 🎉 😕 ❤️ 🚀 👀

Pull requests list

fix: 🐛 merge pr and fix struct statement
#132 by Crescentm was closed Nov 10, 2024 Loading… updated Nov 10, 2024
1
Use context manager to avoid ResourceWarning
#99 by leonardt was merged Dec 23, 2022 Loading… updated Dec 23, 2022
Added end_lineno to indicate the last line number in always, module, …
#88 by dyadav7 was merged Dec 23, 2022 Loading… updated Dec 23, 2022
1
Defparam support
#107 by trharoldsen was closed Jul 27, 2022 Loading… updated Jul 27, 2022
Feature addition: Verilog code in Python strings along with verilog files.
#64 by ndyashas was merged Dec 14, 2020 Loading… updated Dec 14, 2020
2
add parsing rule, function integer ID
#55 by JaewonHur was merged Mar 12, 2020 Loading… updated Mar 12, 2020
Req1. add parsing rule, integer declaration and initialization.
#54 by JaewonHur was merged Mar 12, 2020 Loading… updated Mar 12, 2020
add Sla operator support and fix operator percedence according to latest IEEE verilog document
#49 by tomchean was merged Nov 16, 2019 Loading… updated Nov 16, 2019
Added a number of configuration options
#50 by donn was merged Nov 16, 2019 Loading… updated Nov 16, 2019
Extend parser for n-d array support
#51 by rsetaluri was merged Nov 16, 2019 Loading… updated Nov 16, 2019
1
add-inout
#48 by tomchean was merged Jul 9, 2019 Loading… updated Jul 9, 2019
Add comma separated edgesigs
#45 by hofstee was merged Jul 7, 2019 Loading… updated Jul 8, 2019
add preliminary support for always_latch
#47 by hofstee was merged Jul 7, 2019 Loading… updated Jul 8, 2019
Preliminary support for SystemVerilog logic, always_ff, always_comb, unique case
#38 by leonardt was closed Mar 29, 2019 Loading… updated Mar 29, 2019
3
Add end lineno
#40 by rsetaluri was closed Mar 12, 2019 Loading… updated Mar 12, 2019
Revert "reset detection for issue#14"
#26 by shtaxxx was closed Mar 24, 2018 Loading… updated Mar 24, 2018
Revert "introduce travis ci"
#27 by shtaxxx was closed Mar 24, 2018 Loading… updated Mar 24, 2018
correct a spelling error
#34 by jinluyang was merged May 23, 2017 Loading… updated May 23, 2017
change literals case insencitiveness
#28 by metanest was merged Jan 11, 2016 Loading… updated Jan 11, 2016
reset detection for issue#14
#23 by fukatani was merged Oct 25, 2015 Loading… updated Oct 25, 2015
introduce travis ci
#22 by fukatani was merged Oct 25, 2015 Loading… updated Oct 25, 2015
Replaced reset dection method.
#20 by fukatani was closed Sep 1, 2015 Loading… updated Sep 1, 2015
1
Provisional commit for issue #14. Implemented function for detecting reset.
#19 by fukatani was merged Aug 31, 2015 Loading… updated Aug 31, 2015
Support case statement in function.
#18 by fukatani was merged Aug 23, 2015 Loading… updated Aug 24, 2015
2
Change behavior of walkey.makeTree for assign statement using partselect
#17 by fukatani was merged Aug 23, 2015 Loading… updated Aug 23, 2015
ProTip! What’s not been updated in a month: updated:<2025-06-28.