Skip to content

Pull requests: PyHDI/Pyverilog

New pull request New
Clear current search query, filters, and sorts
7 Open 33 Closed
7 Open 33 Closed
Author
Filter by author
Loading
Label
Filter by label
Loading
Use alt + click/return to exclude labels
or ⇧ + click/return for logical OR
Projects
Filter by project
Loading
Milestones
Filter by milestone
Loading
Reviews
Filter by reviews
No reviews Review required Approved review Changes requested
Assignee
Filter by who’s assigned
Assigned to nobody Loading
Sort
Sort by
Newest Oldest Most commented Least commented Recently updated Least recently updated Best match
Most reactions
👍 👎 😄 🎉 😕 ❤️ 🚀 👀

Pull requests list

casex statement in AST code generator
#10 by tc466 was merged Jun 21, 2015 Loading…
change literals case insencitiveness
#28 by metanest was merged Jan 11, 2016 Loading…
Revert "reset detection for issue#14"
#26 by shtaxxx was closed Mar 24, 2018 Loading…
Revert "introduce travis ci"
#27 by shtaxxx was closed Mar 24, 2018 Loading…
Change behavior of walkey.makeTree for assign statement using partselect
#17 by fukatani was merged Aug 23, 2015 Loading…
Support case statement in function.
#18 by fukatani was merged Aug 23, 2015 Loading…
2
introduce travis ci
#22 by fukatani was merged Oct 25, 2015 Loading…
Replaced reset dection method.
#20 by fukatani was closed Sep 1, 2015 Loading…
1
Provisional commit for issue #14. Implemented function for detecting reset.
#19 by fukatani was merged Aug 31, 2015 Loading…
correct a spelling error
#34 by jinluyang was merged May 23, 2017 Loading…
reset detection for issue#14
#23 by fukatani was merged Oct 25, 2015 Loading…
modify bug: '([0-9]*\'s(d?))?[0-9][0-9_]*' treat as unsigned decimal. (...
#8 by fukatani was closed Apr 5, 2015 Loading…
Work
#9 by fukatani was merged Apr 9, 2015 Loading…
supply0,supply1
#6 by fukatani was merged Apr 1, 2015 Loading…
Work
#4 by fukatani was merged Mar 12, 2015 Loading…
signedに関する修整とcasexの追加
#3 by fukatani was merged Mar 12, 2015 Loading…
1
modify for $signed and $unsigned
#5 by fukatani was merged Mar 12, 2015 Loading…
Sens info
#7 by fukatani was merged Apr 1, 2015 Loading…
Preliminary support for SystemVerilog logic, always_ff, always_comb, unique case
#38 by leonardt was closed Mar 29, 2019 Loading…
3
add-inout
#48 by tomchean was merged Jul 9, 2019 Loading…
add preliminary support for always_latch
#47 by hofstee was merged Jul 7, 2019 Loading…
Add comma separated edgesigs
#45 by hofstee was merged Jul 7, 2019 Loading…
Added a number of configuration options
#50 by donn was merged Nov 16, 2019 Loading…
Add end lineno
#40 by rsetaluri was closed Mar 12, 2019 Loading…
add Sla operator support and fix operator percedence according to latest IEEE verilog document
#49 by tomchean was merged Nov 16, 2019 Loading…
ProTip! What’s not been updated in a month: updated:<2025-06-28.