Characteristics of the implementation :
- VLEN=32, VSEW=32, Vm bit=1 (unmasked),16 ALU lanes, 16 elements could be loaded/stored from/to memory into/from the vector register per clock cycle.
- Instructions considered for Unit-Stride and Vector Integer Arithmetic operations.
- Fetch and decode done in the same cycle.
- Memory access stage for Arithmetic instructions is ignored as memory will not be accessed.