usrp2_alias.patch

Index: usrp2/fpga/sdr_lib/small_hb_dec.v
===================================================================
--- usrp2/fpga/sdr_lib/small_hb_dec.v	(revision 10194)
+++ usrp2/fpga/sdr_lib/small_hb_dec.v	(working copy)
@@ -31,8 +31,8 @@
    always @(posedge clk) go_d3 <= go_d2;
    always @(posedge clk) go_d4 <= go_d3;
 
-   wire [17:0] 		coeff_a = -10690;
-   wire [17:0] 		coeff_b = 75809;
+   wire [17:0] 		coeff_a = 0;
+   wire [17:0] 		coeff_b = 0;
    
    reg [WIDTH-1:0] 	d1, d2, d3, d4 , d5, d6;
    always @(posedge clk)
Index: usrp2/fpga/sdr_lib/hb_dec.v
===================================================================
--- usrp2/fpga/sdr_lib/hb_dec.v	(revision 10194)
+++ usrp2/fpga/sdr_lib/hb_dec.v	(working copy)
@@ -83,20 +83,20 @@
 
    always @*            // Outer coeffs
      case(phase_d1)
-       1 : coeff1 = -107;
-       2 : coeff1 = 445;
-       3 : coeff1 = -1271;
-       4 : coeff1 = 2959;
-       default : coeff1 = -107;
+       1 : coeff1 = 0;
+       2 : coeff1 = 0;
+       3 : coeff1 = 0;
+       4 : coeff1 = 0;
+       default : coeff1 = 0;
      endcase // case(phase)
    
    always @*            //  Inner coeffs
      case(phase_d1)
-       1 : coeff2 = -6107;
-       2 : coeff2 = 11953;
-       3 : coeff2 = -24706;
-       4 : coeff2 = 82359;
-       default : coeff2 = -6107;
+       1 : coeff2 = 0;
+       2 : coeff2 = 0;
+       3 : coeff2 = 0;
+       4 : coeff2 = 0;
+       default : coeff2 = 0;
      endcase // case(phase)
    
    srl #(.WIDTH(IWIDTH)) srl_odd_a