Working OK on MultiSim

Author: PY1CX

74ALS190-VHDL/src/contador.vhd

@@ -19,7 +19,7 @@ begin   process(clock,reset)
          temp <= "0000";
       elsif(rising_edge(clock)) then
          if enable='0' then
-            if temp="1001" then
+            if temp="1111" then
                temp<="0000";
             else
                temp <= temp + 1;

74ALS190-VHDL/src/contador.vhd.bak

@@ -1 +1,31 @@
-
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+
+entity counter_190 is
+   port( enable: in std_logic;
+ 	 clock: in std_logic;
+ 	 reset: in std_logic;
+ 	 output: out std_logic_vector(0 to 3));
+end counter_190;
+ 
+architecture Behavioral of counter_190 is
+   signal temp: std_logic_vector(0 to 3);
+begin   process(clock,reset)
+   begin
+      if reset='1' then
+         temp <= "0000";
+      elsif(rising_edge(clock)) then
+         if enable='0' then
+            if temp="1001" then
+               temp<="0000";
+            else
+               temp <= temp + 1;
+            end if;
+         end if;
+      end if;
+   end process;
+   output <= temp;
+end Behavioral;

74ALS190-VHDL/src/tb_contador.vhd

@@ -34,14 +34,20 @@ counter1: counter_190 port map ( enable => enable_1, clock => clk_1, reset => re
 
 estimulo : process
 begin
-  wait for 5 ns; reset_1 <= '0'; enable_1 <= '0';
+  reset_1 <= '1'; enable_1 <= '1';
+  wait for 5 ns;   
+  enable_1 <= '0'; reset_1 <= '0';
+  wait for 80 ns;
 end process estimulo;
 
 clock_estimulo : process
 
 begin
-  wait for 1 ns; clk_1 <= '0';
-  wait for 1 ns; clk_1 <= '1';
+  clk_1 <= '0';
+  wait for 1 ns;
+  clk_1 <= '1';
+  wait for 1 ns;
+
 end process clock_estimulo;
 
 end counter;

74ALS190-VHDL/src/tb_contador.vhd.bak

@@ -34,14 +34,20 @@ counter1: counter_190 port map ( enable => enable_1, clock => clk_1, reset => re
 
 estimulo : process
 begin
-  wait for 5 ns; reset_1 <= '0'; enable_1 <= '1';
+  reset_1 <= '1'; enable_1 <= '1';
+  wait for 5 ns;   
+  enable_1 <= '0'; reset_1 <= '0';
+  wait for 40 ns;
 end process estimulo;
 
 clock_estimulo : process
 
 begin
-  wait for 1 ns; clk_1 <= '0';
-  wait for 1 ns; clk_1 <= '1';
+  clk_1 <= '0';
+  wait for 1 ns;
+  clk_1 <= '1';
+  wait for 1 ns;
+
 end process clock_estimulo;
 
 end counter;