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| 1 | +/* |
| 2 | + * ads1220.h |
| 3 | + * |
| 4 | + * AD9833 Driver |
| 5 | + * Author: Felipe Navarro |
| 6 | + * |
| 7 | + * Fault Common Numbers: |
| 8 | + * -3 Semaphore |
| 9 | + * -2 SPI |
| 10 | + * -1 Wrong Configuration |
| 11 | + * |
| 12 | + * 1 Represent Success |
| 13 | + * |
| 14 | + */ |
| 15 | + |
| 16 | +#include "main.h" |
| 17 | +#include "stm32f4xx_hal.h" |
| 18 | +#include "cmsis_os.h" |
| 19 | +#include "spi.h" |
| 20 | +#include "gpio.h" |
| 21 | +#include "queue.h" |
| 22 | +#include "arm_math.h" |
| 23 | + |
| 24 | +/* |
| 25 | + * ADS1220 Registers and Command Values |
| 26 | + */ |
| 27 | + |
| 28 | +enum ADS1220_REGISTERS_AND_COMMANDS{ |
| 29 | + |
| 30 | + //Write Single Register Command |
| 31 | + ADS1220_REG0_W = 0x40, |
| 32 | + ADS1220_REG1_W = 0x44, |
| 33 | + ADS1220_REG2_W = 0x48, |
| 34 | + ADS1220_REG3_W = 0x4C, |
| 35 | + |
| 36 | + //Read Single Register Command |
| 37 | + ADS1220_REG0_R = 0x20, |
| 38 | + ADS1220_REG1_R = 0x24, |
| 39 | + ADS1220_REG2_R = 0x28, |
| 40 | + ADS1220_REG3_R = 0x2C, |
| 41 | + |
| 42 | + //Read Data Command |
| 43 | + ADS1220_READ_DATA = 0x10, |
| 44 | + //Start Sync Conversion |
| 45 | + ADS1220_START_SYNC = 0x08, |
| 46 | + //Reset |
| 47 | + ADS1220_RESET = 0x06, |
| 48 | + //Power Down |
| 49 | + ADS1220_POWER_DOWN = 0x02 |
| 50 | +}; |
| 51 | + |
| 52 | +/* |
| 53 | + * ADS1220_CONFIG is an enum for making it easier to enable/disable |
| 54 | + * configs on the ADS1220. |
| 55 | + * |
| 56 | + * EXAMPLE OF USAGE: |
| 57 | + * Multiple bits Config: |
| 58 | + * REG = ( REG & BITMASK ) | VALUE; |
| 59 | + * |
| 60 | + * Single Bit Config: |
| 61 | + * REG |= ( 1UL << BIT POSITION ); |
| 62 | + */ |
| 63 | +enum ADS1220_CONFIG_VALUES{ |
| 64 | + |
| 65 | + // Config Register 0 |
| 66 | + ADS1220_GAIN_1 = 0x00, |
| 67 | + ADS1220_GAIN_2, |
| 68 | + ADS1220_GAIN_4, |
| 69 | + ADS1220_GAIN_8, |
| 70 | + ADS1220_GAIN_16, |
| 71 | + ADS1220_GAIN_32, |
| 72 | + ADS1220_GAIN_64, |
| 73 | + ADS1220_GAIN_128, |
| 74 | + ADS1220_GAIN_BITMASK = 0xF1, |
| 75 | + |
| 76 | + //ADS1220 MUX CONFIG |
| 77 | + //Named as: First AINp Last AINn |
| 78 | + |
| 79 | + ADS1220_MUX_AIN0_AIN1 = 0x00, |
| 80 | + ADS1220_MUX_AIN0_AIN2, |
| 81 | + ADS1220_MUX_AIN0_AIN3, |
| 82 | + ADS1220_MUX_AIN1_AIN2, |
| 83 | + ADS1220_MUX_AIN1_AIN3, |
| 84 | + ADS1220_MUX_AIN2_AIN3, |
| 85 | + ADS1220_MUX_AIN1_AIN0, |
| 86 | + ADS1220_MUX_AIN3_AIN2, |
| 87 | + ADS1220_MUX_AIN0_AVSS, |
| 88 | + ADS1220_MUX_AIN1_AVSS, |
| 89 | + ADS1220_MUX_AIN2_AVSS, |
| 90 | + ADS1220_MUX_AIN3_AVSS, |
| 91 | + //There is more FOUR cases not listed here |
| 92 | + //because they're not going to be used anyway. |
| 93 | + ADS1220_MUX_BITMASK = 0x0F, |
| 94 | + |
| 95 | + // Config Register 1 |
| 96 | + |
| 97 | + ADS1220_DATA_RATE_0 = 0x00, |
| 98 | + ADS1220_DATA_RATE_1, |
| 99 | + ADS1220_DATA_RATE_2, |
| 100 | + ADS1220_DATA_RATE_3, |
| 101 | + ADS1220_DATA_RATE_4, |
| 102 | + ADS1220_DATA_RATE_5, |
| 103 | + ADS1220_DATA_RATE_6, |
| 104 | + ADS1220_DATA_RATE_7, //Reserved |
| 105 | + ADS1220_DATA_RATE_BITMASK = 0x1F, |
| 106 | + |
| 107 | + ADS1220_MODE_NORMAL = 0x00, |
| 108 | + ADS1220_MODE_DUTY_CYCLE, |
| 109 | + ADS1220_MODE_TURBO, |
| 110 | + ADS1220_MODE_BITMASK = 0xE7, |
| 111 | + |
| 112 | + // Config Register 2 |
| 113 | + ADS1220_IDAC_OFF = 0x00, |
| 114 | + ADS1220_IDAC_RES, |
| 115 | + ADS1220_IDAC_50ua, |
| 116 | + ADS1220_IDAC_100ua, |
| 117 | + ADS1220_IDAC_250ua, |
| 118 | + ADS1220_IDAC_500ua, |
| 119 | + ADS1220_IDAC_1000ua, |
| 120 | + ADS1220_IDAC_1500ua, |
| 121 | + ADS1220_IDAC_BITMASK = 0xF8, |
| 122 | + |
| 123 | + ADS1220_VREF_INTERNAL = 0x00, |
| 124 | + ADS1220_VREF_REFP0_REFN0, |
| 125 | + ADS1220_VREF_AIN0_AIN3, |
| 126 | + ADS1220_VREF_ANALOG_SUPPLY, |
| 127 | + ADS1220_VREF_BITMASK = 0x3F, |
| 128 | + |
| 129 | + // Config Register 3 |
| 130 | + ADS1220_IDAC1_DISABLED = 0x00, |
| 131 | + ADS1220_IDAC1_AIN0_REFP1, |
| 132 | + ADS1220_IDAC1_AIN1, |
| 133 | + ADS1220_IDAC1_AIN2, |
| 134 | + ADS1220_IDAC1_AIN3_REFN1, |
| 135 | + ADS1220_IDAC1_REFP0, |
| 136 | + ADS1220_IDAC1_REFN0, |
| 137 | + ADS1220_IDAC1_RESERVED, |
| 138 | + ADS1220_IDAC1_BITMASK = 0x1F, |
| 139 | + |
| 140 | + ADS1220_IDAC2_DISABLED = 0x00, |
| 141 | + ADS1220_IDAC2_AIN0_REFP1, |
| 142 | + ADS1220_IDAC2_AIN1, |
| 143 | + ADS1220_IDAC2_AIN2, |
| 144 | + ADS1220_IDAC2_AIN3_REFN1, |
| 145 | + ADS1220_IDAC2_REFP0, |
| 146 | + ADS1220_IDAC2_REFN0, |
| 147 | + ADS1220_IDAC2_RESERVED, |
| 148 | + ADS1220_IDAC2_BITMASK = 0xE3, |
| 149 | + |
| 150 | +}ADS1220_CONFIG_VALUES; |
| 151 | + |
| 152 | +enum ADS1220_CONFIG_POS{ |
| 153 | + |
| 154 | + // Config Register 0 |
| 155 | + ADS1220_CONFIG_PGA_BYPASS = 0x0, |
| 156 | + ADS1220_CONFIG_GAIN = 0x1, |
| 157 | + ADS1220_CONFIG_MUX = 0x4, |
| 158 | + |
| 159 | + // Config Register 1 |
| 160 | + ADS1220_CONFIG_BCS = 0x0, |
| 161 | + ADS1220_CONFIG_TS = 0x1, |
| 162 | + ADS1220_CONFIG_CONV_MODE = 0x2, |
| 163 | + ADS1220_CONFIG_OP_MODE = 0x3, |
| 164 | + ADS1220_CONFIG_DATA_RATE = 0x5, |
| 165 | + |
| 166 | + // Config Register 2 |
| 167 | + ADS1220_CONFIG_IDAC = 0x0, |
| 168 | + ADS1220_CONFIG_PSW = 0x3, |
| 169 | + ADS1220_CONFIG_FIR_FILTER = 0x4, |
| 170 | + ADS1220_CONFIG_VREF = 0x6, |
| 171 | + |
| 172 | + // Config Register 3 |
| 173 | + ADS1220_CONFIG_RESERVED = 0x0, // Never change this register to 1 |
| 174 | + ADS1220_CONFIG_DRDYM = 0x1, |
| 175 | + ADS1220_CONFIG_I2MUX = 0x2, |
| 176 | + ADS1220_CONFIG_I1MUX = 0x5, |
| 177 | + |
| 178 | +}ADS1220_CONFIG_POS; |
| 179 | + |
| 180 | +enum ADS1220_FAULTS{ |
| 181 | + ADS1220_SEMAPHORE_FAULT = -3, |
| 182 | + ADS1220_SPI_FAULT = -2, |
| 183 | + ADS1220_CONFIG_FAULT = -1, |
| 184 | + ADS1220_SUCCESS = 0 |
| 185 | +}ADS1220_FAULTS; |
| 186 | +// Functions and Tasks Prototypes |
| 187 | + |
| 188 | + |
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